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A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems

Ann Gordon-Ross1*, Saleh Abdel-Hafeez2, and Mohamad Hammam Alsafrjalni3

1
Department of Electrical and Computer Engineering University of Florida (UF), Gainesville, FL, USA
2
Jordan University of Science and Technology, Irbid 22110, Jordan; sabbatical at Qassim University, Saudi Arabia
3
Department of Electrical and Computer Engineering University of Miami (UM), Coral Gables, FL, USA
*Also with the NSF Center for High Performance Reconfigurable Computing (CHREC) at UF
E-mail: 1ann@ece.ufl.edu, 2sabdel@just.edu.jo, 3alsafrjalani@miami.edu

Abstract—We present an efficient synchronous first-in
first-out (FIFO) buffer for enhanced memory management
units and inter-core data communication in manycore
systems. Our design significantly reduces hardware
overhead and eliminates latency delays by using both the
rising and falling clock edges during read and write, which
makes our design suitable for increased processing element
(PE) utilization by increasing the memory bandwidth in
complex network and system on-chip solutions. Compared
to prior work, our design can operate 5X faster at the
same supply voltage, or up to 44X faster with a 2.5X
increase in supply voltage. Our design’s total power
consumption is 7.8 mW with a total transistor count of
34,470.
I. INTRODUCTION
Traditional microprocessors have increasing numbers of
processing elements (PEs) on a single die in order to afford
continued performance improvements. To leverage these
performance improvements, applications must be written such
that the work can be efficiently divided across the PEs, often
resulting in different cores operating on the same data or
coordinating data passing between PEs, presenting a significant
challenge in keeping up with memory bandwidth requirements
in order to eliminate/reduce PE idleness while waiting for data
transfers. The memory management unit that orchestrates this
data movement can introduce significant performance
degradation, which worsens as the number of PEs and data
sharing/passing increases. One way to alleviate this bottleneck
is to migrate a portion of the most frequently used memory
management software units to hardware components [1][2]
A frequently used memory management unit is the buffer
management software defining the first-in first-out (FIFO)
buffer rules between PEs. Fig. 1 depicts a generic circuit
architecture for a conventional FIFO buffer design comprised
of three stages. The address-pointer stage generates the address
pointers, the address-decoder stage generates the memory
address word line, and the isolate stage isolates these two
operations. We note that this architecture can have different
circuit components depending on the power consumption and
speed optimization requirements [6][11][7][8][13].
One of the drawbacks of this generic architecture is the N
registers required to isolate the memory address line updates
and increment operations to ensure that the correct memory
address lines are active at the correct times. These registers
impose a large power consumption and area overhead [4]. To
reduce switching activity, prior works (e.g., [11][8]) introduced
a gray counter in the address-pointer stage while other works
[7][13] introduced a shift register, however, even though these
methods are efficient, they still require a large number of
registers.
Another major drawback is the delay control circuit needed
to compensate for the address-decoder’s stage setup/hold time
by delaying the clock signal. To address these drawbacks,
some works used a counter-based pointer [11], or replicated the
write and read detector pointers [6]. However, both approaches
had complex layout designs to align with and meet the
setup/hold timing criteria between the address-decoder stage
and input/output for the data memory, requiring complex
control units and self-timing, which imposed additional design

Fig. 1. Conventional FIFO design


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Fig. 2. (a) FIFO block diagram; (b) Write operation; (c) Read operation

increase in supply voltage. Our design’s total power

complexity and degraded the operating speed. consumption is 7.8 mW with a total transistor count of 34,470.
To address these drawbacks, we propose a new architecture
that isolates the address-pointer and address-decoder stages II. FIFO QUEUE HARDWARE
using a non-overlapping circuit [3], which eliminates the need Fig. 2 (a) depicts the architectural block structure for our FIFO
for the N isolation registers using a novel separated two-phase design. The finite state machine (FSM) flow charts in Fig. 2 (b)
non-overlapping clocking system structure. Our circuit uses the and (c) depict the structure’s write and read functionalities,
main system clock CLK to generate two phase-clock signals respectively, along with the associated input/output signals.
CLKN and CLKP that are the exact complement of each other The rectangular boxes in the FSM are states that occur on non-
and whose edges are isolated, thus the two are mutually overlapping clock cycles, where the clock edges are shown
exclusive events occurring on the rising and falling edges of next to the boxes. TABLE 1 depicts the input/output signals’
the system clock [10]. abbreviations and descriptions.
Prior designs used the isolate stage’s N registers to Before operation, the write address-pointer (WAP), read
synchronize with the delay control circuit, which was needed to address-pointer (RAP), and up-down counter (CT) are
insert a large enough delayed to adhere to the setup time initialized to zero. During the write operation, the M-bit input
criteria for reading and writing to the SRAM. Our approach data is stored at the memory location pointed to by the memory
obviates the use of these N registers, and eliminates all design write word line (WWL) of size 2N-row for N-bit WAP on the
challenges, additional timing, and all associated overhead rising system clock (CLK) edge (i.e., the WAP is an up counter
circuitries. Race conditions are safely avoided between the of size N-bit). During the falling CLK edge, WAP and CT are
address-pointer and address-decoder stages (i.e., maintaining incremented, and WWL is disabled. Once CT reaches the full
isolation between the stages without the N registers) and the state, the write operation ends even if there are outstanding
setup/hold time between the memory word line increments and write requests. The read operation is similar, wherein the M-bit
data accesses are sufficient for at least half of a clock cycle, output data (DOUT) is released during the rising CLK edge.
eliminating the need for the delay control circuit. By restricting During the falling CLK edge, the RAP is incremented using a
the address-pointer and address-decoder stages’ activities to simple N-bit up counter, while the CT is decremented and
separate halves of the clock cycle, the isolate stage and delay RWL is disabled. Once CT reaches zero, the empty state, the
control circuits are eliminated, enabling high-speed read/write
operations and power consumption reduction by eliminating
unnecessary components and restricting switching activity to TABLE 1
only the needed components during the required clock phase. SIGNAL DEFINITIONS
Input-Output Representation
Another novel feature of our proposed design is the method
Signals
for generating the empty and full flags using circuitry that
WE Write enable for the write operation
checks for an address roll-over instead of tracking every RE Read enable for the read operation
storage address or data register in the FIFO. This structure CLK System clock
eliminates any arithmetic operation circuitry, such as a RES Reset for state initialization
subtractor and gray code mapping, a long right-left shift EMPTY Flag for the empty buffer
register, or a logic-expensive up/down counter FULL Flag for the full buffer
[2][6][11][7][8][13]. Furthermore, the flags require only four DIN [M-1:0] Input data bus of size M
DFFs, regardless of the depth of the FIFO, and thus limit the DOUT [M-1:0] Output data bus of size M
cost and hardware overhead associated with deeper FIFOs. RAP [N-1:0] Read address-pointer of size N
Compared to prior work, our design can operate 5X faster WAP [N-1:0] Write address-pointer of size N
at the same supply voltage, or up to 44X faster with a 2.5X WWL [2N-1:0] Memory write word line of size 2N
RWL [2N-1:0] Memory read word line of size 2N




Fig. 3. Detailed hardware diagram for our proposed FIFO design
read operation ends even if there are outstanding read requests.
Fig. 3 depicts the read and write operations’ hardware with
respect to CLK. The FIFO’s core storage unit is constructed
using an 8T-Cell SRAM circuit. The write and read decoders
are divided into two separate components: the address-pointer
and address-decoder. The circuit structure of the address-
pointer is the up counter and is based on the state look-ahead

address-decoders are enabled when CLKP is asserted high and
Fig. 4. Empty/Full flag circuitry.



parallel counter logic presented in [9].
The two-phase clock signals, CLKN and CLKP, are
derived from CLK and represent CLK’s negative and positive
versions, respectively. CLKP and CLKN are at the opposite
phase of each other and their transition edges are non-
overlapping, which ensures that there are no race conditions
between address-pointer and address-decoder, such that while
address-pointer is disabled/enabled, address-decoder is
enabled/disabled, respectively. The clock signal source and
traditional back-to-back NAND two-phase clocking systems
[9] are usually susceptible to fabrication process, voltage, and
temperature (PVT) variation, as well as noise jitter variation.
All these variations can have a negative impact on the duty
cycle of the two phases and non-overlapping margin, thus
negatively impacting overall circuit timing performance.
Usually, a delay-locked-loop circuit (DLL) [14] is used to
control the PVT variations and preserve clock skew, however,
due to its complexity, power consumption, and area cost and
large overhead in manycore architectures, we use a simpler
circuit [10] with similar achievements. [10] showed that
simulations over PVT corners, for non-ideal clock signals
provides non-overlapping phases with low values of root mean
square (RMS) jitter.
There are two parallel counters, one for each read and write
address-pointer. Each counter is triggered by CLKN, which is
gated with the read/write operation enable signals, REN/WEN,
respectively, such that the counter is incremented whenever a
write/read operation occurs. Alternatively, the write/read
is gated with the WEN/REN signals, respectively.


Fig. 4 depicts our empty-full flag circuitry solution. The
empty-full flag detects the roll-over of the read and write
address-pointers using two serially-connected DFFs for each
operation (i.e., one pair of DFFs for the read operation and
another pair for the write operation). Both pairs of serially
connected DFFs are initialized to ‘10.’ The least significant bits
(LSBs) are XNORed for evaluation of the flags’ statuses in
combination with the read and write address-pointers. If the
address-pointers’ values are equal and the serially-connected
DFFs’ LSBs are equal, the empty flag is asserted high, and
alternatively, if the address-pointers’ values are equal and the
serially-connected DFFs’ LSBs are different, full is asserted
high. When the associated read/write address-pointer reaches
the full state, then the associated pair of serially-connected
DFFs change state to ‘01’ on the rising CLKP edge, as shown
on the DFFs’ clock signal in Fig. 4.
III. TIMING CONSTRAINTS
In order to evaluate the scalability of our approach, the timing
of all critical paths including the setup/hold-gated with the two-
phase clocks, CLKN and CLKP must be independent of the
technology. To the best of our knowledge, our design is the
first implementation of a FIFO that uses a non-overlapping
two-phase clocking system. Our design uses only a basic
CMOS logic gate structure with basic width/length sizes for
design layout clarity and cost-effectiveness for continued
technology scaling. We evaluate our proposed FIFO circuit
based on an 8T-Cell SRAM structure of size 64-entry x 64-bit
as a common size for many applications.
Fig. 5 enumerates all of the possible path delays generated
in the data path by the non-overlapping two-phase clocking
system. The circuit generation of the clocking system
approximates the non-overlapping time as three gate delays
(GDs) for a worst-case timing scenario:
Non-Overlap = 3 * GDs (1)
such that, on the falling CLK edge, CLKN is rising after three
gate delays and CLKP is falling after one gate delay.
Alternatively, on the rising CLK edge, CLKN is falling after
three gate delays and CLKP is rising after one CLK delay.
The address-pointer stage is triggered by the rising CLKN
edge (Fig. 5, Path2). The time to increment the counter that
Fig. 5. Critical paths in our proposed design

generates the address-pointer is only the delay of a single DFF.
A single DFF delay is composed of two gate delays as a
precaution for a worst-case timing scenario:
CT = 2 * GDs (2)
A portion of the address-decoder logic, except the last
stage, is integrated into the address-pointer stage, giving an
additional three gate delays. Thus, the total gate delay count for
generating the memory word line address prior to the last stage
of address-decoder is:
Path2-End1 = 5 GDs (3)
This delay is shown as Path2-End1 in Fig. 5.
The empty and full flags are evaluated at the rising edge of
the CLKN signal that follows the incrementing of the address-
pointer. CLKN is implemented using XNOR and AND gate
logic that requires two gate delays
Path2-End2 = 2 GDs (CT) + 2 GDs (XNORs&AND) = 4 GDs
(4)
This delay is shown as Path2-End2 in Fig. 5.
The roll-over status is pre-evaluated in the empty and full
flag circuitry on the rising CLKP edge after incrementing the
address-pointer. This operation enables a large fan-in AND
gate, which requires two gate delays:
Path2-End3=2 GDs (CT) + 2 GDs (large fan-in AND)= 4
GDs (5)
This delay is shown as Path2-End3 in Fig. 5.
The evaluation of the roll-over status is stored in the 2-bit
serial shifter in the flag circuitry at the rising CLKP edge. This
evaluation ensures that Path2-End3 ends before the 2-bit serial
shifter changes its state. Therefore, one of the possible worst-
case timing scenarios for CLK includes the worst-case timing
of CLKN, with the addition of three gate delays for the non-
overlapping operation:
CLK = 5 GDs (CLKN high) + 5 GDs (CLKN low) + 3 GDs
(Non-Overlap) = 13 GDs (6)
The SRAM read-write word lines accessed in the last stage
of the address-decoder are gated with CLKP and the REN or


Fig. 6. Timing diagram with associated events during one clock
cycle
WEN signals, as depicted in Fig. 5. The last stage of the
address-decoder requires three gate delays, even though it is
driven by only one gate, due to the loading parasitic effect. As
a result, considering the worst-case word line access timing
scenario, the read operation starts from Path1 and ends at the
input/output to the SRAM memory:
Path1-End1 = 6 GDs (SRAM read) + 3 GDs (last stage
decoder) + 1 GD (gated CLKP) = 10 GDs (7)
This delay is shown as Path1-End1 in Fig. 5. This path creates
a CLK timing scenario that can be approximated using the
worst-case timing of CLKP plus the three gate delays for the
non-overlapping operation:
CLK = 20 GDs (2*Path1-End1) + 3 GDs (Non-Overlap)
= 23 GDs (8)
The slew rate is approximated as three for each of the rising
and falling edges and is added to the overall CLK cycle time,
giving the final CLK cycle time of:
CLK = 23 GDs (CLK) + 6 GDs (slew rate) = 29 GDs (9)
The control unit structure for the FIFO (Fig. 3) generates
the write enable WEN and read enable REN signals within one
gate delay. A single gate delay is all that is required to
guarantee that the WEN or REN signals are active high for one
complete CLK cycle, even if the signals RE and WE are not
originally aligned with the CLK. Therefore, the total worst-
case CLK cycle time is:
CLK = 30 GDs (10)
Fig. 6 summarizes a FIFO access during one CLK cycle,
where the events labeled as Path1-End1, Path1-End2, Path2-
End1, Path2-End2, Path2-End3, and Pre-charge occur within
the two non-overlapping two-phase signals, CLKN and CLKP,
with a safe non-overlapping margin.
IV. RESULTS AND ANALYSIS
Without loss of generality and for comparison purposes, we
implemented, tested, and verified our FIFO queue buffer
hardware architecture of size 64-entry x 64-bits using SRAM
8T-Cells, which is similar to many prior hardware queue
integrated circuits [2][6][11][7][8][13]. We architected our
proposed queue buffer hardware at the CMOS transistor level
using 65-nm Taiwan Semiconductor Manufacturing Company
(TSMC) technology with a 1 V power supply. Additionally, it
is well known that two-phase clocking systems are becoming
tdominant in emerging technology markets, which is evident

when studying processor evolution, such as the ARM-1 to
ARM-9, with recent technologies.
We verify the functionality of our proposed FIFO using a
Verilog HDL implementation. For brevity, we omit the
behavioral simulation waveforms without SRAM. The
waveforms show the changes in the write and read address-
pointers, word line activities based on these pointers, and the
full and empty flag operations, using the signals defined in
Table 1 for write operations followed by read operations. The
FIFO is initially empty and the following sequential operations
occur: (1) a write operation for 10 clock cycles; (2) a read
operation for 12 clock cycles; (3) a write operation for 66 clock
cycles; and (4) a read operation for 68 consecutive cycles.
These operations and cycle durations verify correct operation
for all possible scenarios for the full and empty flags
conditions, the read and write address-pointers as well as the
address-pointers’ incrementing on the positive CLKN edge
and holding on the positive CLKP edge, and the SRAM word
address lines showing activity only on the rising CLKP edge
based on the empty and full flag assertions.
We gathered timing delay values, total power consumption,
and total transistor counts using HSPICE [12] simulations,
which show that our proposed FIFO buffer’s read/write
operations can execute at a system clock frequency CLK =
1.15GHz with a slew rate rise-fall of 0.15 v/ns. This design
frequency is very close to the timing analysis derived in
Section IV, with a system clock CLK cycle timing of
approximately 30 gate delays as derived in equation (10).
To reduce power consumption, we used a non-overlapping
clocking system that is commonly used in the ARM
architecture. This design approach has no latency delay (i.e.,
the write or read cycle happen in exactly one clock cycle).
The gate delay for the 65-nm technology ranges from 0.015
ns to 0.035 ns depending on the parasitic components and the
components’ sizes, wherein the minimum technology size for
the length is used. For all transistors, we use a channel length
of 65 nm where the widths range from 3 μm to 5 μm except the
inverter driver widths that are Wp = 15 μm and Wn = 10 μm.
The 8T-Cell SRAM is 65 nm, which is a standard geometry
size from Intel [5]. The overall design’s total power
consumption is approximately 7.8 mW.
TABLE 2 shows the characteristics and component
architecture details for our FIFO compared to related work
[6][11][7] for continued technology scaling. We detail the
address-pointer, control, data storage, and the empty/full flag
circuitry. The related works’ structures follow recent
advancements in technology implementation trends and have
circuits that are targeted for high-speed operation with a low
power budget. This comparison evaluates the designs’
complexities and scalabilities independent of the underlying
technology since it is challenging to find comparable designs
with the same technology parameters, however, the comparison
still provides insights about the power consumption, speed,
scalability, and design layout complexity. Compared to prior
work, our design can operate 5X faster at the same supply
voltage, or up to 44X faster with a 2.5X increase in supply
voltage.


TABLE 2
COMPARISON BETWEEN PRIOR WORKS AND OUR PROPOSED FIFO DESIGN
Address-Pointer Control Unit Storage Unit Flag Unit Freq/
Voltage
[6] Event-driven self-timed Self-timed management 10T-Cell SRAM Up/down indicators 22.7 MHz/
pointers using replica units and power 256-word X 16- 0.4V
write and read pulses switched control circuit bit

[11] Adder and binary registers Counter control unit Dual-port RAM Johnson counter 200 MHz/
128-word X 32- 1V
bit
[7] Cyclic address with one- Latches are connected Latched-based No flags are used, 27 MHz/
hot bubble-encoding and in parallel forming requiring N*(N- all pipeline lanes are 0.28V
shift register lanes activated every 1) latches for N full, then output is
other cycle lanes released
Our Carry look-ahead state Non-overlapping clock 8T-Cell SRAM Rollover detection 1 GHz/
Work counter using 2 opposing phase- 64-word X 64-bit and comparison 1V
clocks circuit

V. CONCLUSIONS [5] S. Abdel-Hafeez, M. Shatnawi, and A. Gordon-Ross, A DOUBLE

Our proposed FIFO design provides high-speed operation, and
large SRAM-based storage capacity with a simple scalable
design. The design uses two phase-clocks , which eliminates
the race conditions between incrementing the addresses and
accessing the data for write/read operations. Our design
leverages the key advantages of the two-ported SRAM
memory 8T-Cell for high-speed operation. The empty/full flag
circuitry is simplified to record the roll-over of the FIFO’s
maximum address values, which precludes the use of large
circuits with continuous switching activity. In future work, we
will adapt the design for asynchronous behavior using two
independent separate clocks signals for the read and write
operations.
VI. ACKNOWLEDGEMENTS
The authors would like to acknowledge the support of National
Science Foundation (CNS-1718033) and Jordan University of
Science and Technology for both providing the financial
support to complete this work. Any opinions, findings, and
conclusions or recommendations expressed in this material are
those of the authors and do not necessarily reflect the views of
the National Science Foundation.
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