1 Logic Gate

S Smart Course Questions (A) NOR, OR (B) OR, NAND

(C) NAND, OR (D) AND, NAND
Q.1 The Boolean function Y = AB + CD is to
Q.6
be realized using only 2-input NAND gates.
A EX-OR
The minimum number of gates required is B
_____________.
Q.2 Which one of the following is the correct AND

output (f) of the below circuit ? C X

EX-NOR
For the logic circuit shown in the above
figure, what is the required input condition
(A, B, C) to make output X = 1 ?
( )
(A) ( a + b ) c + d ( )( )
(B) a + b c + d (A) 1, 0, 1 (B) 0, 0, 1
(C) 1, 1, 1 (D) 0, 1, 1
(C) ( a + b )( c + d ) (D) ( a + b ) ( a + d ) Q.7 Match the logic gates in Column A with
Q.3 The Boolean expression Y(A, B, C) = A + their equivalents in Column B.
BC is to be realized using 2-input gates of [GATE 2010, IIT Guwahati]
only one type. What is the minimum Column A Column B
number of gates required for the realization P. 1.
? ___________.
Q.4 The minimum number of 2-input NAND Q. 2.
gates required to implement the Boolean
function Z = AB C , assuming that A, B and
R. 3.
C are available is [GATE 1998, IIT Delhi]
(A) two (B) three
S. 4.
(C) five (D) six
Q.5 In the figure shown, the output Y is required
Codes : P Q R S
to be Y = AB + C D . The gates G1 and G2
(A) 2 4 1 3
must be, [GATE 2015, IIT Kanpur] (B) 4 2 1 3
A (C) 2 4 3 1
G1
(D) 4 2 3 1
B Y
G2 Q.8 Which one of the following expressions
C does NOT represent exclusive NOR of x
D and y? [GATE 2013, IIT Bombay]
 2 Digital Electronics : Smart Course Workbook GATE ACADEMY ®

(A) xy + x’y’ (B) x ⊕ y' Q.12 Let x1 ⊕ x2 ⊕ x3 ⊕ x4 = 0 where x1 , x2 , x3 ,

(C) x' ⊕ y (D) x' ⊕ y' x4 are Boolean variables, and ⊕ is the
Q.9 For the output F to be 1 in the logic circuit XOR operator.
shown, the input combination should be Which one of the following must always be
[GATE 2010, IIT Guwahati] TRUE? [GATE 2016, IISc Bangalore]
A (A) x1 x2 x3 x4 = 0
B (B) x1 x3 + x2 = 0
(C) x1 ⊕ x3 = x2 ⊕ x4
F
(D) x1 + x2 + x3 + x4 = 0
Q.13 Assume that only x and y logic input are
C
available, and their complements x and y
(A) A = 1, B = 1, C = 0
are not available. What is the minimum
(B) A = 1, B = 0, C = 0
number of 2-input NAND gates required to
(C) A = 0, B = 1, C = 0 implement x ⊕ y ? __________.
(D) A = 0, B = 0, C = 1
Q.14 All the logic gates shown in the figure have
Q.10 A, B, C and D are input bits and Y is the a propagation delay of 20 ns. Let A = C = 0
output bit in the XOR gate circuit of the and B = 1 unit time t = 0 . At t = 0 , all the
figure below. Which of the following inputs flip (i.e. A = C = 1 and B = 0 ) and
statements about the sum S of A, B, C, D and remain in that state. For t > 0 , output Z = 1
Y is correct? [GATE 2007, IIT Kanpur] for a duration (in ns) of ________.
A [GATE 2015, IIT Kanpur]
XOR
B A
Z
B
XOR Y
C
Q.15 Consider the following circuit composed of
C
XOR XOR gates as non – inverting buffers.
D
A B
(A) S is always either zero or odd. d2 = 4
d1 = 2
(B) S is always either zero or even. The non- inverting buffers have delays
(C) S = 1 only if the sum of A, B, C and D δ1 = 2 ns and δ2 = 4 ns as shown in the
is even.
figure. Both XOR gates and all wires have
(D) S = 1 only if the sum of A, B, C and D zero delay. Assume that all gate inputs,
is odd. outputs and wires are stable at logic level 0
Q.11 If the input to the digital circuit consisting at time 0. If the following waveform is
of a cascade of 20 X-OR gates is X, then the applied at input A, how many transition(s)
output Y is equal to (change of logic levels) occur(s) at B during
[GATE 2002, IISc Bangalore] the interval from 0 to 10 ns?
1 [GATE 2003, IIT Madras]
Y
Logic 1

A Logic 0
X
(A) 0 (B) 1 Time 0 1 2 3 4 5 6 7 8 9 10 ns 11 ns
(A) 1 (B) 2
(C) X (D) X
(C) 3 (D) 4
GATE ACADEMY ® Logic Gate 3

Q.16 The gates G1 and G2 in figure have Q.17 For the ring oscillator shown in the figure,
propagation delays of 10 nsec and 20 nsec the propagation delay of each inverter is
100 pico-sec. What is the fundamental
respectively. If the input Vi makes an
frequency of the oscillator output?
abrupt change from logic 0 to 1 at time
[GATE 2001, IIT Kanpur]
t = t0 , then the output waveform V0 is
V0
[GATE 2002, IISc Bangalore]
G1
0 G2
V0 (A) 10 MHz (B) 100 MHz
1
Vi Vi 1 (C) 1 GHz (D) 2 GHz
0 Vi
t0

z (t1 = t0 + 10 nsec, t2 = t0 + 20 nsec,

t3 = t0 + 30 nsec)
(A) 1

0
t0 t1 t2 t3

(B) 1

0
t0 t1 t2 t3

(C) 1

0
t0 t1 t2 t3

(D) 1

0
t0 t1 t2 t3

A Answer Keys

Smart Course Questions

1. 3 2. A 3. 3 4. C 5. A

6. D 7. D 8. D 9. D 10. B

11. B 12. C 13. 4 14. 40 15. D

16. B 17. C