Basics of VLSI (ECB 351)

B Tech ECE 6th semester

Design of Flip Flop with MOS Logic
Take the approach of gate level design and then
for individual gate use standard MOS logic and
take care of connections and feed back path.
Gate design already covered
For SR latch design NOR gate based approach is
shown in next slide. Two Nor Gate have been
used with feedback paths.
 Operation
Consider the individual transistor and assume one
initial value of Q and Qbar.
Consider that there is lumped capacitance on nodes
Q and Qbar. Take the values of S and R and see
the individual transistor condition.
If any transistor in pull up is in on condition then it
will charge the node. If any transistor in pull
down is in on condition then it will discharge the
node. Operation will be more clear in next slide.
Operation of SR Latch
NOR based (SR latch) depletion load
with reduced transistor count
NAND based SR Latch
 Clocked SR latch
With addition of clock we require two more AND
gate with SR latch. Accordingly the clock will
be attached by a series transistor with S and R
input. Take two transistor in parallel for Nor
gate and one additional transistor in series for
AND gate for pull down.
Always design the pull down network first and
then design a dual network of pull down for
pull up.
Transistor Level design
NAND Based clocked SR latch
NOR based JK Flip flop
CMOS based normal approach for DFF
In the previous slide you can design the D flip
flop by SR latch design/normal gate design.
This is one method but it consumes more
transistor.
In the next slides we will design DFF by
transmission gate based approach. Design of
master slave flip flop is also shown with less
complexity.
Tri state inverter based approach
 Dynamic Logic circuits
CMOS static logics have many advantages and
widely used circuit design method for VLSI.
But for any additional input added to the gate
we need two transistor one in pull down and
one in pull up network.
Another type of logic to design the circuit is
dynamitic logic circuits having some
advantages.
Role of pull up network in static logic is only to
charge the nodes whereas the pull down
network is responsible for logic computations.
Using this technique we can design dynamic
logic circuits. In static logic every node is
connected to either VDD or ground at any
time.
In dynamic logics computation is done only
when clock is high so saving in power .
With additional clock added we can design the
logic. Figure shown in next slide explain this.
Dynamic logic circuits
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reserved.
 In dynamic logic circuits clock is applied in pull up
and pull down network. There is pre charge
phase and evaluation phase.
During the pre charge phase the pull up networks
charges the output node as clock is low.
At this time inputs are also required to settle.
In the evaluation phase the clock is high and logic
is computed. Depending upon the input
combinations either the output node will
remain at VDD or it will discharge.
 If we have applied such a input combination that
the output node remains at high(VDD) as it was
in precharge phase. Then we have saved the low
to high propagation delay and circuit will be fast.
Some input combination will definitely have
this.
In the other case when the input combinations is
such that the out put node discharge this is the
case as same as standard CMOS logic and will
have definite high to low propagation delay.
A 4 input NAND gate is shown in next slide.
© Oxford University Press 2013. All rights
reserved.
 Non ideal effects in dynamic logic
circuit

Dynamic circuits have some disadvantages like

1. Unequal noise margin
2. Leakage of charge
3. Charge sharing
4. Cascading of gates
© Oxford University Press 2013. All rights
reserved.
© Oxford University Press 2013. All rights
reserved.
© Oxford University Press 2013. All rights
reserved.
Domino Logic Gates
© Oxford University Press 2013. All rights
reserved.
© Oxford University Press 2013. All rights
reserved.
Reference: Microelectronic Circuits by Sedra Smith
A flip-flop is a bistable device, with inputs, that remains in a
given state as long as power is applied and until input signals
are applied to cause its output to change

Latches are flip-flops for which the timing of the output

changes are not controlled.
• For a latch, the output essentially responds immediately to
changes on the input lines (and possibly the presence of a
clock pulse).
• A flip-flop is designed to change its output at the edge of a
controlling clock signal.
The simplest sequential circuit or storage element is
a bistable element, which is constructed with two
inverters connected sequentially in a loop as shown
in Figure 1. It has no inputs and two outputs labeled
Q and Q’. Since the circuit has no inputs, we cannot
change the values of Q and Q’. However, Q will take
on whatever value it happens to be when the circuit
is first powered up. Assume that Q = 0 when we
switch on the power. Since Q is also the input to the
bottom inverter, Q’, therefore, is a 1.
 A bistable element has memory in the sense that it
can remember the content (or state) of the circuit
indefinitely. Using the signal Q as the state variable to
describe the state of the circuit, we can say that the
circuit has two stable states: Q = 0, and Q = 1; hence
the name “bistable.”

An analog analysis of a bistable element, however, reveals that it

has three equilibrium points and not two as found from the digital
analysis. Assuming again that Q = 1, and we plot the output
voltage (Vout1) versus the input voltage (Vin1) of the top inverter,
we get the solid line in Figure 2. The dotted line shows the
operation of the bottom inverter where Vout2 and Vin2 are the
output and input voltages respectively for that inverter.
Figure 2 shows that there are three intersection points,
two of which corresponds to the two stable states of the
circuit where Q is either 0 or 1. The third intersection
point labeled metastable, is at a voltage that is neither a
logical 1 nor a logical 0 voltage. Nevertheless, if we can
get the circuit to operate at this voltage, then it can stay at
that point indefinitely. Practically, however, we can never
operate a circuit at precisely a certain voltage. A slight
deviation from the metastable point as cause by noise in
the circuit or other stimulants will cause the circuit to go
to one of the two stable points. Once at the stable point, a
slight deviation, however, will not cause the circuit to go
away from the stable point but rather back towards the
stable point because of the feedback effect of the circuit.