1 2 3 4 5 6

Spartan-6 LX9 MicroBoard

Avnet Design Services

www.em.avnet.com/s6microboard
Function Sheet Number

Lead Sheet 1

A Block Diagram 2 A

Architecture 3

FPGA Bank 0 4

FPGA Bank 1 5

FPGA Bank 2 6

FPGA Bank 3 7

Power / USB JTAG 8

LPDDR Memory 9

FPGA 10/100 Ethernet PHY 10

Spartan-6 LX9 MicroBoard Rev C

B B

8/2/2012
2:45:45 PM

C C

Modified Rev A Boards are Functionally Equivalent to Rev B Boards.

Copyright 2012, Avnet, Inc. All Rights Reserved.
Modified Rev B Boards are Functionally Equivalent to Rev C Boards.
This material may not be reproduced, distributed, republished, displayed, posted, transmitted or copied in any form or by any means without the prior written
permission of Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All trademarks and trade names are the properties of their
respective owners and Avnet, Inc. disclaims any proprietary interest or right in trademarks, service marks and trade names other than its own.
X's are a "No ERC" directive to the Design Rule Checker to ignore rule violations.
D Avnet is not responsible for typographical or other errors or omissions or for direct, indirect, incidental or consequential damages related to this material or D
resulting from its use. Avnet makes no warranty or representation respecting this material, which is provided on an "AS IS" basis. AVNET HEREBY
DISCLAIMS ALL WARRANTIES OR LIABILITY OF ANY KIND WITH RESPECT THERETO, INCLUDING, WITHOUT LIMITATION, REPRESENTATIONS Avnet Engineering Services
REGARDING ACCURACY AND COMPLETENESS, ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, SUITABILITY OR Title:
FITNESS FOR A PARTICULAR PURPOSE, TITLE AND/OR NON-INFRINGEMENT. This material is not designed, intended or authorized for use in Sheet 1 - Lead Sheet
medical, life support, life sustaining or nuclear applications or applications in which the failure of the product could result in personal injury, death or property Size: Document Number: Rev:
damage. Any party using or selling products for use in any such applications do so at their sole risk and agree that Avnet is not liable, in whole or in part,
for any claim or damage arising from such use, and agree to fully indemnify, defend and hold harmless Avnet from and against any and all claims, B S6-LX9-SCH-C C
damages, loss, cost, expense or liability arising out of or in connection with the use or performance of products in such applications.
Date: 8/2/2012 Sheet 1 of 10

1 2 3 4 5 6
 1 2 3 4 5 6

A A

B B

C C

X's are a "No ERC" directive to the Design Rule Checker to ignore rule violations.
D D

Avnet Engineering Services

Title:
Sheet 2 - Block Diagram
Size: Document Number: Rev:

B S6-LX9-SCH-C C
Date: 8/2/2012 Sheet 2 of 10

1 2 3 4 5 6
 1 2 3 4 5 6

U_04 - FPGA Bank 0

04 - FPGA Bank 0.SchDoc
CLOCK_Y3

A A

U_10 - FPGA 10_100 Ethernet PHY U_05 - FPGA Bank 1

10 - FPGA 10_100 Ethernet PHY.SchDoc 05 - FPGA Bank 1.SchDoc
FPGA_ETH_RX_CLK FPGA_ETH_RX_CLK CLOCK_Y2
FPGA_ETH_RX_D0 FPGA_ETH_RX_D0
FPGA_ETH_RX_D1 FPGA_ETH_RX_D1
FPGA_ETH_RX_D2 FPGA_ETH_RX_D2
FPGA_ETH_RX_D3 FPGA_ETH_RX_D3
FPGA_ETH_RX_ER FPGA_ETH_RX_ER
FPGA_ETH_RX_DV FPGA_ETH_RX_DV
FPGA_ETH_TX_CLK FPGA_ETH_TX_CLK
FPGA_ETH_TX_D0 FPGA_ETH_TX_D0
FPGA_ETH_TX_D1 FPGA_ETH_TX_D1
FPGA_ETH_TX_D2 FPGA_ETH_TX_D2
FPGA_ETH_TX_D3 FPGA_ETH_TX_D3
FPGA_ETH_TX_EN FPGA_ETH_TX_EN
FPGA_ETH_COL FPGA_ETH_COL
FPGA_ETH_CRS FPGA_ETH_CRS
FPGA_ETH_MDC FPGA_ETH_MDC
FPGA_ETH_MDIO FPGA_ETH_MDIO
B FPGA_ETH_RESET# FPGA_ETH_RESET# B

U_06 - FPGA Bank 2

06 - FPGA Bank 2.SchDoc
CLOCK_Y2
CLOCK_Y3

C C
FPGA_MOSI_MISO0
FPGA_CCLK
FPGA_D0_DIN_MISO_MISO1
FPGA_SPI_CS#

U_09 - LPDDR Memory U_07 - FPGA Bank 3

09 - LPDDR Memory.SchDoc 07 - FPGA Bank 3.SchDoc
FPGA_LPDDR_DATA FPGA_LPDDR_DATA
FPGA_LPDDR_ADDRESS FPGA_LPDDR_ADDRESS
FPGA_LPDDR_CONTROL FPGA_LPDDR_CONTROL

U_08 - Power / USB JTAG

08 - Power_USB_JTAG.SchDoc
FPGA_MOSI_MISO0
FPGA_CCLK
FPGA_D0_DIN_MISO_MISO1
X's are a "No ERC" directive to the Design Rule Checker to ignore rule violations.
FPGA_SPI_CS#
D D

Avnet Engineering Services

COMTG2
MTG2 COMTG3
MTG3 COMTG1
MTG1 Title:
Sheet 3 - Architecture
Size: Document Number: Rev:
MOUNTING HOLE 125mil MOUNTING HOLE 125mil MOUNTING HOLE 125mil
C S6-LX9-SCH-C C
Date: 8/2/2012 Sheet 3 of 10
1 2 3 4 5 6
 1 2 3 4 5 6

COG1
G1 COG2
G2
A A
TEST PAD TEST PAD
+3.3V
COU4A
U4A
BANK 0
COR36
R36
PIG101 PIG201
D4 FPGA_HSWAPEN
IO_L01p_0_HSWAPEN PIU40D4 PIR3601 PIR3602
C4 4K87 0402
IO_L01n_0_VREF PIU40C4
B2
IO_L02p_0 PIU40B2
A2
IO_L02n_0 PIU40A2
D6 GND GND
IO_L03p_0 PIU40D6
C6 COSW1
SW1 +3.3V
IO_L03n_0 PIU40C6
B3 1 8
IO_L04p_0 PIU40B3 PISW101 PISW108
A3 2 7
IO_L04n_0 PIU40A3 PISW102 PISW107
B4 3 6
IO_L05p_0 PIU40B4 PISW103 PISW106
A4 4 5
IO_L05n_0 PIU40A4 PISW104 PISW105
C5
IO_L06p_0 PIU40C5 4CH SMT DIP SW
IO_L06n_0
NC
A5
PIU40A5
F7 PIR108 PIR107 PIR106 PIR105

8
7
6
5
PIU40F7
E6
NC PIU40E6
CORP1
RP1
B6
IO_L08p_0 PIU40B6
4K7 DNP Use Internal Pull Down Resistor If
A6
IO_L08n_0_VREF PIU40A6 Resistor Pack Is Not Installed.
E7
NC PIU40E7
E8
NC PIU40E8
IO_L10p_0
C7
PIU40C7
PIR10 PIR102 PIR103 PIR104
1
2
3
4
A7
IO_L10n_0 PIU40A7
B D8 B
IO_L11p_0 PIU40D8
C8
IO_L11n_0 PIU40C8
G8
NC PIU40G8
F8 GND
NC PIU40F8
B8
IO_L33p_0
Bank 0

PIU40B8
A8
IO_L33n_0 PIU40A8
3.3V

D9
IO_L34p_0_GCLK19 PIU40D9
C9
IO_L34n_0_GCLK18 PIU40C9
B9
IO_L35p_0_GCLK17 PIU40B9
A9
IO_L35n_0_GCLK16 PIU40A9
D11
IO_L36p_0_GCLK15 PIU40D11
C11
IO_L36n_0_GCLK14 PIU40C11
C10 POCLOCK0Y3
IO_L37p_0_GCLK13 PIU40C10 CLOCK_Y3 6
A10
IO_L37n_0_GCLK12 PIU40A10
G9
IO_L38p_0 PIU40G9
F9
IO_L38n_0_VREF PIU40F9
B11
IO_L39p_0 PIU40B11
A11
IO_L39n_0 PIU40A11
G11
NC PIU40G11
F10
NC PIU40F10
B12
IO_L41p_0 PIU40B12
A12
IO_L41n_0 PIU40A12
F11
NC PIU40F11
E11
NC PIU40E11
D12
C NC PIU40D12
C
C12
NC PIU40C12
C13
NC PIU40C13
A13
NC PIU40A13
F12
NC PIU40F12
E12
NC PIU40E12
B14
IO_L62p_0 PIU40B14
A14
IO_L62n_0_VREF PIU40A14
F13
IO_L63p_0_SCP7 PIU40F13
E13
IO_L63n_0_SCP6 PIU40E13
C15
IO_L64p_0_SCP5 PIU40C15
A15
IO_L64n_0_SCP4 PIU40A15
D14
IO_L65p_0_SCP3 PIU40D14
C14
IO_L65n_0_SCP2 PIU40C14
B16
IO_L66p_0_SCP1 PIU40B16
A16
IO_L66n_0_SCP0 PIU40A16

XC6SLX9-2CSG324

X's are a "No ERC" directive to the Design Rule Checker to ignore rule violations.
D D

Avnet Engineering Services

Title:
Sheet 4 - FPGA Bank 0
Size: Document Number: Rev:
S6-LX9-SCH-C C
B
Date: 8/2/2012 Sheet 4 of 10

1 2 3 4 5 6
 1 2 3 4 5 6

A A

COU4B
U4B
BANK 1
F15 FPGA_PMOD1_P1 +3.3V
IO_L01p_1_A25 PIU40F15
F16 FPGA_PMOD1_P2
IO_L01n_1_A24_VREF PIU40F16
IO_L29p_1_A23_M1A13
C17
PIU40C17
FPGA_PMOD1_P3 PIC8701 PIC8 02 PIC9701 PIC9802
C18 FPGA_PMOD1_P4 COC87
C87 COC88
C88 COC97
C97 COC98
C98
IO_L29n_1_A22_M1A14 PIU40C18 PMOD Headers must be placed in line
IO_L30p_1_A21_M1RESET
F14
PIU40F14
FPGA_PMOD1_P7
with 400mil spacing pin 6 center to
PIC8702 4.7uF 6.3V 0402 PIC8 01 0.22uF 6.3V 0201 PIC9702 4.7uF 6.3V 0402 PIC9801 0.22uF 6.3V 0201
G14 FPGA_PMOD1_P8 DNP
IO_L30n_1_A20_M1A11 PIU40G14 following pin 1 center.
D17 FPGA_PMOD1_P9
IO_L31p_1_A19_M1CKE PIU40D17
D18 FPGA_PMOD1_P10 GND
IO_L31n_1_A18_M1A12 PIU40D18
COJ5
H12 FPGA_PMOD2_P1 J5
IO_L32p_1_A17_M1A8 PIU40H12
NLFPGA0PMOD10P1 NLFPGA0PMOD10P7
G13 FPGA_PMOD2_P2 FPGA_PMOD1_P1 1 7 FPGA_PMOD1_P7
IO_L32n_1_A16_M1A9 PIU40G13
NLFPGA0PMOD10P2
PIJ501 P1 P7 PIJ507
NLFPGA0PMOD10P8
E16 FPGA_PMOD2_P3 FPGA_PMOD1_P2 2 8 FPGA_PMOD1_P8
IO_L33p_1_A15_M1A10 PIU40E16
NLFPGA0PMOD10P3
PIJ502 P2 P8 PIJ508
NLFPGA0PMOD10P9
E18 FPGA_PMOD2_P4 FPGA_PMOD1_P3 3 9 FPGA_PMOD1_P9
IO_L33n_1_A14_M1A4 PIU40E18
NLFPGA0PMOD10P4
PIJ503 P3 P9 PIJ509
NLFPGA0PMOD10P10
K12 FPGA_PMOD2_P7 FPGA_PMOD1_P4 4 10 FPGA_PMOD1_P10
IO_L34p_1_A13_M1WE PIU40K12 PIJ504 P4 P10 PIJ5010
K13 FPGA_PMOD2_P8 5 11
IO_L34n_1_A12_M1BA2 PIU40K13 PIJ505 GND GND PIJ5011
B F17 FPGA_PMOD2_P9 6 12 B
IO_L35p_1_A11_M1A7 PIU40F17 PIJ506 VCC VCC PIJ5012
F18 FPGA_PMOD2_P10
IO_L35n_1_A10_M1A2 PIU40F18
H13 6x2-2.54mm-SMT
IO_L36p_1_A9_M1BA0 PIU40H13
H14
IO_L36n_1_A8_M1BA1 PIU40H14
H15
IO_L37p_1_A7_M1A0 PIU40H15
H16
IO_L37n_1_A6_M1A1 PIU40H16
G16 GND
IO_L38p_1_A5_M1CLKp PIU40G16
G18
IO_L38n_1_A4_M1CLKn PIU40G18
J13 +3.3V
IO_L39p_1_M1A3
Bank 1

PIU40J13
K14
3.3V

IO_L39n_1_M1ODT PIU40K14

IO_L40p_1_GCLK11_M1A5
L12
PIU40L12
PIC90 1 PIC8402 PIC9401 PIC9502
L13 COC90
C90 COC84
C84 COC94
C94 COC95
C95
IO_L40n_1_GCLK10_M1A6 PIU40L13

IO_L41p_1_GCLK9_IRDY1_M1RASN
K15
PIU40K15
NLCLOCK0Y2
CLOCK_Y2 POCLOCK0Y2
CLOCK_Y2 6
PIC90 2 4.7uF 6.3V 0402 PIC8401 0.22uF 6.3V 0201 PIC9402 4.7uF 6.3V 0402 PIC9501 0.22uF 6.3V 0201
K16 DNP
IO_L41n_1_GCLK8_M1CASN PIU40K16
L15 NLFPGA0ETH0RX0CLK
FPGA_ETH_RX_CLK
IO_L42p_1_GCLK7_M1UDM PIU40L15 POFPGA0ETH0RX0CLK
FPGA_ETH_RX_CLK 12
L16 GND
IO_L42n_1_GCLK6_TRDY1_M1LDM PIU40L16
H17 NLFPGA0ETH0TX0CLK
FPGA_ETH_TX_CLK COJ4
J4
IO_L43p_1_GCLK5_M1DQ4 PIU40H17 POFPGA0ETH0TX0CLK
FPGA_ETH_TX_CLK 12
H18 NLFPGA0PMOD20P1
FPGA_PMOD2_P1 1 7 NLFPGA0PMOD20P7
FPGA_PMOD2_P7
IO_L43n_1_GCLK4_M1DQ5 PIU40H18 PIJ401 P1 P7 PIJ407
J16 NLFPGA0ETH0TX0D3
FPGA_ETH_TX_D3 NLFPGA0PMOD20P2
FPGA_PMOD2_P2 2 8 NLFPGA0PMOD20P8
FPGA_PMOD2_P8
IO_L44p_1_A3_M1DQ6 PIU40J16 POFPGA0ETH0TX0D3
FPGA_ETH_TX_D3 12 PIJ402 P2 P8 PIJ408
J18 NLFPGA0ETH0TX0D2
FPGA_ETH_TX_D2 NLFPGA0PMOD20P3
FPGA_PMOD2_P3 3 9 NLFPGA0PMOD20P9
FPGA_PMOD2_P9
IO_L44n_1_A2_M1DQ7 PIU40J18 POFPGA0ETH0TX0D2
FPGA_ETH_TX_D2 12 PIJ403 P3 P9 PIJ409
K17 NLFPGA0ETH0TX0D1
FPGA_ETH_TX_D1 NLFPGA0PMOD20P4
FPGA_PMOD2_P4 4 10 NLFPGA0PMOD20P10
FPGA_PMOD2_P10
IO_L45p_1_A1_M1LDQSp PIU40K17 POFPGA0ETH0TX0D1
FPGA_ETH_TX_D1 12 PIJ404 P4 P10 PIJ4010
K18 NLFPGA0ETH0TX0D0
FPGA_ETH_TX_D0 5 11
IO_L45n_1_A0_M1LDQSn PIU40K18 POFPGA0ETH0TX0D0
FPGA_ETH_TX_D0 12 PIJ405 GND GND PIJ4011
L17 NLFPGA0ETH0TX0EN
FPGA_ETH_TX_EN 6 12
IO_L46p_1_FCS_B_M1DQ2 PIU40L17 POFPGA0ETH0TX0EN
FPGA_ETH_TX_EN 12 PIJ406 VCC VCC PIJ4012
L18 NLFPGA0ETH0MDIO
FPGA_ETH_MDIO
IO_L46n_1_FOE_B_M1DQ3 PIU40L18 POFPGA0ETH0MDIO
FPGA_ETH_MDIO 12
M16 NLFPGA0ETH0MDC
FPGA_ETH_MDC 6x2-2.54mm-SMT
C IO_L47p_1_FWE_B_M1DQ0 PIU40M16 POFPGA0ETH0MDC
FPGA_ETH_MDC 12 C
M18 NLFPGA0ETH0COL
FPGA_ETH_COL
IO_L47n_1_LDC_M1DQ1 PIU40M18 POFPGA0ETH0COL
FPGA_ETH_COL 12
N17 NLFPGA0ETH0CRS
FPGA_ETH_CRS
IO_L48p_1_HDC_M1DQ8 PIU40N17 POFPGA0ETH0CRS
FPGA_ETH_CRS 12
N18 NLFPGA0ETH0RX0ER
FPGA_ETH_RX_ER
IO_L48n_1_M1DQ9 PIU40N18 POFPGA0ETH0RX0ER
FPGA_ETH_RX_ER 12
P17 NLFPGA0ETH0RX0DV
FPGA_ETH_RX_DV GND
IO_L49p_1_M1DQ10 PIU40P17 POFPGA0ETH0RX0DV
FPGA_ETH_RX_DV 12
P18 NLFPGA0ETH0RX0D3
FPGA_ETH_RX_D3
IO_L49n_1_M1DQ11 PIU40P18 POFPGA0ETH0RX0D3
FPGA_ETH_RX_D3 12
N15 NLFPGA0ETH0RX0D2
FPGA_ETH_RX_D2
IO_L50p_1_M1UDQSp PIU40N15 POFPGA0ETH0RX0D2
FPGA_ETH_RX_D2 12
N16 NLFPGA0ETH0RX0D1
FPGA_ETH_RX_D1
IO_L50n_1_M1UDQSn PIU40N16 POFPGA0ETH0RX0D1
FPGA_ETH_RX_D1 12
T17 NLFPGA0ETH0RX0D0
FPGA_ETH_RX_D0
IO_L51p_1_M1DQ12 PIU40T17 POFPGA0ETH0RX0D0
FPGA_ETH_RX_D0 12
T18 NLFPGA0ETH0RESET#
FPGA_ETH_RESET#
IO_L51n_1_M1DQ13 PIU40T18
U17
POFPGA0ETH0RESET#
FPGA_ETH_RESET# 12
IO_L52p_1_M1DQ14 PIU40U17
U18
IO_L52n_1_M1DQ15 PIU40U18
M14
IO_L53p_1 PIU40M14
N14
IO_L53n_1_VREF PIU40N14
L14
IO_L61p_1 PIU40L14
M13
IO_L61n_1 PIU40M13
P15
IO_L74p_1_AWAKE PIU40P15
P16
IO_L74n_1_DOUT_BUSY PIU40P16

XC6SLX9-2CSG324C

X's are a "No ERC" directive to the Design Rule Checker to ignore rule violations.
D D

Avnet Engineering Services

Title:
Sheet 5 - FPGA Bank 1
Size: Document Number: Rev:
S6-LX9-SCH-C C
B
Date: 8/2/2012 Sheet 5 of 10

1 2 3 4 5 6
 1 2 3 4 5 6

POFPGA0CCLK
FPGA_CCLK
POFPGA0MOSI0MISO0
FPGA_MOSI_MISO0
POFPGA0D00DIN0MISO0MISO1
FPGA_D0_DIN_MISO_MISO1
POFPGA0SPI0CS#
FPGA_SPI_CS#

Allow for trace cut SPI Flash ROM Signal / Pin Equivalences
Place serial termination Mode1=0, Mode0=1 +3.3V C = Clock = Input
A resistor close to the FPGA +3.3V DQ0 = Serial Data In = Input A
. PIR20 1 PIR1701 PIR1501 DQ1 = Serial Data Out = Output
COU4C
U4C COR20
R20 COR17
R17 COR15
R15 S_N = CS = Input
COR22
R22 4K87 0402 100K 0402
BANK 2 PIR2201 PIR2202
FPGA_CCLK GND 100K 0402
R15 NLCCLK
CCLK
IO_L01p_2_CCLK PIU40R15 22R 0402
IO_L01n_2_M0_CMPMISO
T15
PIU40T15
FPGA_MODE0 PIR20 2 PIR1702 PIR1502 COU2
U2
+3.3V
U16 NLFPGA0CCLK
FPGA_CCLK 6 8
IO_L02p_2_CMPCLK PIU40U16 PIU206 C VCC PIU208

IO_L02n_2_CMPMOSI
V16
PIU40V16
NLFPGA0MOSI0MISO0
FPGA_MOSI_MISO0 5
PIU205 DQ0
PIC2902 PIC3401
R13 NLFPGA0D00DIN0MISO0MISO1
FPGA_D0_DIN_MISO_MISO1 FPGA_D0_DIN_MISO_MISO1 2 COC29
C29 COC34
C34
IO_L03p_2_D0_DIN_MISO_MISO1 PIU40R13 PIU202 DQ1
IO_L03n_2_MOSI_CSI_B_MISO0
T13
PIU40T13
FPGA_MOSI_MISO0 PIC2901 0.22uF 6.3V 0201 PIC3402 4.7uF 6.3V 0402
U15 NLFPGA0SPI0CS#
FPGA_SPI_CS# 1
NC PIU40U15 PIU201 S
V15
NC PIU40V15
NLFPGA0D20MISO3
T14 FPGA_D1_MISO2 FPGA_D2_MISO3 7 4
IO_L12p_2_D1_MISO2 PIU40T14
NLFPGA0D10MISO2
PIU207 Hold/DQ3 GND PIU204
V14 FPGA_D2_MISO3 +3.3V FPGA_D1_MISO2 3
IO_L12n_2_D2_MISO3 PIU40V14 PIU203 W/VPP/DQ2
N12 FPGA_MODE1
IO_L13p_2_M1 PIU40N12 COR18
R18 4K87 0402DNP N25Q128A13BSE40F
P12 Use Internal Pull Up Resistor If
IO_L13n_2_D10 PIU40P12 PIR1801 PIR1802
U13 Resistor Is Not Installed. GND
IO_L14p_2_D11 PIU40U13
V13 +1.8V COX1
X1 COR19
R19 4K87 0402DNP
IO_L14n_2_D12 PIU40V13
M11 1 2 PIR1902 PIR1901
NC PIU40M11 COR42 4K87 0402
R42 PIX101 PIX102
N11
NC PIU40N11 PIR4201 PIR4202
R11 27MHz 12pF 50 Ohm
IO_L16p_2 PIU40R11 COR43 4K87 0402
R43
T11 +1.8V COU1 Do Not place power or ground
IO_L16n_2_VREF PIU40T11 PIR4302 PIR4301 U1
T12 1 14 planes under device crystal to
NC PIU40T12 PIU101 Xin/CLK Xout PIU1014 To Banks 0, 1
NC
V12
PIU40V12
PIC2501 PIC2602 2
PIU102 S0 S1/SDA
13
PIU1013
reduce stray capacitance. NLCLOCK0Y2
CLOCK_Y2 POCLOCK0Y2
CLOCK_Y2 5
N10 COC25
C25 COC26
C26 3 12 NLCLOCK0Y3
CLOCK_Y3
NC PIU40N10 PIU103 Vdd S2/SCL PIU1012 COR13
R13 POCLOCK0Y3
CLOCK_Y3 4
B NC
P11
PIU40P11
PIC2502 4.7uF 6.3V 0402 PIC2601 0.22uF 6.3V 0201 4
PIU104 Vctr Y1
11
PIU1011 PIR1301 PIR1302 B
M10 +3.3V 5 10 22R 0402
NC PIU40M10 PIU105 GND GND PIU1010
COD14
N9 6 9 D14
NC PIU40N9
U11 GND PIC2701 PIC2802 PIU106 Vddout
7
Y2 PIU109
8
COR14
R14 +5V_USB_B +3V3_USB_B +3V3_USB_B +5V_USB_B ZEN056V130A24LS
IO_L23p_2 PIU40U11
COC27
C27 COC28
C28
PIU107 Vddout Y3 PIU108 PIR1401 PIR1402
V11 22R 0402 3 1
IO_L23n_2 PIU40V11 cdce913 PID1403 Vout Vin PID1401
IO_L29p_2_GCLK3
R10
PIU40R10
PIC2702 4.7uF 6.3V 0402 PIC2801 0.22uF 6.3V 0201 COR12
PIC9201 PIC6302 PIR3201 PIC6402

Gnd
T10 R12 COC92
C92 COC63
C63 COR32
R32 COC64
C64
IO_L29n_2_GCLK2
Bank 2

PIU40T10 PIR1201 PIR1202

U10 GND GND 22R 0402 4.7uF 6.3V 0402PIC9202 PIC6301 0.22uF 6.3V 0201 4K87 0402 PIC60.22uF
401 6.3V 0201 EARTH_U
IO_L30p_2_GCLK1_D13 PIU40U10
3.3V

IO_L30n_2_GCLK0_USERCCLK
V10
PIU40V10
GND NLUSER0CLOCK
USER_CLOCK
PID1402

2
IO_L31p_2_GCLK31_D14
R8
PIU40R8
NLBACKUP0CLOCK
BACKUP_CLOCK PIR3202 COJ3
J3

6
IO_L31n_2_GCLK30_D15
T8
PIU40T8
Place 22 ohm series termination PIU807 PIU806 S1
PIJ30S1 S1
IO_L32p_2_GCLK29
T9 PIR2302 resistors close to clock source. S2
PIJ30S2 S2

VDD
REGIN
PIU40T9
V9 COR23
R23 COU8
U8 S3
IO_L32n_2_GCLK28 PIU40V9
22R 0402 Route USB D+/- as 90 ohm PIJ30S3 S3
M8 CP2102
NC PIU40M8 differential pairs, 45 ohm to GND
N8 DNP +5V_USB_B 1
NC PIU40N8 PIJ301 USB5V0
IO_L41p_2
U8
PIU40U8
+3.3V PIR2301 X4 COX4 +3.3V 8
VBUS PIU808
NLUSBB0N
USBB_N 2
PIJ302 D-
V8 1 8 4 NLUSBB0P
USBB_P 3
IO_L41n_2_VREF PIU40V8 PIX401 OUT NC PIX408 D+ PIU804 PIJ303 D+
IO_L43p_2
U7
PIU40U7
PIC302 2
PIX402 VCC NC
7
PIX407
5
D- PIU805
4
PIJ304 ID
IO_L43n_2
V7 COC3
C3 3
PIX403 VCC PDN
6
PID15COD15
01
D15 COD12
D12
PID1201PIR4 02 5
GND

1
PIU40V7 PIX406 PIJ305
NC
N7
PIU40N7
PIC301 0.22uF 6.3V 0201 4
PIX404 GND GND
5
PIX405
12
SUSPEND PIU8012
PESD0402-140 PESD0402-140 R44 COR44
P8 DNP 11 0R0 S4
NC PIU40P8 SUSPEND PIU8011 PIJ30S4 S4
IO_L45p_2
T6
PIU40T6
DS1088LU-66+ 28
PIU8028 DTR PID1502 PID120 S5
PIJ30S5 S5

2
IO_L45n_2
V6
PIU40V6
GND DNP 24
PIU8024 RTS RESET
9
PIU809
PIR4 01 S6
PIJ30S6 S6
IO_L46p_2
R7
PIU40R7
NLUSB0RS2320RXD
USB_RS232_RXD 26
PIU8026 SOUT
PIR10 2 USB Micro AB
T7 NLUSB0RS2320TXD
USB_RS232_TXD 25 10
C IO_L46n_2 PIU40T7 PIU8025 SIN NC PIU8010
C
N6 2 13 COR10
R10 EARTH_U
NC PIU40N6 UserReset PIU802 RI NC PIU8013
P7 1 14 300R 0402
NC PIU40P7 COSW5
SW5 PIU801 DCD NC PIU8014
IO_L48p_2_D7
R5
PIU40R5 SW_PB_SPST_4POS_SMT
27
PIU8027 DSR NC
15
PIU8015
PIR10 1 Note: USB Micro AB pin
IO_L48n_2_RDWR_B_VREF
T5
PIU40T5 Preferred Switch
23
PIU8023 CTS NC
16
PIU8016
PID602 definition corrected in RevC, added
U5 17 COD6
D6
IO_L49p_2_D3 PIU40U5 NC PIU8017
LED_Yellow R44.
V5 +3.3V +3.3V 18
IO_L49n_2_D4 PIU40V5 NC PIU8018
R3 1 2 19
IO_L62p_2_D5 PIU40R3 PISW501 PISW502 NC PIU8019
T3 Optional Switch 3 was 20
IO_L62n_2_D6 PIU40T3
T4 removed for Rev B
NC PIU8020
21 PID601 COR31 0R0
R31
IO_L63p_2 PIU40T4 NC PIU8021 PIR3101 PIR3102
V4 USER_RESET
NLUSER0RESET 3 4 22
IO_L63n_2 PIU40V4 PISW503 PISW504 NC PIU8022
IO_L64p_2_D8
N5
PIU40N5
PIC8901
IO_L64n_2_D9
P6
PIU40P6 COR21
R21
+3.3V COC89
C89 PIR40 1 EARTH_U
U3 FPGA_INIT
NLFPGA0INIT PIC8902 4.7uF 6.3V 0402 COR40
R40

GND
GND

GND
IO_L65p_2_INIT_B PIU40U3 PIR2101 PIR2102
4K87 0402
V3 FPGA_SPI_CS# 4K87 0402 DNP
IO_L65n_2_CSO_B PIU40V3
DNP
Use Internal Pull Down If
GND PIR40 2 Resistor Is Not Installed. PIU8030 PIU8029 PIU803

30
29

3
XC6SLX9-2CSG324C

GND

X's are a "No ERC" directive to the Design Rule Checker to ignore rule violations.
D D

Avnet Engineering Services

Title:
Sheet 6 - FPGA Bank 2
Size: Document Number: Rev:
S6-LX9-SCH-C C
B
Date: 8/2/2012 Sheet 6 of 10

1 2 3 4 5 6
 1 2 3 4 5 6

A A

COU4D
U4D
BANK 3
N4 N4 Reserved Internally for RZQ LPDDR_Data_Bus
IO_L01p_3 PIU40N4 VREF is not required or recommended for LPDDR. It is left NLFPGA0LPDDR0DQ0
N3 FPGA_LPDDR_DQ0
IO_L01n_3_VREF PIU40N3 disconnected. NLFPGA0LPDDR0DQ1 FPGA_LPDDR_DQ0
P4 FPGA_GPIO_LED1 FPGA_LPDDR_DQ1
IO_L02p_3 PIU40P4 RZQ defaults to N4 in MIG 3.6 NLFPGA0LPDDR0DQ2 FPGA_LPDDR_DQ1
P3 FPGA_LPDDR_DQ2
IO_L02n_3 PIU40P3 LPDDR does not support calibrated input termination thus NLFPGA0LPDDR0DQ3 FPGA_LPDDR_DQ2
L6 FPGA_GPIO_LED2 FPGA_LPDDR_DQ3
IO_L31p_3 PIU40L6 no resistor is required for RZQ, and ZIO is not required. NLFPGA0LPDDR0DQ4 FPGA_LPDDR_DQ3
M5 FPGA_LPDDR_DQ4
IO_L31n_3_VREF PIU40M5 RZQ and ZIO are left "no connect" no traces should connect NLFPGA0LPDDR0DQ5 FPGA_LPDDR_DQ4
U2 FPGA_LPDDR_DQ14 FPGA_LPDDR_DQ5
IO_L32p_3_M3DQ14 PIU40U2 to these pins. NLFPGA0LPDDR0DQ6 FPGA_LPDDR_DQ5
U1 FPGA_LPDDR_DQ15 FPGA_LPDDR_DQ6
IO_L32n_3_M3DQ15 PIU40U1
NLFPGA0LPDDR0DQ7 FPGA_LPDDR_DQ6
T2 FPGA_LPDDR_DQ12 FPGA_LPDDR_DQ7 POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ15
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ14
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ13
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ12
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ11
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ10
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ9
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ8
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ7
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ6
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ5
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ4
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ3
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ2
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ1
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ0
POFPGA0LPDDR0DATA
IO_L33p_3_M3DQ12 PIU40T2
NLFPGA0LPDDR0DQ8 FPGA_LPDDR_DQ7 FPGA_LPDDR_DATA 9
T1 FPGA_LPDDR_DQ13 FPGA_LPDDR_DQ8
IO_L33n_3_M3DQ13 PIU40T1
NLFPGA0LPDDR0DQ9 FPGA_LPDDR_DQ8
P2 FPGA_LPDDR_UDQS FPGA_LPDDR_DQ9
IO_L34p_3_M3UDQSp PIU40P2 When using the MCB with a Low Power DDR device such NLFPGA0LPDDR0DQ10 FPGA_LPDDR_DQ9
P1 P1 Reserved Internally FPGA_LPDDR_DQ10
IO_L34n_3_M3UDQSn PIU40P1 as the MT46H32M16LFBF-5, the LDQSn and UDQSn pins NLFPGA0LPDDR0DQ11 FPGA_LPDDR_DQ10
N2 FPGA_LPDDR_DQ10 FPGA_LPDDR_DQ11
IO_L35p_3_M3DQ10 PIU40N2 cannot be configured as user IOs. NLFPGA0LPDDR0DQ12 FPGA_LPDDR_DQ11
N1 FPGA_LPDDR_DQ11 FPGA_LPDDR_DQ12
IO_L35n_3_M3DQ11 PIU40N1
NLFPGA0LPDDR0DQ13 FPGA_LPDDR_DQ12
M3 FPGA_LPDDR_DQ8 FPGA_LPDDR_DQ13
IO_L36p_3_M3DQ8 PIU40M3
NLFPGA0LPDDR0DQ14 FPGA_LPDDR_DQ13
M1 FPGA_LPDDR_DQ9 FPGA_LPDDR_DQ14
IO_L36n_3_M3DQ9 PIU40M1 All DDR Signal routing should conform to the PCB Layout NLFPGA0LPDDR0DQ15 FPGA_LPDDR_DQ14
L2 FPGA_LPDDR_DQ0 FPGA_LPDDR_DQ15
IO_L37p_3_M3DQ0 PIU40L2 Considerations section in the Spartan-6 FPGA Memory FPGA_LPDDR_DQ15
L1 FPGA_LPDDR_DQ1
IO_L37n_3_M3DQ1 PIU40L1 Controller User Guide, UG388..
B K2 FPGA_LPDDR_DQ2 B
IO_L38p_3_M3DQ2 PIU40K2
K1 FPGA_LPDDR_DQ3
IO_L38n_3_M3DQ3 PIU40K1
L4 FPGA_LPDDR_LDQS
IO_L39p_3_M3LDQSp PIU40L4 For LPDDR, only DQ bitswapping within a data group
L3 L3 Reserved Internally LPDDR_Address_Bus
IO_L39n_3_M3LDQSn (DQ0-7 or DQ8-15) is permitted.
Bank 3

PIU40L3
J3 FPGA_LPDDR_DQ6 NLFPGA0LPDDR0A0
FPGA_LPDDR_A0
1.8V

IO_L40p_3_M3DQ6 PIU40J3
NLFPGA0LPDDR0A1 FPGA_LPDDR_A0
J1 FPGA_LPDDR_DQ7 FPGA_LPDDR_A1
IO_L40n_3_M3DQ7 PIU40J1
NLFPGA0LPDDR0A2 FPGA_LPDDR_A1
H2 FPGA_LPDDR_DQ4 FPGA_LPDDR_A2
IO_L41p_3_GCLK27_M3DQ4 PIU40H2
NLFPGA0LPDDR0A3 FPGA_LPDDR_A2
H1 FPGA_LPDDR_DQ5 FPGA_LPDDR_A3
IO_L41n_3_GCLK26_M3DQ5 PIU40H1
NLFPGA0LPDDR0A4 FPGA_LPDDR_A3
K4 FPGA_LPDDR_UDM FPGA_LPDDR_A4
IO_L42p_3_GCLK25_TRDY2_M3UDM PIU40K4
NLFPGA0LPDDR0A5 FPGA_LPDDR_A4
K3 FPGA_LPDDR_LDM FPGA_LPDDR_A5
IO_L42n_3_GCLK24_M3LDM PIU40K3
NLFPGA0LPDDR0A6 FPGA_LPDDR_A5
L5 FPGA_LPDDR_RAS# FPGA_LPDDR_A6
IO_L43p_3_GCLK23_M3RASN PIU40L5
NLFPGA0LPDDR0A7 FPGA_LPDDR_A6
K5 FPGA_LPDDR_CAS# FPGA_LPDDR_A7 POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0BA1
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0BA0
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A12
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A11
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A10
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A9
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A8
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A7
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A6
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A5
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A4
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A3
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A2
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A1
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A0
POFPGA0LPDDR0ADDRESS
IO_L43n_3_GCLK22_IRDY2_M3CASN PIU40K5
NLFPGA0LPDDR0A8 FPGA_LPDDR_A7 FPGA_LPDDR_ADDRESS 9
H4 FPGA_LPDDR_A5 FPGA_LPDDR_A8
IO_L44p_3_GCLK21_M3A5 PIU40H4 FPGA_LPDDR_A8
H3 FPGA_LPDDR_A6 NLFPGA0LPDDR0A9
FPGA_LPDDR_A9
IO_L44n_3_GCLK20_M3A6 PIU40H3 FPGA_LPDDR_A9
L7 FPGA_LPDDR_A3 NLFPGA0LPDDR0A10
FPGA_LPDDR_A10
IO_L45p_3_M3A3 PIU40L7 FPGA_LPDDR_A10
K6 NLFPGA0LPDDR0A11
FPGA_LPDDR_A11
IO_L45n_3_M3ODT PIU40K6 FPGA_LPDDR_A11
G3 FPGA_LPDDR_CK_P NLFPGA0LPDDR0A12
FPGA_LPDDR_A12
IO_L46p_3_M3CLKp PIU40G3 FPGA_LPDDR_A12
G1 FPGA_LPDDR_CK_N NLFPGA0LPDDR0BA0
FPGA_LPDDR_BA0
IO_L46n_3_M3CLKn PIU40G1 FPGA_LPDDR_BA0
J7 FPGA_LPDDR_A0 NLFPGA0LPDDR0BA1
FPGA_LPDDR_BA1
IO_L47p_3_M3A0 PIU40J7 FPGA_LPDDR_BA1
J6 FPGA_LPDDR_A1
IO_L47n_3_M3A1 PIU40J6
COD2
D2
F2 FPGA_LPDDR_BA0
IO_L48p_3_M3BA0 PIU40F2
F1 FPGA_LPDDR_BA1 NLFPGA0GPIO0LED1
FPGA_GPIO_LED1
IO_L48n_3_M3BA1 PIU40F1 PID202 PID201
H6 FPGA_LPDDR_A7
IO_L49p_3_M3A7 PIU40H6
H5 FPGA_LPDDR_A2 LED, Red, LTST-C190CKT, 0603
IO_L49n_3_M3A2 PIU40H5
E3 FPGA_LPDDR_WE# LPDDR_Control
C IO_L50p_3_M3WE PIU40E3
COD3
D3 C
E1 NLFPGA0LPDDR0CAS#
FPGA_LPDDR_CAS#
IO_L50n_3_M3BA2 PIU40E1 FPGA_LPDDR_CAS#
F4 FPGA_LPDDR_A10 NLFPGA0GPIO0LED2
FPGA_GPIO_LED2 NLFPGA0LPDDR0RAS#
FPGA_LPDDR_RAS#
IO_L51p_3_M3A10 PIU40F4 PID302 PID301 FPGA_LPDDR_RAS#
F3 FPGA_LPDDR_A4 NLFPGA0LPDDR0WE#
FPGA_LPDDR_WE#
IO_L51n_3_M3A4 PIU40F3 FPGA_LPDDR_WE#
D2 FPGA_LPDDR_A8 LED, Red, LTST-C190CKT, 0603 NLFPGA0LPDDR0CKE
FPGA_LPDDR_CKE
IO_L52p_3_M3A8 PIU40D2 FPGA_LPDDR_CKE
D1 FPGA_LPDDR_A9 NLFPGA0LPDDR0CK0P
FPGA_LPDDR_CK_P
IO_L52n_3_M3A9 PIU40D1
COD9
D9 FPGA_LPDDR_CK_P
H7 FPGA_LPDDR_CKE NLFPGA0LPDDR0CK0N
FPGA_LPDDR_CK_N
IO_L53p_3_M3CKE PIU40H7 FPGA_LPDDR_CK_N POFPGA0LPDDR0CONTROL0FPGA0LPDDR0WE#
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0UDQS
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0UDM
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0RAS#
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0LDQS
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0LDM
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0CKE
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0CK0P
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0CK0N
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0CAS#
POFPGA0LPDDR0CONTROL
FPGA_LPDDR_CONTROL 9
IO_L53n_3_M3A12
G6
PIU40G6
FPGA_LPDDR_A12 PID902 PID901
NLFPGA0LPDDR0UDQS
FPGA_LPDDR_UDQS
FPGA_LPDDR_UDQS
IO_L54p_3_M3RESET
E4
PIU40E4
NLFPGA0LPDDR0LDQS
FPGA_LPDDR_LDQS
FPGA_LPDDR_LDQS
IO_L54n_3_M3A11
D3
PIU40D3
FPGA_LPDDR_A11 LED, Red, LTST-C190CKT, 0603 NLFPGA0LPDDR0UDM
FPGA_LPDDR_UDM
FPGA_LPDDR_UDM
F6 FPGA_LPDDR_LDM
NLFPGA0LPDDR0LDM
IO_L55p_3_M3A13 PIU40F6
COD10
D10 FPGA_LPDDR_LDM
F5 FPGA_GPIO_LED3 FPGA_GPIO_LED3
NLFPGA0GPIO0LED3
IO_L55n_3_M3A14 PIU40F5
C2 FPGA_GPIO_LED4 FPGA_GPIO_LED4
NLFPGA0GPIO0LED4
IO_L83p_3 PIU40C2 PID1002 PID1001
C1
IO_L83n_3_VREF PIU40C1
LED, Red, LTST-C190CKT, 0603

XC6SLX9-2CSG324C

GND

X's are a "No ERC" directive to the Design Rule Checker to ignore rule violations.
D D

Avnet Engineering Services

Title:
Sheet 7 - FPGA Bank 3
Size: Document Number: Rev:
S6-LX9-SCH-C C
B
Date: 8/2/2012 Sheet 7 of 10

1 2 3 4 5 6
 1 2 3 4 5 6

Route USB D+/- as 90 ohm Place 22 ohm series termination COD11

D11
differential pairs, 45 ohm to GND resistors close to USB XCVR.
ZEN056V130A24LS +5V_USB_A
COP1
P1 1
PID1101 Vin 3
Vout PID1103
VBUS
1
PIP101 COR7
PIC6201

Gnd
2 NLUSBA0n
USBA_n R7 NLUSBA10n
USBA1_n COC62
C62
D- PIP102 PIR701 PIR702

D+
3
PIP103
NLUSBA0p
USBA_p 22R 0402 PIC6202 0.22uF 6.3V 0201
GND
4
PIP104
PID1 02

2
PID401 PID501 COR9

1
5 R9 NLUSBA10p
USBA1_p
SHD PIP105
COD4
D4 COD5
D5
PIR901 PIR902
6 22R 0402
SHD PIP106

PID402 PESD0402-140
PID502 PESD0402-140 GND Two 0.22 0201 Ceramic Caps are substituted

2
USBA RA SMT for each Xilinx recommended 0.47 0402
Ceramic Caps.

+1.2V +3.3V
A GND +3V3_USB_A A
PIC2101 COC21
C21 PIC4501 PIC5801 PIC4901 PIC5 01 PIC4201
PIC7101 PIC4702 PIC6102 COC45
C45 COC58
C58 COC49
C49 COC55
C55 COC42
C42
Floating Avcc pin 32 was connected COC71
C71 COC47
C47 COC61
C61 PIC2102 100uF 6.3V 1206 PIC4502 4.7uF 6.3V 0402 PIC5802 4.7uF 6.3V 0402 PIC4902 4.7uF 6.3V 0402 PIC5 02 100uF 6.3V 1206 PIC4202 4.7uF 6.3V 0402
to +3V3_USB_A for Rev B PIC7102 4.7uF 6.3V 0402 PIC4701 0.22uF 6.3V 0201 PIC6101 0.22uF 6.3V 0201 DNP

COU3
U3 AT90USB162-16MUR
PIU30 3 PIU30 2 PIU30 1 PIU30 PIU3029 PIU3028 PIU3027 PIU3026 PIU3025

33
32
31
30
29
28
27
26
25
Footprint was fixed for Rev B
/ ATMEGA162U2 GND PIC4802 PIC50 2 PIC3701 PIC4301 PIC3502 PIC3602 PIC4 02 PIC3902
1 COC48
C48 COC50
C50 COC37
C37 COC43
C43 COC35
C35 COC36
C36 COC44
C44 COC39
C39
PIU301 XTAL1

PAD
AVCC
UVCC

D+/SCK
UGND
UCAP
D-/SDATA

(PCINT10)PC4
(PCINT9/OC.1B)PC5
COX2
X2 2
PIU302 XTAL2(PC0)
PIC4801 0.22uF 6.3V 0201 PIC50 1 0.22uF 6.3V 0201 PIC3702 0.22uF 6.3V 0201 PIC4302 0.22uF 6.3V 0201 PIC3501 0.22uF 6.3V 0201 PIC3601 0.22uF 6.3V 0201 PIC4 01 0.22uF 6.3V 0201 PIC3901 0.22uF 6.3V 0201
1 4 3
PIX201 NC PIX204 PIU303 GND
2 3 4
PIX202 NC PIX203 PIU304 VCC
5 GND GND
PIU305 PC2(PCINT11) Diode is used to prevent any
PIC1 01 COC11
C11 8MHz PIC10 1 COC10
C10 6
PIU306 PD0(OC.0B/INT0) current backflow from a Parallel IV
7 +3.3V
PIU307 PD1(AIN0/INT1) cable connection.
PIC1 02 15pF 25V 0402 PIC10 2 15pF 25V 0402 8
PIU308 PD2(RXD1/AIN1/INT2) COJ6 Xilinx Parallel IV Connector
J6
PIC2301 PIC70 1
PD7(CTS/HWB/T0/INT7)

PB2(PDI/MOSI/PCINT2)

COC23 COC70
GND GND GND 24
COTP1
TP1
PIJ6013 PIJ601 PIJ609 PIJ607 PIJ605 PIJ603 PIJ601 +3.3V
PIC2302
C23
100uF 6.3V 1206 PIC70 2
C70
4.7uF 6.3V 0402

13
11
PD5(XCK/PCINT12)

PB1(SCLK/PCINT1)

(PC1/dW)Reset PIU3024
PITP101

9
7
5
3
1
23 GND
PID801 PIR308 PIR307 PIR306 PIR305
PD3(TXD1/INT3)

(OC.1A/PCINT8)PC6 PIU3023
PB0(SS/PCINT0)

22 TEST PAD
PD6(RTS/INT6)

(INT4/ICP1/CLK0)PC7

GND
GND
GND
GND
GND
GND
GND
PIU3022

8
7
6
5
21 COD8
D8 COU4E
U4E
(PCINT7/OC.0A/OC.1C)PB7 PIU3021

PID803 PIC6702 PIC3802 PIC40 2 PIC80 1

CORP3
PIU40G7 PIU40H9 PIU40H1 PIU40J8 PIU40J1 PIU40K9 PIU40K1 PIU40L8 PIU40L1 PIU40M7 PIU40M12 PIU40B1 PIU40B17 PIU40E5 PIU40E9 PIU40E1 PIU40G1 PIU40J12 PIU40K7 PIU40M9 PIU40P5 PIU40P1 PIU40P1
PD4(INT5)

20 BAS16 RP3 XC6SLX9-2CSG324C

M12
H11

K11

G10
(PCINT6)PB6

B17
PIU3020

E14
L10

P10
P14
J10

M7

J12

M9
VREF
COC67
C67 COC38
C38 COC40
C40 COC80
C80

G7
H9

K9

K7
B1
19 4K7

E5
E9
L8

P5
J8
TDO

TMS
TCK
(PCINT5)PB5 PIU3019

TDI
PIC6701 PIC3801 PIC40 1 PIC80 2

NC
NC
18 0.22uF 6.3V 0201 0.22uF 6.3V 0201 0.22uF 6.3V 0201 0.22uF 6.3V 0201
(T1PCINT4)PB4 PIU3018
COR24 17 +3.3V
R24 0R0 0402 (PDO/MISO/PCINT3)PB3

VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
PIU3017
POFPGA0D00DIN0MISO0MISO1
FPGA_D0_DIN_MISO_MISO1 PIR2401 PIR2402
PIJ6014 PIJ6012 PIJ601 PIJ608 PIJ60 PIJ604 PIJ602 PIR301 PIR302 PIR30 PIR304 VCCO_0
B5
PIU40B5

14
12
10
8
6
4
2

1
2
3
4
COR25
R25 0R0 0402 PIU309 PIU301 PIU301 PIU3012 PIU3013 PIU3014 PIU3015 PIU3016 VCCO_0
B10
PIU40B10
GND
9
10
11
12
13
14
15
16

B15
POFPGA0MOSI0MISO0
FPGA_MOSI_MISO0 PIR2501 PIR2502 VCCO_0 PIU40B15
D7
COR26
R26 0R0 0402 VCCO_0 PIU40D7
D13 +3.3V
POFPGA0CCLK
FPGA_CCLK PIR2601 PIR2602 COR38
R38 0R0 0402 VCCO_0 PIU40D13
E10
COR28
R28 0R0 0402 PIR3801 PIR3802 VCCO_0 PIU40E10
POFPGA0SPI0CS#
FPGA_SPI_CS# PIR2801 PIR2802 COR39
R39 0R0 0402
NLFPGA0TCK
FPGA_TCK A17
PIU40A17 TCK
PIC8201 PIC6801
PIR3901 PIR3902
NLFPGA0TMS
FPGA_TMS B18
PIU40B18 TMS
+3.3V COC82
C82 COC68
C68
COJ2
J2 COR8
R8 0R0 0402
NLFPGA0TDO
FPGA_TDO D16
PIU40D16 TDO VCCO_1
E17
PIU40E17
PIC8202 100uF 6.3V 1206 PIC6802 4.7uF 6.3V 0402
NLFPGA0TDI
FPGA_TDI D15
PIU40D15 TDI
G15
PIR801 PIR802 VCCO_1 PIU40G15
1 J14
PIJ201 COR37
R37 0R0 0402 VCCO_1 PIU40J14
B 2 J17 B
PIJ202 PIR3701 PIR3702 VCCO_1 PIU40J17
VCCO_1
M15
PIU40M15
PIC7902 PIC7 02 PIC5702 PIC7801
R17 COC79
C79 COC77
C77 COC57
C57 COC78
C78
HEADER 2/SM VCCO_1 PIU40R17
GND PIR30 2 PIC7901 0.22uF 6.3V 0201 PIC7 01 0.22uF 6.3V 0201 PIC5701 0.22uF 6.3V 0201 PI0.22uF
C7802 6.3V 0201
Boot Program En Not COR30
R30 +3.3V +3.3V
0R0 0402 NLFPGA0PROG
FPGA_PROG V2 P9
PIU40V2 PROGRAM_B_2 VCCO_2 PIU40P9
FRAGILE, USE PIR4101 COR35 0R0 0402
R35 VCCO_2
R6
PIU40R6
GND
SHUNTS ONLY PIR30 1 COR41
R41
PIR3501 PIR3502
SUSPEND R16
PIU40R16 SUSPEND VCCO_2
R12
PIU40R12
4K87 0402 U4
Suspend not used VCCO_2 PIU40U4
Program Start
NLFPGA0DONE
FPGA_DONE V17
PIU40V17 DONE_2 VCCO_2
U9
PIU40U9
+3.3V
PIR4102 VCCO_2
U14
PIU40U14
COSW4
SW4
PIC9301 PIC601 PIC5601
COC93
C93 Reserved +1.8V COC6
C6 COC56
C56
SW_PB_SPST_4POS_SMT
Preferred Switch PIC9302 4.7uF 6.3V 0402 P13
PIU40P13 CMPCS_B_2 VCCO_3
E2
PIU40E2
PIC602 100uF 6.3V 1206 PIC5602 4.7uF 6.3V 0402
DNP G4
VCCO_3 PIU40G4
J2
VCCO_3 PIU40J2
1 2 GND GND +3.3V J5
PISW401 PISW402 VCCO_3 PIU40J5
VCCO_3
M4
PIU40M4
PIC6902 PIC5102 PIC8102 PIC5901
PIR201 VCCO_3
R2
PIU40R2
COC69
C69 COC51
C51 COC81
C81 COC59
C59
3 4 COR2
R2 PIC6901 0.22uF 6.3V 0201 PIC5101 0.22uF 6.3V 0201 PIC8101 0.22uF 6.3V 0201 PIC5902 0.22uF 6.3V 0201

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PISW403 PISW404
300R 0402

PIR202
GND GND
PIU40A1 PIU40A18 PIU40B7 PIU40B13 PIU40C3 PIU40C16 PIU40D5 PIU40D1 PIU40E15 PIU40G2 PIU40G5 PIU40G12 PIU40G17 PIU40H8 PIU40H1 PIU40J PIU40J9 PIU40J1 PIU40J15 PIU40K8 PIU40K1 PIU40L9 PIU40L1 PIU40M2 PIU40M6 PIU40M17 PIU40N13 PIU40R1 PIU40R PIU40R9 PIU40R1 PIU40R18 PIU40T16 PIU406 PIU4012 PIU40V1 PIU40V18 GND

A1

B7

C3

D5

E15
G2
G5

H8

J4
J9
J11
J15
K8

M2
M6

R1
R4
R9

T16
U6

V1
A18

B13

C16

D10

G12
G17

H10

K10
L9
L11

M17
N13

R14
R18

U12

V18
PID102
2
Optional Switch 2 was
removed for Rev B COD1
D1 +1.8V
PID10 LTST-C193TBKT-5A
1

PIC9601 PIC101
COC96
C96 COC1
C1
GND PIC9602 100uF 6.3V 1206 PIC102 4.7uF 6.3V 0402
GND

PIC5202 PIC4602 PIC4102 PIC60 1

C52
COC52 C46
COC46 C41
COC41 C60
COC60
PIC5201 0.22uF 6.3V 0201 PIC4601 0.22uF 6.3V 0201 PIC4101 0.22uF 6.3V 0201 PIC60 2 0.22uF 6.3V 0201

C GND C

+5V_USB_A D13
COD13 +5VUSB Route in a similar scheme to the example in the data sheet.
2 1
PID1302 PID1301
PIC7201 PIC7301
DFLS130L-7 C72
COC72 C73
COC73 +3.3V
PIC7202 4.7uF 6.3V 0402 PIC7302 4.7uF 6.3V 0402
+5V_USB_B D16
COD16 DNP PIC8601 PIC9101
2 1 C86
COC86 C91
COC91
PID1602 PID1601 U7
COU7 L2
COL2
GND B4
PIU70B4 VCC 2.2UH 600MA 0805 PIC8602 4.7uF 6.3V 0402 PIC9102 4.7uF 6.3V 0402
DFLS130L-7 C1 D2 DNP
PIU70C1 VIN1 L1 PIU70D2 PIL201 PIL202
C2
FB1 PIU70C2
PIC7601 PIC7401 PGND1
D1
PIU70D1 L1
COL1
GND
C76
COC76 C74
COC74 +1.8V
2.2UH 600MA 0805
PIC7602 4.7uF 6.3V 0402 PIC7402 4.7uF 6.3V 0402 C4
PIU70C4 VIN2
D3
L2 PIU70D3 PIL101 PIL102
DNP C3
FB2 PIU70C3 PIC8501 PIC8301
D4 C85
COC85 C83
COC83
PGND2 PIU70D4
+3.3V GND PIC8502 4.7uF 6.3V 0402 PIC8302 4.7uF 6.3V 0402
A2 A1 DNP +5VUSB
PIU70A2 VINLDO1 VLDO1 PIU70A1
PIC5401 +1.8V +2.8V
C54
COC54 A3
PIU70A3 VINLDO2 VLDO2 PIU70A4
A4 GND PIR1 01
PIC5402 4.7uF 6.3V 0402 PIC5301 R33
COR33 0R0 PIC6501 R11
COR11
DNP C53
COC53 B2 B1 C65
COC65 681R 0402
PIR3302 PIR3301 PIU70B2 PWM ISINK PIU70B1
PIC5302 4.7uF 6.3V 0402 DNP +1.2V PIC6502 4.7uF 6.3V 0402
GND
R34
COR34 0R0
B3
PIU70B3 MODE
DNP PIR1 02
PIR3402 PIR3401 TPS65708 PIC6 01 PID702
GND GND C66
COC66 GND D7
COD7
+1.2V PIC6 02 4.7uF 6.3V 0402 LED_Green

PIC7501 GND POWER_GOOD_LED

NLPOWER0GOOD0LED PID701
C75
COC75
PIC7502 4.7uF 6.3V 0402 PIC2401
C24
COC24
PIC2402 4.7uF 6.3V 0402
+5VUSB
GND
D Allow for trace cut GND D

X's are a "No ERC" directive to the Design Rule Checker to ignore rule violations.

Avnet Engineering Services

Title:
Sheet 8 - Power / USB JTAG
Size: Document Number: Rev:

C S6-LX9-SCH-C C
Date: 8/2/2012 Sheet 8 of 10

1 2 3 4 5 6
 1 2 3 4 5 6

A A

LPDDR_Address_Bus
NLFPGA0LPDDR0A0
FPGA_LPDDR_A0
FPGA_LPDDR_A0 NLFPGA0LPDDR0A1
FPGA_LPDDR_A1
FPGA_LPDDR_A1 NLFPGA0LPDDR0A2
FPGA_LPDDR_A2
FPGA_LPDDR_A2 NLFPGA0LPDDR0A3
FPGA_LPDDR_A3
FPGA_LPDDR_A3 NLFPGA0LPDDR0A4 All DDR Signal routing should conform to the PCB Layout
FPGA_LPDDR_A4
FPGA_LPDDR_A4 NLFPGA0LPDDR0A5 Considerations section in the Spartan-6 FPGA Memory
FPGA_LPDDR_A5
FPGA_LPDDR_A5 NLFPGA0LPDDR0A6 Controller User Guide, UG388..
FPGA_LPDDR_A6
FPGA_LPDDR_A6 NLFPGA0LPDDR0A7
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0BA1
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0BA0
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A12
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A11
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A10
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A9
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A8
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A7
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A6
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A5
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A4
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A3
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A2
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A1
POFPGA0LPDDR0ADDRESS0FPGA0LPDDR0A0
POFPGA0LPDDR0ADDRESS FPGA_LPDDR_A7
7 FPGA_LPDDR_ADDRESS FPGA_LPDDR_A7 NLFPGA0LPDDR0A8
FPGA_LPDDR_A8
FPGA_LPDDR_A8 NLFPGA0LPDDR0A9
FPGA_LPDDR_A9
FPGA_LPDDR_A9 NLFPGA0LPDDR0A10
FPGA_LPDDR_A10
FPGA_LPDDR_A10 NLFPGA0LPDDR0A11
FPGA_LPDDR_A11
FPGA_LPDDR_A11 NLFPGA0LPDDR0A12
FPGA_LPDDR_A12 +1.8V +1.8V
FPGA_LPDDR_A12 NLFPGA0LPDDR0BA0
FPGA_LPDDR_BA0
FPGA_LPDDR_BA0
PIC2 01 PIC201 PIC402 PIC502 PIC702 PIC802
FPGA_LPDDR_BA1
NLFPGA0LPDDR0BA1
FPGA_LPDDR_BA1 COU5
U5
PIU50A9 PIU50F9 PIU50K9 PIU50A7 PIU50B1 PIU50C9 PIU50D1 PIU50E9 COC22
C22 COC2
C2 COC4
C4 COC5
C5 COC7
C7 COC8
C8

A9

K9

A7

D1
B1
C9
MT46H32M16LFBF-5

E9
F9
PIC2 02 100uF 6.3V 1206 PIC202 4.7uF 6.3V 0402 PIC401 0.22uF 6.3V 0201 PIC501 0.22uF 6.3V 0201 PIC701 0.22uF 6.3V 0201 PIC801 0.22uF 6.3V 0201

VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
FPGA_LPDDR_A0 J8 A8 FPGA_LPDDR_DQ1
PIU50J8 A0 DQ0 PIU50A8
LPDDR_Control FPGA_LPDDR_A1 J9 B7 FPGA_LPDDR_DQ0 GND
NLFPGA0LPDDR0CAS#
PIU50J9 A1 DQ1 PIU50B7
B FPGA_LPDDR_CAS# FPGA_LPDDR_A2 K7 B8 FPGA_LPDDR_DQ3 B
FPGA_LPDDR_CAS# NLFPGA0LPDDR0RAS#
PIU50K7 A2 DQ2 PIU50B8
FPGA_LPDDR_RAS# FPGA_LPDDR_A3 K8 C7 FPGA_LPDDR_DQ5
FPGA_LPDDR_RAS# NLFPGA0LPDDR0WE#
PIU50K8 A3 DQ3 PIU50C7
FPGA_LPDDR_WE# FPGA_LPDDR_A4 K2 C8 FPGA_LPDDR_DQ2
FPGA_LPDDR_WE# NLFPGA0LPDDR0CKE
PIU50K2 A4 DQ4 PIU50C8
FPGA_LPDDR_CKE FPGA_LPDDR_A5 K3 D7 FPGA_LPDDR_DQ4
FPGA_LPDDR_CKE NLFPGA0LPDDR0CK0P
PIU50K3 A5 DQ5 PIU50D7
FPGA_LPDDR_CK_P FPGA_LPDDR_A6 J1 D8 FPGA_LPDDR_DQ6 LPDDR_Data_Bus
FPGA_LPDDR_CK_P NLFPGA0LPDDR0CK0N
PIU50J1 A6 DQ6 PIU50D8
NLFPGA0LPDDR0DQ0
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0WE#
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0UDQS
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0UDM
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0RAS#
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0LDQS
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0LDM
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0CKE
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0CK0P
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0CK0N
POFPGA0LPDDR0CONTROL0FPGA0LPDDR0CAS#
POFPGA0LPDDR0CONTROL FPGA_LPDDR_CK_N FPGA_LPDDR_A7 J2 E7 FPGA_LPDDR_DQ7 FPGA_LPDDR_DQ0
7 FPGA_LPDDR_CONTROL FPGA_LPDDR_CK_N NLFPGA0LPDDR0UDQS
PIU50J2 A7 DQ7 PIU50E7
NLFPGA0LPDDR0DQ1 FPGA_LPDDR_DQ0
FPGA_LPDDR_UDQS FPGA_LPDDR_A8 J3 E3 FPGA_LPDDR_DQ9 FPGA_LPDDR_DQ1
FPGA_LPDDR_UDQS NLFPGA0LPDDR0LDQS
PIU50J3 A8 DQ8 PIU50E3
NLFPGA0LPDDR0DQ2 FPGA_LPDDR_DQ1
FPGA_LPDDR_LDQS FPGA_LPDDR_A9 H1 D2 FPGA_LPDDR_DQ8 FPGA_LPDDR_DQ2
FPGA_LPDDR_LDQS NLFPGA0LPDDR0UDM
PIU50H1 A9 DQ9 PIU50D2
NLFPGA0LPDDR0DQ3 FPGA_LPDDR_DQ2
FPGA_LPDDR_UDM FPGA_LPDDR_A10 J7 D3 FPGA_LPDDR_DQ11 FPGA_LPDDR_DQ3
FPGA_LPDDR_UDM NLFPGA0LPDDR0LDM
PIU50J7 A10/AP DQ10 PIU50D3
NLFPGA0LPDDR0DQ4 FPGA_LPDDR_DQ3
FPGA_LPDDR_LDM FPGA_LPDDR_A11 H2 C2 FPGA_LPDDR_DQ10 FPGA_LPDDR_DQ4
FPGA_LPDDR_LDM PIU50H2 A11 DQ11 PIU50C2
NLFPGA0LPDDR0DQ5 FPGA_LPDDR_DQ4
FPGA_LPDDR_A12 H3 C3 FPGA_LPDDR_DQ12 FPGA_LPDDR_DQ5
PIU50H3 A12 DQ12 PIU50C3
NLFPGA0LPDDR0DQ6 FPGA_LPDDR_DQ5
B2 FPGA_LPDDR_DQ13 FPGA_LPDDR_DQ6
DQ13 PIU50B2
NLFPGA0LPDDR0DQ7 FPGA_LPDDR_DQ6
FPGA_LPDDR_BA0 H8 B3 FPGA_LPDDR_DQ14 FPGA_LPDDR_DQ7 POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ15
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ14
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ13
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ12
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ11
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ10
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ9
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ8
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ7
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ6
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ5
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ4
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ3
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ2
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ1
POFPGA0LPDDR0DATA0FPGA0LPDDR0DQ0
POFPGA0LPDDR0DATA
PIU50H8 BA0 DQ14 PIU50B3 FPGA_LPDDR_DQ7 FPGA_LPDDR_DATA 7
FPGA_LPDDR_BA1 H9
PIU50H9 BA1
A2 FPGA_LPDDR_DQ15 NLFPGA0LPDDR0DQ8
FPGA_LPDDR_DQ8
DQ15 PIU50A2 FPGA_LPDDR_DQ8
NLFPGA0LPDDR0DQ9
FPGA_LPDDR_DQ9
FPGA_LPDDR_DQ9
NLFPGA0LPDDR0CS#
FPGA_LPDDR_CS# H7 E2 FPGA_LPDDR_UDQS NLFPGA0LPDDR0DQ10
FPGA_LPDDR_DQ10
PIU50H7 CS# UDQS PIU50E2 FPGA_LPDDR_DQ10
FPGA_LPDDR_CAS# G8
PIU50G8 CAS#
E8 FPGA_LPDDR_LDQS NLFPGA0LPDDR0DQ11
FPGA_LPDDR_DQ11
LDQS PIU50E8 FPGA_LPDDR_DQ11
FPGA_LPDDR_RAS# G9
PIU50G9 RAS#
NLFPGA0LPDDR0DQ12
FPGA_LPDDR_DQ12
FPGA_LPDDR_DQ12
FPGA_LPDDR_WE# G7
PIU50G7 WE#
F2 FPGA_LPDDR_UDM NLFPGA0LPDDR0DQ13
FPGA_LPDDR_DQ13
UDM PIU50F2 FPGA_LPDDR_DQ13
F8 FPGA_LPDDR_LDM NLFPGA0LPDDR0DQ14
FPGA_LPDDR_DQ14
LDM PIU50F8 FPGA_LPDDR_DQ14
FPGA_LPDDR_CKE G1 NLFPGA0LPDDR0DQ15
FPGA_LPDDR_DQ15
PIU50G1 CKE FPGA_LPDDR_DQ15
FPGA_LPDDR_CK_P G2
PIU50G2 CK
D9
TEST PIU50D9
FPGA_LPDDR_CK_N G3
PIU50G3 CK#

VSSQ
VSSQ
VSSQ
VSSQ
F7

VSS
VSS
VSS
COR3
R3 n/c PIU50F7
PIR501 PIR101 PIR301 PIR302
F3PIU50F3
n/c
GND
C COR5
R5 COR1
R1 C
100R 0402
100R 0402 4K87 0402
PIU50A1 PIU50F1 PIU50K1 PIU50A3 PIU50B9 PIU50C1 PIU50E1

A1
F1
K1

A3
B9
C1
E1
Place clock termination resistor as close as possible
PIR502 PIR102 to MT46H32M16LFBF-5 LPDDR device.

GND

GND

X's are a "No ERC" directive to the Design Rule Checker to ignore rule violations.
D D

Avnet Engineering Services

Title:
Sheet 9 - LPDDR Memory
Size: Document Number: Rev:
S6-LX9-SCH-C C
B
Date: 8/2/2012 Sheet 9 of 10

1 2 3 4 5 6
 1 2 3 4 5 6

+3.3V
A A
COFB1
FB1

COC12
C12 PIPIFB101 PIFB102
C1202 75R0, 300mA, 0603 PIC1702 COC17
C17

4.7uF 6.3V 0402 PIC1201 PIC1701 0.22uF 6.3V 0201

Place power decoupling

GND
capacitors close to the
DP83848J. Place Resistors and capacitors close to
+3.3V
DP83848J.
PIC1C19
9COC19
02 PIC1C16
6COC16
02 PIC2C20
0COC20
2
PIC14.7uF
901 6.3V 0402 PIC10.22uF
601 6.3V 0201 PIC20.22uF
01 6.3V 0201 +3.3V +3.3V

PIC30 2 PIC3102
GND
COC30
C30
PIR208 PIR207 PIR206 PIR205 COC31
C31

8
7
6
5
+3.3V 0.22uF 6.3V 0201 PIC30 1 PIC3101 0.22uF 6.3V 0201
CORP2
RP2
PIR601 49R9 +3.3V +3.3V
COR6
R6
1K50 0402
PIU601 PIU602 PIU6018 COU6
U6
DP83848J
GND GND
PIR2701

26

10

18
1

8
9
PIU608 PIU609 PIU6010 COR27
B
PIR201 PIR20 PIR203 PIR204 R27 B

1
2
3
4
PIR602 Route TD+/- and RD+/- as 100-120
300R 0402

RSVD1
RSVD2
RSVD3

AVDD33
IOVDD33
IOVDD33
NLFPGA0ETH0MDC
FPGA_ETH_MDC 25MHz Max 25 COJ1
J1
POFPGA0ETH0MDC
5 FPGA_ETH_MDC PIU6025 MDC ohm differential pairs.
POFPGA0ETH0MDIO NLFPGA0ETH0MDIO
FPGA_ETH_MDIO 24 11 12 PIR2702
5 FPGA_ETH_MDIO PIU6024 MDIO PIJ1011 D4 D3 PIJ1012

NLFPGA0ETH0RX0CLK
FPGA_ETH_RX_CLK 31 15 NLETH0TD0P
ETH_TD_P 1
POFPGA0ETH0RX0CLK
5 FPGA_ETH_RX_CLK PIU6031 Rx_CLK TD+ PIU6015 PIJ101 TD+ RJ-1 TXP
NLFPGA0ETH0RX0D0
FPGA_ETH_RX_D0 36 2
POFPGA0ETH0RX0D0
5 FPGA_ETH_RX_D0 PIU6036 RXD0/PHYAD1 PIJ102 TD- RJ-2 TXN
NLFPGA0ETH0RX0D1
FPGA_ETH_RX_D1 37 14 NLETH0TD0N
ETH_TD_N 3
POFPGA0ETH0RX0D1
5 FPGA_ETH_RX_D1 PIU6037 RXD1/PHYAD2 TD- PIU6014 PIJ103 RD+ RJ-3 RXP
NLFPGA0ETH0RX0D2
POFPGA0ETH0RX0D2 FPGA_ETH_RX_D2
5 FPGA_ETH_RX_D2
38
PIU6038 RXD2/PHYAD3
4
PIJ104 TCT RJ-4
+3.3V
39 5
PIU6039 RXD3/PHYAD4 PIJ105 RCT RJ-5
34
PIU6034 RX_ER/MDIX_EN RD-
11
PIU6011
NLETH0RD0N
ETH_RD_N 6
PIJ106 RD- RJ-6 RXN
PIR1601
32 7 COR16
R16
NLFPGA0ETH0RX0D3
PIU6032 RX_DV/MII_MODE NLETH0RD0P
PIJ107 NC RJ-7 300R 0402
POFPGA0ETH0RX0D3 FPGA_ETH_RX_D3 12 ETH_RD_P 8
5 FPGA_ETH_RX_D3 RD+ PIU6012 PIJ108 C1 RJ-8
NLFPGA0ETH0RX0ER
FPGA_ETH_RX_ER 2
POFPGA0ETH0RX0ER
5 FPGA_ETH_RX_ER PIU602 TX_CLK
POFPGA0ETH0RX0DV
5 FPGA_ETH_RX_DV
NLFPGA0ETH0RX0DV
FPGA_ETH_RX_DV 4
PIU604 TX_D0
10
PIJ1010 D2 D1
9
PIJ109
PIR1602
NLFPGA0ETH0TX0CLK
FPGA_ETH_TX_CLK 5 NLETH0LNK0LED#
22 ETH_LNK_LED# 13 14
POFPGA0ETH0TX0CLK
5 FPGA_ETH_TX_CLK PIU605 TX_D1 LED_LNK/AN0 PIU6022 PIJ1013 GND GND PIJ1014
6 21 NLETH0SPD0LED#
ETH_SPD_LED#
PIU606 TX_D2 LED_SPEED/AN1 PIU6021
7 Mag45
PIU607 TX_D3 COR4
R4 COR29 0R0 0402
R29
3
PIU603 TX_EN PIR401 PIR402 PIR2901 PIR2902
NLFPGA0ETH0TX0D0
FPGA_ETH_TX_D0 20 4K87 0402
POFPGA0ETH0TX0D0
5 FPGA_ETH_TX_D0 RBIAS PIU6020
NLFPGA0ETH0TX0D1
FPGA_ETH_TX_D1 35 EARTH_E EARTH_E
POFPGA0ETH0TX0D1
5 FPGA_ETH_TX_D1 PIU6035 COL/PHYAD0
NLFPGA0ETH0TX0D2
FPGA_ETH_TX_D2 33 16 COC14
C14 GND
POFPGA0ETH0TX0D2
5 FPGA_ETH_TX_D2 PIU6033 CRS/CRS_DV/LED_CFG PFBIN1 PIU6016PIC1401 PIC1402
NLFPGA0ETH0TX0D3
FPGA_ETH_TX_D3 30 0.22uF 6.3V 0201 GND EARTH_E
POFPGA0ETH0TX0D3
5 FPGA_ETH_TX_D3 PFBIN2 PIU6030
23 COC15
C15 Place pad w/ cutable bypass trace
PIU6023 RESET PIC1501 PIC1502
19 0.22uF 6.3V 0201
C PFBOUT PIU6019 Place two 4.7uF and one .22uF close C
NLFPGA0ETH0TX0EN
FPGA_ETH_TX_EN COC13
C13
POFPGA0ETH0TX0EN
5 FPGA_ETH_TX_EN PIC1301 PIC1302 to pin 19 of DP83848J.
0.22uF 6.3V 0201

IOGND
Place one .22uF close to pin 30 and

DGND

AGND
AGND
COC9
C9

PAD
PIC901 PIC902 place one .22uF close to pin 16.
NLFPGA0ETH0COL
FPGA_ETH_COL 4.7uF 6.3V 0402

X1
X2
POFPGA0ETH0COL
5 FPGA_ETH_COL
COC18
C18
PIC1801 PIC1802

28
PIU6028 PIU6027 PIU6041 PIU6029 PIU604 PIU6013 PIU6017 4.7uF 6.3V 0402

27

41
29
40
13
17
NLFPGA0ETH0CRS
FPGA_ETH_CRS
POFPGA0ETH0CRS
5 FPGA_ETH_CRS
GND
NLFPGA0ETH0RESET#
FPGA_ETH_RESET#
POFPGA0ETH0RESET#
5 FPGA_ETH_RESET#
COX3
X3 GND
1PIX301 3
PIX303

PIC3201 25.000MHz PIC3 01

COC32
C32 COC33
C33
PIC3202 27pF 25V 0402 PIC3 02 27pF 25V 0402

GND GND
Do Not place ground planes under
device crystal or capacitor pins to
reduce stray capacitance.
X's are a "No ERC" directive to the Design Rule Checker to ignore rule violations.
D D

Avnet Engineering Services

Title:
Sheet 10 - FPGA 10/100 Ethernet PHY
Size: Document Number: Rev:
S6-LX9-SCH-C C
B
Date: 8/2/2012 Sheet 10 of 10

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