Design of Low Power CMOS Based Schmitt

Trigger in 180nm Technology

Sameer Kumar Jha Parv Verma Manoj Taleja
University School of Information, University School of Information, University School of Information,
Communication and Technology, Communication and Technology, Communication and Technology,
GGSIPU GGSIPU GGSIPU
Delhi, India Delhi, India Delhi, India
sameerjha1997@gmail.com parv.usict.018164@ipu.ac.in manojtaleja@yahoo.com

Abstract—In this paper, CMOS based Schmitt Trigger
circuits have been considered using the one pMOS two layer
feedback approach and an nMOS only Schmitt Trigger with
voltage enhancer procedure. Schmitt Trigger is a vital circuit
used in obtaining the digitized output of an input signal. The
paper explores the design and scrutiny of low power
techniques. The simulations have been carried out in SPICE
based on TSMC 180nm CMOS technology. Conventional
Schmitt Trigger by means of the primary CMOS inverters is
used as reference circuit. Evaluation of power dissipation of
the circuit is carried out. The conventional model had the
power dissipation of 123.07pW with a supply voltage of 1.8V.
The proposed circuit which was made by using the one pMOS
two layer feedback technique had the power dissipation of
112.72pW while the proposed circuit using nMOS only pull up
network with a voltage enhancer showed a power dissipation of
71.45pW which gave 41.94% reduction in power consumption
as compared to the conventional circuit. The study gives us a
perception about the performance of the circuit when exposed
to various approaches, in so doing refining specific
characteristics of the circuit.
Keywords—CMOS, Hysteresis Width, NBTI, Noise Margin,
Schmitt Trigger, Voltage Enhancer
A. Working of Schmitt Trigger
The Schmitt Trigger circuit embodies positive feedback.
As a consequence, when the input is higher than the
threshold, the output equates to high. While, if the input is
lower than the other defined threshold, the output goes low.
If the input is amidst the thresholds, it retains its value. This
dual threshold action is characterized as hysteresis, and
hence the trigger is named so since it maintains its value until
the input changes sufficiently enough to prompt a change [4].
The perk of a Schmitt Trigger over a circuit having only a
single input threshold is the greater stability, i.e., noise
immunity. For circuits having only one threshold, a noise-
affected input near the threshold could cause the output to
fluctuate rapidly back and forth from the noise alone [5].
The conventional CMOS Schmitt Trigger circuit [1] as
shown in Fig. 2 is a general inverter circuit, i.e., it consists of
a dual transistor inverter comprising of two more transistors
to cater the act of hysteresis. The hysteresis loop is depicted
in Fig. 1.

I. INTRODUCTION
In VLSI, the power consumed by a circuit plays a crucial
role in determining the use & effective application of the
circuit. The power consumed by a circuit proliferates the on-
chip temperature which subsequently may alter the
performance factors of the circuit [1]. It is therefore vital to
cut the power dissipation of the circuit and enhance the
performance. Fig. 1. Voltage Transfer Characteristics of conventional Schmitt Trigger
In the propounded work, the intention is to enhance the
speed & moderate the switching delays along with enhancing
the noise immunity of a CMOS Schmitt Trigger, and
subsequently diminish the power dissipation of the circuit.
Often an input signal to a digital circuit may or may not
directly fit the description of a digital signal. Due to
numerous explanations, it might be having slow rise or fall
times, or it may have even acquired some noise from the
surrounding which can be detected with the help of specific
circuits. All the reasons as mentioned earlier require a
particular circuit to “clean up” the analog signal and hence
“force” it into its true digital shape. This specific circuit is
known as a Schmitt Trigger [1]. It has two possible stages
like any multivibrator [2]. However, the trigger for the circuit
to change its states is an input voltage signal rather than a
digital pulse. Thus, the output state depends on the input
voltage level, and will only improve as the input voltage
crosses the pre-defined threshold [3].

Fig. 2. Conventional CMOS Schmitt Trigger

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B. Modified Schmitt Trigger
The modified Schmitt trigger [6], containing one pMOS
and three nMOS, four MOSFETs in total is shown in Fig. 3.
Fig. 3. Modified Schmitt Trigger with 1 pMOS & 3 nMOS
The hysteresis curve is obtained because of the presence
of the nMOS N2 and N3. The transfer characteristic curve is
of the shape of hysteresis which can be seen in the Fig. 1.
Because the positive feedback is obtained using the nMOS
N3, when its state is changed it works like a source follower.
With input voltage equal to zero, nMOS N1 and N2 are in
off state, and with Vin is HIGH, pMOS P1 and nMOS N2 are
also off, so there is negligible consumption in both static
states. Assuming that the input voltage is increasing from
LOW to the HIGH. Then, the Vin vs Vout characteristic curve
can be seen in Fig. 1. The first region is for 0 ≤ Vin ≤ Vn2,
where Vn2 is the threshold voltage of the nMOS N2. In this
case, N1 and N2 are OFF, and P1 and N3 are ON, where P1
is non-saturated, and N3 are in the saturation state. The
output voltage Vout = VDD and the source voltage of N1 and
N3 are VSn1 = VSn3 = VDSn2 = VDD - Vn3, where Vn3 is the
threshold voltage of N3, VDSn2 is a drain to source voltage of
nMOS N2 taking into account the influence of the
substrate/source voltage. In the second region, nMOS N2 is
ON and saturated, while the state of the other MOSFETs
remains unchanged. VDSn2 is decreasing linearly. [6]
II. CIRCUIT DESCRIPTION
A. Consequence of alteration of W/L ratio of transistors on
the hysteresis curve
Fig. 4. Normal voltage transfer characteristics of a normal Schmitt Trigger
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The following discussion is based on the circuit in Fig. 2.
As the W/L ratio of the transistor N1 is increased the
hysteresis curve corresponding to it shifts a bit towards the
left-hand side in contrast to the hysteresis curve
corresponding to normal Schmitt Trigger. This happens since
the nMOS here is strong and hence will pull/drain the output
sharply to logic 0 (LOW).
Fig. 5. Effect of variation of W/L of transistor N1 on voltage transfer
characteristics
While, when the ratio for transistor N2 is being made to
vary, i.e., either increased or decreased, there happens to be
no effect of it on the hysteresis curve.
While, if the transistor sizing for N3 is increased, then it
only affects the VH level (the upper threshold level) because
when the input signal is made to improve gradually from
LOW to HIGH the transistor N3 plays the crucial role in
controlling VH, and hence its sizing would result in shifting
of the curve towards the right.
Fig. 6. Effect of variation of W/L of transistor N3 on voltage transfer
characteristics
Now, upon varying the sizing for transistor P1 the curve
shifts towards the right. It happens because in the pull-up
network of the circuit this transistor plays a crucial role in
maintaining the VL threshold level, so the curve shifts right.
Fig. 7. Effect of variation of W/L of transistor P1 on voltage transfer
characteristics
Similar to the case of transistor N2, the increment or
decrement of the aspect ratio of transistor P2 does not have
any effect on the hysteresis curve.
On the other hand, if the ratio for transistor P3 is
increased, it results in the hysteresis curve shifting towards
the left. The reason for shifting of the curve is because the
pMOS P3 controls the lower input threshold level, VL, and
hence if the W/L of P3 is increased it inevitably lowers the
VL threshold, and consequently, the curve gets displaced
towards left.
Fig. 8. Effect of variation of W/L of transistor P3 on voltage
transfer characteristics
Thus, from the above perusal, we can reckon that the
aspect ratio of P1 & P3 transistors govern the VL threshold
level, while the aspect ratio of N1& N3 transistor governs the
VH threshold level. And, transistors’ N2 & P2 aspect ratio
has no role to play in moulding the threshold levels.
The area under the hysteresis curve deduces the extent of
noise immunity provided by the circuit. Thus, more
pronounced is the difference between the two thresholds, VL
& VH, the more is the susceptibility of the circuit.
B. Importance of Hysteresis
In a Schmitt Trigger, hysteresis width is the amount of
noise that can change the output from one trip point
(threshold) to the other [7].
In a comparator, noise can change the input slightly due
to the addition of noise to the input signal, which may
inadvertently change the output from +Vsat to -Vsat or vice-
versa. There is a provision for immunity to noise which
hampers the performance of the circuit.
But unlike comparator, the Schmitt Trigger has a
tolerance limit which is called as hysteresis width. In the
simplest words, hysteresis width is the maximum amount of
noise that a Schmitt Trigger can tolerate. If the magnitude of
noise exceeds this hysteresis width, the output of Schmitt
Trigger may change from one trip point to the other one.
Hysteresis width is defined as the magnitude of the
voltage difference between the upper trip point and the lower
trip point in a Schmitt Trigger. Schmitt Trigger will give the
same constant output of positive or negative Vsat when the
hysteresis width is more significant than noise. So, noise
can’t disrupt the working of a Schmitt Trigger much.
Moreover, this noise immunity also makes it an almost
distortion less system. In general, noise may bring change in
output somewhat similar to the race-around condition which
can occur quickly in a comparator.
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III. PROPOSED CIRCUITS
A. Proposed Circuit-I [One pMOS Two Layered Feedback]
Since, nMOS has the property of pulling down the
voltage correctly as compared to pMOS. Similarly, pMOS
has the feature of sustaining the voltage at a high level very
effectively as compared to nMOS. This fundamental reason
leads us to pull up and pull down circuit entirely made of
pMOS and nMOS respectively. As a consequence, stronger
is the transistor better is its pulling capacity. A robust
transistor can be formed by controlling the W/L ratio.
Increasing the W/L ratio of nMOS will make the pull down
network of the circuit to pull down the output sharply and
rapidly. And upon increasing the W/L ratio for pMOS will
enhance the pulling up ability of the pull up network to shoot
up the voltage levels sharply.
Increasing the W/L of P1 will shift the hysteresis towards
the right so that the higher voltage will be maintained for a
more extended period; similarly, nMOS N1 will make the
hysteresis shift left. The feedback transistor N2 will control
the VH as explained earlier.
VDD
P1
IN OUT
N1
N5 VDD
N2
N4 VDD
N3
Fig. 9. Proposed circuit–I comprising of 1 pMOS and an nMOS only two
layered feedback
In the proposed circuit, shown in Fig. 9, the intention has
been to try to improve the hysteresis obtained by Modified
Schmitt Trigger [8], and hence only one pMOS P1 is used
which does not affect the hysteresis.
As discussed earlier, hysteresis width is directly
proportional to noise margin, and better is the noise margin
better the device. Thus, the proposed circuit allows to widen
the width of hysteresis by a multi-layered feedback
mechanism as the conventional Schmitt Trigger uses positive
feedback mechanism to increase the switching threshold of
the inverter and very sharp transfer characteristics are hence
obtained. In this circuit the two layered positive feedback
mechanism is used, in this process the two more nMOS are
used, N3 and N4. The nMOS N3 is parallel to nMOS N2 and
serves as feedback to nMOS N1. This circuit is right where
we require a larger width to increase the noise margin [5],
and as the number of pMOS is less, so many adverse effects
of pMOS is reduced.
 Since, pMOS require twice the area as compared to Thus, in the propounded circuit, shown in Fig. 9, an
nMOS for providing the same impedance, so this is the nMOS only Schmitt Trigger with a voltage enhancer and
reason nMOS has greater packing density [9]. Moreover, feedback is being presented. The critical feature is that since
factor such as parasitic capacitance is directly dependent on the whole circuit is comprised of nMOS transistors only,
the size of the junction, nMOS has a smaller proportion of hence the effect of NBTI on Schmitt Trigger is eradicated
junction, so their parasitic capacitance is also very less, in and an appreciable advancement in power & delay is
turn, they are faster than pMOS. observed [16]. Howbeit, since an nMOS only pull up
network, does not provide with a sharp and high logic 1, ergo
B. Proposed Circuit-II [nMOS only Schmitt Trigger with
a voltage enhancer is being deployed to boost the low
Voltage Enhancer]
voltage to a higher level thereby making it efficiently useful
for further use.
In the emerging race of minimising and making
everything compact, CMOS technology is left no behind.
IV. SIMULATION AND RESULTS
The scaling of CMOS technology has constituted several
Fig. 10 depicts the output waveforms obtained for a
challenges too for circuit designers. Reliability and power
conventional CMOS Schmitt Trigger in 180nm technology
consumption of the circuit plays an indispensable role in and a VDD of 1.8V. The power consumed the circuit varies
deciding whether to incorporate the circuit design in the from 16.33pW to 123.07pW as is evident from table I.
circuit or not [10]. Negative Bias Temperature Instability
(NBTI) [11] is one of the most important figures that
determines if the circuit is fit for use. Since NBTI is more
pronounced in p-channel MOS devices (pMOS devices), it
hence often results in a significant drift in the threshold
voltage at high temperatures (125°C) with time, which
thereby causes poor drive current and also reduces the circuit
lifetime [12]. It is due to the vulnerability of the CMOS
inverter to latch-up and the influence of NBTI on a pMOS
transistor that an nMOS only output buffer is found to be
more efficient and useful. This modified Schmitt Trigger Fig. 10. Simulation waveforms of conventional Schmitt Trigger
circuit causes a remarkable reduction in the chip area of the
Schmitt Trigger without altering the performance and hence Following the footsteps of the conventional Schmitt
finds its application in Static Random Access Memory Trigger, and with the aim of refining the in effect CMOS
(SRAM) [13] – [15]. The upshot of NBTI is modulated by Schmitt Trigger circuit, two circuits have been recommended
replacing the pMOS pull up network with voltage enhancing in this monograph.
circuit. The only downside of an nMOS only pull up network
is that the logic 1 voltage (VDD) is not quite sharp, and hence In Fig. 11 the waveforms for a simulation of proposed
a voltage enhancing circuit is deployed. circuit-I have been depicted. For simulation a VDD of 1.8V is
VD Voltage Enhancer supplied in 180nm technology, and the power consumption
contrasts from 15.94pW to 112.72pW as has been shown in
table I.
P
This circuit involves only one pMOS with an improved
N feedback network. Reduction in number of p-channel
MOSFETs by one has not only resulted in better noise
immunity to the circuit and faster & smooth switching, but
OUT also reduced the power consumption, though by a minimal
margin. In addition, a better “true” form of the input signal
IN
was observed due to better noise immunity.
N2
N4 VD

N3

Fig. 9. Proposed circuit–II comprising of nMOS only pull up network with a Fig. 11. Simulation waveforms of proposed circuit-I of Schmitt Trigger
voltage enhancer
Fig. 12 gives information about the waveforms obtained
after the simulation of proposed circuit-II. The power

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consumed by the circuit ranged from 10.59pW to 71.45pW In Fig. 13 the graphical comparison of the power
as the supply voltage traversed from 0.6V to 1.8V. consumption of the conventional circuit, proposed circuit-I
and proposed circuit-II for VDD ranging from 0.6V to 1.8V
has been plotted for better comparison of the three circuits.

VI. CONCLUSION
The prime concern of the work was reducing the power
of the circuit and enhancing the noise immunity. The
simulations have been performed with calculations of power
dissipation with a VDD ranging from 0.6V to 1.8V. The paper
parallels the circuits of CMOS Schmitt Trigger with different
Fig. 12. Simulation waveforms of proposed circuit-II of Schmitt Trigger
procedures for the reduction in power dissipation and noise
immunity, in so doing making it superior than its classical
V. COMPARATIVE ANALYSIS OF VARIOUS CMOS SCHMITT circuit. The scaling down of a number of characteristics of
TRIGGER CIRCUITS the transistors like dimensions, supply voltage, and threshold
voltage open the doors to increase in leakage current which
The detailed power consumption for various supply in turn causes an involuntary advancement in leakage power
voltages has been shown in table I. dissipation. With progressively scaling, the leakage current
becomes exceptionally vital and of utmost importance. The
Table I. Power Consumption of Conventional, Proposed Circuit-I and
Proposed Circuit-II CMOS based Schmitt Trigger power dissipation of the circuits organized in ascending
Conventional Proposed Proposed
fashion is as follows:-
VDD Conventional ST < Proposed Circuit-I < Proposed Circuit-II
Schmitt Trigger Circuit-I Circuit-II
(in V)
(pW) (pW) (pW)
0.6 16.33 15.94 10.59
0.8 26.02 25.59 16.54 VII. REFERENCES
1.0 38.71 37.52 23.93 [1] O.H. Schmitt. “A thermionic trigger” J. Sci Instrum., Vol 15, pp, 24-26,
1.2 54.34 51.96 32.93 jan, 1938
1.4 74.52 69.15 43.71 [2] CMOS digital integrated circuits: analysis and design by Sung-Mo
1.6 96.79 89.31 56.48 Kang, Yusuf Leblebici
1.8 123.07 112.72 71.45 [3] Adel S. Sedra, Kenneth C. Smith: Book Microelectronic Circuits:
Theory and Applications Seventh Edition
The 41.94% reduction in power consumption compared [4] Pfister, A. Novel CMOS Schmitt trigger with controllable hysteresis.
with classical CMOS Schmitt Trigger is for the reason that IEE Electronics Letters, 28(7), 639–641, (1992)
the number of transistors have been reduced from 3 pMOS [5] Schamis, R.S.: 'Reduce system noise with CMOS circuits', Electron.
Des., 1973,25, pp. 112-115
& 3 nMOS to only 1 pMOS & 4 nMOS in the circuit. Also, [6] Dokic, B. L.: 'CMOS Schmitt triggers', IEE Proc. G, 1984, 131, (5), pp.
reduction in p-channel MOSFETs has narrowed and 197-202
diminished the NBTI effect which would or else have had [7] CMOS Schmitt Trigger—A Uniquely Versatile Design Component--
amplified the threshold voltage for the circuit at higher Fairchild Semiconductor Application Note 140 June 1975
[8] C. T. Chuang and J. B. Kuang, "SOI CMOS Schmitt trigger circuits
temperature. with controllable hysteresis," U.S. Patent 6 441 663, Aug. 27, 2002
[9] Millman, J., and Grabel, A.: Microelectronics’ (McGraw-Hill, 1987),
Only reduction in power is not what was taken into pp. 679–683
account, but furthermore the noise immunity of the circuit [10] Al-Sarawi, S.F.: ‘Low power Schmitt trigger circuit’, Electron. Lett.,
2002, 38, (18), pp. 1009–1010
was enhanced than all the circuits and a reduced amount of [11] Schroder, D.K.: ‘Negative bias temperature instability: what do we
spikes were observed at the output signal [17]. As, the understand?’ Microelectron. Reliab., 2007, 47, (6), pp. 841–852
nMOS only pull up network would not have delivered an [12] M. A. Alam and S. Mahapatra, “A comprehensive model of PMOS
adequate logic 1 voltage, a voltage enhancer circuit was NBTI degradation,” Microelectron. Reliab., vol. 45, no. 1, pp. 71–81, Jan.
2005.
installed in the pull up network to boost the output voltage [13] A. P. Shah, N. Yadav, A. Beohar and S. K. Vishvakarma, "On-Chip
at higher voltage and make it more profitable to be of use Adaptive Body Bias for Reducing the Impact of NBTI on 6T SRAM
[18]. Cells," in IEEE Transactions on Semiconductor Manufacturing, vol. 31, no.
2, pp. 242-249, May 2018.
[14] J. Kulkarni, K. Kim, and K. Roy, “A 160 mV robust Schmitt trigger
based sub-threshold SRAM,” IEEE J. Solid-State Circuits, vol. 42, no. 10,
pp. 230–2313, Oct. 2007
[15] Singh, J., and Vijaykrishnan, N.: ‘A highly reliable NBTI resilient 6 T
SRAM cell’, Microelectron. Reliab., 2013, 53, (4), pp. 565–572
[16] Paul BC, Kang K, Kufluoglu H, Alam MA, Roy K. Impact of NBTI
on the temporal performance degradation of digital circuits. IEEE Electron
Dev Lett 2005; 26:560–2
[17] Lorenzo, R. and Chaudhury, S. (2016) Review of Circuit Level
Leakage Minimization Techniques in CMOS VLSI Circuits. IETE
Technical Review, 33, 1-23
[18] M.-B. Lin, Introduction to VLSI Systems: A Logic, Circuit, and
System Perspective. Boca Raton, FL, USA: CRC, 2011
Fig. 13. Comparison of powers of conventional, proposed circuit-I and
proposed circuit-II Schmitt Trigger

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