Analysis of Half Adder based on FinFET

Technology

A Thesis Submitted

In the Partial Fulfillment of the Requirements for

the Degree of

Bachelor of Technology

in
Electronics and Communication Engineering

JYOTIRADITYA MANI TRIPATHI (2021042010)

GAURAV SINGH (2021042007)

SUMAN SINGH (2021042023)

RITIK KUMAR CHAUDHARY (2021042018)

Under the Guidance of

Prof. B.P Pandey

(Professor, ECED, M.M.M.U.T)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Madan Mohan Malaviya University of Technology, Gorakhpur

May 2024
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© M.M.M. University of Technology, Gorakhpur,

(U.P) – 273010, INDIA
ALL RIGHTS RESERVED
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CERTIFICATE

This is to be certified that Jyotiraditya Mani Tripathi (2021042010), Gaurav Singh

(2021042007), Suman Singh (2021042023) and Ritik Kumar Chaudhary (2021042018) have
carried out the research work presented in this thesis entitled “Analysis of Half Adder based on
FinFET Technology” for the award of Bachelor of Technology from Madan Mohan Malviya
University of Technology, Gorakhpur under my supervision. The thesis embodies result of
original work and studies carried out by Student themselves and the contents of the thesis do not
form the basis for the award of any other degree to the candidate or to anybody else.

___________________

Signature of Supervisor
Prof. B.P Pandey
(Assistant Professor)
Electronics and Communication Engineering
MMMUT Gorakhpur

12 May 2024
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Candidate’s Declaration

I declare that this written submission represents my work and ideas in my own words and where
others’ ideas or words have been included. I have adequately cited and referenced the original
sources. I also declare that I have adhered to all principles of academic honesty and integrity
and have not misrepresented or falsified any idea/data/fact/source in my submission. I
understand that any violation of the above will be cause for disciplinary action by the
University and can also evoke penal action from the sources which have thus not been properly
cited or from whom proper permission has not been taken when needed.

Jyotiraditya Mani Tripathi (2021042010)

Gaurav Singh (2021042007)

Suman Singh (2021042023)

Ritik Kumar Chaudhary (2021042018)

Electronics and Communication Engineering Department

Madan Mohan Malviya University of Technology, Gorakhpur

Date: .......................................
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Approval Sheet

This project report entitled “Analysis of Half Adder based on FinFET Technology” by
“Jyotiraditya Mani Tripathi (2021042010), Gaurav Singh (2021042007), Suman Singh
(2021042023) and Ritik Kumar Chaudhary (2021042018)” is approved for the degree of
Bachelor of Technology in Electronics and Communication Engineering.

Examiner

________________________

________________________

________________________

Supervisor

________________________

Head of Department

________________________

Dean, Research & Development or

Other Dean/Professor to be nominated
by the Vice Chancellor in his absence

________________________

Date: ..........................................

Place: MMMUT Gorakhpur, UP

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ACKNOWLEDGEMENT

It is matter of great pleasure and satisfaction for me to present this dissertation work entitled
“Analysis of Half Adder based on FinFET Technology”, as a part of curriculum for award
of “Bachelor of Technology” from Madan Mohan Malaviya University of Technology,
Gorakhpur (U.P.) India. We are very grateful to the Head of the Department Prof. S. K. Soni.
It has been truly reassuringto know that he is always willing to share his quest for new
problem and new solutions forms a very challenging and rewarding environment with us. He
provides all kind of academic as well asadministrative support for smooth completion of my
dissertation work. Without his valuableguidance, this work would never have been a successful
one.
We are very much thankful to our supervisor, Prof. B.P Pandey for encouraging me to perform
work in emerging area of research, as well as his continuous and support throughout my work.
We would also like to thank all our classmates for their valuable suggestions and helpful
discussions.
At last, we are grateful to our family members especially my beloved parents, for their
encouragement and tender. Without them, we were unable to have enough strength to finish
this dissertation.

Jyotiraditya Mani Tripathi (2021042010)

Gaurav Singh (2021042006)
Suman Singh (2021042023)
Ritik Kuman Chaudhary (2021042018)

Date: .................................
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LIST OF FIGURES

Figure 1: Structure of FinFET __________________________________________________ 7

Figure 2: Pin Diagram of FinFET _______________________________________________ 7
Figure 3. Half Adder Circuit ___________________________________________________ 8
Figure 4: Inverter Circuit using FinFET Technology _______________________________ 13
Figure 5: Transient Response of Inverter Circuit ___________________________________ 15
Figure 6: DC Response of Inverter _____________________________________________ 17
Figure 7: NAND Gate Based on FinFET Technology _______________________________ 19
Figure 8: Transient Response of NAND Gate _____________________________________ 20
Figure 9: Block Diagram and Internal Circuit of Half Adder _________________________ 21
Figure 10: Circuit Diagram of XOR Gate based on FinFET __________________________ 22
Figure 11: Symbol and Internal Circuit of XOR Gate _______________________________ 23
Figure 12: Transient Response of XOR Gate _____________________________________ 24
Figure 13: Symbol of AND Gate _______________________________________________ 25
Figure 14: Transient Response of AND Gate _____________________________________ 25
Figure 15: FinFET Based Half Adder Circuit _____________________________________ 26
Figure 16: Transient Response of conventional Half Adder __________________________ 26
Figure 17: Transient Analysis of FinFET Based Half Adder__________________________ 27
Figure 19: Noise Response of FinFET based Half Adder ____________________________ 36

LIST OF TABLES

Table 1. Truth table of Half Adder _______________________________________________ 8

Table 2: Truth table of Inverter Circuit __________________________________________ 12
Table 3: Truth Table of NAND Gate ____________________________________________ 18
Table 4: Truth Table of Half Adder _____________________________________________ 21
Table 5: Truth Table of XOR Gate _____________________________________________ 23
Table 6: Truth Table of AND Gate _____________________________________________ 25
Table 7: Comparative Power Analysis of FinFET Half Adder with Conventional Half Adder 34
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ABSTRACT

This project explores the design and analysis of a half adder circuit utilizing CMOS FinFET (Fin
Field Effect Transistor) technology. The half adder, a fundamental building block in digital
circuitry, forms the basis of arithmetic operations in computing systems. Leveraging the
advantages of FinFET technology, including enhanced performance and reduced power
consumption, this study investigates the potential improvements and future prospects of half
adder circuits.

The project begins with a comprehensive review of CMOS FinFET technology, highlighting its
key features and benefits over traditional MOSFETs. Subsequently, the design methodology
employed in realizing the half adder circuit using FinFET devices is elucidated, encompassing
transistor-level implementation and logical arrangement to achieve accurate arithmetic
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TABLE OF CONTENT

Certificate iii

Candidate’s Declaration iv

Approval Sheet v

Acknowledgement vi

List of figures vii

List of tables vii

Abstract viii

Table of content ix

CHAPTER 1 1

Introduction 1

Overview of FinFET Technology: 4

Advantages over Traditional Planar CMOS Technology: 5

Applications in Digital Circuit Design: 6

Review of Half Adder Circuits 8

CHAPTER 2 10

Literature review 10

CHAPTER 3 12

Background 12

Review of inverter circuit 12

Design of the inverter circuit based on FinFET Technology: 13

Analysis of the Inverter Circuit: 14

Review of NAND gate 18

Design of the NAND Gate based on FinFET Technology: 19

Analysis of the NAND Gate: 20

CHAPTER 4 21

FinFET based half adder 21

Introduction 21
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Design and Performance Analysis of XOR Gate 22

Design and Performance Analysis of AND Gate 25

Circuit Design of Half Adder 26

Output of half adder FinFET circuit 26

Technological Software 28

Technology Nodes 30

Technology Library 31

Analysis and Result 33

CHAPTER 5 37

Conclusion and Future Scope 37

References 38
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CHAPTER 1
INTRODUCTION

INTRODUCTION
As nanometer process technologies have advanced, chip density and operating frequency have
increased, making power utilization in devices a crucial issue. So, for the designers of VLSI (Very
Large-Scale Integration) the main goal is to fulfill performance requirements within a power
requirement. Hence there is an increased importance of power efficiency. In FinFET technology,
which is an emerging technology, offering interesting power delay trade-offs, is likely to augment
CMOS (Complementary metal Oxide semiconductor) when scaled down to 32nm and beyond. In
design metrics, we have performance, area, cost, and time to open-air market. Since the beginning
of the Integrated Circuit industry, the desire to optimize this design metrics has not changed.
Moore’s law, in fact, is all about optimizing these parameters. However, as scaling continued,
and the manufacturing nodes progressed towards 20nm, some parameters especially the power
supply voltage, which is the main factor in determining the dynamic power could not be scaled
any further. One more issue was optimizing in one variable demands in big compromises in other
variables, for example, performance optimization caused degradation in power factor. Hence the
design window was shrinking for optimizing among the design variables. But FinFET broadens
the design window once again. Dynamic and static power was saved significantly as operating
voltage continues scaling down. Short cannel effects are reduced significantly. Hence continuing
to improve performance compared to planar device at an identical node. Performance advantages
of the FinFET widen compared to its planar equivalent, because of superior gate control of the
channel in FinFET. As compared to budget are counterpart, one major design optimization benefit
of FinFET is the fact that it gives much higher performance at the very same power budget, or at
a much minimum power budget it provides equal performance. Hence giving the designers and
engineers the potential to extract the higher performance for the minimum power, which is a
much-needed requirement for devices which operate on batteries. In VLSI, thousands of circuits
based on transistors are connected and combined to create integrated circuits (IC’s). One example
of VLSI device is a microprocessor. In the current era, VLSI architectures are used in the
manufacturing of almost each and every chip today. To meet these demands size, efficiency and
power must be reduced. For the design of both analog and dialog circuits, power dissipation is
the most important objective to be optimized.
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As Gordon Moore predicted, over the last three decades number of transistors in a single chip has
been increased significantly from thousand to several billion. As a result of this, the advancements
in technologies gave us high- speed multi-core processor technology, huge size memory devices,
etc. Yet, today’s emerging advanced robotic systems and embedded systems need higher speeds,
smaller sized IC’s to push boundaries of their performance and current IC technologies are unable
to deliver their requirement. Hence development of such systems remains a challenge. To support
development of such systems, it is necessary for IC technology to scale down the transistors and
increases the speed and performance. Every circuit consists of an inverter, NAND and NOR
circuits. The shrinking of the CMOS technology has been increased very aggressively with ultra-
thin sizes. This creates many significant challenges and reliability issues in design which causes
augmented process variations, SCEs, power densities and leakage currents etc. Thus Inverter,
NAND and NOR circuits are one of the essential parts of digital system. The operations of such
device are usually valued by taking its operation parameters like switching speed in terms of
delay of operation and power consumption. Since the MOSFET’s failure at the nanometer regime
beyond 90nm and our focus is on operations at the lower node technology such as 45nm where
alternative MOSFET called FinFET comes into picture and its performance must be studied and
we shall prove that it is the solution for conventional MOSFET’s failure

Constant voltage scaling and constant field scaling are the two types of scaling used in the VLSI
sector. As implied by the name, constant voltage scaling involves reducing other device
characteristics by a scaling factor while maintaining a constant power supply voltage. In the case
of constant field scaling, the size of the internal electric field stays constant while the other MOS
parameters are scaled back by a factor. Constant field scaling is thought to improve reliability,
although some characteristics, such as the silicon material’s energy gap and thermal voltage,
cannot be scaled down by lowering dimensions or voltage. Scaling down of threshold voltage,
sub-threshold slope, and leakage current are a few of this method’s limitations. Contrarily,
constant voltage scaling results in an increase in the channel electric field as the gate length
shrinks. Mobility deterioration, velocity saturation, leakage current, and numerous reliability
problems, such as oxide breakdown, hot carrier degradation, and electro-migration, are only a
few of the scaling drawbacks. To improve the scaling process, generalized scaling and quasi-
constant scaling are introduced. In these methods, different factors are used to scale down the
voltage, and the dimensions of devices are scaled by the scaling factor. Although scaling provides
various advantages, electronics devices still suffer from different side effects like process
variability, static power, and reliability issues.
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As the dimensions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) decreases,
the short channel effect (SCE) becomes a dominating concern in VLSI. The Short channel effect
causes an exponential increase in the leakage current. To reduce the SCE and hence leakage
current, a new technology has been developed in recent years. In this recent technology a 3D
multiple gate MOSFETs like FinFET (Fin Field Effect Transistor) has been developed which
possess numerous advantages over conventional MOSFETs and has attracted many engineers
and designers. FinFET is the new growing technology that works in the nm range to minimize
short channel effects. Many companies (like Intel) have started using FinFET technology. This
document is a review paper of current research on FinFET technology and discusses how it can
be used in future to design new logic devices (like Adder, Comparator, MUX and De-MUX etc.)
and memory devices. Various parameters of FinFET like reduced short channel effects, less
leakage current, low power consumption, less propagation delay and less time delay are
discussed. Various mathematical models and software (Hspice) were used to simulate power,
delay, power delay product, average power dissipation and energy delay product. Thus, FinFET
technology was designed to eliminate the problem of SCE by permitting transistors to be scaled
down into sub 20nm range.

In this paper, the main motive is performance analysis of Half Adder based on FinFET
Technology. FinFET current travels parallel to the plane of the wafer. It has multiple gates on a
single piece of hardware. A thin silicon film coats the channel that serves as the body of this
device. This structure resembles a fish’s fin. As a result, it is known as a FinFET. The channel’s
width is determined by the fin’s thickness (tsi) to the gate. The channel is determined by the
thickness of the fin from source to drain.
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Overview of FinFET Technology:

FinFET technology represents a significant advancement in semiconductor technology,

particularly in the realm of digital circuit design. Here's an overview of FinFET technology, its
advantages over traditional planar CMOS technology, and its applications in digital circuit
design:

1. Structure:

FinFETs are a type of field-effect transistor (FET) where the conducting channel is formed
on a thin silicon "fin" that protrudes from the substrate, instead of being confined to the
substrate surface like in traditional planar CMOS technology.
The gate wraps around the three sides of the fin, providing better electrostatic control of the
channel, hence the name "FinFET" (Fin Field-Effect Transistor).

2. Subthreshold Slope:

One of the key advantages of FinFETs is their steep subthreshold slope, which results in
lower leakage currents and improved energy efficiency compared to planar CMOS
transistors.

3. Gate Control:

FinFETs offer better gate control over the channel due to the gate's surrounding geometry,
enabling superior switching performance and reduced susceptibility to short-channel effects.

4. Scaling Potential:

FinFET technology has demonstrated superior scalability compared to planar CMOS

technology, allowing for continued transistor scaling and integration of more functionality
into smaller chip areas.

5. Manufacturability:

Although initially more complex to manufacture, FinFET technology has matured over the
years, and manufacturing processes have been developed to enable high-volume production
with good yields.
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Advantages over Traditional Planar CMOS Technology:

1. Improved Performance:

FinFET technology offers superior performance in terms of speed, power consumption, and
noise immunity compared to traditional planar CMOS technology.

2. Reduced Leakage Currents:

The steep subthreshold slope of FinFETs results in lower leakage currents, leading to
improved energy efficiency, especially in low-power applications.

3. Better Control over Short-Channel Effects:

FinFETs exhibit reduced short-channel effects, such as drain-induced barrier lowering

(DIBL) and subthreshold leakage, allowing for more reliable operation at smaller feature
sizes.

4. Enhanced Scalability:

FinFET technology enables continued scaling of transistor dimensions while maintaining

acceptable performance and power characteristics, thus supporting the advancement of
Moore's Law.

5. Robustness to Process Variations:

The three-dimensional structure of FinFETs provides better immunity to process variations,

ensuring consistent transistor performance across different manufacturing conditions.
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Applications in Digital Circuit Design:

1. High-Performance Processors:

FinFET technology is widely used in the fabrication of high-performance microprocessors

and system-on-chip (SoC) designs, where superior speed and energy efficiency are
paramount.

2. Low-Power Mobile Devices:

In the realm of mobile devices and IoT (Internet of Things) applications, FinFET technology
enables the development of low-power, high-performance chips that prolong battery life and
enhance user experience.

3. Memory Devices:

FinFET technology is also employed in the fabrication of memory devices, such as DRAM
(Dynamic Random-Access Memory) and NAND flash memory, to improve density, speed,
and power efficiency.

4. Networking and Communication Systems:

FinFET technology plays a crucial role in networking and communication systems,

facilitating the implementation of high-speed, energy-efficient circuits for data transmission
and processing.
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Overall, FinFET technology represents a significant advancement in semiconductor

manufacturing, offering improved performance, energy efficiency, and scalability compared to
traditional planar CMOS technology. Its applications span a wide range of domains, from high-
performance computing to low-power mobile devices and beyond, driving innovation in digital
circuit design and enabling the development of next-generation electronic systems.

Figure 1: Structure of FinFET

Figure 2: Pin Diagram of FinFET

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Review of Half Adder Circuits

1. Purpose:

Half adder circuits are designed to add two single-bit binary numbers and produce two
outputs: the sum and the carry. They serve as the basic unit for arithmetic operations in digital
circuits.

2. Basic Architecture:

A half adder typically consists of two inputs, labeled A and B, representing the two bits to be
added, and two outputs: the sum (S) and the carry (C).
The sum output (S) represents the result of adding the two input bits, while the carry output
(C) indicates whether a carry-over occurred in the addition process.

Figure 3. Half Adder Circuit

3. Truth Table:

The behavior of a half adder is defined by its truth table, which shows the output values (sum
and carry) for all possible combinations of input values (A and B).
The truth table for a half adder is relatively simple, with four rows corresponding to the four
possible input combinations (00, 01, 10, 11).

Table 1. Truth table of Half Adder

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4. Boolean Expressions:

The sum (S) and carry (C) outputs of a half adder can be expressed using Boolean algebra.
The sum output (S) is given by the XOR (exclusive OR) operation of the input bits:
S= A⊕ B
The carry output (C) is given by the AND operation of the input bits: C=A.B

5. Implementation:

Half adder circuits can be implemented using basic logic gates such as XOR gates and AND
gates.
In traditional CMOS technology, the implementation typically involves a combination of
transistors arranged to perform the required logical operations.

6. Performance Metrics:

When evaluating half adder circuits, key performance metrics include:

Speed: How quickly the circuit can produce the correct output given a set of input values.
Power Consumption: The amount of power consumed by the circuit during operation.
Area Efficiency: The physical size of the circuit relative to its functionality.
Robustness: The circuit's ability to maintain correct operation in the presence of noise or
variations in operating conditions.

7. Limitations:

One limitation of basic half adder circuits is that they cannot handle carry inputs from
previous stages of addition. This limitation is addressed by full adder circuits, which
incorporate additional logic to handle carry inputs.

8. Applications:

Half adder circuits are fundamental components in digital systems, used in various
applications such as arithmetic logic units (ALUs), counters, and data processing units.
They form the basis for more complex arithmetic operations and data manipulation in digital
circuits.

In summary, half adder circuits play a crucial role in digital logic design, providing a simple yet
essential mechanism for binary addition. Understanding their operation and characteristics is
fundamental to the design and analysis of digital systems
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CHAPTER 2
LITERATURE REVIEW

Numerous studies have contributed to the understanding of designing and evaluating the
performance of digital circuits utilizing FinFET technology. Key literature in this domain
includes works by Sahil Rashied and Raju Hazare, among others.

Sahil Rashied et al – This paper focuses on the design and performance analysis of logic
circuits employing FinFET technology. The study investigates the efficacy of FinFETs in
enhancing circuit speed, reducing power consumption, and improving overall performance
metrics. Through comprehensive simulations and analyses, Rashied and Dhillon demonstrate the
advantages of utilizing FinFETs in digital logic circuitry. Their findings provide valuable insights
into the potential of FinFET technology to revolutionize digital circuit design, paving the way for
more efficient and high-performance electronic systems.
The performance analysis of FinFET based digital applications such as comparator MUX,
DeMUX etc. at 20nm technology nodes is also discussed.

Raju Hazare - Raju Hazare’s conference paper delves into the design and evaluation of
FinFET-based digital circuits tailored for high-speed integrated circuits (ICs). The study
meticulously examines the performance characteristics of FinFET technology in the context of
high-speed IC design, aiming to harness its inherent advantages for achieving superior speed and
efficiency. Through rigorous design methodologies and comprehensive evaluation techniques,
Hazare presents compelling evidence of the potential of FinFETs in advancing the performance
boundaries of digital circuits. The paper serves as a valuable resource for researchers and
practitioners seeking to leverage FinFET technology for the development of next-generation
high-speed ICs, thereby contributing to the ongoing evolution of semiconductor technologies.
The performance analysis of FinFET technology based digital applications such as inverter
NAND and NOR gates at 22nm technology nodes is also discussed using HSPICE.
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Himani Singh Rana et al. - has proposed the key features and challenges associated with
FINFET and the comparison of FinFET with CMOS. Subsequent discussions reviewed some of
the unique features of FinFET, which result in behavior different from simplicity of MOS
transistors. Their research paper gives a comparison of FinFET with CMOS, so FinFET inverter
and CMOS inverter values are taken to resolve the problem of average power, maximum power,
delay, and power dissipation.

This paper also shows that FinFET technology is far better than CMOS technology. FinFET
operates at a minimum voltage because of their low threshold voltage and the leakage current is
reduced by about 89%. FinFET technology has authorized the development in Integrated Circuit
technology to continue to obey Moore’s law.

Bibin Lawrence R Jency Rubia J - worked on FinFET Technology and Circuit Design
Challenges. In their research they have discussed FinFET technology and the circuit designs using
FinFET technology. Their work gives a clear picture of both advantages and disadvantages of
FinFET. This paper gives the key features and challenges associated with FINFET. Considerable
changes have been put forward to circuit design by FinFET. There are yet various challenges and
constraints that FinFET technology must face to be more successful than other technologies: fin
shape, doping, isolation, stressing, pitch & crystallographic orientation as well as device
performance was discussed.
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CHAPTER 3
BACKGROUND

REVIEW OF INVERTER CIRCUIT

A digital inverter circuit is a fundamental building block in digital electronics. Its primary
function is to invert the input signal, meaning it converts a logical high (usually represented by
a voltage level like 5V) into a logical low (usually 0V), and vice versa. In digital systems, this
inversion is crucial for various operations like signal amplification, logic operations, and signal
buffering.

Here's a basic overview of a digital inverter circuit:

Transistor-based: Traditional digital inverters are built using transistors, usually MOSFETs
(Metal-Oxide-Semiconductor Field-Effect Transistors) or BJTs (Bipolar Junction Transistors).
MOSFET-based inverters are more common due to their low power consumption and high
input impedance.

Operation: When the input signal is at a logical high, the transistor is turned on, creating a low
resistance path between the output and the ground. This results in the output being pulled down
to a logical low.
When the input signal is at a logical low, the transistor is turned off, isolating the output from
the ground. This allows a pull-up resistor to pull the output up to a logical high.

Logic levels: In digital electronics, logical high and low levels are typically represented by
specific voltage levels. For example, in a CMOS (Complementary Metal-Oxide-
Semiconductor) inverter, a logical high might be represented by a voltage close to the supply
voltage (e.g., 5V), and a logical low might be close to the ground voltage (e.g., 0V).

Table 2: Truth table of Inverter Circuit

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Propagation delay: Digital inverters introduce a slight delay between the input signal changing
state and the output responding. This delay is known as propagation delay and is an important
parameter in digital circuit design.

Applications: Digital logic gates: Inverters are fundamental components in building more
complex digital logic gates like AND, OR, and XOR gates.
Signal conditioning: Inverters can be used to condition digital signals for transmission over long
distances or between different voltage domains.
Clock signal generation: Inverters are often used in clock signal generation circuits.

Design of the inverter circuit based on FinFET Technology:

Firstly, the schematic of inverter circuit based on 45nm FinFET Technology is designed on the
software called “Cadence Virtuoso”,
Then its circuit simulation is done and also its parameters are analyzed as follows:

Circuit Design in Cadence:

Figure 4: Inverter Circuit using FinFET Technology

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Analysis of the Inverter Circuit:

1. Transient Analysis

Transient analysis of an inverter circuit involves studying its behavior during the transition
period when the input signal changes from one state to another. In the context of digital
inverters, transient analysis focuses on how the output voltage responds when the input
signal transitions from a logical high to a logical low, or vice versa.

Here's how transient analysis of an inverter circuit typically works:

a) Initial state: The analysis starts with the inverter circuit in a stable state, where the
input signal is either at a logical high or a logical low, and the output has settled to the
corresponding state.

b) Input transition: At a certain point in time, the input signal changes state. For
example, if the input was at a logical high, it transitions to a logical low. This transition
triggers the transient analysis.

c) Propagation delay: The inverter circuit takes some time to respond to the input
transition due to various factors such as transistor switching times, parasitic
capacitances, and interconnect delays. This delay is known as the propagation delay.

d) Output transition: During the propagation delay period, the output voltage of the
inverter circuit begins to transition from its initial state to its final state, following the
input transition.

e) Settling time: Once the output voltage reaches its final state, it may exhibit some
ringing or oscillations before settling down to a stable level. The time taken for the
output voltage to settle within a certain tolerance of its final value is known as the
settling time.

Analysis: During transient analysis, engineers study various parameters such as propagation
delay, rise/fall times, overshoot, undershoot, and settling time to ensure that the inverter
circuit meets the required performance specifications.
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Transient analysis is essential for understanding the dynamic behavior of digital circuits,
especially in high-speed applications where signal transitions occur rapidly. It helps in
optimizing circuit design, ensuring signal integrity, and minimizing issues such as signal
distortion, ringing, and jitter. Advanced simulation tools like SPICE (Simulation Program
with Integrated Circuit Emphasis) are often used for performing transient analysis of
complex digital circuits.

Figure 5: Transient Response of Inverter Circuit

2) DC Analysis

Analyzing the DC characteristics of an inverter circuit involves understanding how the

circuit behaves when it's in a steady state, without any input signal variations. Here's a step-
by-step guide on how to perform a DC analysis of an inverter circuit:

a) Circuit Description: Understand the circuit components and their connections. A

basic inverter circuit typically consists of a MOSFET (Metal-Oxide-Semiconductor
Field-Effect Transistor) and a load resistor connected between the power supply
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and ground.

b) MOSFET Behavior: MOSFETs are the key components in inverter circuits. They
have three terminals: Gate (G), Source (S), and Drain (D). In an inverter, the
MOSFET is used in its switching region, meaning it operates either in cut-off (off)
or saturation (on) mode.

c) DC Operating Point Analysis:

 Determine MOSFET State: Assume an initial state for the MOSFET, either off or
on. This choice depends on the circuit design and operating conditions.
 Calculate Gate Voltage: If the MOSFET is on, the gate voltage (Vgs) is sufficient
to keep it in the saturation region. If it's off, the gate voltage is zero.
 Determine Drain-Source Voltage (Vds): Based on the gate voltage and MOSFET
state, calculate the drain-source voltage. In the off state, Vds equals the power
supply voltage (Vdd). In the on state, it depends on the drain current and the load
resistor.
 Check for Saturation: Ensure that the MOSFET is operating in the saturation region
(if it's supposed to be on). This typically involves verifying that Vds is greater than
the threshold voltage (Vth) of the MOSFET.
 Load Line Analysis: Plot the load line on the Vds-Vgs graph. The load line
represents the relationship between Vds and Vgs for the given circuit. It intersects
the MOSFET characteristic curve, helping to determine the operating point.

d) Operating Point Calculation: The intersection points of the load line and the
MOSFET characteristic curve gives the DC operating point (Q-point) of the circuit.
From this point, you can determine important parameters like drain current (Id) and
drain-source voltage (Vds).

e) Power Dissipation Calculation: Calculate the power dissipated by the MOSFET

and the load resistor. This helps in understanding the efficiency and thermal
considerations of the circuit.
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By following these steps, you can perform a comprehensive DC analysis of an inverter

circuit, which is crucial for understanding its behavior under steady-state conditions.

Figure 6: DC Response of Inverter

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REVIEW OF NAND GATE

Analyzing the DC characteristics of a NAND gate involves understanding its behavior under
steady-state conditions, particularly with respect to voltage levels and current flow. Here's a basic
guide to analyze a NAND gate:

1) Circuit Description: A NAND gate typically consists of multiple transistors arranged in

a way that the output is low (logic 0) only when all inputs are high (logic 1).

2) Transistor Behavior: NAND gates are often built using MOSFETs (Metal-Oxide-
Semiconductor Field-Effect Transistors) or BJTs (Bipolar Junction Transistors).
Understanding the behavior of these transistors is crucial for analyzing the gate.

3) DC Operating Point Analysis:

 Input Conditions: Assume input conditions (either high or low) based on the logic levels
you're analyzing.
 Transistor States: Determine the states (conducting or non-conducting) of the transistors
in the gate based on the assumed input conditions.
 Output Calculation: Based on the transistor states, calculate the output voltage. For a
NAND gate, the output is typically high (logic 1) unless all inputs are high (logic 1), in
which case it goes low (logic 0).

4) Voltage and Current Levels:

Analyze voltage levels at different points in the circuit (input, output, transistor terminals).
Calculate current flow through the transistors and resistors in the circuit.
Propagation Delay: In addition to DC characteristics, it's also important to consider the
propagation delay of the NAND gate, which is the time taken for a change in input to result
in a corresponding change in output.

Table 3: Truth Table of NAND Gate

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5) Noise Margin: Evaluate the noise margin of the gate, which is the amount of noise that
can be present on the inputs without affecting the output logic levels.

6) Power Consumption: Analyze the power consumption of the gate, which depends on
factors such as transistor switching activity and static power dissipation.

By performing these analyses, you can gain insights into the behavior of a NAND gate under DC
conditions, which is essential for understanding its role in digital circuits and ensuring reliable
operation in practical applications.

Design of the NAND Gate based on FinFET Technology:

Firstly, the schematic of NAND Gate based on 45nm FinFET Technology is designed on the
software called “Cadence Virtuoso”,
Then its circuit simulation is done and also its parameters are analyzed as follows:

Figure 7: NAND Gate Based on FinFET Technology

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Analysis of the NAND Gate:

1. Transient Analysis

Transient analysis of a NAND Gate involves studying its behavior during the transition
period when the input signal changes from one state to another. In the context of digital
NAND, transient analysis focuses on how the output voltage responds when the input signal
transitions from a logical high to a logical low, or vice versa.

Figure 8: Transient Response of NAND Gate

Findings: The implementation of FinFET technology has demonstrated a notable improvement

in circuit speed and throughput compared to traditional CMOS technology.

Discussion: The unique characteristics of FinFETs, such as reduced leakage current and
improved control over channel conductivity, contribute to enhanced performance, making them
suitable for highspeed digital circuit.
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CHAPTER 4
FinFET BASED HALF ADDER

INTRODUCTION

A half adder is a fundamental digital circuit used in computer engineering and digital electronics.
It's designed to add two single-bit binary numbers and produce the sum and carry output. The
half adder has two inputs, typically labeled A and B, representing the two bits to be added. It
produces two outputs: the sum (S) and the carry (C).

Circuit Diagram of Half Adder

Figure 9: Block Diagram and Internal Circuit of Half Adder

Table 4: Truth Table of Half Adder

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As you can see, the sum output (S) represents the least significant bit of the addition, while the
carry output (C) indicates if there's a carry-over to the next higher significant bit.

In terms of logic gates, a half adder can be implemented using an XOR gate for the sum and an
AND gate for the carry. The XOR gate computes the sum, while the AND gate computes the
carry.

The logic equations for the sum (S) and carry (C) outputs of a half adder are:
S=A⊕B
C=A⋅B
Here,
⊕ represents the XOR operation and
⋅ represents the AND operation.

The half adder is a building block for more complex arithmetic circuits like full adders, which
can add multiple bits and handle carry inputs from previous stages.

Design and Performance Analysis of XOR Gate

XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a digital logic gate
that gives a true (1 or HIGH) output when the number of true inputs is odd.

Figure 10: Circuit Diagram of XOR Gate based on FinFET

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Figure 11: Symbol and Internal Circuit of XOR Gate

Table 5: Truth Table of XOR Gate

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Figure 12: Transient Response of XOR Gate

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Design and Performance Analysis of AND Gate

The AND gate is a basic digital logic gate that implements logical conjunction (∧) from
mathematical logic – AND gate behaves according to the truth table. A HIGH output (1) results
only if all the inputs to the AND gate are HIGH (1). If not all inputs to the AND gate are HIGH,
LOW output results.

Figure 13: Symbol of AND Gate

Table 6: Truth Table of AND Gate

Figure 14: Transient Response of AND Gate

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Circuit Design of Half Adder

Figure 15: FinFET Based Half Adder Circuit

OUTPUT OF HALF ADDER FINFET CIRCUIT

Figure 16: Transient Response of conventional Half Adder

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Figure 17: Transient Analysis of FinFET Based Half Adder

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TECHNOLOGICAL SOFTWARE

The software we used for the designing and analysis of the FinFET based digital circuits (like
inverter, AND Gate, NAND Gate, XOR Gate and Half Adder) is “Cadence Virtuoso”.

Cadence Virtuoso
Cadence Virtuoso is a widely-used Electronic Design Automation (EDA) software suite
developed by Cadence Design Systems. It's primarily used for designing and simulating complex
analog, mixed-signal, and RF integrated circuits (ICs). Virtuoso is highly regarded in the
semiconductor industry for its comprehensive toolset and advanced capabilities.

Here are some key features and aspects of Cadence Virtuoso:

1) Schematic Capture: Virtuoso provides a user-friendly environment for creating and

editing circuit schematics. Designers can place and connect electronic components, such
as transistors, resistors, capacitors, and other devices, to create complex analog or mixed-
signal circuits.

2) Layout Design: Virtuoso includes powerful layout tools for designing the physical
layout of integrated circuits. Designers can create custom layout geometries, perform
placement and routing, and ensure adherence to design rules and specifications.

3) Simulation: Virtuoso offers a range of simulation capabilities to verify the functionality

and performance of IC designs. This includes circuit simulation, such as transient, AC,
DC, and noise analyses, as well as more specialized simulations like Monte Carlo
analysis for statistical variation analysis.

4) Verification and Debugging: The software provides features for verifying and
debugging designs to ensure they meet specifications and performance requirements.
Design rule checking (DRC) and layout versus schematic (LVS) verification help catch
errors and inconsistencies between the schematic and layout.

5) Customization and Automation: Virtuoso allows users to customize and automate

various aspects of the design process through scripting and programming interfaces. This
enables designers to streamline repetitive tasks and adapt the software to specific design
methodologies or requirements.
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6) Integration with Other Tools: Virtuoso integrates with other Cadence tools and third-
party software to provide a comprehensive design environment. This includes integration
with tools for digital design, verification, and manufacturing process design.

7) Support for Advanced Technologies: Virtuoso supports advanced semiconductor

technologies, including FinFET, SOI (Silicon-on-Insulator), and SiP (System-in-
Package) designs. It also provides features for designing RF (Radio Frequency) and high-
speed mixed-signal circuits.

Overall, Cadence Virtuoso is a powerful and versatile tool used by IC designers and engineers
for designing and simulating complex analog and mixed-signal integrated circuits, helping to
accelerate the development of cutting-edge semiconductor products.
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TECHNOLOGY NODES
FinFET technology, which stands for Fin Field-Effect Transistor, is a type of 3D transistor
structure that has become the standard for modern semiconductor manufacturing processes. The
term "technological nodes" refers to the different generations or iterations of FinFET technology,
each representing a shrinking of transistor dimensions and improvements in performance, power
efficiency, and density. Here are some of the major technological nodes in FinFET technology:

1) 22nm: Intel was one of the pioneers in commercializing FinFET technology with their
22nm process node, which was introduced in 2011. This node offered significant
improvements in performance and power efficiency compared to earlier planar transistor
technologies.

2) 14nm / 16nm: Following the 22nm node, several semiconductor manufacturers

transitioned to the 14nm or 16nm FinFET node. Companies like Intel, TSMC, and
Samsung introduced their respective 14nm or 16nm FinFET processes, offering further
improvements in transistor density and power efficiency.

3) 10nm: The 10nm node represents another significant advancement in FinFET

technology, enabling even smaller transistor dimensions and higher transistor density.
Companies like Intel, TSMC, and Samsung have developed their 10nm processes, which
offer improved performance and power efficiency compared to previous nodes.

4) 7nm: The 7nm node represents the current state-of-the-art in FinFET technology,
offering further improvements in transistor density, performance, and power efficiency.
Companies like TSMC, Samsung, and GlobalFoundries have introduced their 7nm
processes, which are widely used for manufacturing high-performance CPUs, GPUs, and
other advanced semiconductor devices.

5) 5nm and Beyond: Semiconductor manufacturers are currently working on developing

FinFET processes with even smaller transistor dimensions, such as 5nm and beyond.
These future nodes are expected to offer continued improvements in performance, power
efficiency, and density, enabling the development of even more advanced semiconductor
devices.
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Each new technological node in FinFET technology represents a significant milestone in

semiconductor manufacturing, driving advancements in various industries such as computing,
telecommunications, automotive, and IoT. These advancements enable the development of more
powerful, energy-efficient, and compact electronic devices that shape our modern world.

TECHNOLOGY LIBRARY
A FinFET technology library, in the context of semiconductor design, refers to a collection of
predefined transistor models, cell libraries, and design rules specific to FinFET transistor
technology. These libraries are essential for designing and simulating integrated circuits (ICs)
using FinFET transistors.

Here are some key components typically found in a FinFET technology library:

1) Transistor Models: These are mathematical representations of FinFET transistors that

capture their electrical behavior under different operating conditions. Transistor models
provide information such as threshold voltage, channel length modulation, capacitances,
and parasitic resistances, which are crucial for simulating transistor-level circuit behavior
accurately.

2) Cell Libraries: Also known as standard cell libraries, these libraries contain a set of pre-
designed logic cells, such as gates, flip-flops, and latches, implemented using FinFET
transistors. Cell libraries provide designers with a comprehensive set of building blocks
for constructing digital circuits at the register-transfer level (RTL) or gate level.

3) Physical Design Kits (PDKs): PDKs are collections of design rules, technology files,
and parameterized layout cells (PCells) that enable physical design and layout of
integrated circuits using FinFET technology. PDKs provide information about layout
constraints, design rules, metal layers, vias, and other physical aspects of the
semiconductor manufacturing process.

4) Simulation Models: In addition to transistor models, FinFET technology libraries may

include various simulation models for other circuit components, such as passive
components (resistors, capacitors, inductors), interconnects, and semiconductor devices
(diodes, BJTs, etc.). These simulation models are used for circuit simulation, analysis,
and verification.
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5) Design Rule Checking (DRC) Rules: DRC rules define geometric constraints and
constraints that must be adhered to during the layout design process to ensure
manufacturability and reliability of the integrated circuit. FinFET technology libraries
provide DRC rules specific to the FinFET manufacturing process to prevent layout errors
and violations.
6) Layout Versus Schematic (LVS) Checks: LVS checks ensure consistency between the
schematic and layout representations of the integrated circuit design. FinFET technology
libraries include LVS rules and checks to verify that the layout accurately reflects the
intended circuit topology and connectivity.

7) Process Variability Models: With shrinking transistor dimensions and increasing

process variations, FinFET technology libraries may include models and tools to account
for process variability effects during circuit design and simulation. These models help
designers analyze and mitigate the impact of process variations on circuit performance
and yield.

Overall, a FinFET technology library provides designers with a comprehensive set of resources,
models, and design kits tailored to the specific characteristics and requirements of FinFET
transistor technology, enabling efficient and accurate design of advanced semiconductor
integrated circuits.
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ANALYSIS AND RESULT

Designing and analysing a half adder on FinFET technology using Cadence involves a
comprehensive process.

We'll set up simulations using Cadence's simulation tools like Virtuoso or HSPICE to verify the
functionality, performance, and reliability of the half adder circuit. These simulations include
transient analysis to observe its behaviour under different input conditions, DC analysis to ensure
proper biasing, AC analysis to evaluate frequency response, power analysis to optimize for low
power, and noise analysis to assess its susceptibility to various noise sources.

1) Power Analysis of Half Adder

Power analysis of a half adder involves assessing the power consumption of the circuit
under different operating conditions. Power consumption is crucial in integrated circuit
design as it directly impacts battery life, heat dissipation, and overall system efficiency.
Here's how power analysis can be performed for a half adder:

a) Static Power Analysis: Leakage Power: Static power consumption, also known
as leakage power, occurs even when the circuit is in a static state (no inputs
changing). It's primarily due to leakage currents in transistors and other
components. Analysing leakage power involves estimating the leakage current
of individual transistors and multiplying it by the supply voltage.
b) Dynamic Power Analysis: Switching Power: Dynamic power consumption
occurs when the circuit switches states, such as during input changes or clock
transitions. It's primarily caused by charging and discharging of capacitive loads,
as well as current flowing through active devices.
c) Transient Analysis: Transient power analysis involves simulating the circuit
under typical operating conditions and measuring the instantaneous power
consumption over time. This analysis provides insights into how power varies
during different phases of operation and helps identify potential power-hungry
sections of the circuit.
d) Power Gating and Clock Gating: Power gating involves selectively turning off
power to unused circuit blocks or modules to reduce static power consumption.
Clock gating involves stopping the clock signal to inactive logic elements to
reduce dynamic power consumption. Incorporating power gating and clock
gating techniques can significantly reduce overall power consumption in the
circuit.
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e) Optimization Techniques: Design optimization techniques, such as transistor

sizing, logic restructuring, and voltage scaling, can be employed to minimize
power consumption while meeting performance requirements. These techniques
aim to reduce both static and dynamic power by optimizing transistor sizes, gate
configurations, and operating voltages.

By performing comprehensive power analysis and employing optimization techniques,

designers can minimize the power consumption of a half adder circuit while ensuring it
meets the required performance specifications.

Voltage Power Dissipation in Power Dissipation in

conventional (µW) FinFET (µW)

0.6 1.98 1.38

0.8 2.01 1.407

1.0 2.05 1.435

Table 7: Comparative Power Analysis of FinFET Half Adder with Conventional Half Adder

Conventional FinFET to 18nm FinFET technology reduces power dissipation in a half adder
circuit by 30%. This would mean that the power dissipation in the 18nm FinFET half adder
is 70% of that in the conventional FinFET half adder .

2) Noise Analysis

Analyzing noise in digital circuits like a half adder is crucial for understanding how they
perform in real-world conditions, especially in noisy environments. Noise can come from
various sources such as electromagnetic interference, thermal noise, or crosstalk from
adjacent circuits.
In a half adder circuit, noise can affect both inputs and outputs. Here are a few
considerations for noise analysis:

a) Input Noise Immunity: Digital circuits like half adders typically have a certain
level of noise immunity, meaning they can tolerate a certain amount of noise on
their inputs without producing incorrect results. This tolerance is determined by
the voltage levels used in the circuit and the noise margins defined by the
technology.
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b) Propagation of Noise: Noise can propagate through logic gates and affect the
final output. For example, if there's noise on one of the inputs of the half adder,
it can potentially cause incorrect output due to the way the logic gates operate.

c) Sensitivity to Crosstalk: In integrated circuits where multiple signals are routed

closely together, crosstalk can occur. Crosstalk is the unwanted coupling of
signals between adjacent wires or traces on a circuit board. It can lead to
interference and affect the behavior of the circuit.

d) Output Noise Margins: The noise margin is the difference between the
minimum acceptable voltage for a logic level and the maximum allowable
voltage for the preceding logic level. Analyzing noise margins helps determine
the circuit's robustness against noise.

e) Power Supply Noise: Variations in the power supply voltage can also introduce
noise into the circuit. Voltage fluctuations can cause glitches or unexpected
behavior, especially in sensitive digital circuits.

To perform a thorough noise analysis of a half adder, you would typically simulate the circuit
using specialized software tools that consider various noise sources and their effects. Monte Carlo
simulations, for example, can help analyze the circuit's performance across a range of possible
input conditions and noise scenarios.

Additionally, techniques such as adding noise filters, shielding sensitive components, or using
differential signaling can help mitigate noise issues in digital circuits.
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Figure 18: Noise Response of FinFET based Half Adder

Frequency Conventional Half Adder FinFET Half Adder

Noise Response (at 100Hz) 19.44 16.20
[nV/sq (Hz)]

The noise decreases by approximately 20% when transitioning from conventional FinFET to
18nm FinFET technology.
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CHAPTER 5
CONCLUSION AND FUTURE SCOPE

Simulation outcomes for digital applications utilizing FinFET technology at 18nm nodes have
been examined extensively. The inherent limitations associated with MOSFET devices,
particularly concerning short channel effects, have been effectively addressed by adopting
FinFETs. Our findings indicate significant enhancements in the performance of nanoscale devices
facilitated by FinFET integration. Notably, the noise margin values derived from our
investigation underscore the superior reliability and tolerance capabilities of FinFET-based Half
Adders. Consequently, FinFET emerges as a highly promising solution for current and future
fabrication processes of high-speed integrated circuits. By leveraging FinFET-based digital
circuits, modern devices stand to benefit from enhanced functionalities, heightened speed, and
reduced power consumption, thus marking a significant advancement in semiconductor
technology. Intel has already announced the tri-gate FinFET as its choice, at the technology node
of 7nm for the manufacturing of its processors.
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