Full chip CIC Training

KICG (PDC)
JUL 1st 2021
- restricted -
Design Environment
Topic Details Reference
1. icmpm for work area setup KeanSek passdown- work setup
2. bsub/LSF Job submission https://confluencewikiprod.intra.infineon.com/display/DFDoc/Compute+Load+Sharing
3. icmp4 for data management and revision
control
4. VNC setup https://confluencewikiprod.intra.infineon.com/display/DFDoc/Remote+Desktop+Project
Design Environment
5. NX setup https://confluencewikiprod.intra.infineon.com/display/DFDoc/Remote+Desktop+Project+NX+System
6. How to launch tools and override default
version
7. HOBTO variables https://confluencewikiprod.intra.infineon.com/x/86ibDw
AARR-102 DESCRIPTION OF HOBOT CIC FLOW VARIABLES

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VNC/NX setup

› https://remotedesktop.india.cypress.com/userReLogin.php
› https://remotedesktop.aus.cypress.com/NXactiveSns.php
› India use VNC and Austin use NX session
› VNC info:
https://confluencewikiprod.intra.infineon.com/display/DFDoc/Remote+Desktop+Project
› NX info:
https://confluencewikiprod.intra.infineon.com/display/DFDoc/Remote+Desktop+Project
+NX+System

Lab
› To create India VNC and be able to create cyw20829 workspace

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Icmpm work area setup

› Link for more details

https://confluencewikiprod.intra.infineon.com/display/DFDoc/IC+Manage
› The Project Administrator has three different tools that he will primarily use:
– icmpm – A GUI used for project maintenance. This tool allows the user to
create and modify projects.
– pm – A command line version of icmpm. This tool will be required if the Project
Administrator wants to script any common tasks.
– icmp4 – This is IC Manage’s version of the perforce p4 command. This is the
command used by Design Users to do everyday tasks such as adding, editing,
and submitting files. This tool is used by the Project Administrator to manage
the protections table (access controls).

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Icmpm work area setup- Lab
› cd /proj/gpfs/<userid>
› icmpm &
› dev_all or specific config given by CAD. Ex: dev_all_cic

Issue:
Perforce password (P4PASSWD) invalid or unset
icmp4 login
setenv P4PASSWD <passwd>

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 Project directory structure
› After populating a configuration, the users workarea physically has the following format:
– cds.lib (generated after running virtuoso/icfb for the first time)
– cds.libicm
– ddc
– abv
– atpg
– doc
– oa
– libname
– cdsinfo.tag
– data.dm
– top
– schematic
master.tag
sch.oa
– symbol
master.tag
symbol.oa
– co-developed_ddc
– oa
– libname
– cdsinfo.tag
– data.dm
– cell
cellView
– files
– vaulted_ip
– cds.lib
– oa -> /proj/gpfs/ipvault/<vaulted_ip>/<vault_release>/<vaulted_ip>/oa
– doc -> /proj/gpfs/ipvault/<vaulted_ip>/<vault_release>/<vaulted_ip>/doc
– Note that that user's cds.lib is automatically generated for that project.

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HOBTO setup

› goto/HOBTO
› Populate HOBTO scripts into work area
– cd <workarea>
– setenv DMWA <workarea>
– setenv DESIGN <workarea>
– cd <ddc>
Ex:/proj/gpfs/kicg/kicg_s40bt52radio_1.0-dev_15
cd /proj/gpfs/kicg/kicg_s40bt52radio_dev_10/s40bt52radio
make -f $DMWA/HOBTO_CIC_FLOW/common/cic_flow/Makefile prep
TASKS="atpg fv ir mvrc pnr power rcx sta syn dft v"
CELLS=cyw20829_top BRANCH=NORMAL

› Notes: ddc equivalent to top cell or top IP name

› Notes: cell equivalent to sub cell childs to the parent IP

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How to launch tools & override tools version
› cd <DESIGN>/cyw20829/pnr/cyw20829_top/run_innovus
– bsub -Ip -n 1 -J innovus innovus -wait 1000
› ** To override default Innovus version, modify the local.env file.
– Example:
– /proj/gpfs/ksek/ksek_cyw20829_1.0-dev_92/cyw20829/pnr/cyw20829_top/run_innovus/local.env
innovus installDir string "/tools/apps/local/cadence"
innovus version_amd64 string "innovus19.13"
innovus version string "INNOVUS-19.13-s080_1"
innovus version_amd64 string "INNOVUS-19.13-s080_1"
innovus version_lnx86 string "INNOVUS-19.13-s080_1"

Lab
› Be able to cd to innovus directory
› Launch innovus from the work area and check the tools version
› innovus> restoreDesign /proj/gpfs/hsjs/cyw20829/hsjs_cyw20829_1.0-
dev_61/cyw20829/pnr/cyw20829_top/run_innovus/DBS/Powerplanupd_13.enc.
dat cyw20829_top –noTiming -noTimingGraph

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LSF job queue

› https://confluencewikiprod.intra.infineon.com/display/DFDoc/Compute+Load+Sharing
Executable Description
bjobs bjobs is used to view jobs currently in the queue or recently completed. The -l
[job number] will tell why a job is PENDing. The syntax is:
bjobs [-l] [-u <user|all>] [job number]
blinfo blinfo is used to list all of the license features scheduled by LSF. The syntax is:
blinfo
blstat blstat is used to show the current status of license features scheduled by
LSF. The syntax is
blstat blstat -t <feature> blstat -c <feature>
bqueues bqueues is used to list all queues, as well as their current priority and job
limits. The syntax is:
bqueues [-l] [queue name]
bsub bsub is used to submit a job to the queue for dispatch to a compute server. The
syntax is:
bsub [-I] [-q queue] [-R resource_requirements] your_command
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Icmp4 command

The following are examples of most commonly used commands the user may run:
• Adding a file to the changelist:
icmp4 add <filename>
• Submitting the default changelist:
icmp4 submit –d “checking in a bunch of stuff”
• Editing a file:
icmp4 edit <filename>
• Looking at the users open files:
icmp4 opened –a | grep <username>
• Populating (syncing) a workspace:
icmp4 sync
• Getting file history:
icmp4 filelog <filename>
• Getting a list of all the commands:
icmp4 help commands
• Getting information on any command:
icmp4 help <command>

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Full chip analog route

Topic Details Reference

1. BROS access Sharing of PSoC6A256K_ip_integration requirements. How about cyw20829?
2. Product XLS https://svn.design.cypress.com:18080/svn/chips/trunk/s40/MXS40Sv2/CYW20829/cyw20829_psvp/SAS/CMR2.1/
3. Basic overview to load up the command
4. dbGet command to look up analog route
5. Analog route approach Innovus command for manual edits
5.1 - manual edit KICG-22 PSOC6A-256K FULLCHIP FINAL ANALOG AND POWER ROUTES FOR CFR/PR3/TO
5.2 - SPR save and load from reference database KeanSek passdown-analog route?
Fullchip analog route
5.3 KeanSek's semi - automation KSEK-108 CIC SCRIPTING - AUTO POLY SHIELD FOR ANALOG ROUTES
KSEK-110 CIC SCRIPTING - SCRIPT FOR ANALOG ROUTE PRODUCTIVITY
KSEK-112 SCRIPTING - HIERARCHICAL CHANGE LAYER
KSEK-121CIC SCRIPTING - AUTO VIA INSERTION FOR ANALOG ROUTES AND SHIELDS
6. IO Frame Generation SBHA-42 MXS40: IO FRAME GENERATION ACTIVITY STATUS (GLOBALIZE PHASE)
7.1 Database import
7.2 Resistance check

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Background of full chip analog route

› Full chip consist of IO ring area and PNR region. All digital route are done in PNR
digital implementation. There are analog routes that required NDR- Non default
routing rules that cant be routed using PNR. Ex: 2x width, coaxial shield, side
shield with different width and pwr/ground nets, off track route.
› In the current flow, this part handled by custom full chip analog route. Mainly to
connect the analog route from IO pad cells to IP placed at PNR region.
› Some projects (Austin) requires pwr/ground mesh planning on top of IP, to
complete the supply mesh from each IP to the PNR region, and from IO pad/pwr
pad/ground pad to the IP. Special requirement like star route has to be fulfilled.
› Efuse GR and ME1 guardring around the chip will be part of the custom route
also.

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 BROS access
Power Analog
route for route for Review Ticket ref
IP BROS no. PDF SOURCE review? review? ticket 512 Comment/Follow up
s40srssa_regmod 001-00259 VIEW (pdf) SOURCE (zip) Ready Ready 344839 regmod placement - IO, >50u from IO diff
vref_0p8_unbuf and right side of eco2 ME1/2 signal overlap, srss_eco_in/out shielding vias, clean up
s40srssa 002-10661 VIEW (pdf) SOURCE (zip) Ready Ready legacy ME6
s40backup 002-02764 VIEW (pdf) SOURCE (zip) Ready Ready shielding of srss_wco_out/in for ME3/4
s40sisobuck_top 002-20509 VIEW (pdf) SOURCE (zip) Ready Ready
s40usbfsphy_top 002-10841 VIEW (pdf) SOURCE (zip) Ready Ready vssusb pad, vssa, vdda, amuxbus_a/b_main
s40tk_pwrsw_sram 002-03349 VIEW (pdf) SOURCE (zip) Ready N/A
s40sramulp 002-10319 VIEW (pdf) SOURCE (zip) Ready N/A
s40flash 001-97816 VIEW (pdf) SOURCE (zip) Ready Ready 344842
s40pllsys 001-99228 VIEW (pdf) SOURCE (zip) Ready Ready
srom0_top_64k 002-10358 VIEW (pdf) SOURCE (zip) Ready N/A
mxs40smartio 002-11113 VIEW (pdf) SOURCE (zip) Ready N/A
s40efuse 002-11281 VIEW (pdf) SOURCE (zip) Ready N/A
Met5 shield needed if placed in the IO ring. Cell:mxlpcomp_s40_met5_shield. If placed in the IO ring the
GPIO cells must have end-cap cells on each
side of this IP. There must be a deep nwell guard-ring surrounding the IP
and a met5 shield connecting to a low resistance quiet ground
mxlpcomp 002-10742 VIEW (pdf) SOURCE (zip) Ready Ready 344843 (vsub_vic_lpcomp).
Not
mxs40pass 002-11127 VIEW (pdf) SOURCE (zip) Ready Ready 344840
Not
s40csdv2_top 002-10685 VIEW (pdf) SOURCE (zip) Ready Ready 344841
Ip lvl
s40iolib 002-02511 VIEW (pdf) SOURCE (zip) ready N/A
mxs40srss_clkactfllmux

General
Analog route status 344506
Power 344513
Analog IP integration 344838 326423
LEF vs analog IP matches 336344

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Product XLS

› https://svn.design.cypress.com:18080/svn/chips/trunk/s40/MXS40Sv2/Platform/M
XS40Sv2-SAS/Configuration/
› To look up information like supplies (for LVS), pins (for IO frame generation,
verification of IO placement and leadframe ARC), package (for leadframe ARC)
used for the project.

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Useful innovus command to work with analog route

› Innovus> source /proj/gpfs/slqx/20829/CMR/slqx_cyw20829_1.0-

dev_79/cyw20829/pnr/cyw20829_top/run_innovus_upfIssue_pass4/DBS/Powe
rplanupd_12.enc
Ex: /proj/gpfs/hsjs/cyw20829/hsjs_cyw20829_1.0-
dev_61/cyw20829/pnr/cyw20829_top/run_innovus/DBS/Powerplanupd_13.enc
› Tips: Innovus alias used in project
/home/kicg/cadInvalias
› Tips: scripts to query pg and analog route
source /proj/gpfs/kicg/tcl/reference/whsh/find_analog.tcl
source /proj/gpfs/kicg/tcl/reference/whsh/find_pg.tcl
find_pg or find_analog

innouvs> dbGet top.insts.instTerms.cellTerm.type analogTerm -p2 -u -

e]

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Analog route approach
› Method 1: Manual edit using Innovus command/GUI
› Innovus User Guide-> Editing Wire (page 1521)

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Analog route approach (cont)

› Method 2: SPR save and load from reference database

› 1. To select, tag and save SPR and to load in the dbs after
source /proj/gpfs/catu/innovus_scripts/spr_load_save.tcl
cic_spr_select <userclass>
cic_spr_tag <userclass>
cic_spr_save <userclass>
cic_spr_load <userclass> <SPR file pointer>
› 2. To save/load full SPR
loadSpecialRoute <SPR file pointer>
saveSpecialRoute <SPR file pointer>
› 3. To load SPR by userclass
source /proj/gpfs/kicg/spr/spr.tcl
› 4. To save SPR by userclass after edits of the day
source /proj/gpfs/kicg/spr/to_resave_spr.tcl
› 5. To delete all SPR by userclass
source /proj/gpfs/kicg/spr/deletespr.tcl
› 6. To check analog route connection
source /proj/gpfs/kicg/tcl/reference/whsh/verify_analog.tcl
› 7. To check power connection
verifyConnectivity -type all -noAntenna -noWeakConnect -noSoftPGConnect - error 99999 -
warning 50 -nets [dbGet top.pgterms.name]

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IO Frame Generation

› To be conducted by YCTA

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Database processing from Innovus to Virtuoso

› defout full def and via lef

Innovus> defOut -floorplan -noTracks -unit 1000 -usedVia -routing
./output/cyw20829_top.def
Innovus> dumpOutVias -all_via -file ./output/all_via.lef
› Note: to release files in $DESIGN/<DDC>/pnr/<CELL>/release

› defout selected instance

Innovus> selectInst [dbGet [dbGet top.insts.name -p *_overlay].name
*s40iolib*]
Innovus> selectInst [dbGet top.insts.pgTermNets.name vsub_io -p2]
Innovus> defOut -floorplan -noTracks -unit 1000 -usedVia –routing -
selected <filename>

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Generate GDS from DEF / Via LEF Output : HOBTO Flow Setup
› This is brief steps for HOBTO GDS generation: Reference MEMO : APOE 213
› https://confluencewikiprod.intra.infineon.com/pages/viewpage.action?pageId=261859571
› 1. Have a DEF / Via LEF generate from Innovus and store it in a location.
Example:
$DESIGN/cyw20829/pnr/cyw20829_top/run_innovus/output/cyw20829_top.def
$DMWA/cyw20829/pnr/cyw20829_top/run_innovus/output/all_via.lef
› Unix> setenv DESIGN <workarea> and setenv DMWA <workarea>
Example:
setenv DESIGN /proj/gpfs/whsh/whsh_cyw20829_dev_47
setenv DMWA /proj/gpfs/whsh/whsh_cyw20829_dev_47
setenv HOBTO_PCIOS 001-97729
› Unix> cd $DESIGN/cyw20829
› Unix> make -f $DMWA/HOBTO_CIC_FLOW/$HOBTO_PCIOS/cic_flow/Makefile prep
CELLS=“cyw20829_top" TASKS="v"
› Check $DESIGN/cyw20829/v/cyw20829/cyw20829_top to have the following:
Makefile
script
Generate GDS from DEF / Via LEF Output : HOBTO Flow Generating GDS
› Open ./script/cic.gen.vars.tcl and change the following variables:
DEF_FILE_PATH -> Point to the correct DEF file
VIA_LEF -> Point to the correct Via LEF file

› Unix> cd $DESIGN/cyw20829/v/cyw20829/cyw20829_top
Then start running : make def_gds
make add_ip
make sealring
make hier
make gen_fill
make add_fill

› For each make steps run, check each GDS output using “caldrv <gds name>
› To check:-
– Sealring correctly placed?
– Is there any LVS text label on it?
– Is there any overlay cells?
– Does the chip structure resemble the chip hierarchy structure?
› FYI. there are some problems regarding the Hobto GDS generation (APOE-213). The command make def_gds, make
ip_gds, make sealring are fine, but the make hier could not generate the chip gds.
Import to database to Virtuoso
› CIW
– File->Import->Stream
– Fill in Stream File, Library, Top Cell(Create new library
psoc6a256k_strmin in ICM first), the layout will be in psoc6a256k_strmin
with cell name psoc6a256k_top
– Click Options, remove anything in “Ref Lib File Name”
Resistance Check

› To be conducted by GLKH
› https://confluencewikiprod.intra.infineon.com/display/DFDoc/Resistance+Measure
ment+Tool

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Full chip PV
Topic Details Reference
1. Setup of the flow using replay file KeanSek passdown - PV
2. PV run
3. Debug of the violations. Viewing of RVC
Fullchip PV
4. Bonding diagram creation and ARC KeanSek passdown - Bonding diagram creation

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Full chip PV

› To be conducted by YCTA
› https://confluencewikiprod.intra.infineon.com/display/DFDoc/DRC%2C+Stress
%2C+Latchup%2C+and+Softconn

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Database processing from Innovus to Virtuoso (cont)

› Method1: DEFin2OA flow (Legacy method)

- This flow automatically defin the DEF to Virtuoso Layout View.
› Method2: HOBTO CIC Flow to generate GDS from DEF. (New method)
– Generate GDS from DEF and merge with any other GDS (overlay etc.)
provided.
– Memo APOE 213
Etech Top Level
Chip structure
cyw20829_top LVS Text

cyw20829_top_dummy_fill cyw20829_logo_partnum_cell

cyw20829_top_defin
cyw20829_top_overlay
cyw20829_top_sealring 1. DEFin2OA
2. HOBTO CIC Flow

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Chip GDS Structure (cont)
Etech Top Level This packaging GDS will be used for tape out

cyw20829_top This gds level will be used for PV. It’s the implementation level GDS.

These are LVS Text labels (AL_CAD TEXT) that will be used for PV and to generate plots.
LVS Text

This contains all IPs/IOs/routings/standard cells. This GDS will be generated using output
cyw20829_top_defin DEF / Via LEF from Innovus using either DEFin2OA or HOBTO CIC Flow GDS generation.

Contains seal ring. Layout is checked in at:

cyw20829_top_sealring Library : cyw20829 / Cell : cyw20829_top_sealring / View : layout
Contains IO guard rings / Efuse guard rings / analog poly shielding+cont / ME6 short layers
cyw20829_top_overlay for any additional route to fix the connection and drc at top level
Library : cyw20829 / Cell : cyw20829_top_overlay / View : layout
Contains logo / mark / copyright / part numbers / year
cyw20829_logo_partnum_cell Library : cyw20829 / Cell : cyw20829_logo_partnum_cell / View : layout

Contains waffling/tiling for diffusion and metal layers. This GDS will be generate using
cyw20829_top_dummy_fill HOBTO CIC Flow or it can be generated manually using PV dummy_pd and dummy_met
Generating Chip Abstract : Run DEFin2OA Setup (Method1)

› Output and save a DEF from Innovus that contains only IO/Block with pads.
selectInst [dbGet top.insts.instTerms.net.name *_pad -p3]
defOut -selected ./out/cyw20829_top.def
› Defin into Virtuoso.
unix > setenv $DESIGN to your workarea.
unix> cp /home/ksek/cic/vir/s40s_def_to_pv.sh $DESIGN
unix> cp –r /home/ksek/cic/vir/lefdef2pv $DESIGN
› Modify the “master_replay.txt” inside $DESIGN/lefdef2pv for the
following parameters:
-top_cell <Top Cell Name> e.g. cyw20829_top
-lib_name <Library name> e.g. cyw20829
-pnr_def <Path to DEF> e.g. /proj/gpfs/ksek/ksek_cyw20829_1.0-
dev_92/cyw20829/pnr/cyw20829_top/run_innovus/out/cyw20829_top.def

Lab
› Create your own library inside IC Manage.
› Copy the following top cell layout “cyw20829_top” from library “cyw20829” to newly created
library
› Change the parameter “-lib_name” inside master_replay.txt to “-lib_name <new library>”
Generating Chip Abstract : Run DEFin2OA (Method1)

› Unix> cd $DESIGN
› Unix> ./s40s_def_to_pv.sh
› A layout view will be created inside library <new library> example:
Library : cyw20829_training
Cell : cyw20829_defApr101040_inApr101916
› Top level cell is cyw20829_top and it should contain only :
- seal ring
- cyw20829_defApr101040_inApr101916
- cyw20829_logo_partnum_cell
- top level pin text (AL_CAD TEXT)
› Check the following
– Die aspect Ratio (X : Y in um) before shrink without scribe
– Total Die Area X x Y= ?
– Not to use DEFin2OA
– Need to streamout to gds
– Some Vias will be missing.
HOBTO Generate GDS from DEF / Via LEF Output :Method2
› Open ./script/cic.gen.vars.tcl and change the following variables:
DEF_FILE_PATH -> Point to the correct DEF file
VIA_LEF -> Point to the correct Via LEF file

› Unix> cd $DESIGN/cyw20829/v/cyw20829/cyw20829_top
Then start running : make def_gds
make add_ip
make sealring
make hier
make gen_fill
make add_fill

› For each make steps run, check each GDS output using “caldrv <gds name>
› To check:-
– Sealring correctly placed?
– Is there any LVS text label on it?
– Is there any overlay cells?
– Does the chip structure resemble the chip hierarchy structure?
› FYI. there are some problems regarding the Hobto GDS generation (APOE-213). The command make def_gds, make
ip_gds, make sealring are fine, but the make hier could not generate the chip gds.
Generate GDS from DEF / Via LEF Output : HOBTO Flow (Workaround)
1. Create directory “gds” at $DESIGN
Example:
/proj/gpfs/whsh/whsh_cyw20829_dev_47/gds
2. Streamout gds from the following cells:
Library : cyw20829 / Cell : cyw20829_top_sealring / View : layout
Library : cyw20829 / Cell : cyw20829_top_overlay / View : layout
Library : cyw20829 / Cell : cyw20829_top_lvs_text / View : layout_bk
Library : cyw20829 / Cell : cyw20829_logo_partnum_cell / View : layout
3. $DESIGN/gds should contain the following gds:
cyw20829_logo_partnum_cell.gds.gz
cyw20829_top_lvs_text.gds.gz
cyw20829_top_overlay.gds.gz
cyw20829_top_sealring.gds.gz
4. Copy
/proj/gpfs/whsh/whsh_cyw20829_dev_47/cyw20829/v/cyw20829/cyw20829_top/script/cic.gen.v
ars.tcl to replace your default cic.gen.vars.tcl
Change $DESIGN to your own directory
5. Copy
/proj/gpfs/whsh/whsh_cyw20829_dev_47/cyw20829/v/cyw20829/cyw20829_top/gds/generate/gen
_chip_hier/merge_gds_data.tcl to replace your
$DESIGN/cyw20829/v/cyw20829/cyw20829_top/gds/generate/gen_chip_hier/merge_gds_data.tcl
Generate GDS from DEF / Via LEF Output : HOBTO Flow (Workaround)
6. Go to $DESIGN/cyw20829/v/cyw20829/cyw20829_top
Then start running : make def_gds
make add_ip
7. Still at $DESIGN/cyw20829/v/cyw20829/cyw20829_top
Start running using the following command : calibredrv
./gds/generate/gen_chip_hier/merge_gds_data.tcl
Notes:
1. This workaround flow with custom edit “merge_gds_data.tcl” will create
GDS up to cyw20829_top and merge with all the required cells (overlay,
sealring, partnum, lvs_text)
2. This will also flatten cell “cyw20829_top_lvs_text” to create LVS
labels at cyw20829_top level.
3. Newly created GDS can be used for PV run.
Make gen_top
Copy /proj/gpfs/whsh/whsh_cyw20829_dev_47/config/common_setup.tcl to your
$DESIGN/config/ overwriting your common_setup.tcl
LVS text: To generate pad labels (Innovus)

› Copy file below to run_innovus dir:

/proj/gpfs/ksek/ksek_cyw20829_1.0-
dev_92/cyw20829/pnr/cyw20829_top/run_innovus/s40s_text.map

› Source script below:

source /home/ksek/cic/tcl/printNStreamTermLabel_2.tcl

› Make sure all the IO pad are selected, if not, type command below:
selectInst [dbGet top.insts.instTerms.net.name *_pad -p3]

› Run function below:

printNStreamTermLabel {print stream} {termLabel.txt
./out/cyw20829_top_lvs_text.gds.gz} {"" s40s_text.map} selected {pad} {} {} {}

2021-03-09 restricted Copyright © Infineon Technologies AG 2021. All rights reserved. 33

LVS Text: To generate pad labels (Virtuoso)

› Source script below:

load "/home/ksek/cic/sk/createLabelFromFile.il“

› Run function below:

createLabelFromFile("/proj/gpfs/ksek/ksek_cyw20829_1.0-
dev_92/cyw20829/pnr/cyw20829_top/run_innovus/termLabel.txt" 13
13 0.5)

2021-03-09 restricted Copyright © Infineon Technologies AG 2021. All rights reserved. 34

Create Full chip view
1. Full chip cellview cyw20829_top should contain:
– cyw20829_defApr101040_inApr101916 (defin from Innovus)
– Origin at (13,13)
– cyw20829_top_sealring
– Origin at (0,0)
– Create using cell (Library:s40cytech_1p6m1t0h0a1u,
– Cell Name: sealring_bigCorner)
– Sealring size (x, y) = die size (before shrink) OR
– Sealring size (x, y) = defin block size + 2x13um
– cyw20829_logo_partnum_cell
– Instantiate anywhere empty, need to confirm with project lead.
– Create using cell ( Library:s40cytech_1p6m1t0h0a1u, Cell Name:
– partNum (text and layer can be changed)
– s40cytech_gen_trademark_al_rdl
– s40cytech_gen_copy_al_rdl
– s40cytech_gen_ifx_logo_al_rdl
– cyw20829_top_iot
– Contains s40bt52radio/ s40adcmic/ s40power_pmu/ s40power_hvldo30m
– Please confirm the coordinates and orientations of the blocks is same as in Innovus.
– All the pad labels (using layer AL_CAD TEXT) checkout misc
Generating Chip Abstract : Run Chip Abstract
› Open layout view “cyw20829_top”.
Go to “Cypress” -> “Bonding Tools”
-> “Generate Chip Abstract”
› Options as shown on the right figure:
- Text layer : AL_CAD TEXT
- Top level text choice : YES
- Logo CellName : s40cytech_gen_logo_al_rdl
- Logo CellName : cyw20829_logo_partnum_cell
- Scribe : 80 / 80
- CellName Chip Abstract : cyw20829_chip_abstract
- User Library Name : cyw20829
- Overwrite exists : YES
- Pad Name Label Size : 10, 15, 20 (Up to you)
- Shrink Factor : 0.9 (Important)

– Notes before create abstract:

– 1. Run DRC to make sure pad-to-pad spacing (AL_RDL at least 2um) is met.
– 2. Make sure cyw20829_chip_abstract is not in editing mode.
– - In editing mode, the layout view will be locked.
– - This prevent the stream-in process of the abstract (with shrinked size) to overwrite the layout.
Generating Chip Abstract : Chip Abstract (Post-processing)
› Open layout abstract view
“cyw20829_chip_abstract”.
› Delete any label found at 0,0

› Stretch all four corners by 4um, making each

side a total width of 40um(equivalent to scribe
line of 80um x 80um)
– Bug of the script that shrink the scribe line
from 40um to 36um, the scribe line should
not be shrink.
› Total die size measuring from edge to edge
should be: ?
› Check die aspect ratio ( X : Y in um) after
shrink with scribe
› Check total die area X x Y= ?
Stream in package or leadframe GDS into Virtuoso
1. Go to $DESIGN
cd /proj/gpfs/ksek/ksek_cyw20829_1.0-dev_92
2. Invoke lmt GUI:
lmt&
3. Fill options as:
Package Name : QFN/TQFP
(Click Button “Package Name)
Lib Name : cyw20829
Pin Count : 68/68
4. Click Search
5. Select the package GDS
– Confirm with packaging team on which
GDS to use
6. Click StreamIn
** GDS will be stream-in into Virtuoso (cell
name: e.g. a129800)
Create bonding diagram cellview
1. Create empty layout view:
– E.g. Library: cyw20829, CellName: cyw20829_bd_68qfn
2. Instantiate both chip abstract and package instance into the empty layout.
– cyw20829_chip_abstract at (0,0), R0
– A129800 at (0,0), R0
– **Orientation of chip_abstract is based on the pin-to-pad mapping.
Create Pin2 pad mapping
› Ppt from KSEK
Autobonder

1. Open layout view cyw20829_chip_abstract.

2. Go to pulldown menu “Cypress->Bonding Tools->Autobonder”
3. Fill options as:
Assembly Sites: : ASEK
Package Family : Leadframe (for TQFP) or QFN
Directives File Name : <Path to pin-to-pad mapping file>
** Refer to KSEK#081 to generate the pin-to-pad mapping file from Product XLS
(SAS).
Autobonder (cont)
4. Delete all y1 layers if any.
− y1 is just a processing layer for autobonder.
5. Pull the wires bond to the edge of DBAREA
layer.

Initial end of
wire bond
Autobonder (cont)
› For TQFP packages, connect at least one ground pad to die paddle, consult chip
lead on which pad to be connected.
ARC check
› Open layout view cyw20829_chip_abstract.
› Go to “Cypress” -> “Bonding Tools” -> “Assembly Rules
Checker”
› Fill options as:
– Assembly Sites: : ASEK
– Package Family : Leadframe
(for TQFP) or QFN
– Die Attach Type : Epoxy
– Bond Wire Materia : Cu
– Die Thickness : 275 (TQFP)
or 250 (QFN)
– Package Thickness : 1

› Fix any errors that being found.

– - Either fix by:
– 1. Move the bondwires (on pin end).
– 2. Move location (x,y) of abstract
together with all bond wires.
– 3. Request to move IO pad
**Arc report can be found in ARC run path
– E.g. arc_report_cyw20829_bd_64tqfp.csv
Generating Chip Abstract : Extracting Pad Coordinates
› At Virtuoso CIW, load the following script “load
/home/whsh/skill_library/padcoordinates.il”
› Run the function using command at CIW:
› print_pad_order(“south-0”)
› After running, it will create a csv file at /home/<Initial>/
› For more information on this tool, please refer to memo SSNR-105

› Please check the extracted numbers of pad versus product SAS XLS
Reference of cyw20829
› Check out package cell name/leadframe used for bonding diagram
– Example: 64TQFP-EPAD, 68QFN and 80TQFP
– Cyw20829:
Library: cyw20829
Cell: cyw20829_top_bd
View: layout
› Pin2 pad mapping file
/proj/gpfs/ksek/ksek_cyw20829_1.0-dev_92/cyw20829/mfg/bonding/40-QFN_pintopad_mapping.txt
/proj/gpfs/ksek/ksek_cyw20829_1.0-dev_92/cyw20829/mfg/bonding/56-QFN_pintopad_mapping.txt
–
› Chip abstract and bonding diagram GDS
Library: cyw20829
Cells:
cyw20829_56QFN_A29417_0
cyw20829_40QFN_A29221_A
cyw20829_40QFN_A29222_B

› ARC
/proj/gpfs/ksek/ksek_cyw20829_1.0-dev_92/v/cyw20829/cyw20829_56QFN_A29417_0 – Clean
/proj/gpfs/ksek/ksek_cyw20829_1.0-dev_92/v/cyw20829/cyw20829_40QFN_A29221_A – Clean
/proj/gpfs/ksek/ksek_cyw20829_1.0-dev_92/v/cyw20829/cyw20829_40QFN_A29222_B – 34 Errors
related to automotive, should be able to ignored.
Tips from Kean Sek
› Misc

› Issues

› Scripting

› HOBTO GDS Generation