Seat No.: ________ Enrolment No.

___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER– IV(NEW) EXAMINATION – SUMMER 2023
Subject Code:3140707 Date:13-07-2023
Subject Name:Computer Organization & Architecture
Time:10:30 AM TO 01:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.

Marks
Q.1 (a) Write the name of basic computer registers with their functionalities. 03
(b) Discuss 4-bit binary adder with neat diagram. 04
(c) Enlist various kinds of addressing modes. Explain any five of same and support 07
your answer by taking small example.

Q.2 (a) Write sequence of microoperations to execute the following instructions: 03

- AND
- STA
(b) Write assembly language program to subtract two numbers. 04
(c) Write two address, one address and zero address instructions program for the 07
following arithmetic expression:
X = (A + B) * (C – D / E) + F * G
OR
(c) Assume A = + 6 and B = + 7, apply Booth algorithm for multiplying A and B. 07
Make necessary assumptions if required.

Q.3 (a) Explain Flynn’s classification for computers in brief. 03

(b) Draw the flowchart for first pass of assembler and explain the same in brief. 04
(c) Elaborate CPU-IOP communication. 07
OR
Q.3 (a) Explain pipeline conflicts in brief. 03
(b) Discuss three state bus buffers with neat diagram. 04
(c) Write a detailed note on associative memory. 07
Q.4 (a) Explain DMA in brief. 03
(b) Write a note on SIMD array processor. 04
(c) A computer uses a memory unit with 256K words of 32 bits each. A binary 07
instruction code is stored in one word of memory. The instruction has four
parts: an indirect bit, an operation code, a register code part to specify one of 64
registers, and an address part.
1. How many bits are there in operation code, the register code part and the
address part?
2. Draw the instruction word format and indicate the number of bits in
each part.
3. How many bits are there in the data and address inputs of the memory?
OR

Q.4 (a) Write a brief note on memory hierarchy. 03

(b) In certain scientific computations it is necessary to perform the arithmetic 04
1
 operation (Ai + Bi) * (Ci + Di) with a stream of numbers. Specify pipeline
configuration to carry out this task. List the contents of all registers in the
pipeline for i=1 through 4.
(c) Discuss microprogrammed control organization with neat diagram. 07

Q.5 (a) Perform A – B (subtract) operation for the following numbers using signed 03
magnitude number format. (Write necessary assumptions if required)
A = + 11 and B = - 6
(b) Explain status bit conditions with neat diagram. 04
(c) Discuss cache coherence problem in detail. 07
OR
Q.5 (a) Write the difference(s) between arithmetic shift left and logical shift left 03
instruction. Support your answer with proper illustration.
(b) State the differences between RISC and CISC. 04
(c) Explain any two types of mapping procedures when considering the 07
organization of cache memory.

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2
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–IV (NEW) EXAMINATION – WINTER 2023
Subject Code:3140707 Date:19-01-2024
Subject Name: Computer Organization & Architecture
Time: 10:30 AM TO 01:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.

Marks

Q.1 (a) Draw the block diagram of a hypothetical basic computer. 03

(b) Show different ways to represent fixed-point positive integers including 04
zero.
(c) Explain using flowchart the working of Booth’s multiplication algorithm of 07
signed-2’s complement numbers.

Q.2 (a) Which address sequencing capabilities are required in a control memory? 03
(b) Explain any four Arithmetic operations carried out by ALU. 04
(c) Discuss various memory hierarchies. 07
OR
(c) Explain the concept of Address Translation and working of the Translation 07
Look-Aside Buffer.

Q.3 (a) Discuss the importance of “control word” in a processor. 03

(b) Justify the use of STA instruction in assembly program with an example. 04
(c) Apply J K flip-flops to design a 3-bit synchronous binary counter. 07
OR
Q.3 (a) Analyze the 20-bits microinstruction code format with 7 bit used for address. 03
(b) Apply BUN instruction in assembly program that needs to use a looped sub- 04
routine to check a flag.
(c) Apply the combinational circuits to design a 4-bit adder/subtracter circuit 07
which performs subtraction using 2’s complement.

Q.4 (a) Calculate and show the number of clock cycles required to execute BSA 03
instruction.
(b) Write assembly program for the arithmetic shift-left operation on a number 04
stored in register B. Stop the program in case of overflow.
(c) What is the fundamental difference between a subroutine call and an interrupt 07
request? Analyze the possibility of common memory stack for both.
OR
Q.4 (a) Show the working of LDA instruction using RTL. 03
(b) Write a program in assembly language to multiply two numbers in registers 04
B and C in case the processor has only ADD instruction.
(c) A subroutine return address can be stored in an index register instead of a 07
stack. Analyze the advantages and disadvantages of both configurations.

Q.5 (a) A RAM operates with 8-bit data bus, 2 chip select lines and 7-bit address 03
lines. Calculate the number of such RAM chips required to have 512 bytes
of main memory.

1
 (b) An address space is specified by 24 bits and the corresponding memory space 04
by 16 bits. How many words are there in the address space and in the memory
space?
(c) Discuss various Dynamic Arbitration Algorithms for Interprocessor 07
Arbitration.
OR
Q.5 (a) Calculate the size of a ROM chip which operates using 8-bit data bus, two 03
chip select lines and 9-bit address bus.
(b) How many 128 x 8 RAM chips are needed to provide a memory capacity of 04
4096 bytes?
(c) Discuss in brief the interconnection structures of a multiprocessor system. 07

**********

2
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER– IV EXAMINATION – SUMMER 2020
Subject Code: 3140707 Date:27/10/2020
Subject Name: Computer Organization & Architecture
Time: 10:30 AM TO 01:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.

Marks

Q.1 (a) Enlist register reference instructions and explain any one of them in 03
detail.
(b) What is combinational circuit? Explain multiplexer in detail. How 04
many NAND gates are needed to implement 4 x 1 MUX?
(c) Draw the flowchart for instruction cycle and explain. 07

Q.2 (a) What is RAM and ROM? 03

(b) One hypothetical basic computer has the following specifications: 04
Addressing Mods = 16
Total Instruction Types = 4 (IT1, IT2, IT3, IT4)
Each of the instruction type has 16 different instructions.
Total General-Purpose Register = 8
Size of Memory = 8192 X 8 bits
Maximum number of clock cycles required to execute one instruction
= 32

Each instruction of the basic computer has one memory operand and
one register operand in addition to other required fields.
a. Draw the instruction word format and indicate the number of
bits in each part.
b. Draw the block diagram of control unit.

(c) Write an assembly language program to find the Fibonacci series up 07

to the given number.
OR
(c) Write an assembly language program to find average of 15 numbers
stored at consecutive location in memory.

Q.3 (a) Which are different pipeline conflicts. Describe. 03

(b) What is assembler? Draw the flowchart of second pass of the 04
assembler.
(c) Write a note on arithmetic pipeline. 07
OR
Q.3 (a) What is address sequencing? Explain. 03
(b) Design a simple arithmetic circuit which should implement the 04
following operations: Assume A and B are 3 bit registers.
Add : A+B, Add with Carry: A+B+1, Subtract: A+B’, Subtract with
Borrow: A+B’+1, Increment A: A+1, Decrement A: A-1, Transfer A:
A

1
 (c) Explain how addition and subtraction of signed data is performed if a 07
computer system uses signed magnitude representation.

Q.4 (a) Enlist different status bit conditions. 03

(b) What is addressing mode? Explain direct and indirect addressing mode 04
with example.
(c) What is cache memory address mapping? Which are the different 07
memory mapping techniques? Explain any one of them in detail.
OR
Q.4 (a) Differentiate isolated I/O and memory mapped I/O. 03
(b) Compare and contrast RISC and CISC. 04
(c) Explain booth’s multiplication algorithm with example. 07

Q.5 (a) What is associative memory? Explain. 03

(b) Differentiate between paging and segmentation techniques used in 04
virtual memory.
(c) Write a note on asynchronous data transfer. 07
OR
Q.5 (a) Write about Time-shared common bus interconnection structure. 03
(b) Explain the working of Direct Memory Access (DMA). 04
(c) Write a note on interprocess communication and synchronization. 07

*********

2
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–IV (NEW) EXAMINATION – SUMMER 2021
Subject Code:3140707 Date:06/09/2021
Subject Name:Computer Organization & Architecture
Time:02:30 PM TO 05:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.

Marks
Q.1 (a) State differences between hardwired control unit and 03
microprogrammed control unit.
(b) Explain register stack and memory stack. 04
(c) Show the contents of registers E, AC, BR, QR and SC during the 07
process of multiplying 11111 with 10101.

Q.2 (a) Write down RTL statements for the fetch and decode operation 03
of basic computer.
(b) Define pipelining. For arithmetic operation (Ai *Bi + Ci) with a 04
stream of seven numbers (i=1 to 7). Specify a pipeline
configuration to carry out this task.
(c) Write a program to evaluate the arithmetic statement: 07
A*B+C*D+E
i. Using an accumulator type computer.
ii. Using a stack organized computer.
OR
(c) A non-pipeline system takes to process a task. The same task 07
can be processed in a six segment pipeline with a clock cycle of
10ns. Determine the speedup ratio of the pipeline for 100 tasks.
What is the maximum speed up that can be achieved?
Q.3 (a) List down six major characteristics of RISC processors. 03
(b) Explain how (r-1)’s complement is calculated. Calculate 9’s 04
complement of 546700.
(c) Elaborate CPU-IOP communication. 07
OR
Q.3 (a) List and explain major instruction pipeline conflicts. 03
(b) Define RTL. Give block diagram and timing diagram of transfer 04
of R1 to R2 when P=1.
(c) Elaborate content addressable memory (CAM). 07
Q.4 (a) Explain memory hierarchy in brief. 03
(b) Draw and explain flowchart for first pass of assembler. 04
(c) Explain using a flowchart how address of control memory is 07
selected in microprogrammed control unit.
OR
Q.4 (a) Briefly explain DMA. 03
(b) Write assembly level program to subtract two given numbers. 04
(c) Write the symbolic microprogram routine for the BSA 07
instruction. Use the microinstruction format of basic
microprogrammed control unit.

1
Q.5 (a) How many AND gates and Adders will be required to multiply a 03
5 bit number with a 3 bit number? Also say size of adder (bits).
How many bits will be there in the result?
(b) What do you mean by cache memory? Justify the need of cache 04
memory in computer systems.
(c) Discuss multistage switching network with neat diagrams. 07
OR
Q.5 (a) Explain the non-restoring methods for dividing two numbers. 03
(b) Discuss source-initiated transfer using handshaking in 04
asynchronous data transfer.
(c) Elaborate cache coherence problem with its solutions. 07

*******************

2
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–IV (NEW) EXAMINATION – SUMMER 2022
Subject Code:3140707 Date:29-06-2022
Subject Name:Computer Organization & Architecture
Time:10:30 AM TO 01:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS

Q.1 (a) What is binary and decimal equivalent of F8 hexadecimal value? 03

(b) Write Steps for two n digit numbers subtraction in base r. 04
(c) List and explain Memory reference instructions in detail. 07

Q.2 (a) What is arithmetic micro operation? 03

(b) What is RAM and ROM? 04
(c) Draw and explain working of 4 bit binary adder. 07
OR
(c) State and Explain any seven logic micro operation. 07

Q.3 (a) List out Register for basic computer. 03

(b) Explain register reference instruction format. 04
(c) Explain register transfer using block diagram and timing diagram. 07
OR
Q.3 (a) Draw and explain control unit diagram for basic computer. 03
(b) State various phases of instruction cycle. 04
(c) Explain any four input output reference instruction. 07

Q.4 (a) Draw flowchart of first pass assembler. 03

(b) Write assembly language program to add two numbers. 04
(c) Write assembly language program to multiply two numbers. 07
OR
Q.4 (a) What is address sequencing? 03
(b) Write assembly language program to subtract one number from other 04
number.
(c) Explain booth’s multiplication algorithm with example. 07

Q.5 (a) Explain register stack. 03

(b) What is difference between two address and three address instructions? 04
(c) Write a note on asynchronous data transfer. 07
OR
Q.5 (a) What is difference between direct and indirect addressing mode? 03
(b) Explain arithmetic pipeline. 04
(c) Write a short note on virtual memory. 07

*************

1
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE- SEMESTER–IV (NEW) EXAMINATION – WINTER 2020
Subject Code:3140707 Date:15/02/2021
Subject Name:Computer Organization & Architecture
Time:02:30 PM TO 04:30 PM Total Marks:56
Instructions:
1. Attempt any FOUR questions out of EIGHT questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.

MARKS
Q.1 (a) What is PSW? Explain each bit of it 03
(b) Write ALP for addition of 10 numbers 04
(c) List and explain Memory reference instructions in detail 07

Q.2 (a) Design a digital circuit for 4-bit binary adder 03

(b) Explain 4 bit arithmetic circuit with suitable diagram. 04
(c) Draw and briefly explain flowchart for second pass of assembler. 07

Q.3 (a) Explain any three register reference instruction in detail. 03

(b) Explain BCD adder in brief 04
(c) Draw and explain micro program sequencer circuit with diagram. 07

Q.4 (a) State the differences between hardwired control and micro programmed 03
control.
(b) Explain hardware implementation of common bus system using three- 04
State buffers. Mention assumptions if required.
(c) Explain delay load and delay branch with respect to RISC pipeline. 07

Q.5 (a) Draw and briefly explain flowchart for first pass of assembler 03
(b) State the major characteristics of RISC processor 04
(c) Elaborate 4-segment instruction pipeline with neat sketches. 07

Q.6 (a) State the major characteristics of CISC processor 03

(b) List various types of addressing modes and explain any four of them. 04
(c) What is virtual memory? Explain relation between address space and 07
memory space in virtual memory system.

Q.7 (a) Briefly explain source initiated transfer using handshaking. 03

(b) Differentiate Programmed I/O and Interrupt initiated I/O 04
(c) Write a short note on associative memory. 07

Q.8 (a) How main memory is useful in computer system? Explain the memory 03
address map of RAM and ROM.
(b) Explain daisy chain priority interrupt 04
(c) Explain CPU-IOP communication with diagram. 07

*************

1
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–IV (NEW) EXAMINATION – WINTER 2021
Subject Code:3140707 Date:03/01/2022
Subject Name:Computer Organization & Architecture
Time:10:30 AM TO 01:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.

Marks

Q.1 (a) Explain three state buffers. 03

(b) Describe BUN and BSA memory reference instructions in detail. 04
(c) What is interrupt? Describe interrupt cycle with neat diagram. 07

Q.2 (a) Differentiate assembly language and machine language. 03

(b) What is the need of common bus? Draw common bus cycle. 04
(c) Write an assembly language program to find whether the given number 07
is prime or not.
OR
(c) Write an assembly language program to find factorial of the given
number.

Q.3 (a) Define followings: 03

1. Control Memory
2. Control Word
3. Control Address Register
(b) Draw the flowchart of first pass of the assembler and explain working 04
of the same.
(c) What is the significance of pipelining in computer architecture? Write 07
a note on instruction pipeline.
OR
Q.3 (a) What is address sequencing? Explain. 03
(b) Construct a 4-bit adder-subtractor circuit. 04
(c) What addressing mode means? Explain any three addressing modes in 07
detail with example.

Q.4 (a) Enlist the characteristics of RISC. 03

(b) Write a program to evaluate X = (a*b)/c+d in two address and three 04
address instruction formats.
(c) Draw neat and clean flowchart for divide operation. Explain with 07
example.
OR
Q.4 (a) Differentiate isolated I/O and memory mapped I/O. 03
(b) Describe pipeline conflicts. 04
(c) What is cache memory address mapping? Compare and contrast direct 07
address mapping and set-associative address mapping.

Q.5 (a) What is the importance of virtual memory? 03

(b) Explain multiport memory and crossbar switch with reference to 04
interconnection structures in multiprocessors.
1
 (c) Assume a computer system uses 5 bit (1 sign + 4 Magnitude) registers 07
and 2’s complement representation. Perform multiplication of number
10 with the smallest number in this system using booth algorithm.
Show step-by-step multiplication process.
OR
Q.5 (a) What is cache coherence? Describe. 03
(b) A 4-way set-associative cache memory unit with a capacity of 16 KB 04
is built using a block size of 8 words. The word length is 32 bits. The
size of the physical address space is 4 GB. How many bits for the will
be required for TAG field?
(c) Which are the different ways to transfer data to and from peripheral 07
devices? Explain any one of them in detail.

2
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–IV(NEW) EXAMINATION – WINTER 2022
Subject Code:3140707 Date:15-12-2022
Subject Name:Computer Organization & Architecture
Time:10:30 AM TO 01:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS
Q.1 (a) Draw the block diagram of 4-bit combinational circuit shifter. 03
(b) Construct diagram of common bus system of four 4-bits registers with 04
diagram.
(c) What is the role of sequence counter(SC) in control unit? Interpret its 07
concept with the help of its three inputs using diagram.

Q.2 (a) List out names of eight main registers of basic computer with their 03
symbolic name and purpose.
(b) Summarize following addressing modes with example. 04
1) Implied mode 2) Register mode
(c) Which are the different phases of Instruction Cycle? Describe Register 07
transfer for fetch phase with its diagram.
OR
(c) Define: microinstruction; Identify different types of 16 bits instruction 07
formats for basic computer using figure.

Q.3 (a) Use BSA and BUN instruction with example and diagram. 03
(b) Criticize Three-Address Instructions and Zero address instruction with 04
common example.
(c) Describe how control unit determine instruction type after the 07
decoding using flowchart for instruction cycle.
OR
Q.3 (a) Prepare flowchart of CPU-IOP communication. 03
(b) Differentiate RISC and CISC architecture. 04
(c) What is cache memory? Interpret direct addressing mapping with 07
diagram.

Q.4 (a) Draw and criticize memory hierarchy in a computer system. 03

(b) Write an Assembly level program for addition of 50 numbers. 04
(c) Draw the flowchart of first pass of the assembler and explain working 07
of the same.
OR
Q.4 (a) Interpret the following instructions: INP, ISZ and LDA 03
(b) Write an Assembly level program to move one block of data to another 04
location.
(c) List out modes of transfer. Formulate direct memory access technique 07
in detail.

Q.5 (a) Summarize major hazards in pipelined execution. 03

1
 (b) What is a data dependency conflict in instruction pipeline? 04
Recommend solutions for data dependency conflicts.
(c) Demonstrate four-segment instruction pipeline in detail 07
OR
Q.5 (a) Sketch Microinstruction code format. Quote BR and CD field in brief. 03
(b) Compare following terms: 04
1. Write through-cache and Write back cache.
2. Spatial locality and Temporal locality
(c) Elaborate flynn’s classification scheme with proper diagram. 07

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