Lecture 2 Transistors BJT and FET - Updated 2 (Corrected)

Lecture #2: Transistors
BJT and FET

Modified by Mai Linh, PhD
Faculty of Electronics and
Telecommunications,
VNU-University of Engineering and
Technology
1
Outline
• Bipolar Junction Transistor (BJT)
✓ Simplified Structure and Modes of Operation
✓ I-V Characteristics
✓ Biasing of the BJT
✓ BJT Circuit at DC
✓ Small-Signal Operating Model
• Field Effect Transistor (FET)
✓ Introduction
✓ JFET and MOSFET
✓ Small-Signal Operating Model
Textbook: Adel. S. Sedra, Kenneth C. Smith. Microelectronic
Circuits. Oxford University Press. 2011/2014 (Chapter 5 & 6).
2
1. Bipolar Junction Transistor (BJT)
1.1 Simplified Structure and Modes of Operation
❖ BJT is constructed with 3 doped semiconductor regions separated by 2 PN-junctions
❖ 3 regions are called emitter (E), base (B), and collector (C).
❖ The base is lightly doped and very narrow compared with the heavily doped emitter
& moderately collector.
❖ It is used as an electrical signal amplifier or an electronic switch.
Fig.: Cross-section of an npn BJT.

3
NPN transistor PNP transistor
BJT Modes of Operation

Mode EBJ CBJ
Cutoff Reverse Reverse
Active Forward Reverse
Saturation Forward Forward
4
Operation of the npn-Transistor
in the Active Mode
• Active mode is “most important.”
• Two external voltage sources are required for biasing to
achieve it.
• Forward bias on emitter-base junction will cause current
to flow.
• This current has two components:
Fig.: Current flow in an npn transistor biased
– electrons injected from emitter into base to operate in the active mode.
– holes injected from base into emitter.
• It will be shown that first (of the two above) is desirable. This is achieved with heavy doping of emitter,
light doping of base.
• emitter current (iE) – is current which flows across EBJ. Flows “out” of emitter lead
• minority carriers – in p-type region.
‒ These electrons will be injected from emitter into base.
‒ Opposite direction.
• Because base is thin, concentration of excess minority carriers within it will exhibit constant gradient.
5
np ( x )=concentration of minority carriers a position x (where 0 represents EBJ boundary)np 0
np 0 = thermal-equilibrium value of minority carrier (electron) concentration in base regionnp 0 Straight line represents
vBE =voltage applied across base-emitter junctionnp 0
VT =thermal voltage (constant)np 0 constant gradient.
(eq1) np ( 0 ) = np 0 evBE /VT
Oxford University Publishing

Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith
(0195323033)
Current Flow
• Concentration of minority carrier

np at boundary EBJ is defined by
np ( x )=concentration of minority carriers a position
(eq1). x (where 0 represents EBJ boundary)np 0
np 0 = thermal-equilibrium value of minority carrier
• Concentration of minority (electron) concentration in base regionnp 0
VT =thermal voltage (constant)np 0
carriers np at boundary of CBJ is
(eq1) np ( 0 ) = np 0 evBE /VT
zero.
– Positive vCB causes these electrons
to be swept across junction.
Current Flow
• Tapered minority-carrier
AE =cross-sectiona area of the base-emitter junction
concentration profile exists. q = magnitude of the electron charge
Dn = electron diffusivity in base
W = width of base
• It causes electrons injected into
base to diffuse through base dnp ( x )
(eq2) In = AE qDn
toward collector. dx
 −dnp ( 0 ) 
• As such, electron diffusion current (eq2) In = AE qDn  
(In) exists.  W 
this simplification
may be made if
gradient assumed
to be straight line
Current Flow
• Some “diffusing” electrons will combine with holes (majority carriers in

base).
• Base is thin, however, and recombination is minimal.
• Recombination does, however, cause gradient to take slightly curved
shape.
– The straight line is assumed.
np ( x )=concentration of minority carriers a position x (where 0 represents EBJ boundary)np 0
np 0 = thermal-equilibrium value of minority carrier (electron) concentration in base regionnp 0 Recombination causes
VT =thermal voltage (constant)np 0 actual gradient to be
(eq1) np ( 0 ) = np 0 evBE /VT curved, not straight.
The Collector Current
• It is observed that most diffusing

(eq3) iC = IS evBE /VT
electrons will reach boundary of
collector-base depletion region. −−−−−−−−−−−−−−−−−−
• Because collector is more positive AE qDn np 0
saturation current: IS =
than base, these electrons are W
swept into collector. −−−−−−−−−−−−−−−−−−
➢ collector current (iC) is AE qDn ni2
approximately equal to In. (eq4) IS =
W NA
➢ iC = In ni = intrinsic carrier density
NA= doping concentration of base
The Collector Current
• Magnitude of iC is independent of vCB.

– As long as collector is positive, with respect to base.
• Saturation current (IS) – is inversely proportional to W and directly
proportional to area of EBJ.
– Typically between 10-12 and 10-18A
– Also referred to as scale current.
Operation of the npn-Transistor The Base Current
 = transistor parameter
• base current (iB) – composed of two components: iC

* ib1 – due to holes injected from base region (eq5) iB =

into emitter.
−−−−−−−−−−−−
* ib2 – due to holes that have to be supplied by
external circuit to replace those recombined. IS vBE /VT
(eq6) iB = e

• common-emitter current gain (.) – is influenced by two factors:
– width of base region (W)
– relative doping of base emitter regions (NA/ND)
• High Value of 
– thin base (small W in nano-meters)
– lightly doped base / heavily doped emitter (small NA/ND)
Operation of the npn-Transistor The Emitter Current
this equation is generated through combination of (5) and (7)
 +1  +1
(eq8 & 9) iE =

iC =

( IS ev BE /VT
)
• All current which enters iC
transistor must leave. −−−−−−−−−−−−−−−−−−−−−−−

(eq10) iC =  iE
➢iE = iC + iB (eq7)
−−−−−−−−−−−−−−−−−−−−−−−
this parameter is reffered to
as common-base current gain
 
(eq11)  = , (eq13)  =
 +1
1 −
−−−−−−−−−−−−−−−−−−−−−−−
IS vBE /VT
(eq12) iE = e

iC = I S e vBE /VT
iC
iB =

iC =  iE
iE = iC + iB Fig.: Current flow in an npn transistor biased to
operate in the active mode.
IS : dòng bão hòa
 : hệ số khuếch đại dòng (50÷200); (β is a transistor parameter or common-
emitter current gain)
 : hệ số khuếch đại dòng (≤1) ; (common-base current gain)
 
= =
1−  +1
15
• Three different transistor circuit configurations:
Common-Base (CB) Common-Emitter (CE) Common-Collector (CC)
16
Small signal equivalent circuit models for npn transistor in active mode
• BJT is a Current-Controlled Current Source (CCCS) or a Voltage-Controlled Current Source (VCCS).
Fig.: 2 slightly different versions of the simplified hybrid-p model for the small-signal operation
of the BJT. The equivalent circuit in (a) represents the BJT as a VCCS (a transconductance
amplifier), and that in (b) represents the BJT as a CCCS (a current amplifier).
17
Small signal equivalent circuit models for npn transistor in active mode
Fig.: 2 slightly different versions of what is known as the T model of the BJT. The circuit in (a) is a
VCCS representation and that in (b) is a CCCS representation. These models explicitly show the
emitter resistance re rather than the base resistance rp featured in the hybrid-p model.
18
Large signal equivalent circuit models for npn transistor in active mode
VCCS CCCS
Expressing the
The diode 𝐷𝐸 has a scale current of the
𝐼
current 𝐼𝑆𝐸 = 𝑆 and thus controlled
𝛼
provides a current 𝑖𝐸 source as α𝑖𝐸
controlled by 𝑣𝐵𝐸
Diode 𝐷𝐵 conducts
the base current Expressing 𝑖𝐶 as
𝐼 𝜷𝑖𝐵
𝐼𝑆𝐵 = 𝑆
𝛽
These models apply to any positive value of 𝑣𝐵𝐸 => Large signal models 19
Example 1
• npn transistor: 𝐼𝑆 = 10−15 A and 𝛽 = 100. Terminal E is grounded, B is fed with constant-
current source supplying a dc current of 10 𝜇𝐴, C is connected to a 5 V dc supply via a
resistance 𝑅𝐶 = 3 𝑘Ω. Assuming the transistor is in the active mode, find 𝑽𝑩𝑬 and 𝑽𝑪𝑬 ?
❖ Solution: which model should we choose?

we know 𝐼𝐵 = 10𝜇𝐴 => choose CCCS (d)
𝐼𝐶 𝛽𝐼
• 𝑉𝐵𝐸 = 𝑉𝑇 ln = 𝑉𝑇 ln 𝐵
𝐼𝑠 𝐼𝑠
100∗10 −6
→ 𝑉𝐵𝐸 = 25 ln = 690 𝑚𝑉
10−15
• 𝑉𝐶𝐸 = 𝑉𝑐𝑐 − 𝑅𝐶 𝐼𝐶
𝐼𝐶 = 𝛽𝐼𝐵 = 1𝑚𝐴
→ 𝑉𝐶𝐸 = 2𝑉
𝑉𝑐 = 2 𝑉; 𝑉𝐵 = 0.69 𝑉 → CBJ is Reverse.

=> Transistor is indeed operating in the active mode
20
Example 1 (continued…)
Replace the current source of the circuit in example
1 with a resistance (RB) connected from the base to
the 5 V dc supply. Find RB to result in the same
operating conditions?
VCC − VBE 5V − 0.69V

RB = = = 431 k 
IB 10  A
Replace the current source with a

resistance from the base to 5 Vdc supply
21
• Saturation mode (npn):
✓ EBJ & CBJ are forward biased.
✓ 𝑖𝑐 = 𝐼𝑠 𝑒 𝑣𝐵𝐸Τ𝑉𝑇 − 𝐼𝑆𝐶 𝑒 𝑣𝐵𝐶Τ𝑉𝑇
⇒ 𝑣𝐵𝐶 increases, causing 𝑖𝑐 to decrease and reach 0.
✓ 𝑖𝐵 = 𝐼𝑠 Τ𝛽 𝑒 𝑣𝐵𝐸Τ𝑉𝑇 + 𝐼𝑆𝐶 𝑒 𝑣𝐵𝐶Τ𝑉𝑇
Why 𝑰𝑪 decreases in saturation?

iC
 forced = 
iB saturation
Active mode Saturation mode
In analyzing a circuit, to determine whether the BJT is in the saturation mode by either of the following 2 tests:
1) Is the CBJ forward biased by more than 0.4 V?
2) Is the ratio iC/iB lower than β?
A transistor deep in saturation has 𝑉𝐶𝐸𝑠𝑎𝑡 = 𝑉𝐵𝐸 − 𝑉𝐵𝐶 ≈ 0.2 𝑉.

22
1. Bipolar Junction Transistor (BJT) PNP transistor
Fig. (a) & (b): Two

large-signal models
for the pnp transistor
operating in the active
mode.
Fig.: Current flow in a pnp transistor biased to

operate in the active mode.
23
Example of BJTs
General purpose / small-signal transistors
Power transistors
24
Example of BJTs
Examples of multiple-transistor packages.
Examples of RF transistor
packages
25
1.2. Current-Voltage Characteristics
npn transistor whose EBJ is forward biased (usually, VBE  0.7 V) will operate in the active mode as long as the
collector voltage does not fall below that of the base by more than approximately 0.4 V.
pnp transistor will operate in the active mode if the EBJ is forward biased (usually, VEB  0.7 V) and the
collector voltage is not allowed to rise above that of the base by more than 0.4 V or so.
Fig.: Circuit symbols for BJTs. Fig.: Voltage polarities and current flow in
transistors biased in the active mode.
26
1.2. Current-Voltage Characteristics
27
Example 2
The transistor has 𝛽 = 100 and 𝑣𝐵𝐸 = 0.7 𝑉 at 𝑖𝐶 = 1 𝑚𝐴.
Design the circuit so that a current of 2 mA flows through C and a
voltage of +5V appears at C. How to:
▪ Determine the operation mode?
▪ Find 𝑅𝐶 , 𝑅𝐸
Solution
Since 𝑉𝐶 = +5𝑉 => CB reverse biased => BJT is in active mode
15−5 10𝑉
𝑅𝐶 = = = 5𝑘 𝛺
𝐼𝑐 2𝑚𝐴
Since 𝑣𝐵𝐸 = 0.7 𝑉 at 𝑖𝐶 = 1 𝑚𝐴, the value of 𝑣𝐵𝐸 at 𝑖𝐶 = 2 𝑚𝐴
2
is 𝑉𝐵𝐸 = 0.7 + 𝑉𝑇 𝑙𝑛 = 0.717 (V)
1
Since the base is at 0V, 𝑉𝐸 = −0.717 𝑉
𝐼𝐶 𝐼𝐶
𝐼𝐸 = = = 2.02 (𝑚𝐴)
∝ 𝛽
𝛽+1
𝑉𝐸 − (−15)
𝑅𝐸 = = 7.07𝑘 (𝛺)
𝐼𝐸 28
1.2 BJT I – V Characteristics
• BJT Input Characteristic (𝑖𝐵 vs. 𝑣𝐵𝐸 )
• BJT Transfer Characteristic (𝑖𝑐 vs. 𝑣𝐵𝐸 or 𝑖𝐶 vs. 𝑖𝐵 )
• BJT Output Characteristic (𝑖𝐶 vs. 𝑣𝐶𝐸 )
BJT Transfer Characteristic: 𝑖𝑐 = 𝑓(𝑣𝐵𝐸 )|𝑉𝐶𝐸 =𝑐𝑜𝑛𝑠𝑡
29
Dependence of iC on the Collector Voltage—The Early Effect
James M. Early
✓ When 𝑣𝐶𝐸 < 0.3V, 𝑉𝐶𝐵 < −0.4V, the CBJ (1922 – 2004) was an American EE
becomes forward biased => the transistor enters the
saturation region.
✓ When extrapolated, the characteristic lines meet at
a point 𝑣𝐶𝐸 = −𝑉𝐴 , it is called the Early Voltage,
𝑉𝐴 ~ 10 𝑡𝑜 100 𝑉.
At a given value of vBE, increasing vCE → decrease in
the effective base width W.
Known as the base-width modulation effect.
The linear dependence of iC on vCE can be
 v 
iC = I S evBE /VT 1 + CE 
 VA  Fig.: The iC vs. vCE characteristics of a practical BJT
30
Dependence of iC on the Collector Voltage—The Early Effect
Nonzero slope of the iC–vCE straight lines indicates that the output resistance (ro) looking into the
collector is not infinite
1 i VA + VCE
= C  ro =
ro vCE vBE = const
IC
Alternatively, we can write

VA
ro 
I C Fig.: Large-signal equivalent-circuit models of an npn BJT operating in the
active mode in the CE configuration with the output resistance ro included
where 𝐼𝐶′ = 𝐼𝑆 𝑒 𝑉𝐵𝐸Τ𝑉𝑇 the collector current with the Early effect neglected
The finite output resistance ro can have a significant effect on the gain of transistor
amplifiers. 31
1.3 BJT Circuits at DC (biasing of the BJT)
❖ To use the BJT for any application like amplification, the 2 junctions CB & CE should be properly
biased according to the required application.
❖ Quiescent point (or the DC operating point) (Q-point): (𝐼𝐵 , 𝑉𝐵𝐸 ), (𝐼𝐶 , 𝑉𝐶𝐸 ): no AC signal
component is present at Q.
❖ Since the current through transistor changes according to temperature, Q is changed according to
temperature, too. So the requirement of the biasing for BJT is the temperature stabilization
for Q.
32
Bias establishes the DC operating point (Q-point) for proper linear operation of an amplifier. If an
amplifier is not biased with correct dc voltages on the input and output, it can go into saturation or
cutoff when an input signal is applied. Fig. shows the effects of proper and improper dc biasing of an
inverting amplifier
33
1.3 BJT Circuits at DC
1. Bipolar Junction Transistor (BJT) (biasing of the BJT)
For the npn transistor in Fig. (b),

the CBJ reverse-bias condition is
ensured by keeping vCE ≥ 0.3 V.
Since vBE = ~ 0.7 V, vBC < 0.4 V
34
DC Load line and Quiescent point of BJT
A DC load line drawn on a family of curves. The bottom of
DC Load line
the load line is at ideal cutoff (IC = 0 & VCE =VCC). The top of
the load line is at saturation (IC = IC(sat) & VCE = VCE(sat)).
vBE =…
vBE =…
vBE =…
IC Q
vBE =…
vBE =…
VCE
35
• Fixed biasing circuit
𝑉𝑐𝑐 𝑅𝐵2
✓ Thenevin equivalent : 𝑉𝐵𝐵 = and 𝑅𝐵 = 𝑅𝐵1 //𝑅𝐵2
𝑅𝐵1 +𝑅𝐵2
𝑉𝐵𝐵 −𝑉𝐵𝐸 𝑉𝐵𝐵
✓ KVL: 𝑉𝐵𝐵 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 → 𝐼𝐵 =
𝑅𝐵
𝑉 −𝑉
✓ KVL: 𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸 → 𝐼𝐶 = 𝐶𝐶 𝐶𝐸
𝑅𝐶
Fig.: 2 schemes for biasing the BJT: (a) by

fixing VBE; (b) by fixing IB. Both result in wide
variations in IC and hence in VCE and therefore
are considered to be “bad.” Neither scheme is
recommended.
36
• Biasing circuit using current feedback resistor RE
𝑉𝑐𝑐 𝑅2
✓ Thévevin equivalent: 𝑉𝐵𝐵 = and 𝑅𝐵 = 𝑅1 //𝑅2
𝑅1 +𝑅2
✓ KVL: 𝑉𝐵𝐵 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸

𝐼𝐸 = 𝐼𝐵 + 𝐼𝐶
ൠ → 𝐼𝐸 = 1 + 𝛽 𝐼𝐵
𝐼𝐶 = 𝛽𝐼𝐵
VBB − VBE VBB − VBE
IB = , IE =
RB + (  + 1) RE RE + RB / (  + 1)
VBB − VBE
IC =
RB /  + RE (1 + 1/  )
Fig.: circuit with the voltage
✓ KVL: 𝑉𝐶𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸 + 𝐼𝐸 𝑅𝐸
divider supplying the B replaced
𝑉𝐶𝐸 > 𝑉𝐶𝐸𝑆𝑎𝑡 ≈ 0.2𝑉: Active mode current feedback with its Thévenin equivalent.
resistor
37
• Biasing circuit using voltage feedback resistor RB
✓ KVL: 𝑉𝐶𝐶 = 𝐼𝐵 + 𝐼𝐶 𝑅𝐶 + 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸

VCC − VBE
IB =
RC (  + 1) + RB
VCC − VBE
IC =
RC (1 + 1/  ) + RB / 
VCC − VBE
IE =
RC + RB / (  + 1)
Fig.: (a) A common-emitter transistor amplifier
𝑅𝐵 is chosen for Q is in the active biased by a feedback resistor RB. (b) Analysis
region (𝑉𝐶𝐸 > 𝑉𝐵𝐸 ≅ 0.7 𝑉) of the circuit in (a).
38
Ex. 3 𝐹𝑖𝑛𝑑 𝑉𝐶 , 𝑉𝐸 , 𝐼𝐵 , 𝐼𝐶 , 𝐼𝐸 ? 𝛽 = 100
39
1.3 Biasing of the BJT
2nd assumption BJT in saturation
Ex. 4 𝐹𝑖𝑛𝑑 𝑉𝐶 , 𝑉𝐸 , 𝐼𝐵 , 𝐼𝐶 , 𝐼𝐸 ? mode (VCEsat = 0.2 V)
𝛽 ≥ 50
1st assumption BJT in
active-mode operation
40
1.3 Biasing of the BJT
Ex. 5 Find 𝑉𝐵 , 𝑉𝐶 , 𝑉𝐸 , 𝐼𝐵 , 𝐼𝐶 , 𝐼𝐸 ? 𝛽 = 100
Assume BJT in
active-mode
VC - VB = 4.03 V, ➔ BJT is in the

Simplifying the B circuit active mode, as had been assumed.
using Thevenin’s theorem 41
1.3 Biasing of the BJT Ex. 6: Determine the voltages at all nodes and
the currents through all branches? 𝛽1 = 𝛽1 = 100
Assume Q1 is still in the active mode.

➢ 1st assumption IB2 << IC1; → find VC1, VE2 (assume Q2 : active
So use the results from the previous ex. 1.3.3:
mode) → VE2, IE2, IC2, VC2, then IB2
VB1 = 4.57 V; IE1 = 1.29 mA; IB1 = 0.0128 mA;
➢ Obtain more accurate results by iterating one more time with
IC1 = 1.28 mA
just calculated value of IB2
42
1.3 Biasing of the BJT Ex. 7 Evaluate the voltages at all nodes and the
currents through all branches? 𝛽 = 100
Assume Q2 is ON → current
will flow from ground through
the 1 k into E of Q2, to B of
Q2 will be flowing out of B
through the 10 k and into the
+5 V supply. This is impossible!
Q1 & Q2 cannot be
ON at the same time. So Q1 is ON and Q2 is OFF. But
whether Q1 is active or saturated?
43
1.4 Applying the BJT in Amplifier Design
❖ Biasing BJT to Obtain Linear Amplification
Fig.: Transfer characteristic of
the circuit in (a). The amplifier is
biased at a point Q, and a small
voltage signal vi is superimposed
on the DC bias voltage VBE. The
resulting output signal vo appears
superimposed on the DC
collector voltage VCE. The
amplitude of vo is larger than that
of vi by the voltage gain Av.
(a) Basic CE amplifier circuit

vBE(t) = VBE + vbe(t)
44
❖The Small-Signal Voltage Gain
• Analog circuits often operate with small signal levels compared
to the bias currents and voltages in the circuit. The small signal
models allow calculation of circuit gain and terminal impedances
easily.
• Consider the BJT operated in the active region about Q-point
(𝐼𝐵 , 𝑉𝐵𝐸 ) or (𝐼𝐶 , 𝑉𝐶𝐸 ).
• A small signal input voltage 𝑣𝑖 is applied in series with 𝑉𝐵𝐸 and
produces a small variation base current 𝑖𝑏 and a small variation
in collector current 𝑖𝑐 . Total values of base and collector currents
are 𝑖𝐵 and 𝑖𝐶 , respectively, and thus
𝑖𝐵 = 𝐼𝐵 + 𝑖𝑏 and 𝑖𝐶 = 𝐼𝐶 + 𝑖𝑐
𝑣𝐵𝐸 = 𝑉𝐵𝐸 + 𝑣𝑏𝑒 𝑣𝐶𝐸 = 𝑉𝐶𝐸 + 𝑣𝑐𝑒
45
❖The Small-Signal Voltage Gain
If the input signal vbe is small → signal at the output vce will be nearly proportional
to vbe with the constant of proportionality being the slope of the almost-linear
segment of the VTC around Q. This is the voltage gain Av of the amplifier, and its
value can be determined by:
dvCE
Av 
dvBE  IC  1. The gain is negative, which signifies that
vBE =VBE Av = −   RC
 VT  the amplifier is inverting; that is, there is
vCE = VCC − RC I S evBE /VT a 180 phase shift between the input and
the output.
I C = I S eVBE /VT 2. The gain is proportional to the collector
bias current IC & to the load resistance RC
I R V −V VCC
Av = − C C = − CC CE Av max maximum gain Av is obtained by biasing the BJT
VT VT VT at the edge of saturation
46
1.5 Small-Signal Operating Model
❖ Collector Current iC & Transconductance gm
vBE = VBE + vbe  (VBE + vbe )/VT
 → i = I e = I eVBE /VT vbe /VT
e
iC = I S e
C S S

vBE /VT
IC
iC = I C evbe /VT
 vbe  IC
If vbe VT → iC I C 1 + =
 C I + vbe = I C + ic
 VT  VT
ic
IC
where ic = g m vbe gm = is called transconductance
VT
A graphical interpretation for gm is equal to the iC

slope of the iC vs. vBE characteristic curve at iC = IC gm =
(i.e., at the bias point Q).
vBE iC = I C
47
❖ Base Current iB and Input resistance at base rp
iC IC
1 IC
Total base current: iB = = + vbe = I B + ib
   VT
1 IC g IC
Signal component ib = vbe = m vbe gm =
 VT  VT
The small-signal input resistance between base and emitter,

looking into the base, is denoted by rπ and is defined as
𝑣𝑏𝑒 𝛽 𝑉𝑇
𝑟𝜋  = =
𝑖𝑏 𝑔𝑚 𝐼𝐵
48
❖ Emitter Current iE and Input resistance at Emitter re
iC IC ic ic IC I
The total emitter current: iE = = + = I E + ie , where ie = = vbe = E vbe
    VT VT
Denote the small-signal resistance between base &

emitter looking into the emitter by re, it can be
defined as
𝑣𝑏𝑒 𝑉𝑇 𝛼 1
𝑟𝑒 ≡ = = ≈
𝑖𝑒 𝐼𝐸 𝑔𝑚 𝑔𝑚
• Relationship between 𝒓𝝅 and 𝒓𝒆 :

vbe = ib rp = ie re  rp = ( ie / ib ) re = (  + 1) re
49
❖ Voltage Gain Av
Total collector voltage vCE
vCE = VCC − iC RC = VCC − ( I C + ic ) RC = (VCC − I C RC ) − ic RC
= VCE − ic RC
VCE is the dc bias voltage at the collector, and the signal voltage vce is
vce = −ic RC = − gmvbe RC = ( − gm RC ) vbe
Thus the voltage gain of this amplifier Av is

vce I R
Av  = − g m RC = − C C
vbe VT
50
❖ Separating the (ac) Signal and the DC quantities
= +
51
❖ Hybrid-𝝅 Model
vbe vbe vbe vbe
ie = + gmvbe = (1 + gmrp ) = (1 +  ) =
rp rp rp re
A slightly different equivalent-circuit model can be obtained by
g m vbe = g m ( ib rp ) = ( g m rp ) ib =  ib
Fig.: 2 slightly different versions of the

hybrid-π model for the small-signal gm =
IC
operation of the BJT. VT
ic = gmvbe rp = VT / I B =  / g m
ib = vbe /rπ VCCS (a transconductance amplifier) CCCS (a current amplifier).
52
❖ Hybrid-𝝅 Model
VA + VCE
with resistance 𝑟𝑜 (Just in case of taking into account for Early Effect) r0 =
IC
(r0 appears in parallel with 𝑅𝑐 (load resistor of the amplifier)
v0
= − g m ( RC r0 )
vbe 53
❖ T-Model (an alternative model) gmvbe = gm ( ie re ) = ( gm re ) ie =  ie
Here, the resistance between base
& emitter, looking into the emitter,
is explicitly shown re
Fig.: T model of the BJT. The circuit in (a) is
a VCCS representation and that in (b) is a
CCCS representation. These models show the
emitter resistance re rather than the base
resistance rπ featured in the hybrid-π model.
vbe vbe vbe vbe    vbe vbe

ib = − g m vbe = (1 − g m re ) = (1 −  ) = 1 − = =
re re re re   + 1  (  + 1) re rp
54
• T-Model with resistance 𝒓𝒐 (Accounting for Early Effect)
The T models can be added by ro to
account for the dependence of ic to vce --
(the Early effect) to obtain the equivalent
circuits
55
❖ Small-Signal Models of the pnp Transistor
Although the above small-signal models were developed for the case of the npn
transistor, they apply equally well to the pnp transistor with no change in polarities.
56
❖ Application of the Small-Signal Equivalent Circuits
The small-signal BJT circuit models makes the analysis of transistor amplifier circuits a
systematic process. The process consists of the 5 following steps:
1. Eliminate the signal source and determine the Q-point of the BJT and in particular
the dc current IC.
2. Calculate small-signal model parameters: gm = IC/VT, rπ = /gm & re = VT/IE = /gm.
3. Eliminate the DC sources: each DC voltage source ➔ a short circuit and each DC
current source ➔ open circuit.
4. Replace the BJT with one of its small-signal equivalent circuit models. Although
any one of the models can be used, one might be more convenient than the others for
the particular circuit being analyzed.
5. Analyze the resulting circuit to determine the required quantities (e.g., voltage gain,
input resistance).
57
Ex. 8: Analyze the transistor amplifier shown in the

𝑣
below Figure to determine its voltage gain 𝑜 . Assume
𝑣𝑖
𝛽 = 100 and neglect the Early effect.
58
Ex. 8: solution Apply the five-step process outlined above
1st step: find the Q point (DC 2nd step: Calculate the values of 3rd step: Replacing VBB & VCC
analysis), as shown in Fig. (b) the small-signal model parameters with short circuits as in Fig. (c)
VT 25
re = = = 10.8 () RC
I E (2.3 / 0.99)
I C 2.3
gm = = = 92 (mA/ V) RBB +
VT 25 vo
 100 vi
rp = = = 1.09 (k ) _
g m 92
(c)
59
Ex. 8: solution (continued)
4th step: the small-signal analysis, employ either of the 5th step: Analysis of the equivalent circuit
2 hybrid- π, equivalent-circuit models (fig. (d)) in Fig. (d)
rp 1.09
vbe = vi = vi
rp + RBB 101.09
= 0.011vi
vo = − g m vbe RC
= −92  0.011vi  3 = −3.04vi
vo
(d) Av = = −3.04 (V/ V)
vi
60
2. Field-Effect Transistor (FET)
2.1 Introduction
• High input impedance (𝑀Ω).
• Temperature stable better than BJT
• Smaller than BJT
• Less noise compare to BJT
𝐼𝑐 𝐼𝐷
Control current 𝑰𝑩 C Control voltage 𝑽𝑮𝑺 D
BJT FET
B G
E S
Three Terminal
Drain-D
Gate-G
Source-S
61
2. FET
2.1 Introduction
(Junction Field-Effect Transistor)
: Insulated-gate FET
(Metal-Oxide Semiconductor FET)
Types of Field – Effect Transistors

62
2. FET
2.2 JFET: Structure and Operation
n-channel JFET p-channel JFET
pinch-off voltage (điện thế thắt): VP 𝑉𝐺𝑆 ≤ −𝑉𝑃

𝑉𝐺𝑆 = 0𝑉 and -𝑉𝑃 < 𝑉𝐺𝑆 < 0 63
2. FET
2.2 JFET: Structure &
Operation
Fig.: Effects of VGS on channel width,

resistance, and drain current (VGG = VGS).
64
2. FET
2.2 JFET: Structure and Operation
• Three different transistor circuit configurations:
Common Source (CS) Common Gate (CG) Common Drain (CD)
65
2. FET
2.3 JFET: I-V Characteristics
• Transfer Characteristic: 𝐼𝑑 = 𝑓(𝑉𝐺𝑆 )|𝑉𝐷𝑆=𝑐𝑜𝑛𝑠𝑡
• Output Characteristic: 𝐼𝑑 = 𝑓(𝑉𝐷𝑆 )|𝑉𝐺𝑆=𝑐𝑜𝑛𝑠𝑡
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )2
𝑉𝐺𝑆𝑜𝑓𝑓
Forward Transcondutance gm
∆𝐼𝐷
𝑔𝑚 =
∆𝑉𝐺𝑆
𝑉𝐺𝑆
𝑔𝑚 = 𝑔𝑚0 1 −
𝑉𝐺𝑆(𝑜𝑓𝑓)
2𝐼𝐷𝑆𝑆
𝑔𝑚0 =
𝑉𝐺𝑆(𝑜𝑓𝑓) Fig.: JFET transfer characteristic curve (n-channel);
gm varies depending on the bias point (VGS) 66
2. FET
• Output Characteristic
✓ Linear/Ohmic/Triode Region
✓ Saturation Region
✓ Breakdown region Linear region
(Ohmic)
Breakdown
Saturation region region
𝑽𝑷𝟎 (Pinch-off voltage)
(b) Drain characteristic

67
2. Field-Effect Transistor
• Family of output Characteristics
Cutoff voltage (VGS(off)) and Pinch-off Voltage (VP)?

68
Example 9:
• For JFET with 𝑉𝐺𝑆(𝑜𝑓𝑓) = −4 𝑉 and 𝐼𝐷𝑆𝑆 = 12 𝑚𝐴. Determine the
minimum value of 𝑉𝐷𝐷 required to put the device in the constant-
current area of operation.
69
Example 9 - Solution
• 𝑉𝐺𝑆(𝑜𝑓𝑓) = −4 𝑉 → 𝑉𝑃 = 4 𝑉
• Minimum value of 𝑉𝐷𝑆 for JFET to be in its saturation region:
𝑉𝐷𝑆 = 𝑉𝑃 = 4 𝑉
• In the constant-current area with 𝑉𝐺𝑆 = 0:
𝐼𝐷 = 𝐼𝐷𝑠𝑠 = 12 𝑚𝐴
• Drop across the drain resistor:
𝑉𝑅𝐷 = 𝐼𝐷 𝑅𝐷 = 12 𝑚𝐴 × 560  = 6.72 𝑉
• Apply the KVL: 𝑉𝐷𝐷 = 𝑉𝐷𝑆 + 𝑉𝑅𝐷 = 4 + 6.72 = 10.7 (𝑉)
70
Example 10:
A particular p-channel JFET has 𝑉𝐺𝑆 𝑜𝑓𝑓 = 4 𝑉. What is 𝐼𝐷
when 𝑉𝐺𝑆 = 6 𝑉?
71
• P-channel JFET required a positive gate-source voltage. More positive voltage,
less drain current.
• 𝑉𝐺𝑆 = 4 𝑉, then 𝐼𝐷 = 0.
• => Further Increase 𝑉𝐺𝑆 (𝑉𝐺𝑆 = 6𝑉), keep JFET cutoff (𝐼𝐷 = 0)
72
❖ N-channel JFET The JFET drain current
The transfer characteristic curve can also be characteristic curves
developed from the drain characteristic
curves by plotting values of ID for the
values of VGS taken from the family of
drain curves at pinch-off,
n-channel JFET
transfer characteristic
curve
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )2
𝑉𝐺𝑆𝑜𝑓𝑓
73
Example 11:
• N-channel JFET 2N5459 has 𝐼𝐷𝑆𝑆 = 9𝑚𝐴 and 𝑉𝐺𝑆(𝑜𝑓𝑓) = −8𝑉 (Maximum). Determine
the drain current for 𝑉𝐺𝑆 = 0𝑉; −1𝑉; −4𝑉 ?
74
2.3 JFET: I-V Characteristics Example 11 - Solution
• 𝑉𝐺𝑆 = 0𝑉, 𝐼𝐷 = 𝐼𝐷𝑆𝑆 = 9𝑚𝐴
𝑉𝐺𝑆 2
Use equation: 𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − ) to calculate drain current ID
𝑉𝑃𝑜
• 𝑉𝐺𝑆 = −1, 𝐼𝐷 = 6.89𝑚𝐴
• 𝑉𝐺𝑆 = −4, 𝐼𝐷 = 2.25𝑚𝐴
75
2.4 JFET: Biasing circuits
• Fixed Bias:
✓ 𝐼𝐺 = 0 → 𝑉𝐺𝑆 = 𝑉𝐺𝐺
𝑉
✓ 𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − 𝐺𝑆 )2
𝑉𝑃𝑜
✓ 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷
• Self-Bias:
✓ 𝐼𝐺 𝑅𝐺 + 𝑉𝐺𝑆 + 𝐼𝑆 𝑅𝑆 = 0
→ 𝑉𝐺𝑆 = −𝐼𝐷 𝑅𝑆
(Note: 𝐼𝐺 = 0 and 𝐼𝑆 = 𝐼𝐷 )
76
Example 12:
• For n-channel JFET in Figure, internal
parameter values such as 𝑔𝑚 , 𝑉𝐺𝑆(𝑜𝑓𝑓) and
𝐼𝐷𝑆𝑆 are such that a drain current (𝐼𝐷 ) of
approximately 5 mA is produced.
Find 𝑉𝐷𝑆 and 𝑉𝐺𝑆 ?
77
• 𝑉𝑠 = 𝐼𝐷 𝑅𝑆 = 5 𝑚𝐴 × 220  = 1.1 𝑉
• 𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 = 15 − 5 𝑚𝐴 × 1 𝑘 = 10 𝑉
• => 𝑉𝐷𝑆 = 𝑉𝐷 − 𝑉𝑆 = 10 𝑉 − 1.1 𝑉 = 8.9 𝑉
• Since 𝑉𝐺 = 0 𝑉 ⇒ 𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = −1.1 𝑉
78
Example 13:
• Determine 𝑅𝑆 required to self-
bias a n-channel JFET that has
transfer characteristic curve as
in Figure at 𝑉𝐺𝑆 = −5 𝑉
79
• From Figure, 𝐼𝐷 = 6.25 𝑚𝐴 at 𝑉𝐺𝑆 = −5 𝑉.
𝑉𝐺𝑆 5𝑉
𝑅𝑠 = = = 800 
𝐼𝐷 6.25 𝑚𝐴
80
(Junction Field-Effect Transistor)
: Insulated-gate FET
(Metal-Oxide Semiconductor FET)
Types of Field – Effect Transistors

81
2. FET
2.5 MOSFET: Structure and Operation
2D view
3D view
Fig.: Physical structure of the enhancement-type NMOS transistor
82
`
2. FET
❖ Operation with Zero Gate Voltage ❖ Creating a Channel for Current Flow
If vGS = 0 V: MOSFET acts like 2 back- If vGS > 0 V: underneath G area, holes are pushed downward → depletion
to-back diodes exist in series between D region; also, attracts electrons from the S & D regions into the channel
& S → prevent current conduction region → created n region connecting the S & D regions (named as
from drain to source when a voltage vDS induced region or n-channel or inversion layer).
is applied. Channel between D & S has a
very high resistance (~ 1012 ).
The voltage across the

oxide is uniform
Fig.: The enhancement-type NMOS

transistor with vGS > 0.
83
2. FET
❖ Creating a Channel for Current Flow
✓ 𝐶𝑜𝑥 : Oxide capacitance per unit gate area [F/𝑚2 ]
✓ 𝜇𝑛 : Mobility of electrons at surface of channel [𝑚2 /V.s]
✓ 𝑉𝑡 [0.3→1 V]: threshold voltage of 𝑣𝐺𝑆 to form a conducting
channel. (Sufficient number of mobile electrons accumulate in the
channel region)
✓ 𝑣𝑂𝑉  𝑣𝐺𝑆 − 𝑉𝑡 : effective voltage or overdrive voltage, is the
quantity that determines the charge in the channel.
❖ Applying a Small vDS > 0
Then, if vDS > 0 → there is current flows (e-) in this channel.
Case of vDS is small (i.e., 50 mV or so). → current in the channel, iD,
will be from D → S.
Calculation of the value of iD.
 W    W  
iD =  nCox   OV  DS  n ox   ( GS
v v =  C v − Vt )  vDS
 L    L  Fig.: An NMOS transistor with vGS > Vt
and with a small vDS applied. 84
2. FET
2.5 MOSFET: Structure and Operation ❖Applying a Small vDS > 0
 W    W  
Calculation of the value of iD iD =  nCox  v v =  C (
 OV  DS  n ox   GS v − V )
t  vDS
 L    L 
The conductance of the channel gDS

Process transconductance parameter kn = n Cox (A/V2) (the subscript n denotes n channel)
MOSFET transconductance parameter kn = kn (W / L ) = ( nCox )(W / L ) (A/V2)
 ox
Cox = Cox: called the oxide capacitance (units of F/m2),
tox
 ox = 3.9 0 = 3.9  8.854 10−12 = 3.45 10−11 ( F / m) (only for the permittivity of the SiO2)
tox: oxide thickness (m) is determined by the process technology used to fabricate the MOSFET
With vDS is small, the MOSFET behaves as a linear resistance rDS whose value is controlled by vGS,
1 1 1
rDS = = =
g DS ( nCox ) (W / L)vOV ( nCox ) (W / L)(vGS − Vt )
85
2. FET
❖ Applying a Small vDS > 0
1 1 1
rDS = = =
g DS ( nCox ) (W / L)vOV ( nCox ) (W / L)(vGS − Vt )
MOSFET works as a voltage-controlled resistance, iD versus vDS

for various values of vGS. The resistance is infinite for vGS ≤ Vt and
decreases as vGS is increased above Vt . Fig.: The iD versus vDS characteristics when
For the MOSFET to conduct → created/induced a channel. Then, vDS, is kept small. The device operates as a
linear resistance whose value is controlled
increasing vGS above the threshold voltage Vt enhances the channel,
by vGS.
→ called: enhancement-mode operation and enhancement-type
MOSFET.
Fig.: 3 equivalent circuit symbol for the n-

channel enhancement-type MOSFET
86
2. FET
❖ Operation as vDS is increased
Assume MOSFET be operated at a constant VOV .
vDS appears across the length of the channel. That is, as we
travel along the channel from S → D, the vDS increases from
0 → vDS.
Since the channel depth depends on vDS → the channel is no
longer of uniform depth as shown in the Figures.
Fig.: (a) MOSFET with vGS = Vt + VOV , vDS causes the voltage drop along
the channel to vary linearly, with an average value of (½)vDS at the
midpoint. Since vGD > Vt , the channel still exists at D end. (b) The channel
shape corresponding to the situation in (a). While the depth of the channel
at the S end is still proportional to VOV , that at the D end is proportional to
(VOV −vDS). 87
2. FET
❖ Operation as vDS is increased
As vDS ↑, the channel becomes more tapered and its
resistance ↑ correspondingly.
The equation of drain current iD is calculated as (in
triode region):
 W  1 
iD = kn   VOV − vDS  vDS
 L  2 
or
W  1 2 

iD = kn   ( vGS − Vt ) vDS − vDS  Fig.: iD versus vDS for an E-NMOS transistor operated
L  2 
with vGS = Vt +VOV > Vt.
88
2. FET
❖ Operation for vDS ≥ VOV: Channel Pinch-Off and Drain Current Saturation iD
When vDS = VOV and vGD = Vt → the zero depth of the channel @ D end, means channel pinch-off. Let
vDS ↑ beyond this value (i.e., vDS > VOV ): the current iD remains constant (thus saturates):
1 W  2
iD = kn   VOV
2 L 
➔ The MOSFET is entered the saturation region/mode

vDS at which saturation occurs is: VDSsat = VOV = VGS − Vt
Note: iD in saturation can be rewritten as the constant

overdrive voltage vOV (= vGS – Vt):
1 W  2 1 W 
iD = kn  iD = kn   ( vGS − Vt )
2
 vOV or
2 L  2 L
89
2. FET
2.5 MOSFET: Structure and
Operation
Table 1: Regions of Operation

of the Enhancement NMOS
Transistor
For practicing, read by

yourself the Example #5.1 in
the p. 243 of the text-book
of S&S 6th Ed.
90
2. FET
❖ The p-Channel MOSFET
Fig.: (a) Physical structure of the PMOS

transistor. Note that all semiconductor regions
are reversed in polarity compares to the NMOS
transistor.
(b) A negative voltage vGS of magnitude greater
than |Vtp | induces a p channel, and a negative
vDS causes a current iD to flow from S → D.
To avoid dealing with negative signs

vGS  Vtp
91
2. FET
2.5 MOSFET: Structure and
Operation
❖ The p-Channel MOSFET
Table 2: Regions of Operation

of the Enhancement PMOS
Transistor
92
2. FET
❖ Complementary MOS or CMOS
The fabrication of both NMOS & PMOS transistors on the same chip that creates complementary MOS,
or CMOS,
Fig.: Cross section of a CMOS integrated circuit.
93
2. FET
VOV = VGS − Vt
2.6 EMOSFET: I-V Characteristics
• iD - vGS Characteristic:
Fig.: CS NMOS transistor configuration
Fig.: The iD−vDS characteristics for an enhancement-type NMOS

transistor 94
2. FET
Since the MOSFET is used to design an
amplifier, it is operated in the saturation
region → in saturation, iD is constant
determined by vGS (or vOV ). The n-MOSFET
operates as a constant-current source.
1 W  1 W  2
iD = kn   ( vGS − Vtn ) iD = kn 
2
or  vOV
2 L 2 L  Fig.: The iD–vGS characteristic of an NMOS
transistor operating in the saturation region.
The iD(vOV) characteristic can be obtained by
simply relabeling the horizontal axis, that is,
shifting the origin to the point vGS = Vtn.
95
2. FET
MOSFET in the saturation region as a
voltage-controlled current source is
illustrated by the equivalent-circuit
representation shown in Fig. The circuit
in Fig. is known as a large-signal
equivalent circuit.
For practicing, read by yourself the Fig.: Large-signal, equivalent-circuit model of an n-channel
Example #5.2 in the p. 269 of the text- MOSFET operating in the saturation region
book of S&S 6th Ed.
96
2. FET
NMOS i-v characteristics iD = f(vGS, vDS)
* Plot for Vt,n = 1 V and μnCox(W/L) = 2.0 mA/V2

97
2. FET
Example 14:
An n-channel MOSFET operating with VOV = 0.5 V exhibits a linear resistance
rDS = 1 k when vDS is very small. What is the value of the device
transconductance parameter kn? What is the value of the current ID obtained
when vDS is increased to 0.5 V? and to 1 V?
1 1
Solution: = 𝑘𝑛 𝑉𝑂𝑉 𝑘𝑛 = → 𝑘𝑛 = 2 (mA/V2)
𝑟𝐷𝑆 𝑟𝐷𝑆 𝑉𝑂𝑉
vDS = 0.5 = VOV so NMOSFET is in saturation region. Therefore:

1 2
𝐼𝐷 = 𝑘𝑛 𝑉𝑂𝑉 → ID = 25 mA
2
98
2. FET
❖ Finite Output Resistance in Saturation
In practice, vDS  beyond vOV does

affect the channel somewhat.
Specifically, as vDS , the channel
pinch-off point is moved slightly
away from the D, toward the S.
Note: with depletion-layer widening, the Fig.: Increasing vDS beyond vDSsat causes the
channel length is in effect reduced, from channel pinch-off point to move slightly away from
L to L − L, a phenomenon known as the drain, thus reducing the effective channel length
channel-length modulation. (by L).
99
2. FET
2.6 EMOSFET: I-V Characteristics Fig.: Effect of vDS on iD in the saturation
region. The n-MOSFET parameter VA is
❖ Finite Output Resistance in Saturation proportional to the channel length L.
Due to this effect, the saturation drain current iD is:
1 W
iD = kn   ( vGS − Vtn ) (1 + vDS ) λ is a device parameter (V−1)
2
2  L
Straight-line iD–vDS characteristics are extrapolated, they
intercept the vDS axis at the point, vDS = −VA,
1
VA = (Early voltage)

For a given vGS, a change vDS → change iD
→ the output resistance ro of the current source
representing iD in saturation is no longer infinite.
−1
 iD 
ro   
 vDS  vGS const .
2. FET
❖ Finite Output Resistance in Saturation
Thus the output resistance:
−1
 kn W 2 1 + VDS 1 VA
ro =  (VGS − Vtn )  = 
 2 L  ID ID I D
where 𝐼𝐷′ is the drain current without channel-length modulation
1 W
I D = kn (VGS − Vtn )
 
2
2 L
Fig. shows the large-signal,

equivalent-circuit model of the n-
channel MOSFET incorporating ro
101
2. FET
❖ Characteristics of the p-Channel MOSFET
Fig.: The circuit symbol for the p-channel

enhancement-type MOSFET
Fig.: The p-MOSFET with voltages applied

and the directions of current flow indicated.
PMOS devices also suffer from the channel-
length modulation effect. Thus PMOS in the
saturation-region expression for iD as follows
Fig.: the large-signal,
 vSD 
1 W
( ) 1 W
(
(1 +  vSD ) = 2 k p  L  vSG − Vtp ) equivalent-circuit model of the
2 2
iD = k p   vSG − Vtp 1 + 
2  L    VA 
p-channel MOSFET
incorporating ro
102
2. FET: Handling Precautions
All MOS devices are subject to damage from electrostatic
discharge (ESD). Because the gate of a MOSFET is insulated from
the channel, the input resistance is extremely high (ideally infinite).
Excess static charge can be accumulated because the input
capacitance combines with the very high input resistance and can
result in damage to the device. To avoid damage from ESD, certain
precautions should be taken when handling MOSFETs:
1) Carefully remove MOSFET devices from their packaging.
They are shipped in conductive foam or special foil
conductive bags. Usually they are shipped with a wire ring
around the leads, which is removed just prior to installing the
MOSFET in a circuit.
2) All instruments and metal benches used in assembly or test should be connected to earth ground.
3) The assembler’s or handler’s wrist should be connected to a commercial grounding strap, which has a high-
value series resistor for safety. The resistor prevents accidental contact with voltage from becoming lethal.
4) Never remove a MOS device from the circuit while the power is on.
5) Do not apply signals to a MOS device while the dc power supply is off.
103
2. FET
2.7 EMOSFET: MOSFET Circuits at DC
Overdrive voltage: VOV = VGS – Vtn for NMOS ; and |VOV| = |VSG − Vtp| for PMOS.
To Solve MOS Circuit: (with Large Signal Model)
1. Hypothesis: assume one of the modes of operation for the MOSFET
2. Solve: Use the equations for the selected mode to solve the circuit
3. Check: at the end perform the check for the selected mode to verify the hypothesis
4. Redo: if the hypothesis check fails, try another hypothesis and start over.
Controlled part:
Controller part: Circuit iD & vDS are set by
connected to GS sets transistor state (&
vGS (or VOV ) outside circuit)
104
2. FET
Example 15:
Design the circuit of Fig.: Obtain the values of RD and
RS so that the transistor operates at ID = 0.4 mA and
VD = +0.5 V. The NMOS transistor has Vt = 0.7 V,
μnCox = 100 μA/V2, L = 1 μm, and W = 32 μm.
Assume that λ = 0.
105
2. FET
Example 15: Sol.
VDD − VD 2.5 − 0.5
RD = = = 5 ( k )
ID 0.4
VD = 0.5 V > VG = 0 → the NMOS transistor is operating
in the saturation region, So we use the saturation-region
expression of iD to determine the required value of VOV ,
1 W 2 1 32 2
ID = nCox VOV  400 = 100  VOV → VOV = 0.5 V
2 L 2 1
→ VGS = Vt + VOV = 0.7 + 0.5 = 1.2 (V )
VS − VSS −1.2 − (−2.5)

RS = = = 3.25 (k )
ID 0.4
106
2. FET
Example 16:
Find the i−v relationship of the resulting two-terminal device in
terms of the MOSFET parameters 𝑘𝑛 = 𝑘𝑛′ (W/L) and Vtn. Neglect
channel-length modulation (i.e., λ = 0).
Sol.: Since vD = vG → NMOS is in the saturation mode:

1 W 
iD = kn   ( vGS − Vtn )
2
2 L
1 W  1
Now, i = iD and v = vGS, ➔ i = kn   ( v − Vtn ) = kn ( v − Vtn )

2 2
2 L 2
107
2. FET
Example 17:
Design the circuit in Fig. to have a VD = 0.1 V. Calculate the
effective resistance rDS between D & S leads at this operating
point? Let Vtn = 1 V and 𝑘𝑛′ (W/L) = 1 mA/ V2.
Sol.:
Since the VD = 0.1 V < VG = 5 V and Vtn = 1 V, → MOSFET is operating
in the triode region. Thus the current ID is
W  1 2   1 
iD = kn   ( vGS − Vtn ) vDS − vDS  = 1   (5 − 1)  0.1 −  0.01  = 0.395 (mA)
 L  2   2 
V −V 5 − 0.1
RD = DD D = = 12.4 (k )
ID 0.395
VDS 0.1 1 1
rDS = = = 253 () or r = = = 250 ()
knVOV 1 (5 − 1)
DS
I D 0.395
108
2. FET
Example 18:
Analyze the circuit in Fig. (a) to find the voltages at all nodes and
the currents through all branches. Let Vtn = 1 V and
𝑘𝑛′ (W/L) = 1 mA/V2. Neglect the channel-length modulation effect.
Sol.: VG = VDD
RG 2
RG 2 + RG1
= 10 
10
10 + 10
= 5 (V ) NMOS is ON
Assume NMOS is in saturation mode, solve the problem NOT valid!

So NMOS is in triode mode: VGS = 5 − 6ID
1 W  1
I D = kn   (VGS − Vtn ) =  1 (5 − 6 I D − 1) 2  18I D2 − 25I D + 8 = 0

2
ID: 0.89 mA & 0.5 mA
2 L 2
ID = 0.5 mA; VS = 0.5 × 6 = +3 (V) ; VGS = 5 − 3 = 2 (V); VD = 10 − 6 × 0.5 = +7 (V )

109
2. FET
Example 19:
Design the circuit of Fig. so that the PMOS operates in saturation
with ID = 0.5 mA and VD = +3 V. Let the PMOS have Vtp = −1 V
and 𝑘𝑝′ (W/L) = 1 mA/V2. Assume λ = 0. What is the largest value
that RD can have while maintaining saturation-region operation?
1 W  1
Sol.: I D = k p 
2 L
 vOV

2
 0.5 =  1 vOV  VOV = 1 V
2
2
VGS = Vtp + VOV = 1 + 1 = 2 (V )
Since the VS = +5 V, VG = +3 V → A possible selection is RG1 = 2 M and RG2 = 3 M.

→RD = VD / ID = 3/0.5 = 6 (k)
Saturation-mode will be maintained up to the point that VD exceeds VG by Vtp:
Vdmax = 3 + 1 = 4 (V)
Thus RD = 4/0.5 = 8 (k)
110
2. FET
Example 20:
The NMOS and PMOS transistors in the circuit of Fig. (a) are matched,
with 𝑘𝑛′ (W/L)n = 𝑘𝑝′ (W/L)p = 1mA/V2 and Vtn = −Vtp = 1 V.
Assuming λ = 0 for both devices, find the drain currents iDN and iDP, as
well as the voltage vO, for vI = 0 V, +2.5 V, and −2.5 V.
Sol.: vI = 0 V as shown in Fig. (b)

QN & QP are perfectly matched and having the same
values of VGS = 2.5 V → circuit is symmetrical,
(vO = 0 V). → both QN & QP are operating with
|VDG| = 0 → in saturation.
1
I DP = I DN = 1 (2.5 − 1) 2 = 1.125 (mA)
2
111
2. FET
Sol. 20: vI = +2.5 V → QP is OFF → Fig. (c)
vO will be negative, and thus vGD will be greater than Vtn, causing QN to
operate in the triode region. For simplicity we shall assume that vDS is
small and thus
I DN kn (W / L) n (VGS − Vtn )VDS = 1[2.5 − (−2.5) − 1][vO − (−2.5)]
0 − vO
I DN (mA) =
10k 
→ IDN = 0.244 mA and vO = −2.44 V

Here, VDS = −2.44 − (−2.5) = 0.06 (V), which is small as assumed
Case of vI = +2.5 V → Fig. (d)
QN will be off. Thus IDN = 0, QP will be operating in the triode region
with IDP = 0.244 mA and vO = +2.44 V.
112
2. FET
2.8 Applying the MOSFET in Amplifier Design output
❖ Obtaining a Voltage Amplifier input
The simple amplifier circuit shown in Fig.
vGS: input voltage, RD (load resistance) converts iD to a voltage (iDRD).
KVL: vo = vDS = VDD − RDiD (1)
Voltage Transfer Characteristic (VTC): represented by

a plot of output voltage (vDS) versus input voltage (vGS).
The segment of greatest slope (→ potentially the largest
amplifier gain) is that labeled AB, corresponds to operation in
the saturation region. Hence the current in this region
1
iD = kn (vGS − Vt ) 2 (2)
2
1
(1) & (2) → vDS = VDD − kn RD (vGS − Vt ) 2 (3)
2
Equ. (3) is a nonlinear. To get linear (or almost-linear)
amplification, we can bias the MOSFET…
113
2. FET
2.8 Applying the MOSFET in Amplifier Design
❖ Obtaining a Voltage Amplifier
1) For vGS < Vt , NMOS is in

cutoff: iD = 0 & 3) As vGS increases:
vDS = VDD − RDiD = VDD ▪ VOV = vGS − Vt and iD become larger;
▪ vDS = VDD − RDiD becomes smaller.
▪ @ B, vDS = VOV
2) Just to the right of point A:

▪ VOV = vGS − Vt is small, so iD is
small.
▪ vDS = VDD − RDiD is close to VDD
▪ Thus, vDS > VOV and NMOS is in
saturation. 4) To the right of B, vDS < VOV = vGS − Vt and
NMOS enters triode.
Point B is called the “Edge of Saturation”
114
2. FET
❖ Biasing the MOSFET to Obtain Linear Amplification
① A DC voltage VGS is selected to obtain operation at a point Q on the segment AB of the VTC.
Approximate the transfer function

with a tangent line @ point Q. Slop
@ Q = voltage gain (Av) ②
② ac signal
vgs(t), is added in
series with VGS
vGS(t) = VGS + vgs(t)
115
2. FET
❖ Response (vo = vDS ) is also
made of a constant part (VDS)
and a signal response part
(vds).
❖ Constant part of the response,
VDS, is ONLY related to VGS.
i.e., if vgs = 0, → vds = 0
❖ The shape of the time varying
portion of the response (vds) is
similar to vgs. i.e., vds is
proportional to the input
signal, vgs
116
2. FET
Constant: Signal &
Although the overall response is non-linear, the
Bias response
transfer function (VTC) for the signal is linear!
vGS = VGS + vgs Note:
Response of the circuit (and its elements) to the
vDS  VDS + vds signal is different than its response to the Bias
(or to Bias + signal):
iD  ID + id ✓ Signal iv characteristics of elements are
different, i.e. relationships among vgs, vds, id
is different from relationships among vGS,
Non-linear Approximately vDS , iD .
relationship among Linear
✓ Signal transfer function of the circuit is
these parameters relationship among
these parameters different from the transfer function for total
input (Bias + signal).
117
2. FET
❖ The Small-Signal Voltage Gain
dvDS
Voltage gain of the amplifier Av  → Av = −kn (VGS − Vt ) RD = −knVOV RD
dvGS vGS =VGS
VOV
➢ The gain Av is negative → the amplifier is inverting; means that: 180 phase shift
between the input and the output.
➢ The gain is proportional to the load resistance RD, to the transistor transconductance kn
parameter, and to the overdrive voltage VOV.
1 I D RD V
Case the DC current @ bias point is I D = knVOV
2
→ Av = − → Av max = DD
2 VOV / 2 VOV / 2
Read yourself the example 5.9 @ p. 272 of S & S text-book 6th Ed.
118
2. FET
❖ Determining the VTC by Graphical Analysis
VDD 1
The load line: iD = − vDS
RD RD
119
2. FET
2.9 Small-Signal Operation and Models
❖ The DC Bias Point Set the signal vgs = 0 and assume no channel-length modulation; thus
1 1
iD = kn (vGS − Vt ) 2 = knVOV
2
2 2
and VDS = VDD – RDID ; must have VDS > VOV to let NMOS in saturation-region operation
ID
VDS
VGS
vGS, vDS, iD VGS, VDS, ID

(vGS = VGS + vgs,…) RD: VR, IR 120
2. FET
❖ The Signal Current in the Drain Terminal
Now with the input signal vgs applied. The total instantaneous gate-to source
voltage will be vGS = VGS + vgs
≡ id
1 1 1
iD = kn (VGS + vgs − Vt ) = kn (VGS − Vt ) + kn (VGS − Vt ) v gs + kn vgs2
2 2
2 2 2 i D  ID + i d
1
vgs should be kept small → kn vgs2 kn (VGS − Vt )vgs → vgs 2VOV
2
id
Let g m  = kn (VGS − Vt ) = knVOV is the MOSFET transconductance
vgs
1 1 2I D 2I
Case of MOSFET work @ I D = kn (VGS − Vt ) 2 = knVOV
2
 gm = = D = 2k n I D
2 2 VGS − Vt VOV
2I D
→ VOV =
kn 121
2. FET
❖ The Signal Current in the Drain Terminal
Fig. shows a graphical interpretation of the

small-signal operation of the MOSFET
amplifier.
Note that gm is equal to the slope of the iD − vGS
characteristic at the bias point,
iD
gm 
vGS vGS =VGS
122
2. FET
❖ The Small Signal Voltage Gain
vDS = vD = VDD – RDiD = VDD – RD(ID + id) = VDS – Rdid ≡ VD + vd
Thus the signal component of the drain voltage is

′ 𝑊
vds = vd = –idRD =−𝑘𝑛 𝑉𝑂𝑉 𝑅𝐷 𝑣𝐺𝑆 = –gmvgsRD
𝐿
indicates that the voltage gain is given by
vds vd W
Av  = 
= −kn VOV RD = − g m RD
vgs vgs L
123
2. FET
❖ Small-Signal Equivalent-Circuit Models
Transconductance (gm): describes how id change with vgs
id i W W
gm  = d = kn (VGS − Vt ) = 2kn I D
vgs vgs L L
vGS =VGS
Output resistance (ro): describes how id change with vds

−1
 iD  1 VA
ro =    = (a) Without ro
 vDS  vGS =const  I D I D
➢ Drain current id varies with vDS due to channel length modulation
➢ Finite ro to model the linear dependence of iD on vDS
➢ The effect can be neglected if ro is sufficiently large
Fig. (a) & (b) represent hybrid p model a.k.a. small-signal

model or a small-signal equivalent circuit. (b) With ro 124
2. FET
T-model
Simple circuit transformation it is

possible to develop an alternative
equivalent-circuit model for the
MOSFET.
Fig. (d) shows that the resistance between gate
and source looking into the source is 1/gm.
Fig.: Development of the T equivalent-circuit

model for the MOSFET. For simplicity, ro has
been omitted; however, it may be added between
D and S in the T model of (d).
(d) (c) 125
2. FET
T-model (NMOS transistor:)
ig = 0, id = gmvgs, and
is = vgs/(1/gm) = gmvgs,
All the same as in the original
model in Fig. (a).
Transconductance:
id W W 2I
gm  = nCox VOV = 2 nCox I D = D
vgs L L VOV
1 VA
Output resistance: ro = = Fig.: (a) The T model of the NMOS with the drain-to-
ID ID source resistance ro. (b) An alternative representation of
the T model
126
2. FET
2.10 Basic MOSFET Amplifier Configurations
❖ Three basic configurations
127
2. FET
❖ Three basic configurations
❖ Characterizing amplifiers
The MOSFET circuits can be characterized by a voltage amplifier model (unilateral model)
The electrical properties of the amplifier is represented by Rin, Ro and Avo
The analysis is based on the small-signal or linear equivalent circuit where dc components are not included
Voltage gain: Overall voltage gain
vo RL v Rin Rin RL
Av  = Avo Gv  o = Av = Avo
vi RL + Ro vsig Rin + Rsig Rin + Rsig RL + Ro
128
2. FET
❖ The common-source (CS) amplifier
❑ Characteristic parameters of the CS amplifier ❑ CS amplifier can provide high Av.
✓ Input resistance: Rin =  ❑ Input and output are out of phase due to
✓ Output resistance: Ro = RD||ro  RD negative gain.
✓ Open-circuit voltage gain: Avo = - gm(RD||ro)  -gmRD ❑ Ro is moderate to high.
✓ Voltage gain: Av = - gm(RD||RL||ro)  -gm(RD||RL) ❑ Small RD reduces Ro at the cost of Av.
✓ Overall voltage gain:
Rin
Gv = − g m ( RD || RL || ro ) = − g m ( RD || RL || ro ) = Av
Rin + Rsig
(a) CS: The bias circuit is omitted. (b) CS: with its hybrid-π model 129
2. FET (a) Circuit without bias details
❖ The CS amplifier with a source resistance Rs
❑ Characteristic parameters (by neglecting ro)
✓ Input resistance: Rin = 
✓ Output resistance: Ro = RD
g R
✓ Open-circuit voltage gain: Avo = − m D
1 + g m Rs
gm (R D || R L )
✓ Voltage gain: Av = −
1 + gm Rs
g m ( RD || RL )
✓ Overall voltage gain: Gv = −
1 + g m Rs
❑ Source degeneration resistance Rs is adopted.
❑ Gain is reduced by the factor (1+gmRs).
❑ It is considered a negative feedback of the amplifier.
Note: A fraction of vi appears between G & S as
1/ g m vi (b) Equivalent circuit
vgs = vi = with NMOS in its T
1/ g m + RS 1 + g m RS
model. 130
2. FET
❖ The CG amplifier
❑ Characteristic parameters of the CG amplifier (by neglecting ro)
✓ Input resistance: Rin = 1/gm
✓ Output resistance: Ro = RD
✓ Open-circuit voltage gain: Avo = gmRD
✓ Voltage gain: Av = gm(RD||RL)
g m ( RD || RL )
✓ Overall voltage gain: Gv =
1 + g m Rsig
❖ CG amplifier can provide high voltage gain.
❖ Input and output are in-phase due to positive gain.
❖ Input resistance Rin is very low.
❖ A single CG stage is not suitable for voltage amplification.
❖ Output resistance Ro is moderate to high.
❖ Small RD reduces Ro at the cost of voltage gain Av.
❖ The amplifier is no longer unilateral if ro is included.
131
2. FET
❖ The CD amplifier
❑ Characteristic parameters of the CD amplifier (by neglecting ro)
✓ Input resistance: Rin = 
✓ Output resistance: Ro = 1/gm
✓ Voltage gain: Av = RL/(RL+1/gm) = gmRL/(gmRL+1)  1
✓ Overall voltage gain: RL/(RL+1/gm) = gmRL/(gmRL+1)  1
❑ CD amplifier is also called source follower.
❑ Input resistance is very high.
❑ Output resistance is very low.
❑ The voltage gain is less than but can be close to 1.
❑ CD amplifier can be used as voltage buffer.
❑ It is noted that, in the analysis, the amplifier is not unilateral.
132
2. FET
2.11 Biasing in MOS Amplifier Circuits
DC bias for MOSFET amplifier
✓ The amplifiers are operating at a proper dc bias point.
✓ Linear signal amplification is provided based on small-signal circuit operation.
✓ The DC bias circuit is to ensure the MOSFET in saturation with a proper
collector current ID.
Biasing by fixing gate-to-source voltage VGS
✓ Fix the dc voltage VGS to specify the saturation current of the MOSFET:
1 1 𝑊
𝐼𝐷 = 𝑘𝑛 𝑉𝐺𝑆 − 𝑉𝑡 2 = 𝑛 𝐶𝑜𝑥 𝑉𝐺 − 𝑉𝑡 2
2 2 𝐿
✓ ID current deviates from the desirable value due to variations in the device
parameters Vt and µn. It is not a good approach to biasing a MOSFET.
Biasing by fixing gate voltage and connecting a source resistance Rs
1
✓ The bias condition is specified by: 𝑉𝐺 = 𝑉𝐺𝑆 + 𝑘𝑛 𝑉𝐺𝑆 − 𝑉𝑡 2 𝑅𝑠 and
2
1
𝐼𝐷 = 𝑘 𝑉𝐺𝑆 − 𝑉𝑡 2
2 𝑛
✓ Drain current has better tolerance to variations in the device parameters
133
2. FET
2.11 Biasing in MOS Amplifier Circuits
Biasing using a drain-to-gate feedback resistor (Fig. 1)
✓ A single power supply is needed. Fig. 1: Biasing the MOSFET
✓ Large RG ensures the MOSFET in saturation (VGS = VDS) using a large drain-to-gate
𝑉 −𝑉 1 feedback resistance, RG.
✓ MOSFET operating point: 𝐷𝐷𝑅 𝐺𝑆 = 2 𝑘𝑛 𝑉𝐺𝑆 − 𝑉𝑡 2
𝐷
✓ The value of the feedback resistor RG affects the small-signal gain.
Biasing using a constant-current source (Fig (a) & (b)) To source of

transistor Q
✓ The MOSFET can be biased with a constant current source I. in Fig.(a)
✓ RD is chosen to operate the MOSFET in saturation mode.
✓ The current source is typically a current mirror.
✓ Current mirror circuit:
▪ MOSFETs Q1 and Q2 are in saturation.
▪ The reference current IREF = I = ID
𝑉𝐷𝐷 − 𝑉𝐺𝑆 1 1
= 𝑘𝑛 𝑉𝐺𝑆 − 𝑉𝑡 ; 𝐼𝑅𝐸𝐹 = 𝑘𝑛 𝑉𝐺𝑆 − 𝑉𝑡 2
2
𝑅𝐷 2 2
▪ When applying to the amplifier circuit, the voltage VD2 has to (a) (b)
be high enough to ensure Q2 in saturation
Fig. (a) Biasing the MOSFET using a constant-current source I.
(b) Implementation of the current source I using a current mirror.
134
2. FET
2.12 Discrete-Circuit MOS Amplifiers Circuit analysis:
DC analysis: 1) Remove all ac sources (short for voltage source and open for current source)
2) All capacitors are considered open-circuit
3) DC analysis of MOSFET circuits for all nodal voltages and branch currents
4) Find the dc current ID and make sure the MOSFET is in saturation
AC analysis: 1) Remove all dc sources (short for voltage source and open for current source)
2) All large capacitors are considered short-circuit
3) Replace the MOSFET with its small-signal model for ac analysis
4) The circuit parameters in the small-signal model are obtained based on the value of ID
Complete amplifier DC equivalent AC equivalent

circuit circuit circuit
= +
135
2. FET
2.12 Discrete-Circuit MOS Amplifiers
❖ The common-source (CS) amplifier
CS : bypass capacitor
CC1 & CC2: coupling capacitors
High input resistance (in the megohm range): Rin = RG
Overall voltage gain: (a) CS amplifier

RG
Gv = − g m ( RD || RL || ro )
RG + Rsig
(b) Equivalent circuit of the

amplifier for small-signal analysis.
136
2. FET
❖ The CS amplifier with a source resistance
RG RD || RL
Gv = −
RG + Rsig 1/ g m + Rs
(a) CS amplifier with a RS

in the source lead.
(b) Small-signal equivalent circuit with ro neglected.
137
2. FET
❖ The Common-gate (CG) amplifier
(a) A common-gate amplifier (b) A small-signal equivalent circuit

138
2. FET
❖ The Common-drain (CD) amplifier or The Source Follower
Bias resistance RG at across the input terminals. → the input
resistance will no longer be infinite and the overall voltage gain
will become
RG ( RL || ro )
Gv =
RG + Rsig ( RL || ro ) + 1/ g m
(a) A source-follower amplifier or CD amplifier (b) Small-signal, equivalent-circuit model

139
2. FET
2.12 Discrete-Circuit MOS Amplifiers The amplifier frequency response
❑ The gain falls off at low frequency band due to the effects of the coupling and by-pass capacitors
❑ The gain falls off at high frequency band due to the internal capacitive effects in the MOSFETs
❑ Midband:
✓ All coupling and by-pass capacitors (large capacitance) are considered short-circuit
✓ All internal capacitive effects (small capacitance) are considered open-circuit
✓ Midband gain is nearly constant and is evaluated by small-signal analysis
✓ The bandwidth is defined as BW = fH – fL
✓ A figure-of-merit for the amplifier is its gain-bandwidth product defined as GB = |AM|BW
Fig.: A sketch of the frequency response

of a CS amplifier delineating the three
frequency bands of interest.
140

Lecture 2 Transistors BJT and FET - Updated 2 (Corrected)

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Lecture #2: Transistors

BJT and FET

Fig.: Cross-section of an npn BJT.

BJT Modes of Operation

Oxford University Publishing

• Concentration of minority carrier

• Some “diffusing” electrons will combine with holes (majority carriers in

• It is observed that most diffusing

• Magnitude of iC is independent of vCB.

• base current (iB) – composed of two components: iC

transistor must leave. −−−−−−−−−−−−−−−−−−−−−−−

Common-Base (CB) Common-Emitter (CE) Common-Collector (CC)

❖ Solution: which model should we choose?

𝑉𝑐 = 2 𝑉; 𝑉𝐵 = 0.69 𝑉 → CBJ is Reverse.

VCC − VBE 5V − 0.69V

Replace the current source with a

Why 𝑰𝑪 decreases in saturation?

A transistor deep in saturation has 𝑉𝐶𝐸𝑠𝑎𝑡 = 𝑉𝐵𝐸 − 𝑉𝐵𝐶 ≈ 0.2 𝑉.

Fig. (a) & (b): Two

Fig.: Current flow in a pnp transistor biased to

General purpose / small-signal transistors

Examples of multiple-transistor packages.

BJT Transfer Characteristic: 𝑖𝑐 = 𝑓(𝑣𝐵𝐸 )|𝑉𝐶𝐸 =𝑐𝑜𝑛𝑠𝑡

Alternatively, we can write

For the npn transistor in Fig. (b),

Fig.: 2 schemes for biasing the BJT: (a) by

✓ KVL: 𝑉𝐵𝐵 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸 + 𝐼𝐸 𝑅𝐸

✓ KVL: 𝑉𝐶𝐶 = 𝐼𝐵 + 𝐼𝐶 𝑅𝐶 + 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸

VC - VB = 4.03 V, ➔ BJT is in the

Assume Q1 is still in the active mode.

(a) Basic CE amplifier circuit

A graphical interpretation for gm is equal to the iC

The small-signal input resistance between base and emitter,

Denote the small-signal resistance between base &

• Relationship between 𝒓𝝅 and 𝒓𝒆 :

vce = −ic RC = − gmvbe RC = ( − gm RC ) vbe

Thus the voltage gain of this amplifier Av is

Fig.: 2 slightly different versions of the

vbe vbe vbe vbe    vbe vbe

Ex. 8: Analyze the transistor amplifier shown in the

Types of Field – Effect Transistors

pinch-off voltage (điện thế thắt): VP 𝑉𝐺𝑆 ≤ −𝑉𝑃

Fig.: Effects of VGS on channel width,

Common Source (CS) Common Gate (CG) Common Drain (CD)

𝑽𝑷𝟎 (Pinch-off voltage)

(b) Drain characteristic

Cutoff voltage (VGS(off)) and Pinch-off Voltage (VP)?

• 𝑉𝐺𝑆 = −4, 𝐼𝐷 = 2.25𝑚𝐴

Types of Field – Effect Transistors

Fig.: Physical structure of the enhancement-type NMOS transistor

The voltage across the

Fig.: The enhancement-type NMOS

The conductance of the channel gDS

MOSFET works as a voltage-controlled resistance, iD versus vDS

Fig.: 3 equivalent circuit symbol for the n-

➔ The MOSFET is entered the saturation region/mode

Note: iD in saturation can be rewritten as the constant

Table 1: Regions of Operation