TIAN SHAN

MV_BUILD
2006.05.25

EE DATE POWER DATE

DRAWER
DESIGN
INVENTEC
CHECK TITLE
RESPONSIBLE TIANSHAN
SIZE = 3 VER : SIZE CODE DOC. NUMBER REV
FILE NAME : XXXX-XXXXXX-XX A3 CS Model_No A01
DATE CHANGE NO. REV P/N XXXXXXXXXXXX SHEET 1 OF 74
 TABLE OF CONTENTS

PAGE PAGE PAGE

5- DC& BATTERY CHARGER 28- DDR2-DAMPING 51- HDD CONN
6- SELECT & BATTERY CONN 29- ATI-M52-T-1 52- ODD CONN
7- SYSTEM POWER(3V/5V) 30- ATI-M52-T-2 53- USB CONN/USB(DB)
8- SYSTEM POWER(+V1.8/+V1.5S) 31- ATI-M52-T-3 54- BLANK
9- SYSTEM POWER(VCCP/VGAVCC) 32- ATI-M52-T-4 55- BLANK
10- SYSTEM POWER(+V1.2S/+V2.5S) 33- ATI-M52-T-5/VGA DAMPING 56- BLANK
11- CPU POWER(VCC_CORE) 34- VIDEO RAM 57- MINICARD CONN
12- DDR TERMINATION VOLTAGE 35- BLANK 58- LAN INTERFACE-1
13- POWER(SLEEP) 36- CRT& SVIDEO CONN 59- LAN RJ45 CONN
14- POWER(SEQUENCE) 37- LCD CONN 60- DOCKING CONN
15- CLOCK_GENERATOR 38- ICH7-1 61- SCREW
16- YONAH-1 39- ICH7-2 62- BLANK
17- YONAH-2 40- ICH7-3 63- TPM V1.2
18- YONAH-3 41- ICH7-4 64- BLUETOOTH
19- YONAH-4 42- ICH7-5 65- BUTTON & SWITCH & LED
20- THERMAL&FAN CONTROLLER 43- KBC 66- LED/SWITCH CONN
21- CALISTOGA-1 44- FWH/SPI/HDD PROTECTION 67- LED/SWITCH BUTTON BOARD
22- CALISTOGA-2-HOST 45- INT.KBC/POINT DEVICES 68- DAUGHTER BOARD CONN(DB)
23- CALISTOGA-3-DDR2 46- SUPER I/O 69- CARDBUS CONTROLLER(DB)
24- CALISTOGA-4-POWER 47- DAUGHTER BOARD CONN 70- PC CARD SLOT(DB)
25- CALISTOGA-5-POWER 48- AC97/AZALIA CODEC 71- SD CARD CONN(DB)
26- DDR2-DIMM0 49- EQ&MIC JACK 72- MDC1.5 CONN(DB)
27- DDR2-DIMM1 50- AUDIO AMP&HP JACK 73- BUTTON&SWITCH&LED(DB)
74- CARDBUS BOARD SCREW(DB)

INVENTEC
TITLE
TIANSHAN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 2 OF 74
 Yonah 478
(uFCPGA)
P16~19 ICS9LP306
S-VIDEO Clock generator
P15
P36

FSB DDR II _SODIMM0 DDR II _SODIMM1

LCM P26 P27
LVDS
P37
M52-T 16X PCIE
Calistoga DDR2 Interface
VGA 1466 PCBGA
(64MB) (128MB) DDR2 Interface
P29~34 PM P21~25
CRT
SPI
P36 EEPROM
P44

DMI
DOCKING SATA
HDD
DVI TMDS P51
P60
3.3V, PCI_Interface,33MHz

ODD
P52 ICH7-M PCI_EXPRESS
652 BGA
Giga-bit LAN
BLUETOOTH

P38~42
MINI CARD

USB3(DB)

BCM 5788M
CONN A

CONN C
CONN B
USB2

USB4

USB5

USB7
USB6
USB1

Dock

P58~59
Dock TI_PCI6612
MINI CARD
CARD BUS(DB)
P57 P69~71

P64 P57 P53 P53 P53 P60 P60

RJ45
P59

SD Card PC CARD
SLOT(DB) SLOT(DB)
3.3V, 33MHz/Azalia
PORT REPLICATOR P71 P70

LPC

BATTERY MDC_1.5/Modem
P5~6 Module 56K AZALIA_1981HD
(DB) Super I/O Kahuna Lite2
P62 P48 FWH
47N217 KBC1021
P44 P46 P43
System Charger &
DC/DC System power RJ11 INVENTEC
TITLE
TIANSHAN
P7~13
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 3 OF 74
 LIMIT_SIGNAL ADP_EN
OCP OCP_OC#
ADP_PS0
ADP_PS1 +V5A +V5S

+V3A
CHGCTRL_3 5/3.3V
Charger
Adapter ADP_PRES +V5AL
(BQ24703) ADP_PRES KBC_PW_ON (TPS51120)
(90W)
SLP_S3#_5R +V3AL
AC_AND_CHG

+V3S
+VBDC

V1.5S_PG
Main Battery SLP_S3#_5R
BATSELB +V1.5S +V1.2S
+VBATA LR
Selector +V2.5S
IO POWER LR
AC_AND_CHG (Discrete) +VBATB
+VCCP
Travel Battery (TPS51124)
CHGCTRL_3 PWR_GOOD_3
VCCP_PG

BATCON LR +V0.9S

+VBATR (TPS51100)
SLP_S3#_3R M_VREF

+V1.8
+V1.8S
SLP_S5#_3R V1.8_PG
IO POWER
(TPS51124)
+VGAVCC SLP_S3#
SLP_S3#_5R

+VCC_CORE
IMVP VI

PWR_GOOD_3 (MAX8736

PM_DPRSLPVR +MAX8552)
VR_PWRGD_CK410

PSI#

INVENTEC
TITLE
TIANSHAN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 4 OF 74
 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-
NOTES:
+VBDC at pin 1 of U15 to connect Place near L14 ON_LM339DR2G_SOP_14P ON_LM339DR2G_SOP_14P
this node directly to pin 2 of R39
60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5- 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-
+VBDCR +VBDC 60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-
BAT54S_30V_0.2A +V5S +V5S +V3S
+VADPBL +VADP DC JACK 6-,5- Kevin sense 6-,5- D1013
FOX_JPD113E_NB103_7F_9P R155 Q1016 R197
L1 1 2 2 1 3 2 1 2
6-,5- Q19 60-,14-
NFM60R30T222 JACK1 U15 D S

8 1 1 2 +VADPTR 3.3A_150mil 10K_5% 1 1 10K_5%

D S 1 1 1IN+ Vcc+ 5 1
7 2 2 3 G
1 BSS84_3P R191 R194
6 3 330K_5% R149 133K_1% R190
C6003 4 3 3 2 GND C172 10K_5% 1 2
1UF_16V 1 1 C1040
5 4 1 1
G 4 2 3 2 100K_5%
1 1 C6 1 C3 1 C5 1 C4 R154 3 1IN- R1096 R1097 5 +
AM4825P_AP
5 1 2
OUT 4 1 2 2 1UF_25V 100K_5% 100K_5% 2 3
U20

0.1UF_25V

10PF_50V

0.1UF_25V
2 2 2 2 10PF_50V 2 0.1UF_25V 100K_1% OUT 2 7 +
1 1 R198
R1022 6 7 8 9 TI_LMV321IDBVR_SOT23_5P 4 - 1
6 - OUT
C1008 1 2 2 U20
1 2K_1%
OPEN 220K_5% R157 R1060 3D +V3S 12
2 0_5% 1 2 C136 2
0.22UF_6.3V 10_5% G 1 12
2 2
C135 1
U14 1 2 Q1015 S
R193
0.1UF_16V 1 2B E
2 SSM3K7002F 1 2
R156 1
60-,14-,5- LIMIT_SIGNAL 2 C
ADP_PRES
1 1 8.06K_1% Q42 58-,43-,7-,6-,5- R192 1 1 C170 604K_1%
D1007 R1023 2
CATHODE SST3906 3 7- 3.9K_5% R189
100K_5% 2 MAX_LX5 80.6K_1% 2
2 1N4148_OPEN D9 ANODE 2
3
2 SSM14_1A40V 2
2 0.027UF_10V
1 1
REF CHENKO_LL4148_2P
D21 D18
ADP_EN# 14- 2 1 14-,11-
1 2 R152
Q17 PWR_GOOD_3
TEC_AZ431LANTR_E1_SOT23_3P 1 2 2 1
D1008 CHENKO_LL4148_2P 8 D S 1 1 R1040 2 Q40 3
U14 need keep U4220 LIMIT_SIGNAL Q41 OPEN CHENKO_LL4148_2P
7 2 2 3 1 R196 2 2B C
6 3 20K_5% S D R153 2

OCP
E 1 14-
5 4 60-,14-,5- 1 100K_5% OCP_OC
G
BSS84_3P G
1 C171 SST3904 1 0_5%
1 AM4825P_AP 1 39-
1 R150 2
R204 2 3900PF_16V Q34 3 OCP_OC#
R1024 1 2 58-,43-,7-,6-,5- 14-
1.5K_5% ADP_PRES VBIAS 2 D 0_5%
270K_5% 1G
1 +VBATR 1 R151 2
16-
2
R1147 11-,9-,8-,7-,6-
R195 S PROC_HOT_OCP_OC#
100K_1% +V5AL 3.9K_1% SSM3K7002F 2 OPEN
13-,7-,5-
2 +VBDC
8 +VBDCR
6-,5-
5 + U1008 AP_AM4835P_T1_PF 6-,5- R39
7 Q16 0.015_1%_1W C75
L7
1
6 - OUT ON_LM393DR2G_SOP_8P 0.1UF_25V 10UF_25V 10UF_25V 1 S D 8 1 2 1 2 10UF_25V
2 7 PLC0755P_10UH_3.9A
R205 4 1 3 6
8.25K_1% R1073 C80 4 5
1 1UF_25V G
150K_5% 1 1 1
2 66-,57-,47-,45-,43-,38-,14-,7-,6- C77 C78 C79
1 C1051 C76
+V3AL R1071 2 1 1 1 1 1 1 1 1 1 2 2 2 10UF_25V
R203 10K_5% 2 4.7UF_25V 1 1 R1041

3
R1042

3
2 R125 2 2 2 D5 R1067 R1066
1 1M_5% 2 100_5% 1K_5% 0_5%
6- AC_AND_CHG 2 D1009
2 SSM34_3A40V 1K_1% 1K_1%
2 2 2 2 C74

1
2 2
CHENMKO_BAT54_3P_OPEN 10UF_25V
1 R124 2 C1047
D1010 0.033UF_16V
+V5AL 1 R1069 1K_5% D8
U1002 RLZ18C CHENMKO_BAT54_3P 1 2
13-,7-,5- Kevin sense
4.7K_5% 8
ACN ACDRV#
25
8 ALARM 6- 9
ACP VCC
22 Kevin sense
3 + U1008 26 21
2VREF 2 ACDET PWM#
1 ON_LM393DR2G_SOP_8P 1 2 5 16
2 - OUT
ENABLE SRP
14-,7- R1106 1K_5% 28 15
ACSEL SRN
1 C1167 R1068 19 12
4 ALARM BATP
1

2 0.1UF_16V 2 24
Q1010 3 100K_5% SRSET BATDRV#
3 ACSET 18
D VS
C1168 1G 1 2 27
VHSP
20
1 ACPRES
1 SSM3K7002F S 24703VREF R1070 100K_5%
13
IBAT BATSET 6
2 0.22UF_6.3V 2 4 VREF BATDEP 1
R1148 7 COMP GND 17
14.3K_1% 1 R1108 2 14 11
Q1009 3 NC NC
23 10
2
SSM3K7002F 1 G
D 100_5% 1
NC NC
THERMAL 29
S
2 R1107 TI_BQ24703_QFN_28P 1
60.4K_1% 2
1 R1072
2 R119 13.7K_1%
D1011 174K_1%
R162 CHENKO_LL4148_2P 2
43-,6-1 2
1
CHGCTRL_3 2
200K_1% 1 1
R163 1 C139 R1074
140K_1% 2 0.1UF_16V 300K_0.1%
1 C1102
2 2
2 4.7UF_6.3V 1
R1105 1
C1103 1 150_5% C1048 1 R1111
1 R1075 2 180PF_50V 2 20K_1%
+VADPBL 1UF_6.3V 2 1 C1101 2 1
1M_5% 1 2
C1105 1 R1113
6-,5- +V5AL 2 150PF_50V 24K_0.1%
OPEN 2
U1003 R1109 1 C1100
R1078 2 13-,7-,5- 2
1 1IN+ 60.4K_1%
+VBDC
1
Vcc+ 5 2 2 4.7UF_6.3V
6- CELLSEL#
100K_1%
6-,5- 2 GND
R1079 2 3 1IN-
1
OUT 4 3 D Q1018 3 D Q1019
100K_1%
R1076
23.7K_1%
1
TI_LMV321IDBVR_SOT23_5P
1 C1052 R1110
7.87K_1%
1

S
G 1
1 R1112
8.87K_1%
(8.87k_0.5%) 2 S
G 1
INVENTEC
2 0.1UF_16V 2 SSM3K7002F TITLE
1 R1077 2 2 2 2 TIANSHAN
DC &BATTERY CHARGER
24K_1% SSM3K7002F
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 5 OF 74
 +V3AL
66-,57-,47-,45-,43-,38-,14-,7-,5-,6- +V3AL
+V3AL
1 66-,57-,47-,45-,43-,38-,14-,7-,5-,6-
+VBATR +VBDCR 66-,57-,47-,45-,43-,38-,14-,7-,5-,6-
R70
100K_5% PDS540_5A_40V
+VADPBL 11-,9-,8-,7-,5- 5-
2 2 1 1
5- 3 1 1
D7 5- 1 R99 R98
R40 2 1 CELLSEL# D15 +VBATA R69 R68 OPEN
1 2 100K_5%
Q15 10K_5% 10K_5%
3K_5% 1 8 +VBDC Q24 Q23 6- 2 2
RLZ18C S D 6-
2 7 1 8 8 1 2 2 BAT6CELL#
Q9 Q10 S D D S
5-,6-
3 6 6- 1 3 3 2 2 7 7 2
4 5 BAT6CELL# S D D S 1 3 6 6 3
G SSM3K7002F 1 R67
2N7002_OPEN Q25 4 G
5 5 G
4 43- 1 2
AM4825P_AP G G R97 R64 1 C55 SDA_MAIN CN8
2 1 470K_5% SST3904 AM4825P_AP 0_5%
3 AM4825P_AP 470K_5%
R16 2 2 C 2 OPEN 8
1 2 B
2 6 6 7
8
E
1
43- 1 R66 2 5 5 7
10K_5% R96 SCL_MAIN
1 0_5% 4 4
3 Q8 470K_5% 1 R100 2 3
R15 D 3
1 2 1G SSM3K7002F 2 100_5% 2 2
+V3AL 1
43- 1 1
10K_5% S
SSM3K7002F R65 THM_MAIN#
66-,57-,47-,45-,43-,38-,14-,7-,5-,6- 2 D16
Q7 4.7K_5% AMP_1746706_6P

3
2
1 C88 1 C87

D
S
1 2
1 C1171 C1 C2
2 47PF_50V
CHENKO_LL4148_2P 2 0.1UF_25V

1G
6- BATSELB# 2 0.1UF_16V
C1104 1
6- CFET_A
0.1UF_16V 2 5 U21 U16 SSM3K7002F A
BATSELB 43-,6- 1 6 1 8 3 Q6 D6 MAIN BATT
7 1G
D
CHENMKO_CHPZ6V2_3P
2 NC7WZ14 2 S Q5
TC7W08FU 2 3
4 D
+V3AL +V3AL
1G
SSM3K7002F
PDS540_5A_40V S 66-,57-,47-,45-,43-,38-,14-,7-,5-,6- 66-,57-,47-,45-,43-,38-,14-,7-,5-,6-
+VBDC 2 1
2 +VBATB 1 1 R89
+V3AL +V3AL 5-,6- 3
1 R87 R86 100K_5%
6-
D10 10K_5% 10K_5%
66-,57-,47-,45-,43-,38-,14-,7-,5-,6- 66-,57-,47-,45-,43-,38-,14-,7-,5-,6- Q21 Q20 2
1 S D 8 8 D S 1 5A_200mil 2 2
2 7 7 2
FAIR_NC7WZ17_SC70_6P 1 3 6 6 3
D1015 SYN_200263MS006G113ZT_6P
CHENKO_LL4148_2P 5 U1009 R127 4 5 5 4 1
43- 1 R85 2
Q29 G G
R129 1 C118 SDA_MBAY
43-,5- 1 6 470K_5% SST3904 0_5% CN1001
CHGCTRL_3 3 AM4825P_AP AM4825P_AP 470K_5% 1 1
2 1 2 2 OPEN
1 1
1 R128 2 2 B
C
2 2
1 2 R1153 R199 E
1 2
43- 1 R88 2 3 3
1 R1151 10K_5% 220K_5% 10K_5% SCL_MBAY 4 4
1 R84 0_5%
C1169 2 470K_5% 470K_5% 1 R90 2 5 5
0.22UF_6.3V 2 Q43 2 SSM3K7002F D17 1
6 6
2 SSM3K7002F U16 2 100_5%
5 8 3 Q30 R158 43-
2

AC_AND_CHG 5- R159 D THM_TRAVEL#

4.7K_5%
D

3
S

1 2 1G 1 2
BATSELB 43-,6- 6 10K_5% Q35 2
S
CHENKO_LL4148_2P
1G

4 TC7W08FU 2
1 C82 1 C119

3
6- CFET_B C2 C1

D
S
ADP_PRES Q37 2 47PF_50V 2 0.1UF_25V
58-,43-,7-,5-,6-

1G
SSM3K7002F SSM3K7002F
3 A
1G
D
D11 TRAVEL BATT
+V3AL CHENMKO_CHPZ6V2_3P
S
2 3
66-,57-,47-,45-,43-,38-,14-,7-,5-,6- D
1G Q36
+VBATB S SSM3K7002F
2
1 C138 +VBATA
6-
2 0.1UF_16V 6-
1 Q22
SSM3K7002F
5 8 U22 D14 3 1 R95 2 3 2 1 R63 2 +V3AL
5- 1 8 U22 3 TC7W02FU DAN202K D S
ALARM 100_5% 0_5% 66-,57-,47-,45-,43-,38-,14-,7-,5-,6-
7 6 CHENKO_LL4148_2P
TC7W02FU2 1 1 G
2
4 2 1
4 2 R92
C83 1.5M_5% D12
0.1UF_25V 1 1 C1170
1 2 CFET_A 6- +V3AL
R161 2 0.1UF_16V
D13 1
47K_5% 1
C137 5 U1009
2
Q38 3 2 UDZS7.5B_ROHM D1014 3 3 4 43- BATCON
1000PF_50V DAN202K
D

BATSELB# 6- 2 1 1G 1 2 FAIR_NC7WZ17_SC70_6P
1 S Q39 2
2 3 R1150
R160 SSM3K7002F 2 5 U21 S D 100K_5%
22K_5% 3 4 CFET_B 6-
+V3AL SSM3K7002F G 2
2 1
2 NC7WZ14 66-,57-,47-,45-,43-,38-,14-,7-,5-,6-

SSM3K7002F
C173
Q45 3
1000PF_50V D
2 1
BATSELB 43-,6-

R200
1
1G
S
2 3 D Q44
158-,43-,7-,5-,6-
INVENTEC
22K_5%
G
ADP_PRES TITLE
S TIANSHAN
2 2 SELECT & BATTERY CONN
SSM3K7002F
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 6 OF 74
 +VBATR +VBATP
11-,9-,8-,6-,5- 7-
PAD1
3 For power test
4
POWERPAD_4A

1 C1098
2 4.7UF_25V

+V3AL
66-,57-,47-,45-,43-,38-,14-,6-,5-,7-

7.32K_1% 30K_1%
5 U24 R1134 2 R1136 2
ADP_PRES 58-,43-,6-,5- 1 1 1
4
43- 2 C1165
KBC_PW_ON TC7S32F 51120GND 1 2
3 2VREF
14-,5-,7-
OPEN

1
2 R1132 1 2 R1133 1 C177 2 R1135 2 +VBATP
1000PF_50V 1
17.4K_1% 7.32K_1%
0_5% 7-
C1164 51120GND 43-,39-
OPEN 51120GND 2 1
RSMRST# 5 6 7 8
R1131 OPEN 1 1 C116 +V5A
2 1 D
G 53-,48-,41-,37-,36-,14-,13-,12-,9-,8-
U1007 R1139 14-,13-,9-,8- 2 2 OPEN
2 1

8
7
6
5
4
3
2
1
SLP_S3#_5R Q18
S
SI4800DY

VO2
COMP2
VFB2
GND
VREF2
VFB1
COMP1
VO1
0_5% C115 MAX5V
4 3 2 1 10UF_25V 6A_200mil
2VREF PAD2
9
EN5
33 R1138 L14
10 EN3 SKIPSEL 32 0_5% 14-,5-,7- 1 2
11 31 2 1
C1096 PGOOD2 TONSEL 5 6 7 8 PLC1055P_4.7UH_5.8A POWERPAD_2_0610
12 30
+VBATP 2 R1130 1
EN2 PGOOD1 R1137 C1166 D
13 29 0.1UF_25V
VBST2 EN1
1
0_5% 2 G Q31
7- 2 1 0_5% 14
DRVH2 VBST1
28
1 C117
0.1UF_25V 15 27 1 2 FDS6690AS 1
LL2 DRVH1
S
C146
65-,64-,63-,60-,58-,44-,41-,40-,39-,37-,16-,14-,13-,9- 16 26 5- MAX_LX5
DRVL2 LL1
220UF_6.3V_OSCON 2 1UF_10V
25
+V3A DRVL1
4 3 2 1

PGND2

PGND1
VREG3

VREG5
V5FILT
6A_200mil

CS2

CS1
1

VIN
D1

PAD1000 L19 2
2 1 5 8

17
18
19
20
21
22
23
24
S1_D2 G1

PLC_0755_4R7_5.1A 6
POWERPAD_2_0610 7
G2 3 +V3AL
4 S2 TI_TPS51120_QFN_32P 66-,57-,47-,45-,43-,38-,14-,6-,5-,7-

C181 C1041 1 Q1017

C179 1 1 10UF_25V 1 1
2 SI4914DY R217 R216 1
1UF_10V 2 10K_1% C145
330UF_4V_OSCON 10K_1% 10UF_6.3V
2
2 2

+V5AL
13-,5-

1
1 C144 1 C1097 R1098
2 0.1UF_16V 10_5%
2 10UF_6.3V
2

1 C178
2 1UF_6.3V

51120GND

INVENTEC
TITLE
TIANSHAN
SYSTEM POWER(3V/5V/12V)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 7 OF 74
 1 R1125 2 1 R1123 2

43.2K_1% 30K_1%

C1161 OPEN
1 2 51124GND

1 R221 2 1 R1126 2
30K_1% 30.9K_1%

C1162 OPEN
51124GND 1 2
+VBATR
11-,9-,7-,6-,5-,8-

V1.8_PG 14-
2 R109514-,13-,9-,7-
1
1 R1124 2 SLP_S3#_5R +VBATR
240K_5%
SLP_S5#_3R 60-,53-,47-,39-,12-
0_5% C1095 1 11-,9-,7-,6-,5-,8-
1 C1036 1 C1037 U1004 2 0.022UF_16V

1
2 2 OPEN
10UF_25V 5 6 7 8

VO2

VFB2

TONSEL

GND

VFB1

VO1
8 7 6 5 1 C1038
25 D +V1.5S
GND 2
D 7 PGOOD1 24 14- G
+V1.8 Q1011 G
PGOOD2 V1.5S_PG 10UF_25V 57-,41-,39-,25-,24-,21-,18-,10-

27-,26-,25-,21-,13-,12-
SI4800DY 0.1UF_16V 8
EN2 EN1 23 S
S Q1012
C1093 R1094 2 C1094 0.1UF_16V
1 2 9 VBST2 VBST1 22 1 4 3 2 1 SI4800DY
1 2 3 4 1 2 R1122 0_5% 0_5% 1 2
10 DRVH1 21
PAD5 DRVH2 PAD3
L20 L15
1 2 11
LL2 LL1 20 1 2
POWERPAD_2_0610
PLC1055_2R0_8.2A PLC1055_2R0_8.2A POWERPAD_2_0610
12
DRVL2 DRVL1 19 5 6 7 8
8 7 6 5

PGND2

PGND1
C183 C148

V5FILT
D

TRIP2

TRIP1
V5IN
1 D G 1
G +V5A
220UF_2.5V 53-,48-,41-,37-,36-,14-,13-,12-,9-,7- 220UF_2.5V

13

14

15

16

17

18
S
S
TI_TPS51124RGER_QFN_24P
4 3 2 1 Q1014
FDS6690AS
Q1013 1 2 3 4
FDS6690AS

1 R171 2
10_5%
1 C1163 1 C147
1 1 2 1UF_6.3V 2 4.7UF_6.3V
R1092 R1093
12K_1% 13.7K_1%
2 2

1 R1127 2
0_5%

51124GND

INVENTEC
TITLE
TIANSHAN
SYSTEM POWER(+V2.5L/+V1.5A)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 8 OF 74
 1 R247 2 1 R246 2 1 R245 2 1 R244 2

12.4K_1% 30K_1% 37.4K_1% 10K_1%

SSM3K17FU
C253 OPEN Q50
S D 1 R220 2 C252 OPEN
1 2 S D
150K_1% 1 2 +V3A
G
65-,64-,63-,60-,58-,44-,41-,40-,39-,37-,16-,14-,13-,7-
G
51124AGND 51124AGND 1 R1128 2 1 R1129 2
200K_5% D Q1023 100K_5%
1 C180 D
GG 29-
PWRPLAY
2 0.01UF_16V S
S SSM3K17FU
VCCP_PG 14-

+VBATR 10- 1 R280 2

1.2S_PG +V3S 14-,10- VGAVCC_PG
11-,8-,7-,6-,5-,9- 0_5% 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,5-
SLP_S3#_5R 1 R279 2
14-,13-,8-,7-,9-
1
OPEN R219 D1012
R1192 2 OPEN 1N4148_OPEN
1 2 1
0_5% 2 R243
2 114-,13-,8-,7-,9-
SLP_S3#_5R +VBATR
0_5%
11-,8-,7-,6-,5-,9-
1 C251
1 C1054
U29 2 OPEN

1
1 C1053 2 OPEN
5 6 7 8

VO2

VFB2

TONSEL

GND

VFB1

VO1
41-,38-,25-,24-,22-,21-,18-,17-,16-,15- 8 7 6 5 1 C1180 1 C1039
2 10UF_25V +VGAVCC
25 Q1028 D
+VCCP GND 2 10UF_25V 2 OPEN
D 7 PGOOD1 24 SI4800DY G
PGOOD2 31-,30-
Q1022 G
SI4800DY 8
EN2 EN1 23 S
S C286
1
R281 2 1 R277 2 C285 0.1UF_16V
9
VBST2 VBST1 22 4 3 2 1
1 2 3 4 1 2 1 2
0.1UF_16V 0_5% 10 DRVH1 21
0_5%
PAD6 DRVH2 PAD7
L26 L28
1 2 11
LL2 LL1 20 1 2
POWERPAD_2_0610
CYNTEC_PCMC063_1R5 CYNTEC_PCMC063_1R5 POWERPAD_2_0610
12
DRVL2 DRVL1 19 5 6 7 8
8 7 6 5

PGND2

PGND1
C249

V5FILT
D

TRIP2

TRIP1
V5IN
D G 1
Q1030 G +V5A
C197 FDS6690AS 53-,48-,41-,37-,36-,14-,13-,12-,8-,7- Q1029 220UF_2.5V

13

14

15

16

17

18
S
1 S FDS6690AS
TI_TPS51124RGER_QFN_24P
220UF_2.5V 4 3 2 1
1 2 3 4

1 R1190 2
10_5%
1 C1195 1 C1196
1 1 2 1UF_6.3V 2 4.7UF_6.3V
R1193 R278
13.0K_1% 12K_1%
2 2

1 R1189 2
0_5%

51124AGND

INVENTEC
TITLE
TIANSHAN
SYSTEM POWER (+VCCP/+VGAVCC)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 9 OF 74
+V3S
+V1.5S
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,9-,5- +V5S
+V5S 57-,41-,39-,25-,24-,21-,18-,8-
60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,5-,10-
60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,5-,10-
+V2.5S
31-,30-,24-,13-
1 1 C273
R103 +V1.2S
2.4K_1% 2 22UF_6.3V
31-,29-,13-
1 C272
2
Q26 2 1UF_6.3V
6 D 1
S 4
5 R264
2 0_5%
1 C91 1 G 3 1 R101 2 1 C293 1 C274
2
2 4.7UF_6.3V AM3446N 0_5% 1 2 22UF_6.3V2 1UF_6.3V
R102
10.2K_1% U28
6
U10 1 C92 1 C129
VCNTL
2
2 OPEN 7 5
2 10UF_6.3V POK VIN 1
CATHODE 1 C275 R268
2 3
VOUT 40.2K_1%
4 2 68PF_50V
ANODE VOUT
3
2
8 2
REF EN FB
1
VIN GND
TEC_AZ431LANTR_E1_SOT23_3P 9 1 ANPEC_APL5913_KAC_TRL_SOP_8P 1
1 R269
1 C93 R104 1
78.7K_1%
10K_1% R265 1
2 OPEN OPEN R266 2
2 100K_5%
2
2

VGAVCC_PG 14-,9-

9- 1.2S_PG

INVENTEC
TITLE
TIANSHAN
SYSTEM POWER(+V1.8/+V2.5L)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 10 OF 74
 LAYOUT NOTES: C1779 C502 C503 PIN2 CONNECT TO Q14 , Q18 GND
+V3S
C1780 C532 C531 PIN2 CONNECT TO Q16 , Q20 GND
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,10-,9-,5-,11-

2 1
D24 CHENKO_LL4148_2P C287
1 2 0.1UF_16V
5 U1011 5 U1011
1 6 1 R282 2 3 4 39-
511K_1% SB_3S_VRMPWRGD
2 FAIR_NC7WZ17_SC70_6P 2 FAIR_NC7WZ17_SC70_6P
1
C1194
0.22UF_10V 2

1 R1182 2
OPEN
+V3S +V5S
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,10-,9-,5-,11- +VBATR
60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,10-,5-
1 9-,8-,7-,6-,5-
R1180
1K_5% 1
R1162
2
10_5%
15-,11- 1 C1178 C250
VR_PWRGD_CK410 11-
2 1 5 6 7 8
MAX8770_VCC 2 2.2UF_6.3V 1 C1251 1 C1249 1 C1234 1 C1246 D
1 C255 68UF_25V G
2 10UF_25V 2 2 2
2 2.2UF_6.3V 0.01UF_50V
S
Q1032
4 3 2 1
0.01UF_50V FDS8876 +VCC_CORE
U1010 VCOREGND
19 25 18-
VCC VDD

R1157 2 L33
TON
8 1 2 1
15- 1 R1183 2 1
IMVP_CKEN# CLKEN# 200K_5% MPC1040LR45_TOKIN
0_5% 1 R1191 2 C1179 0.22UF_25V 56 7 8 5 6 7 8 1
VR_PWRGD_CK410 15-,11- 2 30
PWRGD BST1 1 R313
1 2 D D
2.2_5% R1259
18- TP712 31 G G 2.4K_1%
H_VID0 D0 Q1036 20_5% 1
18- TP717 32 29
H_VID1 D1 DH1 Q1035 2
18- TP713 33 FDS6676AS S S FDS6676AS D1017 1 R314 2 1 R315 2
H_VID2 D2 2
H_VID3 18- TP718 34
D3 LX1
28
4 3 2 1 4 3 2 1 2 6.2K_1% 10K_5%_NTC
H_VID4 18- TP714 35 C1260 1
D4
H_VID5 18- TP719 36 26 2
D5 DL1 1
H_VID6 18- TP715 37
D6 C1259 4700PF_25V 1000PF_50V_X7R C349 0.22UF_6.3V
27 2
PGND1
R1181 GND
18
SSM34_3A40V_OPEN 1 2
17- 1 2 3
PSI# PSI#
17
R1184 2 0_5% CSP1
38-,17- 1 40 16
H_DPRSTP# DPRSTP# CSN1
0_5% R1186 2
39-,21- 1 39 12
PM_DPRSLPVR DPRSLPVR FB 1 C256
R1187 499_1%
14-,5- 1 2 38 10
PWR_GOOD_3 SHDN# CCI C1247 2 OPEN
0_5% R248 1 1 10UF_25V
1 R1188 2 20 1 2 C254 R1160
PM_PWROK 2 1 C1174 BST2
0.22UF_25V R1159
43-,39-,21-
OPEN 9
CCV 2.2_5% 1 2
21 3.24K_1% C1252 VCOREGND
2 1 100PF_50V 11
DH2 1 OPEN 0.01UF_50V 5 6 7 8
REF C1175 2 2 1 1
0.22UF_6.3V C259 22 2 1 1 C1248 D
LX2
2 1R1156 7 470PF_50V 2 2 2 2
G
VCOREGND TIME Q1031
R283 71.5K_1% DL2
24 C1250
11- 1 2 6 1 C1176 1 0.01UF_50V S FDS8876
MAX8770_VCC THRM 1 R1158
23 2 OPEN
10K_5% PGND2 100_1% 4 3 2 1
R1154 L34
5
VRHOT# CSP2
14
2
2 1
20K_5% 1 C1173
R1155 2 2
1 4 15 2 1000PF_50V MPC1040LR45_TOKIN
POUT# CSN2
13
56 7 8 5 6 7 8 1 1
OPEN GNDS D D R318
41 R1258
THERMAL G 2.4K_1%
VCOREGND G
20_5% 1
MAX_MAX8770_TQFN_40P Q1033
S S FDS6676AS
2
D1016 2 1 R317 2 1 R316 2
1 C258 1 C260 18- 2
VCCSENSE 4 3 2 1 4 3 2 1 6.2K_1% 10K_5%_NTC
2 OPEN 2 OPEN C1258 1
1000PF_50V_X7R 2 C350 0.22UF_6.3V
1 2
1 SSM34_3A40V_OPEN
VCOREGND
C1257 Q1034
2 FDS6676AS
4700PF_25V

VCOREGND
1 R1161 2 18- VSSSENSE 1 C257
10_1%
1 C1177 2 OPEN

2 1000PF_50V
1 R249 2 VCOREGND
0_5%
INVENTEC
TITLE
VCOREGND TIANSHAN
CPU POWER(VCC_CORE)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 11 OF 74
 60-,53-,47-,39-,8-
SLP_S5#_3R

60-,58-,43-,39-,13- +V5A
SLP_S3#_3R
53-,48-,41-,37-,36-,14-,13-,9-,8-,7-

1
R1121
0_5%
+V1.8 2

27-,26-,25-,21-,13-,8-
+V0.9S
28-

U1006
11 1
GND VDDQSNS
10 2
VIN VLDOIN
9 3
S5 VTT
8 4
GND PGND
7 5
S3 VTTSNS
6
VTTREF
1 C186 1 C185
TI_TPS51100_DGQ_10P
1 C1160 1 C206 1 C184
2 10UF_6.3V 2 10UF_6.3V
2 1UF_6.3V 27-,26-,21- 2 2 10UF_6.3V
M_VREF 10UF_6.3V

1 C1159

2 0.1UF_16V

NOTE: DDR2 REGULATOR

INVENTEC
TITLE
TIANSHAN
DDR TERMINATION VOLTAGE
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 12 OF 74
 +V1.8 +V1.8S
+V3A 27-,26-,25-,21-,12-,8- 34-,32-,31-

65-,64-,63-,60-,58-,44-,41-,40-,39-,37-,16-,14-,9-,7-
+V3S
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,11-,10-,9-,5-
+V5A
53-,48-,41-,37-,36-,14-,12-,9-,8-,7-
Q51
6 D S 4
+V5S 5
Q1021 60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,11-,10-,5- 2
Q1026 1 3
G
4 S D 1 4 S D 1
2 2 FDC637AN
5 5
3 6 3 6 Q53
G G +V2.5S 6 D S 4
FDC638P FDC638P 5
Q1020 Q46 31-,30-,24-,10- +V1.2S
2
4 S D 1 4 S D 1 1 G
3
31-,29-,10-
2 2
5 5 C210 FDC637AN
3 6 3 6 0.01UF_16V
G G C174
FDC638P FDC638P 22UF_6.3V 1
1 C1172 C1107 4700PF_50V
2
2 OPEN 1 2
1 1 C131
1 1 1
22UF_4V
R1114 C1106
1 47_5% 22UF_4V 1 1 R267
R1149
1 R241 470_5%
2 270K_5% 1 2
470_5% R148 1 C209
2 R1152 2 470_5% 2
22UF_4V
330K_5% 1 R242
2 470_5%
2
R201
220K_5% +V5AL
+V5AL Q47 3 Q32 3 Q52 3 Q54 3
Q1027 3 2 D D 7-,5-,13- D D
7-,5-,13-
D 1G 1G 1
1G 1G
1G S S S S
R1140
S SSM3K7002F 2 SSM3K7002F 2 100K_5% 2 2
SSM3K7002F 2 SSM3K7002F SSM3K7002F
2

5 U18 Q1024 3
60-,58-,43-,39-,12- D

SLP_S3#_3R 2 4 1G 14-,9-,8-,7-
SLP_S3#_5R
S

1 3 TC7SET04F SSM3K7002F 2
R167
10K_5%
2

37- SLP_S3_5R

INVENTEC
TITLE
TIANSHAN
POWER(SLEEP)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 13 OF 74
 +V3A
1 R288 2 65-,64-,63-,60-,58-,44-,41-,40-,39-,37-,16-,13-,9-,7-,14-

1M_5%
D25 CHENKO_LL4148_2P +V3A 1

1 2 65-,64-,63-,60-,58-,44-,41-,40-,39-,37-,16-,13-,9-,7-,14-R289
10K_5%
U33 2
8
11-,5-,14- 1 R321 2 1 R290 2 5 +
PWR_GOOD_3
140K_1% 20K_5% 7 43- PWR_GOOD_KBC
6 - OUT
1
1 C352 R320 4 1 C330 +V3AL +V3AL
OPEN ON_LM393DR2G_SOP_8P
2 0.1UF_16V 2 0.1UF_16V 66-,57-,47-,45-,43-,38-,7-,6-,5-,14- 66-,57-,47-,45-,43-,38-,7-,6-,5-,14-
R218 2
10-,9- 1 2
VGAVCC_PG 1 C175
10K_5% 1
R299 2 R202 2 0.1UF_16V
8- 1
V1.5S_PG 100K_1%
10K_5% +V5A
1 R298 2 2VREF +V3S 2
V1.8_PG 8- 53-,48-,41-,37-,36-,13-,12-,9-,8-,7-
5 U17
10K_5% 7-,5- 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,13-,11-,10-,9-,5-,14-
1
2 4 43- VCC1_POR#_3
9- 1 R300 2
VCCP_PG R292 1 C140 1
10K_5% 1 R293 2 OPEN 3 R164
D26 CHENKO_LL4148_2P 1 2 0.1UF_16V 100K_5%
SLP_S3#_5R 13-,9-,8-,7-
100K_5% 2
TI_SN74LVC1G17DBVR_SOT_5P
1 2 R294
R295 10K_5% PWR_GOOD_5 2
1 2

1M_5% 2
3
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,13-,11-,10-,9-,5-,14- D

+V3S +V3A 2G Q55

S 2N7002_OPEN
65-,64-,63-,60-,58-,44-,41-,40-,39-,37-,16-,13-,9-,7-,14- 1
8
1 R322 2 1 R296 2 3 + U33
1 PWR_GOOD_3
60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,13-,11-,10-,5-,14- 68.1K_1% 20K_5%
2 - OUT
ON_LM393DR2G_SOP_8P 11-,5-,14-
+V5S 1 4
R297 1 C332 1 C331
49.9K_1%
R323 2 2 0.1UF_16V
1 2
2 1000PF_50V
102K_1%

+VADP +V3S
60-,5-,14- 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,13-,11-,10-,9-,5-,14-

60-,5- 5-
+V5S
LIMIT_SIGNAL VBIAS
60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,13-,11-,10-,5-,14-
1
65-,64-,63-,60-,58-,44-,41-,40-,39-,37-,16-,13-,9-,7-,14-
1 +VADP R180
R211 +V3A 71.5K_1%
60-,5-,14-
210K_1% 1 C168 1 C169
R207 1 2 R187
1 2 1 2
2 C176 2 1UF_6.3V 2 0.1UF_10V
1 D22 383K_1%_ OPEN ON_LM393DR2G_SOP_8P 2 0.1UF_25V R188 2 1M_5%
5- 1 1 R184 2
+VADP 1 OCP_OC 1
1 R213 47K_5% 470K_5% R179
60-,5-,14- 2 CHENKO_LL4148_2P
Q49 R1142 10K_5% 10K_5%
1 E C
3 22.6K_1% 8 3
1 2 R185 U20 2
3 + U23 1 2 9 +
1 2
B
SST3906 R212 1 43- 14 43-
ADP_ID ADP_PS0
R209 2 182K_1% 2 - OUT 10K_5% 8 - OUT
47K_5%
2 4 12
2 1
R181
1 21K_1%
R210 1 ON_LM339DR2G_SOP_14P
R214 2
200K_5% 1 2 R165
47K_5%
2 1M_5% 1 R183 2
2
60- ACOCP_EN# 1M_5%
1 1 1
R215 R1143 R182
10K_1% 2.1K_1% 43- 10K_5%
R1145 2 ADP_EN
2 2
1
1 1
3 2
1 R186 2 11 + U20
1M_5% R1146 R208 13 43- ADP_PS1
21K_1%
47K_5% 220K_5% 10 - OUT
1 ON_LM339DR2G_SOP_14P
3 D Q1025 8
2 2
R178 12
G 2 5 + U23 3 3.48K_1%
D
7 D19 1G Q48
6 - OUT
S 2
1 1 2N7002_OPEN 1 2 S
SSM3K7002F
1 CHENKO_LL4148_2P 1 2
R1141 4
0_5% R1144 ON_LM393DR2G_SOP_8P R206
10.7K_1% 220K_5%
2
2 2

INVENTEC
TITLE
5- ADP_EN# TIANSHAN
POWER(SEQUENCE)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 14 OF 74
 +V3S_CLKVDD 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,14-,13-,11-,10-,9-,5-,15-

Layout note: All decoupling 0.047uF disperse closed to pin

39- PCISTOP#_3
+V3S 39- CPUSTOP#_3

Layout note: All decoupling 0.047uF disperse closed to pin

24_5% 1 2 R406 16-

24_5% 1 2
CLK_R_CPUBCLK
R407 16- CLK_R_CPUBCLK#

1 C1279 1 C1278 1 C1282 1 C1284 1 C1281 1 C375 1 C376 1 C1280

2 10UF_10V 2 10UF_10V 2 0.047UF_10V 2 0.047UF_10V 2 0.047UF_10V 2 0.047UF_10V 2 0.047UF_10V 2 0.047UF_10V L1009
BLM11A121S 24_5% 1 2 R408 22-
1 R1283 2 24_5% 1 2
CLK_R_MCHBCLK
R409 22- CLK_R_MCHBCLK#

2
0_5% 1 C1283 1 C1265
2 0.047UF_10V 2 10UF_10V
OPEN 1 2 R410
+VCCP TP3
X4 0_5% 1 2 R411 21-
41-,38-,25-,24-,22-,21-,18-,17-,16-,9-,15- 14.31818MHZ CLK_R_REQC#

2 1 2

OPEN C3731 30PPM

1
C374
U35 0_5% 1 2 R412 57- CLK_R_REQD#
R358 33PF_50V 2 2 33PF_50V 24
VDDSRC
OPEN 1 2 R414
TP4
1 41 55
VDDSRC VDDREF
17-
CPU_BSEL1 24_5% 2
2 5 8 1 R418 39-
VDDPCI PCI_SRC_STOP#
24_5% 2 1 R419
CLK_R_PCIE_ICH
61 39- CLK_R_PCIE_ICH#
R360 Please place close to CLKGEN within 500mils CPU_STOP#
10
1K_5% VDD48
52 CLK_CPUBCLK
+VCCP CPUCLKT0
1 16 51 CLK_CPUBCLK#
VDD CPUCLKC0
41-,38-,25-,24-,22-,21-,18-,17-,16-,9-,15-
33 49 CLK_MCHBCLK
VDDSRC CPUCLKT1
R356 1 2 10K_5% 48 CLK_MCHBCLK#
CPICLKC1
21-,17- R354 1 2 2.2K_5% 50
CPU_BSEL0 1 2 12.1_1%
VDDCPU CLK_XDP
CLK_R3S_ICH48 39- R350 CPUCLKT2_ITP_CLKREQC#
45
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,14-,13-,11-,10-,9-,5-,15- 47- R351 1 2 12.1_1% 57 44 CLK_XDP#
CLK_R3S_CARD48 X1 CPUCLKC2_ITP_CLKREQD#
+V3S 56
R347 X2 CLK_PCIE_ICH
57- 1 2 35
R359 R357 CLK_R3S_LPCPCI CLK_3S_ICH48 SRCCLKT5
24_5% 2 R413
11 34 CLK_PCIE_ICH# 1 57-
2
1K_5% 0_5% 2 33_5% FSLA_USB_48MHZ SRCCLKC5
24_5% 2 R415
CLK_R_PCIE_MINI1
21- 1 1 15 1 57-
MCH_BSEL1 1 2 2.2K_5%
FSLB_TEST_MODE CLK_R_PCIE_MINI1#
CPU_BSEL2 21-,17- R399 59
REF1_FSLC_TEST_SEL SRCCLKT8
43
15- R401 1 2 0_5% R349 1 2 OPEN 42
CLK_3S_REF1 SRCCLKC8
R398 10K_5%
CLK_R3S_CBPCI 47- R352 11, 0.5 2 33_5% CLK_3S_CBPCI 6
PCICLK6 CLK_PCIE_MINI1
1 2
CLK_R3S_SIOPCI 46-
1, 0.5 R345 1 2 33_5% CLK_3S_SIOPCI 2
PCICLK4 SRCCLKT7
39 24_5% 2 1 R416 21- CLK_R_PEG_MCH
CLK_R3S_KBPCI 43-
1, 0.5 R348 1 2 33_5% CLK_3S_KBPCI 3
PCICLK5 SRCCLKC7
38 CLK_PCIE_MINI1# 24_5% 2 1 R417 21- CLK_R_PEG_MCH#
CLK_R3S_FWHPCI 63- R344 1 2 33_5% CLK_3S_FWHPCI 1
PCI_REFSEL_PCICLK3
58-
1, 0.5 R403 1 2 33_5% CLK_3S_LPCPCI 62 37 CLK_PEG_MCH
CLK_R3S_LANPCI 2 10K_5%
SEL_REQ_PCICLK2 SRCCLKT6
R346 1 60 36 CLK_PEG_MCH#
REF0_PCICLK1 SRCCLKC6
R397 1 2 OPEN
15- 54 30 CLK_SATA1 24_5% 2 1 R367 38-
CLK_3S_REF SDATA SRCCLKT4
CLK_SATA1# 24_5% 2 R368
CLK_R_SATA1
57-,44-,39-,27-,26-,20- 53 31 1 38-
57-,44-,39-,27-,26-,20- ICH_3S_SMDATA SCLK SRCCLKC4 CLK_R_SATA1#
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,14-,13-,11-,10-,9-,5-,15- ICH_3S_SMCLK CLK_3S_ICHPCI 0_5%
+V3S CLK_R3S_ICHPCI 40-
1, 0.5 R353 1 2 33_5% 7 28 R365 1 2
SELSRC_LCDCLK#_PCICLK_F1 GNDSRC 0_5%
R355 1 2 10K_5% 29 R366 1 2
GNDSRC
9
Vtt_PwrGd#_PD CLK_DOCK_REF R363
26 24_5% 2 1 60-
1 SRCCLKT3 CLK_DOCK_REF# 24_5% 2 R364
CLK_R_DOCK_REF
46 27 1 60-
R1272 VREF SRCCLKC3 CLK_R_DOCK_REF#
10K_5% 64 22
1 CLKREQA# SRCCLKT2
11- 60-,40- R378 1 2 0_5% 63 23
IMVP_CKEN# 2
R1284 CPPE# CLKREQB# SRCCLKC2
4.7K_1% 4 20
Q1037 3 GND SRCCLKT1
12 21
D 2 GND SRCCLKC1
VR_PWRGD_CK410
11- 2G 40
GNDSRC CLK_PCIE_REF
58 GND 18
S LCDCLK_SST_SRCCLKT0
CLK_PCIE_REF#
2N7002_OPEN 1
17 19
GND LCDCLK_SSC_SRCCLKC0
25
GNDSRC
32 GNDSRC 13
DOTT_96MHZ
47 14
GNDCPU DOTC_96MHz

ICS_ICS9LP306_TSSOP_64P 24_5% 2 1 R361 29-

24_5% 2 1 R362
CLK_R_PCIE_REFCLK
29- CLK_R_PCIE_REFCLK#

SRCCLK8 SRCCLK7 SRCCLK6 SRCCLK5 SRCCLK4 SRCCLK3 SRCCLK2 SRCCLK1 SRCCLK0

CLKREQA# X X X
CLKREQB# X X X
FSA FSB FSC FSB CLOCK HOST CLOCK CLKREQC# X X
FREQUENCY FREQUENCY CLKREQD# X

CLKREQ# OUTPUT CONTROL MAPPING

1 0 0 533 133
1 1 0 667 166 1 2 43- CLK_R3S_KBC14
R405 33_1%

15- 1 2 46-
CLK_3S_REF CLK_R3S_SIO14
R404 33_1%

15- 1 2 39-
CLK_3S_REF1 CLK_R3S_ICH14
R400 33_1%
INVENTEC
TITLE
TIANSHAN
CLOCK_GENERATOR
LAYOUT NOTES : THE R405 , R404 , R400 CLOSED TO U35 SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 15 OF 74
 IF R275 FOR XDP USE,INSTALL 1K_5% RESISTOR

H_A#(31:3) 22- CN13

H_A#(3) J4
A3# ADS#
H1 22- H_ADS#
H_A#(4) L4 E2 22- +VCCP
A4# BNR# H_BNR#
H_A#(5) M3
A5# BPRI#
G5 22- H_BPRI# 41-,38-,25-,24-,22-,21-,18-,17-,15-,9-,16-
H_A#(6) K5
A6# 1
H_A#(7) M1 H5 22- H_DEFER#
A7# DEFER# R1239
H_A#(8) N2
A8# DRDY#
F21 22- H_DRDY#
H_A#(9) J1 E1 22- 56_5%
A9# DBSY# H_DBSY#

ADDR GROUP 0
H_A#(10) N3
A10# 2
H_A#(11) P5
A11# BR0#
F1 22- H_BREQ#0
H_A#(12) P2

CONTROL
A12#
H_A#(13) L1
A13# IERR#
D20
H_A#(14) P4
A14# INIT#
B3 38- H_INIT# CLOSED TO CPU
H_A#(15) P1
A15#
H_A#(16) R1
A16# LOCK#
H4 22- H_LOCK#
22- L2 1 R275 2 TP5
H_ADSTB#0 ADSTB0#
H_REQ#(4:0) 22- B1 22- H_CPURST# OPEN 22- H_RS#(0:2)
RESET#
H_REQ#(0) K3
REQ0# RS0#
F3 H_RS#(0)
H_REQ#(1) H2
REQ1# RS1#
F4 H_RS#(1)
H_REQ#(2) K2 G3 H_RS#(2)
REQ2# RS2#
H_REQ#(3) J3
REQ3# TRDY#
G2 22- H_TRDY#
H_REQ#(4) L5
REQ4#
G6 22- H_HIT#
HIT#
H_A#(17) Y2
A17# HITM#
E4 22- H_HITM#
H_A#(18) U5
A18#
H_A#(19) R3
A19# BPM0#
AD4 TP6
H_A#(20) W6
A20# BPM1#
AD3 TP7

XDP/ITP SIGNALS
H_A#(21) U4 AD1 TP8

ADDR GROUP 1
A21# BPM2#
H_A#(22) Y5
A22# BPM3#
AC4 TP798
H_A#(23) U2
A23# PRDY#
AC2 TP807
H_A#(24) R4 AC1 TP11 16- +VCCP
A24# PREQ# H_BPM5_PREQ#
H_A#(25) T5 AC5 TP808 16- 41-,38-,25-,24-,22-,21-,18-,17-,15-,9-,16-
A25# TCK H_TCK
H_A#(26) T3
A26# TDI
AA6 TP809 16- TDI_FLEX
H_A#(27) W3 AB3 2 1
A27# TDO
H_A#(28) W5
A28# TMS
AB5 TP810 16- H_TMS R1166 56_5%
H_A#(29) Y4
A29# TRST#
AB6
H_A#(30) W2
A30# DBR#
C20 39- XDP_DBRESET# +V3A 1
H_A#(31) Y1
A31#
+VCCP
22- V4 D21 R1240 1 2 56_5% 65-,64-,63-,60-,58-,44-,41-,40-,39-,37-,14-,13-,9-,7- R1169
H_ADSTB#1

THERM
ADSTB1# PROCHOT# 10mils/10mils 2 1 56_5%
A24 41-,38-,25-,24-,22-,21-,18-,17-,15-,9-,16- 20-
THERMDA H_THERMDA
H_A20M# 38- A6 A25 29-,20- THERM_MINUS R1197
A20M# THERMDC 2
H_FERR# 38- A5 1K_5%
FERR#
H_IGNNE# 38- C4 C7 38-,21-,20- PM_THRMTRIP#
IGNNE# THERMTRIP#

H_STPCLK# 38- D5 5- PROC_HOT_OCP_OC#

STPCLK# H CLK
H_INTR 38- C6
LINT0
H_NMI 38- B4 A22 15- CLK_R_CPUBCLK
LINT1 BCLK0
H_SMI# 38- A3 A21 15- CLK_R_CPUBCLK#
SMI# BCLK1

AA1
RSVD01
AA4 T22
RSVD02 RSVD12
AB2
RSVD03
AA3
RESERVED

RSVD04
M4 D2
RSVD05 RSVD13
N5 F6
RSVD06 RSVD14
T2 D3
RSVD07 RSVD15 +VCCP
V3 C1
RSVD08 RSVD16
B2 AF1 41-,38-,25-,24-,22-,21-,18-,17-,15-,9-,16-
RSVD09 RSVD17
C3 D22
RSVD10 RSVD18
C23
RSVD19 R1196 2
B25 C24 1 16-
RSVD11 RSVD20 H_BPM5_PREQ#
56_5%
MLX_47170_4787_YONAH_479P 1 R1165 2 16- TDI_FLEX
56_5%
1 R1164 2 16- H_TMS
56_5%
1 R1163 2 16-
+VCCP H_TCK
GMCH CPU ICH7 56_5%

INVENTEC
TITLE
PM_THRMTRIP# should be T at CPU TIANSHAN
YONAH-1
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 16 OF 74
 H_D#(63:0) 22-,17- CN13 22-,17- H_D#(63:0)
H_D#(0) E22
1, 0.5D0# AA23 H_D#(32)
D32#
H_D#(1) F24
1, 0.5D1# AB24 H_D#(33)
D33#
H_D#(2) E26
1, 0.5D2# V24 H_D#(34)
D34#
H_D#(3) H22
1, 0.5D3# V26 H_D#(35)
D35#
H_D#(4) F23
1, 0.5D4# W25 H_D#(36)
D36#
H_D#(5) G25
1, 0.5D5# U23 H_D#(37)
D37#
H_D#(6) E25
1, 0.5D6# U25 H_D#(38)
D38#
H_D#(7) E23
1, 0.5D7# U22 H_D#(39)

DATA GRP 0

DATA GRP 2
D39#
H_D#(8) K24 AB25
1, 0.5 H_D#(40)
D8# D40#
H_D#(9) G24 W22 H_D#(41)
D9# D41#
H_D#(10) J24
1, 0.5D10# Y23 H_D#(42)
D42#
H_D#(11) J23
1, 0.5D11# AA26 H_D#(43)
D43#
H_D#(12) H26
1, 0.5D12# Y26
1, 0.5 H_D#(44)
D44#
H_D#(13) F26
1, 0.5D13# Y22 H_D#(45)
D45#
H_D#(14) K22 AC26 H_D#(46)
D14# D46#
H_D#(15) H25
1, 0.5D15# AA24 H_D#(47)
D47#
H_DSTBN#0 22- H23 W24 22-1, 0.5 H_DSTBN#2
DSTBN0# DSTBN2#
H_DSTBP#0 22- G22 Y25 22-1, 0.5 H_DSTBP#2
DSTBP0# DSTBP2#
H_DINV#0 22-
1, 0.5 J26 V23 22- H_DINV#2
DINV0# DINV2#

H_D#(63:0) 22-,17- 22-,17- H_D#(63:0)

H_D#(16) N22
1, 0.5D16# AC22 H_D#(48)
D48#
H_D#(17) K25
1, 0.5D17# AC23 H_D#(49)
D49#
H_D#(18) P26
1, 0.5D18# AB22 H_D#(50)
D50#
H_D#(19) R23 AA21 H_D#(51)
D19# D51#
H_D#(20) L25
1, 0.5D20# AB21 H_D#(52)
D52#
H_D#(21) L22 AC25 H_D#(53)
D21# D53#
H_D#(22) L23 AD20 H_D#(54)
D22# D54#

DATA GRP 1

DATA GRP 3
H_D#(23) M23
1, 0.5D23# AE22 H_D#(55)
D55#
H_D#(24) P25
1, 0.5D24# AF23 H_D#(56)
D56#
H_D#(25) P22
1, 0.5D25# AD24 H_D#(57)
D57#
H_D#(26) P23 AE21 H_D#(58)
D26# D58#
H_D#(27) T24 AD21 H_D#(59)
D27# D59#
H_D#(28) R24 AE25 H_D#(60)
+VCCP D28# D60#
H_D#(29) L26
1, 0.5D29# AF25 H_D#(61)
D61#
41-,38-,25-,24-,22-,21-,18-,16-,15-,9-,17- H_D#(30) T25 AF22 H_D#(62)
D30# D62#
H_D#(31) N24 AF26 H_D#(63)
1 1, 0.5 D31# D63#
H_DSTBN#1 22- M24 AD23 22- H_DSTBN#3
R312 1, 0.5 DSTBN1# DSTBN3#
H_DSTBP#1 22- N25 AE24 22- H_DSTBP#3
1K_1% 1, 0.5 DSTBP1# DSTBP3#
H_DINV#1 22- M26 AC20 22- H_DINV#3
DINV1# DINV3#
2
AD26
GTLREF COMP0
R26 R309 1 2 27.4_1%
U26 R310 1 2 54.9_1% +VCCP
1 COMP1
COMP2
U1 R1168 1 2 27.4_1% 41-,38-,25-,24-,22-,21-,18-,16-,15-,9-,17-
R311 C26 V1 R1167 1 2 54.9_1%
2K_1% TEST1 COMP3 1

CLOSED TO CPU WITHIN 0.5" D25 MISC E5 CLOSED TO CPU R274

2 TEST2 DPRSTP# H_DPRSTP# OPEN
B5 38-,11- 38-
DPSLP# H_DPSLP#
D24 22- H_DPWR# 2
DPWR#
CPU_BSEL0 21-,15- B22 D6 38- H_PWRGD
BSEL0 PWRGOOD
CPU_BSEL1 15- B23 D7 38-,22- H_CPUSLP#
BSEL1 SLP#
CPU_BSEL2 21-,15- C21 AE6 11- PSI#
BSEL2 PSI# 1 C279
MLX_47170_4787_YONAH_479P 1 1 2 OPEN
R276 R272
OPEN OPEN
2 2 +VCCP
1 R273 2 TP811
41-,38-,25-,24-,22-,21-,18-,16-,15-,9-,17-
1 1 OPEN
R307 R308
OPEN 51_5%
2 2 IF R273 FOR XDP USE,INSTALL 1K_5% RESISTOR

INVENTEC
TITLE
TIANSHAN
YONAH-2
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 17 OF 74
 +VCC_CORE +VCC_CORE
11-,18- 11-,18-

CN13
A7 AB20
VCC001 VCC068
A9 AB7
VCC002 VCC069
A10 AC7
PLACE THESE INSIDE SOCKET 1 C302 1 C327 1 C298 1 C1238 1 C1197 VCC003 VCC070
A12 AC9
VCC004 VCC071
A13 AC12
CAVITY ON L8 (NORTH SIDE 2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V VCC005 VCC072
A15 AC13
VCC006 VCC073
A17 AC15
SECONDARY) VCC007 VCC074
A18 AC17
VCC008 VCC075
A20 AC18
VCC009 VCC076
B7 AD7
VCC010 VCC077
B9 AD9
VCC011 VCC078
B10 AD10
VCC012 VCC079
B12 AD12
1 C305 1 C299 1 C300 1 C1237 1 C1198 VCC013 VCC080
B14 AD14
VCC014 VCC081
B15 AD15
2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V VCC015 VCC082
B17 AD17
VCC016 VCC083
B18 AD18
VCC017 VCC084
B20 AE9
VCC018 VCC085
C9 AE10
VCC019 VCC086
C10 AE12
VCC020 VCC087
C12 AE13
VCC021 VCC088
C13 AE15
VCC022 VCC089
C15 AE17
1 C323 1 C301 1 C306 1 C284 1 C280 VCC023 VCC090
C17 AE18
VCC024 VCC091
C18 AE20
PLACE THESE INSIDE SOCKET 2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V
D9
VCC025 VCC092
AF9
VCC026 VCC093
D10 AF10
CAVITY ON L8 (SOUTH SIDE VCC027 VCC094
PLACE THESE INSIDE SOCKET
D12 AF12
VCC028 VCC095 +VCCP
SECONDARY) D14
VCC029 VCC096
AF14 CAVITY ON L8 (NORTH SIDE
D15 AF15 41-,38-,25-,24-,22-,21-,17-,16-,15-,9-,18- SECONDARY)
VCC030 VCC097
D17 AF17
VCC031 VCC098
D18 AF18
VCC032 VCC099
E7 AF20
1 C304 1 C308 1 C307 1 C1199 1 C1200 VCC033 VCC0100 +VCCP
E9
VCC034
E10 V6
2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V VCC035 VCCP01 41-,38-,25-,24-,22-,21-,17-,16-,15-,9-,18-
E12 G21
VCC036 VCCP02 1 C326 1 C325 1 C324 1 C283 1 C281 1 C282
E13 J6
VCC037 VCCP03 C303
E15 K6 2 2 2 2 2 2
VCC038 VCCP04 1
E17 M6
VCC039 VCCP05 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V 0.1UF_16V
E18 J21
E20
VCC040 VCCP06
K21
220UF_2V_15mR_Panasonic
VCC041 VCCP07
F7 M21
VCC042 VCCP08
F9 N21
1 C1214 1 C1236 1 C1221 1 C1218 1 C1235 1 C1215 VCC043 VCCP09
F10 N6
VCC044 VCCP10
F12 R21
2 10UF_6.3V 2 10UF_6.3V
2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V
2 10UF_6.3V VCC045 VCCP11
F14 R6
VCC046 VCCP12
F15 T21
VCC047 VCCP13
F17 T6 +V1.5S
VCC048 VCCP14
F18 V21
VCC049 VCCP15
F20 W21 57-,41-,39-,25-,24-,21-,10-,8-,18- +V1.5S
VCC050 VCCP16
AA7
VCC051
AA9 B26 57-,41-,39-,25-,24-,21-,10-,8-,18-
VCC052 VCCA
AA10
VCC053
AA12
1 C1219 1 C1213 1 C1220 1 C1239 1 C1216 1 C1217 VCC054
AA13 AD6 11- H_VID0
VCC055 VID0
AA15 AF5 11- H_VID1
2 10UF_6.3V
2 10UF_6.3V 2 10UF_6.3V 2 10UF_6.3V
2 10UF_6.3V 2 10UF_6.3V VCC056 VID1 +VCC_CORE
AA17 AE5 11- H_VID2
VCC057 VID2
AA18 AF4 11- H_VID3 11-,18-
VCC058 VID3 1 1 C347
AA20
VCC059 VID4
AE3 11- H_VID4 C348
1
AB9
VCC060 VID5
AF2 11- H_VID5 0.01UF_16V 2 2 10UF_6.3V
AC10
VCC061 VID6
AE2 11- H_VID6 R1194
AB10
VCC062 10_1%
AB12 2
VCC063
C297 C296 C322 AB14
VCC064 VCCSENSE
AF7 11- VCCSENSE
1 1 1 AB15
SOUTH SIDE SECONDARY VCC065
AB17
330UF_2.5V 330UF_2.5V VCC066
330UF_2.5V AB18
VCC067 VSSSENSE
AE7 11- VSSSENSE

MLX_47170_4787_YONAH_479P LAYOUT NOTE:

1
PLACE C348 NEAR PIN B26
R1195
10_1%
2
C328 C309 C310
1 1 1
NORTH SIDE SECONDARY
330UF_2.5V 330UF_2.5V 330UF_2.5V

LAYOUT NOTE:
ROUTE VCCSENSE AND VSSSENSE TRACE AT
24.7 OHM WITH 50 MIL SPACEING
PLACE PU AND PD WITHIN I INCH OF CPU

INVENTEC
TITLE
TIANSHAN
YONAH-3
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 18 OF 74
 CN13
A4 P6
VSS001 VSS082
A8 P21
VSS002 VSS083
A11 P24
VSS003 VSS084
A14 R2
VSS004 VSS085
A16 R5
VSS005 VSS086
A19 R22
VSS006 VSS087
A23 R25
VSS007 VSS088
A26 T1
VSS008 VSS089
B6 T4
VSS009 VSS090
B8 T23
VSS010 VSS091
B11 T26
VSS011 VSS092
B13 U3
VSS012 VSS093
B16 U6
VSS013 VSS094
B19 U21
VSS014 VSS095
B21 U24
VSS015 VSS096
B24 V2
VSS016 VSS097
C5 V5
VSS017 VSS098
C8 V22
VSS018 VSS099
C11 V25
VSS019 VSS0100
C14 W1
VSS020 VSS0101
C16 W4
VSS021 VSS0102
C19 W23
VSS022 VSS0103
C2 W26
VSS023 VSS0104
C22 Y3
VSS024 VSS0105
C25 Y6
VSS025 VSS0106
D1 Y21
VSS026 VSS0107
D4 Y24
VSS027 VSS0108
D8 AA2
VSS028 VSS0109
D11 AA5
VSS029 VSS0110
D13 AA8
VSS030 VSS0111
D16 AA11
VSS031 VSS0112
D19 AA14
VSS032 VSS0113
D23 AA16
VSS033 VSS0114
D26 AA19
VSS034 VSS0115
E3 AA22
VSS035 VSS0116
E6 AA25
VSS036 VSS0117
E8 AB1
VSS037 VSS0118
E11 AB4
VSS038 VSS0119
E14 AB8
VSS039 VSS0120
E16 AB11
VSS040 VSS0121
E19 AB13
VSS041 VSS0122
E21 AB16
VSS042 VSS0123
E24 AB19
VSS043 VSS0124
F5 AB23
VSS044 VSS0125
F8 AB26
VSS045 VSS0126
F11 AC3
VSS046 VSS0127
F13 AC6
VSS047 VSS0128
F16 AC8
VSS048 VSS0129
F19 AC11
VSS049 VSS0130
F2 AC14
VSS050 VSS0131
F22 AC16
VSS051 VSS0132
F25 AC19
VSS052 VSS0133
G4 AC21
VSS053 VSS0134
G1 AC24
VSS054 VSS0135
G23 AD2
VSS055 VSS0136
G26 AD5
VSS056 VSS0137
H3 AD8
VSS057 VSS0138
H6 AD11
VSS058 VSS0139
H21 AD13
VSS059 VSS0140
H24 AD16
VSS060 VSS0141
J2 AD19
VSS061 VSS0142
J5 AD22
VSS062 VSS0143
J22 AD25
VSS063 VSS0144
J25 AE1
VSS064 VSS0145
K1 AE4
VSS065 VSS0146
K4 AE8
VSS066 VSS0147
K23 AE11
VSS067 VSS0148
K26 AE14
VSS068 VSS0149
L3 AE16
VSS069 VSS0150
L6 AE19
VSS070 VSS0151
L21 AE23
VSS071 VSS0152
L24 AE26
VSS072 VSS0153
M2 AF3
VSS073 VSS0154
M5 AF6
VSS074 VSS0155
M22 AF8
VSS075 VSS0156
M25 AF11
VSS076 VSS0157
N1 AF13
VSS077 VSS0158
N4 AF16
VSS078 VSS0159
N23 AF19
VSS079 VSS0160
N26 AF21
VSS080 VSS0161
P3 AF24
VSS081 VSS0162

MLX_47170_4787_YONAH_479P

INVENTEC
TITLE
TIANSHAN
YONAH-4
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 19 OF 74
 +V5S
Q1
60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,14-,13-,11-,10-,5-,20-
AO3409
2 3 CN9
S D

1 C13 G
1 1
VCC
2 G1
2 10UF_6.3V 1 C12 GND G
3 G2
REFENCE G
2 0.01UF_16V
MLX_53398_0371_3P

+V5S

60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,14-,13-,11-,10-,5-,20-

U1
PWM_3S_FAN# 43- 1 5
4 1 R6 2

THERM_3S_WARN#
20- 2 1K_5%
3
NC7SZ08M5

+V3S

66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,15-,14-,13-,11-,10-,9-,5-,20-

1 C344
2 0.1UF_16V

C346 2200PF_50V C345 2200PF_50V

1 2 1 2 This resistor is needed to place close to PM_THRMTRIP#
U34
1 10 1 R330 2 38-,21-,16-
VCC OT2# PM_THRMTRIP#
16-
OPEN 57-,44-,39-,27-,26-,15-
H_THERMDA 2 DXP1 SMBDATA 9 ICH_3S_SMDATA
LAYOUT NOTE:
29-,16- 3 DXN
Place split point of THERM_MINUS ALERT# 8 40-,39-
THERM_SCI#
THERM_MINUS near U34 DPLUS 29- 4
DXP2 SMBCLK
7 57-,44-,39-,27-,26-,15-
ICH_3S_SMCLK

THERM_3S_WARN# 20- 5 OT1# GND 6

MAX_MAX6695_SOP_10P
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,15-,14-,13-,11-,10-,9-,5-,20- LAYOUT NOTES: PUT THE THERMAL SENSOR CLOSE TO CPU
+V3S

2 1 1 R329 2

R306 0_5%
2.2K_5%

INVENTEC
TITLE
TIANSHAN
THERMAL&FAN CONTROLLER
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 20 OF 74
 MCH_CFG(12) 21-
MCH_CFG(13) 21- +V3S
MCH_CFG(16) 21- MCH_CFG(18) LOW=1.05V
MCH_CFG(9) 21- 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,20-,15-,14-,13-,11-,10-,9-,5-,21-

MCH_CFG(7) 21- VCC SELECT HIGH=1.5V

MCH_CFG(5) 21-
MCH_CFG(11) 21-
1 1 1 1 1 1
1 R1246 R1249 R1243 R1242 R1247 R1245
OPEN OPEN OPEN OPEN OPEN OPEN 1 1 1 MCH_CFG(19) LOW=NORMAL
R1244
OPEN R1211 R1214 R1215 (DMI LANE
2 2 2 2 2 2
OPEN OPEN OPEN REVERSAL) HIGH=LANES REVERSED
2
2 2 2

MCH_CFG(18) 21-
MCH_CFG(20) LOW=ONLY SDVO OR PCIE X1 IS
MCH_CFG(19) 21-
(PCIE BACKWARD OPERATIONAL
LOW=DMIx2 MCH_CFG(9) MCH_CFG(20) 21- HIGH=SDVO AND PCIE X1 ARE
MCH_CFG(7) LOW=RSVD LOW=Reverse Lane INTERPOERABILITY
MCH_CFG(5) PCIE Graphics OPERATING SIMULTANEOUSLY
HIGH=DMIx4 (CPU Strap) HIGH=Mobile CPU HIGH=Normal operation MODE VIA THE PEG PORT
Lane

LOW=Dynamic ODT MCH_CFG(11) +V1.5S_PCIE

MCH_CFG(13:12) 00=PARTIAL CLOCK GATING DISABLE MCH_CFG(16) LOW=CALISTOGA
Disable 24-
01=XOR MODE ENABLE (FSB Dynamic PSB 4X CLK U31
XOR/ALLZ 10=ALL-Z MODE ENABLE HIGH=Dynamic ODT HIGH=RESERVED R271
ODT) ENABLE D32
L_BKLTCTL EXP_A_COMPI
D40 1 2
Enable J30 D38
11=NORMAL OPERATION L_BKLTEN EXP_A_COMPO 24.9_1%
H30
L_CLKCTLA
H29 F34 30- PEG_C_RXN(0)
L_CLKCTLB EXP_A_RXN_0
G26 G38 30- PEG_C_RXN(1)
L_DDC_CLK EXP_A_RXN_1
G25 H34 30- PEG_C_RXN(2)
L_DDC_DATA EXP_A_RXN_2
U31 B38
L_IBG EXP_A_RXN_3
J38 30- PEG_C_RXN(3)
NOTE: CFG[2:0] STRP : 001b : 533 MT/S T32 AY35 26- M_CLK_DDR0 C35 L34 30- PEG_C_RXN(4)
RSVD_1 SM_CK_0 L_VBG EXP_A_RXN_4
R32 AR1 26- M_CLK_DDR1 F32 M38 30- PEG_C_RXN(5)
RSVD_2 SM_CK_1 L_VDDEN EXP_A_RXN_5
011b : 667 MT/S F3 AW7 27- C33 N34 30-
RSVD_3 SM_CK_2 M_CLK_DDR3 L_VREFH EXP_A_RXN_6 PEG_C_RXN(6)

LVDS
F7 AW40 27- M_CLK_DDR4 C32 P38 30- PEG_C_RXN(7)
RSVD_4 SM_CK_3 L_VREFL EXP_A_RXN_7
AG11 R34 30-
AF11
RSVD_5
RSVD_6
DDR MUXING SM_CK#_0
AW35 26- M_CLK_DDR0# A33
LA_CLK#
EXP_A_RXN_8
EXP_A_RXN_9
T38 30-
PEG_C_RXN(8)
PEG_C_RXN(9)
RSVD

H7 AT1 26- A32 V34 30-

66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,20-,15-,14-,13-,11-,10-,9-,5-,21-

RSVD_7 SM_CK#_1 M_CLK_DDR1# LA_CLK EXP_A_RXN_10 PEG_C_RXN(10)

J19 AY7 27- M_CLK_DDR3# E27 W38 30- PEG_C_RXN(11)
RSVD_8 SM_CK#_2 LB_CLK# EXP_A_RXN_11
A41 AY40 27- M_CLK_DDR4# E26 Y34 30- PEG_C_RXN(12)
RSVD_9 SM_CK#_3 LB_CLK EXP_A_RXN_12
A35 AA38 30- PEG_C_RXN(13)
RSVD_10 EXP_A_RXN_13
A34 AU20 28-,26- M_CKE0 C37 AB34 30- PEG_C_RXN(14)
RSVD_11 SM_CKE_0 LA_DATA#_0 EXP_A_RXN_14
D28 AT20 28-,26- M_CKE1 B35 AC38 30- PEG_C_RXN(15)
RSVD_12 SM_CKE_1 LA_DATA#_1 EXP_A_RXN_15
D27 BA29 28-,27- M_CKE2 A37
RSVD_13 SM_CKE_2 LA_DATA#_2
CPU_BSEL0 17-,15- AY29 28-,27- M_CKE3 D34 30- PEG_C_RXP(0)
SM_CKE_3 EXP_A_RXP_0
MCH_BSEL1 15- F38 30- PEG_C_RXP(1)
EXP_A_RXP_1
17-,15- AW13 28-,26- G34 30-

PCI-EXPRESS GRAPHICS
CPU_BSEL2 R1241 SM_CS#_0 M_CS0# EXP_A_RXP_2 PEG_C_RXP(2)
1K_5% AW12 28-,26- M_CS1# B37 H38 30- PEG_C_RXP(3)
SM_CS#_1 LA_DATA_0 EXP_A_RXP_3
1 2 K16 AY21 28-,27- B34 J34 30-
CFG_0 SM_CS#_2 M_CS2# LA_DATA_1 EXP_A_RXP_4 PEG_C_RXP(4)
K18 AW21 28-,27- M_CS3# A36 L38 30- PEG_C_RXP(5)
CFG_1 SM_CS#_3 LA_DATA_2 EXP_A_RXP_5
R12481 1K_5% 2 J18 M34 30-
MCH_CFG(20:3) 21-
CFG_2 M_OCDCOMP0 EXP_A_RXP_6 PEG_C_RXP(6)
MCH_CFG(3) F18
CFG_3 SM_OCDCOMP_0
AL20
EXP_A_RXP_7
N38 30- PEG_C_RXP(7)
MCH_CFG(4) E15 AF10 27-,26-,25-,13-,12-,8- M_OCDCOMP1 G30 P34 30-
CFG_4 SM_OCDCOMP_1 +V1.8 LB_DATA#_0 EXP_A_RXP_8 PEG_C_RXP(8)
MCH_CFG(5) F15
CFG_5 1 1
D30
LB_DATA#_1 EXP_A_RXP_9
R38 30- PEG_C_RXP(9)
MCH_CFG(6) E18
CFG_6 SM_ODT_0
BA13 28-,26- M_ODT0 F29
LB_DATA#_2 EXP_A_RXP_10
T34 30- PEG_C_RXP(10)

R1251
OPEN
MCH_CFG(7) D19
CFG_7 SM_ODT_1
BA12 28-,26- M_ODT1 1
R1216 EXP_A_RXP_11
V38 30- PEG_C_RXP(11)
MCH_CFG(8) D16
CFG_8 SM_ODT_2
AY20 28-,27- M_ODT2 OPEN EXP_A_RXP_12
W34 30- PEG_C_RXP(12)
R1252
CFG

MCH_CFG(9) G16
CFG_9 SM_ODT_3
AU21 28-,27- M_ODT3 2 2 EXP_A_RXP_13
Y38 30- PEG_C_RXP(13)
MCH_CFG(10) E16 80.6_1% F30 AA34 30-

57-,41-,39-,25-,24-,18-,10-,8-
CFG_10 LB_DATA_0 EXP_A_RXP_14 PEG_C_RXP(14)
MCH_CFG(11) D15 AV9 MCH_SMRCOMPN D29 AB38 30-
CFG_11 SM_RCOMP# 2 LB_DATA_1 EXP_A_RXP_15 PEG_C_RXP(15)
MCH_CFG(12) G15
CFG_12 SM_RCOMP
AT9 F28
LB_DATA_2
MCH_CFG(13) K15
CFG_13 1 EXP_A_TXN_0
F36 22- PEG_TXN(0)
+V3S MCH_CFG(14) C15
CFG_14 SM_VREF_0
AK1 27-,26-,12- M_VREF EXP_A_TXN_1
G40 22- PEG_TXN(1)
MCH_CFG(15) H16
CFG_15 SM_VREF_1
AK41 R1257 +V1.5S EXP_A_TXN_2
H36 22- PEG_TXN(2)
MCH_CFG(16) G18 80.6_1% J40 22- PEG_TXN(3)
CFG_16 EXP_A_TXN_3
MCH_CFG(17) H15 A16 L36 22- PEG_TXN(4)
MCH_CFG(18) J25
CFG_17
AF33 15- 1 C214 2
C18
TV_DACA_OUT EXP_A_TXN_4
M40 22-
1 CFG_18 G_CLKIN# CLK_R_PEG_MCH# TV_DACB_OUT EXP_A_TXN_5 PEG_TXN(5)
MCH_CFG(19) K27 AG33 15- CLK_R_PEG_MCH 20.47UF_6.3V A19 N36 22- PEG_TXN(6)
1 CFG_19 G_CLKIN TV_DACC_OUT EXP_A_TXN_6
CLK

R1213 R1212 MCH_CFG(20) J26 A27 P40 22-

10K_5% CFG_20 D_REFCLKIN# EXP_A_TXN_7 PEG_TXN(7)
OPEN D_REFCLKIN
A26 J20
TV_IREF EXP_A_TXN_8
R36 22- PEG_TXN(8)

TV
2 BM_BUSY# 39- G28 C40 B16 T40 22- PEG_TXN(9)
PM_BMBUSY# D_REFSSCLKIN# TV_IRTNA EXP_A_TXN_9
PM_EXTTS#0 27-,26- F25 D41 B18 V36 22- PEG_TXN(10)
2 PM_EXTTS#_0 D_REFSSCLKIN TV_IRTNB EXP_A_TXN_10
PM

39-,11- H26 B19 W40 22- PEG_TXN(11)

PM_DPRSLPVR PM_EXTTS#_1 TV_IRTNC EXP_A_TXN_11
PM_THRMTRIP# 38-,20-,16- G6 39- DMI_TXN(3:0) Y36 22- PEG_TXN(12)
PM_THRMTRIP# EXP_A_TXN_12
PM_PWROK 43-,39-,11- AH33 AE35 DMI_TXN(0) 41-,38-,25-,24-,22-,18-,17-,16-,15-,9- K30 AA40 22- PEG_TXN(13)
PWROK DMI_RXN_0 TV_DCONSEL0 EXP_A_TXN_13
PLT_RST# 40- 2 1 AH34 AF39 DMI_TXN(1) J29 AB36 22- PEG_TXN(14)
RSTIN# DMI_RXN_1 +VCCP TV_DCONSEL1 EXP_A_TXN_14
100_5% R270 AG35 DMI_TXN(2) AC40 22- PEG_TXN(15)
DMI_RXN_2 EXP_A_TXN_15
AH39 DMI_TXN(3)
MISC

DMI_RXN_3 R1209 2
H28 1 E23 D36 22-
SDVO_CTRLCLK CRT_BLUE EXP_A_TXP_0 PEG_TXP(0)
H27 39- DMI_TXP(3:0) D23 F40 22- PEG_TXP(1)
SDVO_CTRLDATA 0_5% CRT_BLUE# EXP_A_TXP_1
MCH_ICH_SYNC#
40- K28 AC35 DMI_TXP(0) C22 G36 22- PEG_TXP(2)
ICH_SYNC# DMI_RXP_0 CRT_GREEN EXP_A_TXP_2

VGA
CLK_R_REQC# 15- H32 AE39 DMI_TXP(1) B22 H40 22- PEG_TXP(3)
CLK_REQ# DMI_RXP_1 CRT_GREEN# EXP_A_TXP_3
AF35 DMI_TXP(2) A21 J36 22- PEG_TXP(4)
DMI_RXP_2 CRT_RED EXP_A_TXP_4
D1 AG39 DMI_TXP(3) B21 L40 22- PEG_TXP(5)
NC0 DMI_RXP_3 CRT_RED# EXP_A_TXP_5
C41 M36 22- PEG_TXP(6)
NC1 EXP_A_TXP_6
C1 39- DMI_RXN(3:0) N40 22- PEG_TXP(7)
NC2 EXP_A_TXP_7
BA41 AE37 DMI_RXN(0) C26 P36 22- PEG_TXP(8)
NC3 DMI_TXN_0 TP740 CRT_DDC_CLK EXP_A_TXP_8
BA40 AF41 DMI_RXN(1) C25 R40 22- PEG_TXP(9)
NC4 DMI_TXN_1 TP741 CRT_DDC_DATA EXP_A_TXP_9
BA39 AG37 DMI_RXN(2) G23 T36 22- PEG_TXP(10)
NC5 DMI_TXN_2 CRT_HSYNC EXP_A_TXP_10
BA3 AH41 DMI_RXN(3) J22 V40 22- PEG_TXP(11)
NC6 DMI_TXN_3 CRT_IREF EXP_A_TXP_11
BA2 H23 W36 22- PEG_TXP(12)
DMI

NC7 CRT_VSYNC EXP_A_TXP_12

NC

BA1 39- DMI_RXP(3:0) Y40 22- PEG_TXP(13)

NC8 EXP_A_TXP_13
B41 AC37 DMI_RXP(0) AA36 22- PEG_TXP(14)
NC9 DMI_TXP_0 EXP_A_TXP_14
B2 AE41 DMI_RXP(1) AB40 22- PEG_TXP(15)
NC10 DMI_TXP_1 EXP_A_TXP_15
AY41 AF37 DMI_RXP(2)
NC11 DMI_TXP_2
AY1 AG41 DMI_RXP(3) ITL_945PM_MICRO_FCBGA_1466P
NC12 DMI_TXP_3
AW41
NC13
AW1
NC14
A40
NC15
A4
NC16
A39
A3
NC17
NC18 INVENTEC
ITL_945PM_MICRO_FCBGA_1466P TITLE
TIANSHAN
CALISTOGA-1
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 21 OF 74
 17-
H_D#(63:0) 16-
H_D#(63:0) H_A#(31:3)
21- C245 0.1UF_16V 29-
PEG_TXP(0) PEG_C_TXP(0)
21-
C2461 2
0.1UF_16V 29- U31
PEG_TXP(1) PEG_C_TXP(1) H_D#(0) H_A#(3)
C2401 2 F1
1, 0.5H_D#_0 H9
0.1UF_16V H_A#_3
PEG_TXP(2) 21- 29- PEG_C_TXP(2) H_D#(1) J1
1, 0.5H_D#_1 C9 H_A#(4)
H_A#_4
1 2 H_D#(2) H1
1, 0.5H_D#_2 E11 H_A#(5)
C242 0.1UF_16V H_A#_5
PEG_TXP(3) 21- 29- PEG_C_TXP(3) H_D#(3)
1, 0.5 J6 G11 H_A#(6)
H_D#_3 H_A#_6
1 2 H_D#(4)
1, 0.5 H3 F11 H_A#(7)
C236 0.1UF_16V H_D#_4 H_A#_7
PEG_TXP(4) 21- 29- PEG_C_TXP(4) H_D#(5)
1, 0.5 K2 G12 H_A#(8)
H_D#_5 H_A#_8
H_D#(6) H_A#(9)
C2381 2 G1
1, 0.5H_D#_6 F9
0.1UF_16V H_A#_9
PEG_TXP(5) 21- 29- PEG_C_TXP(5) H_D#(7) G2
1, 0.5H_D#_7 H11 H_A#(10)
H_A#_10
1 2 H_D#(8) K9 J12 H_A#(11)
C232 0.1UF_16V H_D#_8 H_A#_11
21- 29- H_D#(9) K1 G14 H_A#(12)
PEG_TXP(6) PEG_C_TXP(6) H_D#_9 H_A#_12
1 2 1, H_D#(10)
0.5 K7
H_D#_10 H_A#_13
D9 H_A#(13)
C235 0.1UF_16V
PEG_TXP(7) 21- 29- PEG_C_TXP(7) 1, H_D#(11)
0.5 J8
H_D#_11 H_A#_14
J14 H_A#(14)
1, H_D#(12) H_A#(15)
C2281 2 0.5 H4 H13
0.1UF_16V H_D#_12 H_A#_15
PEG_TXP(8) 21- 29- PEG_C_TXP(8) H_D#(13)
1, 0.5 J3 J15 H_A#(16)
H_D#_13 H_A#_16
H_D#(14) H_A#(17)
C2311 2 K11 F14
0.1UF_16V H_D#_14 H_A#_17
21- 29- H_D#(15) G4
1, 0.5H_D#_15 D12 H_A#(18)
PEG_TXP(9) PEG_C_TXP(9) H_D#(16) H_A#_18
H_A#(19)
1 2 T10
1, 0.5H_D#_16 H_A#_19
A11
21- C223 0.1UF_16V 29- H_D#(17) W11 C11 H_A#(20)
PEG_TXP(10) PEG_C_TXP(10) 1, 0.5H_D#_17 H_A#_20
1, H_D#(18) H_A#(21)
C2271 2 0.5 T3 A12
0.1UF_16V H_D#_18 H_A#_21
PEG_TXP(11) 21- 29- PEG_C_TXP(11) H_D#(19) U7 A13 H_A#(22)
H_D#_19 H_A#_22
1, H_D#(20) H_A#(23)
C2191 2 0.5 U9 E13
0.1UF_16V H_D#_20 H_A#_23
PEG_TXP(12) 21- 29- PEG_C_TXP(12) H_D#(21) U11 G13 H_A#(24)
H_D#_21 H_A#_24
1 2 H_D#(22) T11 F12 H_A#(25)

HOST
C224 0.1UF_16V H_D#_22 H_A#_25
PEG_TXP(13) 21- 29- PEG_C_TXP(13) H_D#(23) W9
1, 0.5H_D#_23 B12 H_A#(26)
H_A#_26
1 2 H_D#(24) T1
1, 0.5H_D#_24 B14 H_A#(27)
41-,38-,25-,24-,21-,18-,17-,16-,15-,9-,22-
C216 0.1UF_16V H_A#_27
PEG_TXP(14) 21- 29- PEG_C_TXP(14) H_D#(25) T8
1, 0.5H_D#_25 C12 H_A#(28)
H_A#_28 +VCCP
H_D#(26) H_A#(29)
C2201 2 T4 A14
0.1UF_16V H_D#_26 H_A#_29
PEG_TXP(15) 21- 29- PEG_C_TXP(15) H_D#(27) W7 C14 H_A#(30)
H_D#_27 H_A#_30
1 2 H_D#(28) U5 D14 H_A#(31)
H_D#_28 H_A#_31 1
1, H_D#(29)
0.5 T9
H_D#_29
H_D#(30) W6 E8 16- R1256
C243 0.1UF_16V H_D#(31) H_D#_30 H_ADS# H_ADS# 100_1%
PEG_TXN(0) 21- 29- PEG_C_TXN(0) T5 B9 16- H_ADSTB#0
H_D#_31 H_ADSTB#_0
H_D#(32)
C2441 0.1UF_16V
2 AB7 C13 16- H_ADSTB#1 2
H_D#_32 H_ADSTB#_1
PEG_TXN(1) 21- 29- PEG_C_TXN(1) H_D#(33) AA9 J13 H_VREF
H_D#_33 H_VREF
H_D#(34)
C2391 2 W4 C6 16- H_BNR#
0.1UF_16V H_D#_34 H_BNR# 1 C1240 1
21- 29- H_D#(35) W3 F6 16-
PEG_TXN(2) PEG_C_TXN(2) H_D#(36) H_D#_35 H_BPRI# H_BPRI# R1250
1 2 Y3
H_D#_36 H_BREQ#0
C7 16- H_BREQ#0 2 0.1UF_16V
21- C241 0.1UF_16V 29- H_D#(37) Y7 B7 16- 200_1%
PEG_TXN(3) PEG_C_TXN(3) H_D#_37 H_CPURST# H_CPURST#
H_D#(38)
C2341 2 W5 A7 16- H_DBSY#
0.1UF_16V H_D#_38 H_DBSY# 2
PEG_TXN(4) 21- 29- PEG_C_TXN(4) H_D#(39) Y10 C3 16- H_DEFER#
H_D#_39 H_DEFER#
H_D#(40)
C2371 2 AB8
1, 0.5H_D#_40 J9 17- H_DPWR#
0.1UF_16V H_DPWR#
PEG_TXN(5) 21- 29- PEG_C_TXN(5) H_D#(41) W2 H8 16- H_DRDY#
H_D#_41 H_DRDY#
1 2 H_D#(42) AA4 K13
C230 0.1UF_16V H_D#_42 H_VREF
PEG_TXN(6) 21- 29- PEG_C_TXN(6) H_D#(43) AA7
H_D#_43
1 2 H_D#(44)
1, 0.5 AA2 J71, 0.5
1, 0.5
17- H_DINV#0
C233 0.1UF_16V H_D#_44 H_DINV#_0
PEG_TXN(7) 21- 29- PEG_C_TXN(7) H_D#(45) AA6 W8 17- H_DINV#1 LAYOUT NOTE:
H_D#_45 H_DINV#_1
H_D#(46)
C2261 2 AA10 U3 17- H_DINV#2 Place R1256 and R1250 close to MCH
0.1UF_16V H_D#_46 H_DINV#_2
PEG_TXN(8) 21- 29- PEG_C_TXN(8) H_D#(47) Y8 AB10 17- H_DINV#3
H_D#_47 H_DINV#_3
1 2 H_D#(48) AA1
C229 0.1UF_16V H_D#_48
21- 29- H_D#(49) AB4 K41, 0.5 17-
PEG_TXN(9) PEG_C_TXN(9) H_D#(50) H_D#_49 H_DSTBN#_0 H_DSTBN#0
1 2 AC9
H_D#_50 H_DSTBN#_1
T7 17- H_DSTBN#1
21- C221 0.1UF_16V 29- H_D#(51) AB11 Y51, 0.5 17-
PEG_TXN(10) PEG_C_TXN(10) H_D#(52) H_D#_51 H_DSTBN#_2 H_DSTBN#2
C2251 2 AC11 AC4 17- H_DSTBN#3
0.1UF_16V H_D#_52 H_DSTBN#_3
PEG_TXN(11) 21- 29- PEG_C_TXN(11) H_D#(53) AB3
H_D#_53
H_D#(54)
C2171 2 AC2 K3 17- H_DSTBP#0
0.1UF_16V H_D#_54 H_DSTBP#_0 1, 0.5
21- 29- H_D#(55) AD1 T6 17-
PEG_TXN(12) PEG_C_TXN(12) H_D#(56) H_D#_55 H_DSTBP#_1 H_DSTBP#1
1 2 AD9
H_D#_56 H_DSTBP#_2
AA5
1, 0.5 17- H_DSTBP#2
21- C222 0.1UF_16V 29- H_D#(57) AC1 AC5 17-
PEG_TXN(13) PEG_C_TXN(13) H_D#_57 H_DSTBP#_3 H_DSTBP#3
H_D#(58)
C2151 2 AD7
0.1UF_16V H_D#_58
PEG_TXN(14) 21- 29- PEG_C_TXN(14) H_D#(59) AC6
H_D#_59
H_D#(60)
C2181 0.1UF_16V
2 AB5 D3 16- H_HIT#
H_D#_60 H_HIT#
PEG_TXN(15) 21- 29- PEG_C_TXN(15) H_D#(61) AD10 D4 16- H_HITM#
H_D#_61 H_HITM#
1 2 Layout notes: H_D#(62) AD4 B3 16- H_LOCK#
H_D#_62 H_LOCK#
H_D#(63) AC8 16- H_REQ#(4:0)
Trace need be 10 mils H_D#_63

Place to near NB MCH_HXRCOMP 22-

22-
E1
E2
H_XRCOMP
D8 H_REQ#(0)
MCH_HXSCOMP H_XSCOMP H_REQ#_0
H_REQ#(1)
MCH_HXSWING 22- E4 G8
H_XSWING H_REQ#_1
B8 H_REQ#(2)
H_REQ#_2
22- Y1 F8 H_REQ#(3) 16-
MCH_HYRCOMP H_YRCOMP H_REQ#_3
H_REQ#(4)
H_RS#(2:0)
MCH_HYSCOMP 22- U1 A8
H_YSCOMP H_REQ#_4
MCH_HYSWING 22- W1
H_YSWING
B4 H_RS#(0)
H_RS#_0
15- AG2 E6 H_RS#(1)
CLK_R_MCHBCLK H_CLKIN H_RS#_1
H_RS#(2)
CLK_R_MCHBCLK# 15- AG1 D6
H_CLKIN# H_RS#_2

E3 38-,17- H_CPUSLP#
H_SLPCPU#
E7 16- H_TRDY#
H_TRDY#

ITL_945PM_MICRO_FCBGA_1466P

+VCCP +VCCP
41-,38-,25-,24-,21-,18-,17-,16-,15-,9-,22- 41-,38-,25-,24-,21-,18-,17-,16-,15-,9-,22- +VCCP
1 1 +VCCP
41-,38-,25-,24-,21-,18-,17-,16-,15-,9-,22-
R326 R1255 22- R328 1 2 54.9_1%
221_1% 221_1% R305 2 54.9_1%
41-,38-,25-,24-,21-,18-,17-,16-,15-,9-,22- MCH_HXSCOMP
22- 1
MCH_HYSCOMP
2 2
MCH_HYSWING 22- MCH_HXSWING 22-
1 1
R304 1 C339
100_1% 2
0.1UF_16V
R1254 1 C1253
100_1% 2
0.1UF_16V MCH_HYRCOMP 22- R303 1 2 24.9_1% MCH_HXRCOMP 22- R327 1 2 24.9_1%
INVENTEC
2 2 TITLE
TIANSHAN
CALISTOGA-2-HOST
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 22 OF 74
MA_DATA(63:0) MB_DATA(63:0)
26- 27-

U31 U31
AJ35 AU12 28-,26- MA_BS0# AK39 AT24 28-,27- MB_BS0#
SA_DQ0 SA_BS_0 SB_DQ0 SB_BS_0
AJ34 AV14 28-,26- MA_BS1# AJ37 AV23 28-,27- MB_BS1#
SA_DQ1 SA_BS_1 SB_DQ1 SB_BS_1
AM31 BA20 28-,26- MA_BS2# AP39 AY28 28-,27- MB_BS2#
SA_DQ2 SA_BS_2 SB_DQ2 SB_BS_2
AM33 AR41
SA_DQ3 SB_DQ3
AJ36 AY13 28-,26- MA_CAS# 26- MA_DM(7:0) AJ38 AR24 28-,27- MB_CAS# 27- MB_DM(7:0)
SA_DQ4 SA_CAS# SB_DQ4 SB_CAS#
AK35 AJ33 AK38 AK36
SA_DQ5 SA_DM_0 SB_DQ5 SB_DM_0
AJ32 AM35 AN41 AR38
SA_DQ6 SA_DM_1 SB_DQ6 SB_DM_1
AH31 AL26 AP41 AT36
SA_DQ7 SA_DM_2 SB_DQ7 SB_DM_2
AN35 AN22 AT40 BA31
SA_DQ8 SA_DM_3 SB_DQ8 SB_DM_3
AP33 AM14 AV41 AL17
SA_DQ9 SA_DM_4 SB_DQ9 SB_DM_4
AR31 AL9 AU38 AH8
SA_DQ10 SA_DM_5 SB_DQ10 SB_DM_5
AP31 AR3 AV38 BA5
SA_DQ11 SA_DM_6 SB_DQ11 SB_DM_6
AN38 AH4 AP38 AN4
SA_DQ12 SA_DM_7 SB_DQ12 SB_DM_7
AM36 26- MA_DQS(7:0) AR40 27- MB_DQS(7:0)
SA_DQ13 SB_DQ13
AM34 AK33 AW38 AM39
SA_DQ14 SA_DQS_0 SB_DQ14 SB_DQS_0
AN33 AT33 AY38 AT39
SA_DQ15 SA_DQS_1 SB_DQ15 SB_DQS_1
AK26 AN28 BA38 AU35

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY B

SA_DQ16 SA_DQS_2 SB_DQ16 SB_DQS_2
AL27 AM22 AV36 AR29
SA_DQ17 SA_DQS_3 SB_DQ17 SB_DQS_3
AM26 AN12 AR36 AR16
SA_DQ18 SA_DQS_4 SB_DQ18 SB_DQS_4
AN24 AN8 AP36 AR10
SA_DQ19 SA_DQS_5 SB_DQ19 SB_DQS_5
AK28 AP3 BA36 AR7
SA_DQ20 SA_DQS_6 SB_DQ20 SB_DQS_6
AL28 AG5 26- MA_DQS#(7:0) AU36 AN5 27- MB_DQS#(7:0)
SA_DQ21 SA_DQS_7 SB_DQ21 SB_DQS_7
AM24 AK32 AP35 AM40
SA_DQ22 SA_DQS#_0 SB_DQ22 SB_DQS#_0
AP26 AU33 AP34 AU39
SA_DQ23 SA_DQS#_1 SB_DQ23 SB_DQS#_1
AP23 AN27 AY33 AT35
SA_DQ24 SA_DQS#_2 SB_DQ24 SB_DQS#_2
AL22 AM21 BA33 AP29
SA_DQ25 SA_DQS#_3 SB_DQ25 SB_DQS#_3
AP21 AM12 AT31 AP16
SA_DQ26 SA_DQS#_4 SB_DQ26 SB_DQS#_4
AN20 AL8 AU29 AT10
SA_DQ27 SA_DQS#_5 SB_DQ27 SB_DQS#_5
AL23 AN3 AU31 AT7
SA_DQ28 SA_DQS#_6 SB_DQ28 SB_DQS#_6
AP24 AH5 AW31 AP5
SA_DQ29 SA_DQS#_7 SB_DQ29 SB_DQS#_7
AP20 28-,26- MA_A(13:0) AV29 28-,27- MB_A(13:0)
SA_DQ30 SB_DQ30
AT21 AY16 AW29 AY23
SA_DQ31 SA_MA_0 SB_DQ31 SB_MA_0
AR12 AU14 AM19 AW24
SA_DQ32 SA_MA_1 SB_DQ32 SB_MA_1
AR14 AW16 AL19 AY24
SA_DQ33 SA_MA_2 SB_DQ33 SB_MA_2
AP13 BA16 AP14 AR28
SA_DQ34 SA_MA_3 SB_DQ34 SB_MA_3
AP12 BA17 AN14 AT27
SA_DQ35 SA_MA_4 SB_DQ35 SB_MA_4
AT13 AU16 AN17 AT28
SA_DQ36 SA_MA_5 SB_DQ36 SB_MA_5
AT12 AV17 AM16 AU27
SA_DQ37 SA_MA_6 SB_DQ37 SB_MA_6
AL14 AU17 AP15 AV28
SA_DQ38 SA_MA_7 SB_DQ38 SB_MA_7
AL12 AW17 AL15 AV27
SA_DQ39 SA_MA_8 SB_DQ39 SB_MA_8
AK9 AT16 AJ11 AW27
SA_DQ40 SA_MA_9 SB_DQ40 SB_MA_9
AN7 AU13 AH10 AV24
SA_DQ41 SA_MA_10 SB_DQ41 SB_MA_10
AK8 AT17 AJ9 BA27
SA_DQ42 SA_MA_11 SB_DQ42 SB_MA_11
AK7 AV20 AN10 AY27
SA_DQ43 SA_MA_12 SB_DQ43 SB_MA_12
AP9 AV12 AK13 AR23
SA_DQ44 SA_MA_13 SB_DQ44 SB_MA_13
AN9 AH11
SA_DQ45 SB_DQ45
AT5 AW14 28-,26- MA_RAS# AK10 AU23 28-,27- MB_RAS#
SA_DQ46 SA_RAS# SB_DQ46 SB_RAS#
AL5 AK23 TP595 AJ8 AK16 TP602
SA_DQ47 SA_RCVENIN# SB_DQ47 SB_RCVENIN#
AY2 AK24 TP596 BA10 AK18 TP603
SA_DQ48 SA_RCVENOUT# SB_DQ48 SB_RCVENOUT#
AW2 AY14 28-,26- MA_WE# AW10 AR27 28-,27- MB_WE#
SA_DQ49 SA_WE# SB_DQ49 SB_WE#
AP1 BA4
SA_DQ50 SB_DQ50
AN2 AW4
SA_DQ51 SB_DQ51
AV2 AY10
SA_DQ52 SB_DQ52
AT3 AY9
SA_DQ53 SB_DQ53
AN1 AW5
SA_DQ54 SB_DQ54
AL2 AY5
SA_DQ55 SB_DQ55
AG7 AV4
SA_DQ56 SB_DQ56
AF9 1, 0.05 AR5
SA_DQ57 SB_DQ57
AG4 AK4
SA_DQ58 SB_DQ58
AF6 AK3
SA_DQ59 SB_DQ59
AG9 0, 0.05 AT4
SA_DQ60 SB_DQ60
AH6 AK5
SA_DQ61 SB_DQ61
AF4 AJ5
SA_DQ62 SB_DQ62
AF8 AJ3
SA_DQ63 SB_DQ63

ITL_945PM_MICRO_FCBGA_1466P ITL_945PM_MICRO_FCBGA_1466P

INVENTEC
TITLE
TIANSHAN
CALISTOGA-3-DDR2
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 23 OF 74
 NOTE:
CAPS USED IN +V1.5S_PCIE +V1.5S_PCIE
+V1.5S SHOULD BE WITHIN ON TOP 21-
LAYER
57-,41-,39-,25-,21-,18-,10-,8-,24-
1 L27 2
ICB_1206_3.0A
1 C211 1 C277 1 C278
41-,38-,25-,22-,21-,18-,17-,16-,15-,9-,24-
220UF_2.5V
2 10UF_6.3V 2 10UF_6.3V
+V1.5S +VCCP
57-,41-,39-,25-,21-,18-,10-,8-,24- U31
1 L29 2 H22
VCCSYNC
BLM11B121SB VTT_0
AC14
C30 AB14
1 C276 VCC_TXLVDS0 VTT_1
1 C1203 B30 W14 C1225
VCC_TXLVDS1 VTT_2 1 C1202 1 C1224 1 C1242 1
2 10UF_6.3V 2 0.1UF_16V A30
VCC_TXLVDS2 VTT_3
V14
T14 2 2.2UF_6.3V 2 0.22UF_10V
VTT_4 2 4.7UF_6.3V
AJ41 R14
VCC3G0 VTT_5
AB41 P14 220UF_2V_15mR_Panasonic
41-,38-,25-,22-,21-,18-,17-,16-,15-,9-,24- NOTE: +V2.5S VCC3G1 VTT_6
Y41 N14
+VCCP 10UF CAPS USED IN 31-,30-,13-,10- VCC3G2 VTT_7
V41 M14
+V1.5S 3GPLL SHOULD 1 VCC3G3 VTT_8
C1181 R41 L14 PLACE IN CAVITY PLACE ON THE EDGE
R1210 2 BEPLACED IN CAVITY VCC3G4 VTT_9
1 0.1UF_16V N41 AD13
2 VCC3G5 VTT_10
L41 AC13
0_5% +V1.5S_3GPLL VCC3G6 VTT_11
AC33 AB13
VCCA_3GPLL VTT_12
G41 AA13
CLOSE TO NB WITHIN 200mils H41
VCCA_3GBG VTT_13
Y13
VSSA_3GBG VTT_14
W13
+V2.5S_CRTDAC VTT_15
F21 V13
VCCA_CRTDAC0 VTT_16
E21 U13
57-,41-,39-,25-,21-,18-,10-,8-,24- VCCA_CRTDAC1 VTT_17
G21 T13
VSSA_CRTDAC VTT_18
+V1.5S +V1.5S R13
VTT_19
57-,41-,39-,25-,21-,18-,10-,8-,24- R286 1 2 OPEN B26
VCCA_DPLLA VTT_20
N13
L31 CLOSE TO AF1 R1198 1 2 OPEN C39
VCCA_DPLLB VTT_21
M13
1 2 +V1.5S_DPLL AF1 L13
1 VCCA_HPLL VTT_22
C354 1 AB12
BLM11B121SB C337 VTT_23

POWER
A38 AA12
22UF_4V 2 0.1UF_16V VCCA_LVDS VTT_24
B39 Y12
VSSA_LVDS VTT_25
W12
NOTE: VTT_26
AF2 V12
0.1UF CAPS IN +1.5V_xPLL VCCA_MPLL VTT_27
U12
NEED TO BE LOCATED AS VTT_28
H20 T12
VCCA_TVBG VTT_29
+V1.5S EDGE CAPS WITHIN 200 MILS G20
VSSA_TVBG VTT_30
R12
P12
VTT_31
57-,41-,39-,25-,21-,18-,10-,8-,24- N12
1 L32 2
VTT_32
+V1.5S_MPLL M12
VTT_33
BLM11A121S 1
E19
VCCA_TVDACA0 VTT_34
L12
1 C1256 F19 R11
C1255 VCCA_TVDACA1 VTT_35
2 0.1UF_16V +V1.5S C20 P11
2 22UF_6.3V VCCA_TVDACB0 VTT_36
D20 N11
VCCA_TVDACB1 VTT_37
57-,41-,39-,25-,21-,18-,10-,8-,24- E20 M11
+V1.5S VCCA_TVDACC0 VTT_38
F20 R10
VCCA_TVDACC1 VTT_39
57-,41-,39-,25-,21-,18-,10-,8-,24- P10
VTT_40
AH1 N10
VCCD_HMPLL0 VTT_41
AH2 M10
VCCD_HMPLL1 VTT_42
P9
VTT_43
A28 N9
VCCD_LVDS0 VTT_44
B28 M9
VCCD_LVDS1 VTT_45
+V1.5S C28 R8
VCCD_LVDS2 VTT_46
+V3S P8
VTT_47
57-,41-,39-,25-,21-,18-,10-,8-,24- D21 N8
VCCD_TVDAC VTT_48
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,21-,20-,15-,14-,13-,11-,10-,9-,5- M8
VTT_49
A23 P7
VCC_HV0 VTT_50
B23 N7
1 1 C1223 VCC_HV1 VTT_51
C1222 +V1.5S B25
VCC_HV2 VTT_52
M7
10UF_6.3V 2 2 0.1UF_16V VTT_53
R6
57-,41-,39-,25-,21-,18-,10-,8-,24- H19 P6
VCCD_QTVDAC VTT_54
M6
VTT_55 VTTLF_CAP3
AK31 A6
VCCAUX0 VTT_56
AF31 R5
VCCAUX1 VTT_57 1
AE31 P5 C341
VCCAUX2 VTT_58
AC31 N5 2 0.47UF_6.3V
VCCAUX3 VTT_59
AL30 M5
VCCAUX4 VTT_60
AK30 P4
VCCAUX5 VTT_61
AJ30 N4
VCCAUX6 VTT_62
AH30 M4
VCCAUX7 VTT_63
AG30 R3
VCCAUX8 VTT_64
+V1.5S AF30 P3
VCCAUX9 VTT_65
AE30 N3
VCCAUX10 VTT_66
57-,41-,39-,25-,21-,18-,10-,8-,24- AD30 M3
VCCAUX11 VTT_67
AC30 R2
VCCAUX12 VTT_68
AG29 P2
VCCAUX13 VTT_69
AF29 M2
AE29
VCCAUX14 VTT_70
D2
VTTLF_CAP2
1 C1227 VCCAUX15 VTT_71
AD29 AB1
VCCAUX16 VTT_72 1
2 0.1UF_16V AC29
VCCAUX17 VTT_73
R1 VTTLF_CAP1 1 C338
C356
AG28 P1 2 0.22UF_6.3V
VCCAUX18 VTT_74
AF28 N1 2 0.47UF_6.3V
VCCAUX19 VTT_75
AE28 M1
VCCAUX20 VTT_76
AH22
VCCAUX21
AJ21
VCCAUX22
AH21
VCCAUX23
AJ20
VCCAUX24
AH20
VCCAUX25
AH19
VCCAUX26
P19
VCCAUX27
P16
VCCAUX28
AH15
VCCAUX29
P15
VCCAUX30
AH14
VCCAUX31
AG14
VCCAUX32
AF14
VCCAUX33
AE14
Y14
AF13
AE13
VCCAUX34
VCCAUX35
VCCAUX36
INVENTEC
VCCAUX37 TITLE
AF12
AE12
VCCAUX38 TIANSHAN
AD12
VCCAUX39 CALISTOGA-4-POWER
VCCAUX40
SIZE CODE DOC. NUMBER REV
ITL_945PM_MICRO_FCBGA_1466P A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 24 OF 74
 U31
AA33 41-,38-,24-,22-,21-,18-,17-,16-,15-,9-,25-
VCC_0
W33
VCC_1 +VCCP
P33
VCC_2
U31 U31 U31
N33 AU41 AD27 AC41 AK34 AT23 J11
+VCCP VCC_3 VCC_SM_0 VCC_SM_LF4 VCC_NCTF0 VSS_0 VSS_97 VSS_180 VSS_273
L33 AT41 AC27 AE27 AA41 AG34 AN23 D11
VCC_4 VCC_SM_1 VCC_NCTF1 VSS_NCTF0 VSS_1 VSS_98 VSS_181 VSS_274
J33 AM41 VCC_SM_LF5 AB27 AE26 W41 AF34 AM23 B11
41-,38-,24-,22-,21-,18-,17-,16-,15-,9-,25- VCC_5 VCC_SM_2 VCC_NCTF2 VSS_NCTF1 VSS_2 VSS_99 VSS_182 VSS_275
AA32 AU40 AA27 AE25 T41 AE34 AH23 AV10
VCC_6 VCC_SM_3 VCC_NCTF3 VSS_NCTF2 VSS_3 VSS_100 VSS_183 VSS_276
Y32 BA34 Y27 AE24 P41 AC34 AC23 AP10
VCC_7 VCC_SM_4 VCC_NCTF4 VSS_NCTF3 VSS_4 VSS_101 VSS_184 VSS_277
C342 W32 AY34 W27 AE23 M41 C34 W23 AL10
1 1 VCC_8 VCC_SM_5 1 C213 1 C212 VCC_NCTF5 VSS_NCTF4 VSS_5 VSS_102 VSS_185 VSS_278
V32 AW34 V27 AE22 J41 AW33 K23 AJ10
VCC_9 VCC_SM_6 VCC_NCTF6 VSS_NCTF5 VSS_6 VSS_103 VSS_186 VSS_279
P32 AV34 2 0.47UF_6.3V 2 0.47UF_6.3V U27 AE21 F41 AV33 J23 AG10
220UF_2V_15mR_Panasonic VCC_10 VCC_SM_7 VCC_NCTF7 VSS_NCTF6 VSS_7 VSS_104 VSS_187 VSS_280
N32 AU34 T27 AE20 AV40 AR33 F23 AC10
VCC_11 VCC_SM_8 VCC_NCTF8 VSS_NCTF7 VSS_8 VSS_105 VSS_188 VSS_281
C343 M32
VCC_12 VCC_SM_9
AT34 R27
VCC_NCTF9 VSS_NCTF8
AE19 AP40
VSS_9 VSS_106
AE33 C23
VSS_189 VSS_282
W10
220UF_2V_15mR_Panasonic L32 AR34 AD26 AE18 AN40 AB33 AA22 U10
VCC_13 VCC_SM_10 VCC_NCTF10 VSS_NCTF9 VSS_10 VSS_107 VSS_190 VSS_283
J32 BA30 AC26 AC17 AK40 Y33 K22 BA9
VCC_14 VCC_SM_11 VCC_NCTF11 VSS_NCTF10 VSS_11 VSS_108 VSS_191 VSS_284

NCTF
AA31 AY30 AB26 Y17 AJ40 V33 G22 AW9
VCC_15 VCC_SM_12 VCC_NCTF12 VSS_NCTF11 VSS_12 VSS_109 VSS_192 VSS_285
W31 AW30 AA26 U17 AH40 T33 F22 AR9
VCC_16 VCC_SM_13 VCC_NCTF13 VSS_NCTF12 VSS_13 VSS_110 VSS_193 VSS_286
V31 AV30 Y26 AG40 R33 E22 AH9
VCC_17 VCC_SM_14 VCC_NCTF14 VSS_14 VSS_111 VSS_194 VSS_287
T31 AU30 W26 +V1.5S AF40 M33 D22 AB9
1 C1254 1 C340 1 C355 VCC_18 VCC_SM_15 VCC_NCTF15 VSS_15 VSS_112 VSS_195 VSS_288
R31 AT30 V26 AE40 H33 A22 Y9
VCC_19 VCC_SM_16 VCC_NCTF16 VSS_16 VSS_113 VSS_196 VSS_289
P31 AR30 U26 57-,41-,39-,24-,21-,18-,10-,8-B40 G33 BA21 R9
2 10UF_6.3V 2 1UF_6.3V 2 10UF_6.3V VCC_20 VCC_SM_17 VCC_NCTF17 VSS_17 VSS_114 VSS_197 VSS_290
N31 AP30 T26 AY39 F33 AV21 G9
VCC_21 VCC_SM_18 VCC_NCTF18 VSS_18 VSS_115 VSS_198 VSS_291
M31 AN30 R26 AG27 AW39 D33 AR21 E9
VCC_22 VCC_SM_19 VCC_NCTF19 VCCAUX_NCTF0 VSS_19 VSS_116 VSS_199 VSS_292
AA30 AM30 AD25 AF27 AV39 B33 AN21 A9
VCC_23 VCC_SM_20 VCC_NCTF20 VCCAUX_NCTF1 VSS_20 VSS_117 VSS_200 VSS_293
Y30 AM29 AC25 AG26 AR39 AH32 AL21 AG8
VCC_24 VCC_SM_21 VCC_NCTF21 VCCAUX_NCTF2 VSS_21 VSS_118 VSS_201 VSS_294
W30 AL29 AB25 AF26 AN39 AG32 AB21 AD8
VCC_25 VCC_SM_22 VCC_NCTF22 VCCAUX_NCTF3 VSS_22 VSS_119 VSS_202 VSS_295
V30 AK29 AA25 AG25 AJ39 AF32 Y21 AA8
VCC_26 VCC_SM_23 VCC_NCTF23 VCCAUX_NCTF4 VSS_23 VSS_120 VSS_203 VSS_296
U30 AJ29 Y25 AF25 AC39 AE32 P21 U8
1 C1241 1 C1201 1 C1226 VCC_27 VCC_SM_24 VCC_NCTF24 VCCAUX_NCTF5 VSS_24 VSS_121 VSS_204 VSS_297
T30 AH29 W25 AG24 AB39 AC32 K21 K8
VCC_28 VCC_SM_25 VCC_NCTF25 VCCAUX_NCTF6 VSS_25 VSS_122 VSS_205 VSS_298
2 0.22UF_6.3V 2 0.22UF_6.3V 2 0.22UF_6.3V R30 AJ28 V25 AF24 AA39 AB32 J21 C8
VCC_29 VCC_SM_26 VCC_NCTF26 VCCAUX_NCTF7 VSS_26 VSS_123 VSS_206 VSS_299
P30 AH28 U25 AG23 Y39 G32 H21 BA7
VCC_30 VCC_SM_27 VCC_NCTF27 VCCAUX_NCTF8 VSS_27 VSS_124 VSS_207 VSS_300
N30 AJ27 T25 AF23 W39 B32 C21 AV7
VCC_31 VCC_SM_28 VCC_NCTF28 VCCAUX_NCTF9 VSS_28 VSS_125 VSS_208 VSS_301

VSS

VSS
M30 AH27 R25 AG22 V39 AY31 AW20 AP7
VCC_32 VCC_SM_29 VCC_NCTF29 VCCAUX_NCTF10 VSS_29 VSS_126 VSS_209 VSS_302
L30 BA26 AD24 AF22 T39 AV31 AR20 AL7
VCC_33 VCC_SM_30 VCC_NCTF30 VCCAUX_NCTF11 VSS_30 VSS_127 VSS_210 VSS_303
AA29 AY26 AC24 AG21 R39 AN31 AM20 AJ7
VCC_34 VCC_SM_31 VCC_NCTF31 VCCAUX_NCTF12 VSS_31 VSS_128 VSS_211 VSS_304
Y29 AW26 AB24 AF21 P39 AJ31 AA20 AH7
VCC_35 VCC_SM_32 VCC_NCTF32 VCCAUX_NCTF13 VSS_32 VSS_129 VSS_212 VSS_305
W29 AV26 AA24 AG20 N39 AG31 K20 AF7
VCC_36 VCC_SM_33 VCC_NCTF33 VCCAUX_NCTF14 VSS_33 VSS_130 VSS_213 VSS_306
V29 AU26 Y24 AF20 M39 AB31 B20 AC7
VCC_37 VCC_SM_34 VCC_NCTF34 VCCAUX_NCTF15 VSS_34 VSS_131 VSS_214 VSS_307
U29 AT26 W24 AG19 L39 Y31 A20 R7
VCC_38 VCC_SM_35 VCC_NCTF35 VCCAUX_NCTF16 VSS_35 VSS_132 VSS_215 VSS_308
R29 AR26 V24 AF19 J39 AB30 AN19 G7
VCC_39 VCC_SM_36 VCC_NCTF36 VCCAUX_NCTF17 VSS_36 VSS_133 VSS_216 VSS_309
P29 AJ26 U24 R19 H39 E30 AC19 D7
VCC_40 VCC_SM_37 VCC_NCTF37 VCCAUX_NCTF18 VSS_37 VSS_134 VSS_217 VSS_310
M29 AH26 T24 AG18 G39 AT29 W19 AG6
VCC_41 VCC_SM_38 VCC_NCTF38 VCCAUX_NCTF19 VSS_38 VSS_135 VSS_218 VSS_311
L29 AJ25 R24 AF18 F39 AN29 K19 AD6
VCC_42 VCC_SM_39 VCC_NCTF39 VCCAUX_NCTF20 VSS_39 VSS_136 VSS_219 VSS_312
AB28 AH25 AD23 R18 D39 AB29 G19 AB6
VCC_43 VCC_SM_40 VCC_NCTF40 VCCAUX_NCTF21 VSS_40 VSS_137 VSS_220 VSS_313
AA28 AJ24 V23 AG17 AT38 T29 C19 Y6
VCC_44 VCC_SM_41 VCC_NCTF41 VCCAUX_NCTF22 VSS_41 VSS_138 VSS_221 VSS_314
Y28 AH24 U23 AF17 AM38 N29 AH18 U6
VCC_45 VCC_SM_42 VCC_NCTF42 VCCAUX_NCTF23 VSS_42 VSS_139 VSS_222 VSS_315
VCC

V28 BA23 T23 AE17 AH38 K29 P18 N6

VCC_46 VCC_SM_43 VCC_NCTF43 VCCAUX_NCTF24 VSS_43 VSS_140 VSS_223 VSS_316
U28 AJ23 R23 AD17 AG38 G29 H18 K6
VCC_47 VCC_SM_44 VCC_NCTF44 VCCAUX_NCTF25 VSS_44 VSS_141 VSS_224 VSS_317
T28 BA22 AD22 AB17 AF38 E29 D18 H6
VCC_48 VCC_SM_45 VCC_NCTF45 VCCAUX_NCTF26 VSS_45 VSS_142 VSS_225 VSS_318
R28 AY22 V22 AA17 AE38 C29 A18 B6
VCC_49 VCC_SM_46 1 C294 VCC_NCTF46 VCCAUX_NCTF27 VSS_46 VSS_143 VSS_226 VSS_319
P28 AW22 U22 W17 C38 B29 AY17 AV5
VCC_50 VCC_SM_47 VCC_NCTF47 VCCAUX_NCTF28 VSS_47 VSS_144 VSS_227 VSS_320
N28 AV22 2 0.47UF_6.3V T22 V17 AK37 A29 AR17 AF5
VCC_51 VCC_SM_48 VCC_NCTF48 VCCAUX_NCTF29 VSS_48 VSS_145 VSS_228 VSS_321
M28 AU22 R22 T17 AH37 BA28 AP17 AD5
VCC_52 VCC_SM_49 VCC_NCTF49 VCCAUX_NCTF30 VSS_49 VSS_146 VSS_229 VSS_322
L28 AT22 AD21 R17 AB37 AW28 AM17 AY4
VCC_53 VCC_SM_50 VCC_NCTF50 VCCAUX_NCTF31 VSS_50 VSS_147 VSS_230 VSS_323
P27 AR22 V21 AG16 AA37 AU28 AK17 AR4
VCC_54 VCC_SM_51 VCC_NCTF51 VCCAUX_NCTF32 VSS_51 VSS_148 VSS_231 VSS_324
N27 AP22 U21 AF16 Y37 AP28 AV16 AP4
VCC_55 VCC_SM_52 VCC_NCTF52 VCCAUX_NCTF33 VSS_52 VSS_149 VSS_232 VSS_325
M27 AK22 T21 AE16 W37 AM28 AN16 AL4
VCC_56 VCC_SM_53 VCC_NCTF53 VCCAUX_NCTF34 VSS_53 VSS_150 VSS_233 VSS_326
L27 AJ22 R21 AD16 V37 AD28 AL16 AJ4
VCC_57 VCC_SM_54 VCC_NCTF54 VCCAUX_NCTF35 VSS_54 VSS_151 VSS_234 VSS_327
P26 AK21 AD20 AC16 T37 AC28 J16 Y4
VCC_58 VCC_SM_55 VCC_NCTF55 VCCAUX_NCTF36 VSS_55 VSS_152 VSS_235 VSS_328
N26 AK20 V20 AB16 R37 W28 F16 U4
VCC_59 VCC_SM_56 VCC_NCTF56 VCCAUX_NCTF37 VSS_56 VSS_153 VSS_236 VSS_329
L26 BA19 U20 AA16 P37 J28 C16 R4
VCC_60 VCC_SM_57 VCC_NCTF57 VCCAUX_NCTF38 VSS_57 VSS_154 VSS_237 VSS_330
N25 AY19 T20 Y16 N37 E28 AN15 J4
VCC_61 VCC_SM_58 VCC_NCTF58 VCCAUX_NCTF39 VSS_58 VSS_155 VSS_238 VSS_331
M25 AW19 R20 W16 M37 AP27 AM15 F4
VCC_62 VCC_SM_59 VCC_NCTF59 VCCAUX_NCTF40 VSS_59 VSS_156 VSS_239 VSS_332
L25 AV19 AD19 V16 L37 AM27 AK15 C4
VCC_63 VCC_SM_60 VCC_NCTF60 VCCAUX_NCTF41 VSS_60 VSS_157 VSS_240 VSS_333
P24 AU19 V19 U16 J37 AK27 N15 AY3
VCC_64 VCC_SM_61 VCC_NCTF61 VCCAUX_NCTF42 VSS_61 VSS_158 VSS_241 VSS_334
N24 AT19 U19 T16 H37 J27 M15 AW3
VCC_65 VCC_SM_62 VCC_NCTF62 VCCAUX_NCTF43 VSS_62 VSS_159 VSS_242 VSS_335
M24 AR19 T19 R16 G37 G27 L15 AV3
VCC_66 VCC_SM_63 VCC_NCTF63 VCCAUX_NCTF44 VSS_63 VSS_160 VSS_243 VSS_336
AB23 AP19 AD18 AG15 F37 F27 B15 AL3
VCC_67 VCC_SM_64 VCC_NCTF64 VCCAUX_NCTF45 VSS_64 VSS_161 VSS_244 VSS_337
AA23 AK19 AC18 AF15 D37 C27 A15 AH3
VCC_68 VCC_SM_65 VCC_NCTF65 VCCAUX_NCTF46 VSS_65 VSS_162 VSS_245 VSS_338
Y23 AJ19 AB18 AE15 AY36 B27 BA14 AG3
VCC_69 VCC_SM_66 VCC_NCTF66 VCCAUX_NCTF47 VSS_66 VSS_163 VSS_246 VSS_339
P23 AJ18 AA18 AD15 AW36 AN26 AT14 AF3
VCC_70 VCC_SM_67 VCC_NCTF67 VCCAUX_NCTF48 VSS_67 VSS_164 VSS_247 VSS_340
N23 AJ17 Y18 AC15 AN36 M26 AK14 AD3
VCC_71 VCC_SM_68 VCC_NCTF68 VCCAUX_NCTF49 VSS_68 VSS_165 VSS_248 VSS_341
M23 AH17 W18 AB15 AH36 K26 AD14 AC3
VCC_72 VCC_SM_69 VCC_NCTF69 VCCAUX_NCTF50 VSS_69 VSS_166 VSS_249 VSS_342
L23 AJ16 V18 AA15 AG36 F26 AA14 AA3
VCC_73 VCC_SM_70 VCC_NCTF70 VCCAUX_NCTF51 VSS_70 VSS_167 VSS_250 VSS_343
AC22 AH16 U18 Y15 AF36 D26 U14 G3
AB22
VCC_74 VCC_SM_71
BA15
NEAR PIN BA15 ON LAYER T18
VCC_NCTF71 VCCAUX_NCTF52
W15 AE36
VSS_71 VSS_168
AK25 K14
VSS_251 VSS_344
AT2
VCC_75 VCC_SM_72 VCC_NCTF72 VCCAUX_NCTF53 VSS_72 VSS_169 VSS_252 VSS_345
Y22 AY15 V15 AC36 P25 H14 AR2
VCC_76 VCC_SM_73 VCCAUX_NCTF54 VSS_73 VSS_170 VSS_253 VSS_346
W22 AW15 U15 C36 K25 E14 AP2
VCC_77 VCC_SM_74 1 C321 VCCAUX_NCTF55 VSS_74 VSS_171 VSS_254 VSS_347
P22 AV15 T15 B36 H25 AV13 AK2
VCC_78 VCC_SM_75 VCCAUX_NCTF56 VSS_75 VSS_172 VSS_255 VSS_348
N22 AU15 2 0.47UF_6.3V R15 BA35 E25 AR13 AJ2
VCC_79 VCC_SM_76 VCCAUX_NCTF57 VSS_76 VSS_173 VSS_256 VSS_349
M22 AT15 AV35 D25 AN13 AD2
VCC_80 VCC_SM_77 VSS_77 VSS_174 VSS_257 VSS_350
L22
VCC_81 VCC_SM_78
AR15 ITL_945PM_MICRO_FCBGA_1466P AR35
VSS_78 VSS_175
A25 AM13
VSS_258 VSS_351
AB2
AC21 AJ15 AH35 BA24 AL13 Y2
VCC_82 VCC_SM_79 VSS_79 VSS_176 VSS_259 VSS_352
AA21 AJ14 AB35 AU24 AG13 U2
VCC_83 VCC_SM_80 VSS_80 VSS_177 VSS_260 VSS_353
W21 AJ13 AA35 AL24 P13 T2
VCC_84 VCC_SM_81 VSS_81 VSS_178 VSS_261 VSS_354
N21 AH13 Y35 AW23 F13 N2
VCC_85 VCC_SM_82 VSS_82 VSS_179 VSS_262 VSS_355
M21 AK12 W35 D13 J2
VCC_86 VCC_SM_83 +V1.8 VSS_83 VSS_263 VSS_356
L21 AJ12 PLACE IN CAVITY V35 B13 H2
VCC_87 VCC_SM_84 VSS_84 VSS_264 VSS_357
AC20 AH12 27-,26-,21-,13-,12-,8- T35 AY12 F2
VCC_88 VCC_SM_85 VSS_85 VSS_265 VSS_358
AB20 AG12 R35 AC12 C2
VCC_89 VCC_SM_86 VSS_86 VSS_266 VSS_359
Y20 AK11 P35 K12 AL1
VCC_90 VCC_SM_87 VSS_87 VSS_267 VSS_360
W20 BA8 N35 H12
P20
VCC_91 VCC_SM_88
AY8
1 C295 1 C335 M35
VSS_88
E12
VSS_268
VCC_92 VCC_SM_89 VSS_89 VSS_269
N20 AW8 2 10UF_6.3V 2 10UF_6.3V L35 AD11
VCC_93 VCC_SM_90 VSS_90 VSS_270
M20 AV8 J35 AA11
VCC_94 VCC_SM_91 VSS_91 VSS_271
L20 AT8 H35 Y11
VCC_95 VCC_SM_92 VSS_92 VSS_272
AB19 AR8 G35
VCC_96 VCC_SM_93 VSS_93
AA19
VCC_97 VCC_SM_94
AP8 F35
VSS_94
ITL_945PM_MICRO_FCBGA_1466P
Y19 BA6 D35
VCC_98 VCC_SM_95 VSS_95
N19 AY6 AN34
VCC_99 VCC_SM_96 VSS_96
M19 AW6
VCC_100 VCC_SM_97
L19
VCC_101 VCC_SM_98
AV6
VCC_SM_LF2 ITL_945PM_MICRO_FCBGA_1466P
N18 AT6
VCC_102 VCC_SM_99
M18
L18
P17
N17
VCC_103
VCC_104
VCC_105
VCC_SM_100
VCC_SM_101
VCC_SM_102
AR6
AP6
AN6
AL6
VCC_SM_LF1
1 C336 1 C353
INVENTEC
VCC_106 VCC_SM_103 TITLE
M17
N16
VCC_107 VCC_SM_104
AK6
AJ6
2 0.47UF_6.3V 2 0.47UF_6.3V TIANSHAN
M16
VCC_108 VCC_SM_105
AV1
CALISTOGA-5-POWER
VCC_109 VCC_SM_106
L16 AJ1 SIZE CODE DOC. NUMBER REV
VCC_110 VCC_SM_107
A3 CS Model_No A02
ITL_945PM_MICRO_FCBGA_1466P CHANGE by Ho,Thomas 25-May-2006 SHEET 25 OF 74
 28-,23- 23- MA_DATA(63:0)
MA_A(13:0)
CN1003
102 5
A0 DQ0
101 7
A1 DQ1
100 17
A2 DQ2 +V1.8
99 19
A3 DQ3
98 4 27-,25-,21-,13-,12-,8-
A4 DQ4
97 6
A5 DQ5
94 14
A6 DQ6
92 16
A7 DQ7
93 23
A8 DQ8
91 25
A9 DQ9
105 35
A10_AP DQ10
90 37
A11 DQ11
89 20
A12 DQ12
116 22
A13 DQ13
86 36
A14 DQ14
84 38 Layout notes: Place these Caps closed So-Dimm0 CN1003
A15 DQ15
28-,23- 85 43 112 18
MA_BS2# A16_BA2 DQ16
45 111
VDD1 VSS16
24
DQ17 VDD2 VSS17
28-,23- 107 55 117 41
MA_BS0# 28-,23- 106
BA0 DQ18
57 96
VDD3 VSS18
53
MA_BS1# BA1 DQ19 1 C270 1 C317 1 C271 1 C207 1 C269 1 C266 1 C319 1 C315 1 C288 VDD4 VSS19
M_CS0# 28-,21- 110 44 95 42
S0# DQ20 VDD5 VSS20
M_CS1# 28-,21- 115 46 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 2.2UF_16V 2 2.2UF_16V 2 2.2UF_16V 2 2.2UF_16V 2 2.2UF_16V 118 54
S1# DQ21 VDD6 VSS21
21- 30 56 81 59
M_CLK_DDR0 21- 32
CK0 DQ22
58 82
VDD7 VSS22
65
M_CLK_DDR0# 21- 164
CK0# DQ23
61 87
VDD8 VSS23
60
M_CLK_DDR1 21- 166
CK1 DQ24
63 103
VDD9 VSS24
66
M_CLK_DDR1# CK1# DQ25 +V3S VDD10 VSS25
28-,21- 79 73 88 127
M_CKE0 28-,21- 80
CKE0 DQ26
75 104
VDD11 VSS26
139
M_CKE1 28-,23- 113
CKE1 DQ27
62
VDD12 VSS27
128
MA_CAS# CAS# DQ28 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5- VSS28
MA_RAS# 28-,23- 108 64 199 145
RAS# DQ29 VDDSPD VSS29
MA_WE# 28-,23- 109 74 165
WE# DQ30 VSS30
198 76 83 171
SA0 DQ31 NC1 VSS31
200 123 120 172
SA1 DQ32 C12621 1 C1261 NC2 VSS32
ICH_3S_SMCLK 57-,44-,39-,27-,20-,15- 197 125 PM_EXTTS#0 27-,21- 50 177
SCL DQ33 M_VREF NC3 VSS33
ICH_3S_SMDATA 57-,44-,39-,27-,20-,15- 195
SDA DQ34
135 0.1UF_16V 2 2 2.2UF_16V 69
NC4 VSS34
187
137 27-,21-,12- 163 178
1 1 DQ35 NCTEST VSS35
MA_DM(7:0) 23- 28-,21- 114 124 190
R324 R325 M_ODT0 ODT0 DQ36 VSS36
28-,21- 119 126 1 9
10K_5% 10K_5% M_ODT1 ODT1 DQ37
134
VREF VSS37
21
DQ38 VSS38
10 136 201 33
2 2 DM0 DQ39 GND0 VSS39
26 141 202 155
DM1 DQ40 C11581 1 GND1 VSS40
52 143 34
67
DM2 DQ41
151 0.1UF_16V 2 C1092 VSS41
132
DM3 DQ42 2 2.2UF_16V VSS42
130 153 47 144
DM4 DQ43 VSS1 VSS43
147 140 133 156
DM5 DQ44 VSS2 VSS44
23- 170 142 183 168
MA_DQS(7:0) DM6 DQ45 VSS3 VSS45
185 152 77 2
DM7 DQ46 VSS4 VSS46
154 12 3
DQ47 VSS5 VSS47
13 157 48 15
DQS0 DQ48 VSS6 VSS48
31 159 184 27
DQS1 DQ49 VSS7 VSS49
51 173 78 39
DQS2 DQ50 VSS8 VSS50
70 175 71 149
DQS3 DQ51 VSS9 VSS51
131 158 72 161
DQS4 DQ52 VSS10 VSS52
23- 148 160 121 28
MA_DQS#(7:0) DQS5 DQ53 VSS11 VSS53
169 174 122 40
DQS6 DQ54 VSS12 VSS54
188 176 196 138
DQS7 DQ55 VSS13 VSS55
11 179 193 150
DQS#0 DQ56 VSS14 VSS56
29 181 8 162
DQS#1 DQ57 VSS15 VSS57
49 189
DQS#2 DQ58
68 191
DQS#3 DQ59
129 180
DQS#4 DQ60
146 182
DQS#5 DQ61
167 192
DQS#6 DQ62
186 194
DQS#7 DQ63
AMP_SOCKET_DDR2_DIMM_STD_4.0mm_200P
AMP_SOCKET_DDR2_DIMM_STD_4.0mm_200P

SO DIMM0_4.0mm

INVENTEC
TITLE
TIANSHAN
DDR2-DIMM-0
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 26 OF 74
 28-,23- 23- MB_DATA(63:0)
MB_A(13:0)
CN14
102 5
A0 DQ0
101 7
A1 DQ1
100 17
A2 DQ2
99 19
A3 DQ3
98 4
A4 DQ4
97 6
A5 DQ5
94 14
A6 DQ6 +V1.8
92 16
A7 DQ7
93 23 26-,25-,21-,13-,12-,8-,27-
A8 DQ8
91 25
A9 DQ9
105 35
A10_AP DQ10
90 37
89
A11
A12
DQ11
DQ12
20 Layout note: Place these Caps closed So-Dimm1 CN14
116 22 112 18
A13 DQ13 VDD1 VSS16
86 36 111 24
A14 DQ14 VDD2 VSS17
84 38 117 41
A15 DQ15 VDD3 VSS18
28-,23- 85 43 96 53
MB_BS2# A16_BA2 DQ16
45 1 C292 1 C267 1 C316 1 C289 1 C314 1 C320 1 C268 1 C291 1 C290 95
VDD4 VSS19
42
DQ17 VDD5 VSS20
28-,23- 107 55 2 2 118 54
MB_BS0# BA0 DQ18 0.1UF_16V 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 2.2UF_16V 2 2.2UF_16V 2 2.2UF_16V 2 2.2UF_16V 2 2.2UF_16V VDD6 VSS21
28-,23- 106 57 81 59
MB_BS1# 28-,21- 110
BA1 DQ19
44 82
VDD7 VSS22
65
M_CS2# S0# DQ20 VDD8 VSS23
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,27- M_CS3# 28-,21- 115 46 87 60
S1# DQ21 VDD9 VSS24
21- 30 56 +V3S 103 66
M_CLK_DDR4 21- 32
CK0 DQ22
58 88
VDD10 VSS25
127
+V3S M_CLK_DDR4# CK0# DQ23 VDD11 VSS26
21- 164 61 104 139
M_CLK_DDR3 CK1 DQ24 VDD12 VSS27
21- 166 63 128
M_CLK_DDR3# 28-,21- 79
CK1# DQ25
73
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,27-
199
VSS28
145
1 M_CKE2 28-,21- 80
CKE0 DQ26
75
VDDSPD VSS29
165
R301 M_CKE3 28-,23- 113
CKE1 DQ27
62 83
VSS30
171
10K_5% MB_CAS# CAS# DQ28 NC1 VSS31
MB_RAS# 28-,23- 108 64 120 172
RAS# DQ29 1 C333 NC2 VSS32
2 MB_WE# 28-,23- 109
WE# DQ30
74 C334 1 PM_EXTTS#0 26-,21- 50
NC3 VSS33
177
M_VREF
198
SA0 DQ31
76 0.1UF_16V 2 2 2.2UF_16V 69
NC4 VSS34
187
200 123 26-,21-,12- 163 178
SA1 DQ32 NCTEST VSS35
ICH_3S_SMCLK 57-,44-,39-,26-,20-,15- 197 125 190
SCL DQ33 VSS36
57-,44-,39-,26-,20-,15- 195 135 1 9
ICH_3S_SMDATA SDA DQ34 VREF VSS37
137 21
1 DQ35 VSS38
MB_DM(7:0) 23- 28-,21- 114 124 201 33
R302 M_ODT2 28-,21- 119
ODT0 DQ36
126 202
GND0 VSS39
155
10K_5% M_ODT3 ODT1 DQ37
C149 1 1 GND1 VSS40
DQ38
134 C150 VSS41
34
2
10
DM0 DQ39
136 0.1UF_16V 2 2 2.2UF_16V VSS42
132
26 141 47 144
DM1 DQ40 VSS1 VSS43
52 143 133 156
DM2 DQ41 VSS2 VSS44
67 151 183 168
DM3 DQ42 VSS3 VSS45
130 153 77 2
DM4 DQ43 VSS4 VSS46
147 140 12 3
DM5 DQ44 VSS5 VSS47
23- 170 142 48 15
MB_DQS(7:0) DM6 DQ45 VSS6 VSS48
185 152 184 27
DM7 DQ46 VSS7 VSS49
154 78 39
DQ47 VSS8 VSS50
13 157 71 149
DQS0 DQ48 VSS9 VSS51
31 159 72 161
DQS1 DQ49 VSS10 VSS52
51 173 121 28
DQS2 DQ50 VSS11 VSS53
70 175 122 40
DQS3 DQ51 VSS12 VSS54
131 158 196 138
DQS4 DQ52 VSS13 VSS55
23- 148 160 193 150
MB_DQS#(7:0) DQS5 DQ53 VSS14 VSS56
169 174 8 162
DQS6 DQ54 VSS15 VSS57
188 176
DQS7 DQ55
11 179
DQS#0 DQ56
29 181
1, 0.05
DQS#1 DQ57
49 189
DQS#2 DQ58
68 191
DQS#3 DQ59
129 180
0, 0.05
DQS#4 DQ60
146 182
DQS#5 DQ61
167 192 TYCO_C_1734073_2_DDR2_SODIMM_200P
DQS#6 DQ62
186 194
DQS#7 DQ63

TYCO_C_1734073_2_DDR2_SODIMM_200P +V1.8
26-,25-,21-,13-,12-,8-,27-

SO DIMM1 9.2mm 1 C1244 1 C318 1 C1243 1 C1228

2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V

Layout note: Place these Hi_Feq & Resistors closed GMCH

INVENTEC
TITLE
TIANSHAN
DDR2-DIMM-1
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 27 OF 74
+V0.9S
12-,28-

1 C1190 1 C265 1 C262 1 C1208 1 C205 1 C1189 1 C1192 1 C263 1 C200 1 C264 1 C203 1 C1187 1 C1191
2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V

1 C1207 1 C1209 1 C204 1 C261 1 C1204 1 C1185 1 C1188 1 C1206 1 C201 1 C202 1 C1205 1 C1186 1 C1184
2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V

+V0.9S LAYOUT NOTES : PLACE ONE CAP CLOSE TO EVERY 2 PULL UP RESISTOR TERMINATED TO +V0.9S
12-,28-

R11721 2 56_5% 26-,21- M_CKE0

R11731 2 56_5% 26-,21- M_CKE1
R236 1 2 56_5% 27-,21- M_CKE2
R237 1 2 56_5% 27-,21- M_CKE3

R12311 2 56_5% 26-,21-

+V0.9S
M_ODT0
12-,28-
R12531 2 56_5% 26-,21- M_ODT1
R284 1 2 56_5% 27-,21- M_ODT2 2 56_5%
R1207 1 27-,23- MB_BS0#
R12341 2 56_5% 27-,21- M_ODT3
R256 1 2 56_5% 27-,23-
2 56_5%
MB_BS1#
R12191 26-,23- MA_BS0#
R12231 2 56_5% 26-,23- R240 1 2 56_5% 27-,23-
MA_BS1# MB_BS2#
R12021 2 56_5% 26-,23- MA_BS2#
R259 1 2 56_5% 27-,23-
2 56_5%
MB_WE#
R12181 26-,23- MA_WE#
R1208 1 2 56_5% 27-,23- MB_CAS#
R12201 2 56_5% 26-,23- MA_CAS# R258 1 2 56_5% 27-,23-
R12291 2 56_5%
MB_RAS#
26-,23- MA_RAS#

R12281 2 56_5% 26-,21- 27-,23-

M_CS0# MB_A(13:0)
R12171 2 56_5% 26-,21- R263 1 2 56_5% MB_A(0)
M_CS1#
R285 1 2 56_5% 27-,21- R1170 1 2 56_5% MB_A(1)
M_CS2#
R12331 2 56_5% 27-,21- R261 1 2 56_5% MB_A(2)
M_CS3#
R1171 1 2 56_5% MB_A(3)

R262 1 2 56_5% MB_A(4)

26-,23- R1177 1 2 56_5% MB_A(5)

MA_A(13:0)
R12301 2 56_5% MA_A(0) R1175 1 2 56_5% MB_A(6)

R12251 2 56_5% MA_A(1) R1174 1 2 56_5% MB_A(7)

R12261 2 56_5% MA_A(2) R257 1 2 56_5% MB_A(8)

R12241 2 56_5% MA_A(3) R238 1 2 56_5% MB_A(9)

R12011 2 56_5% MA_A(4) R1199 1 2 56_5% MB_A(10)

R12211 2 56_5% MA_A(5) R1176 1 2 56_5% MB_A(11)

R12001 2 56_5% MA_A(6) R239 1 2 56_5% MB_A(12)

R12031 2 56_5% MA_A(7) R260 1 2 56_5% MB_A(13)

R12041 2 56_5% MA_A(8)

R12051 2 56_5% MA_A(9)

R12221 2 56_5% MA_A(10)

R12321 2 56_5% MA_A(11)

R12061 2 56_5% MA_A(12)

INVENTEC
TITLE
R12271 2 56_5% MA_A(13)
TIANSHAN
DDR2-DAMPING
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 28 OF 74
 +V3S
U19 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,29-
22- AE26 W6 R146 1 2 10K_5%
PEG_C_TXP(0) PCIE_RX0P GPIO_0
PEG_C_TXN(0) 22- AD26
PCIE_RX0N
Part 1 of 6 GPIO_1 V6 R1049 1 2 10K_5%
PEG_C_TXP(1) 22- AB26 Y3
PCIE_RX1P GPIO_2
25PPM PEG_C_TXN(1) 22- AA26
PCIE_RX1N GPIO_3
W5
22- AA25 Y4 R1053 1 2 OPEN
2 1 PEG_C_TXP(2) PCIE_RX2P GPIO_4
1 2
22- Y25 V4 R1052 1 2 0_5%
PEG_C_TXN(2) PCIE_RX2N GPIO_5
PEG_C_TXP(3) 22- W26 Y2 R1054 10K_5%
PCIE_RX3P GPIO_6
PEG_C_TXN(3) 22- V26 V5 37- LCM_3S_BKLTEN
X2 PCIE_RX3N GPIO_7
PEG_C_TXP(4) 22- V25 W3 29- GPIO8
27MHZ 22- U25
PCIE_RX4P GPIO_8
Y1 29-
PEG_C_TXN(4) PCIE_RX4N GPIO_9 GPIO9
PEG_C_TXP(5) 22- T26 W2
R229 1 PCIE_RX5P GPIO_10
29-2 2 R227 1 29- 22- R26 V1 29-
XTALIN XTALOUT PEG_C_TXN(5) PCIE_RX5N GPIO_11 GPIO11
OPEN OPEN PEG_C_TXP(6) 22- R25 V3 29- GPIO12
1 1 PCIE_RX6P GPIO_12
PEG_C_TXN(6) 22- P25
PCIE_RX6N GPIO_13
U4 29- GPIO13 R136
C195 2 2 PEG_C_TXP(7) 22- N26
PCIE_RX7P GPIO_14
V2 10K_5%
22PF_50V 22- M26 U2 1 2
PEG_C_TXN(7) PCIE_RX7N GPIO_PWRCNTL
C196 PEG_C_TXP(8) 22- M25 U1 29- GPIO16
PCIE_RX8P GPIO_MEMSSIN
22PF_50V PEG_C_TXN(8) 22- L25 9- PWRPLAY
PCIE_RX8N
PEG_C_TXP(9) 22- K26 AE7 TP766
PCIE_RX9P NC_DVOVMODE
PEG_C_TXN(9) 22- J26
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,29- PCIE_RX9N
+V3S PEG_C_TXP(10) 22- J25 AA1 TP767
PCIE_RX10P DVPDATA_0
PEG_C_TXN(10) 22- H25 AA4 TP768
PCIE_RX10N DVPDATA_1
U26 PEG_C_TXP(11) 22- G26
PCIE_RX11P DVPDATA_2
AB3 TP769 +V3S
1 8 PEG_C_TXN(11) 22- F26 AC2 TP770 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,29-
XIN_CLKIN XOUT PCIE_RX11N DVPDATA_3
PEG_C_TXP(12) 22- F25 AF3
R230 PCIE_RX12P DVPDATA_4
2 7 1 2 22- E25 AD1
VSS VDD PEG_C_TXN(12) PCIE_RX12N DVPDATA_5
PEG_C_TXP(13) 22- D26 AB4
0_5% PCIE_RX13P DVPDATA_6

DVO / EXT TMDS / GPIO

R1080 2

OPEN
OPEN
OPEN
OPEN
1 3 6 22- C26 AC3
SRS PD# 1 C1072 PEG_C_TXN(13) PCIE_RX13N DVPDATA_7
PEG_C_TXP(14) 22- C25 AE2
0_5% 1 R1115 2 PCIE_RX14P DVPDATA_8
GPIO16 29- 4 5 29- XTALIN 2 0.1UF_16V PEG_C_TXN(14) 22- B25 AC4
ModOUT REF PCIE_RX14N DVPDATA_9
PEG_C_TXP(15) 22- B23 AF5 TP778
10K_5% PCIE_RX15P DVPDATA_10

2
2
2
2
PEG_C_TXN(15) 22- A23 AB5 TP777
1 C1108 PULSECORE_P1819BF_08ST_SOIC_8P PCIE_RX15N DVPDATA_11
AD5 TP782
DVPDATA_12
2 22PF_50V AE3 TP779
DVPDATA_13
PEG_RXP(0) 30- W21 AE4
PCIE_TX0P DVPDATA_14

1
1
1
1
OPTION FOR EMI TEST PEG_RXN(0) 30- V21 AD2

R1039
R1036
R1037
R1033
PCIE_TX0N DVPDATA_15
PEG_RXP(1) 30- V22 AD4
PCIE_TX1P DVPDATA_16
PEG_RXN(1) 30- U22 AB6
PCIE_TX1N DVPDATA_17
PEG_RXP(2) 30- U23 AE6 TP786
PCIE_TX2P DVPDATA_18
PEG_RXN(2) 30- T23 AD7 TP784
PCIE_TX2N DVPDATA_19
PEG_RXP(3) 30- T21 AC6 R1038 1 24.7K_5%
PCIE_TX3P DVPDATA_20
PEG_RXN(3) 30- R21
PCIE_TX3N DVPDATA_21
AE5 R1034 1 24.7K_5%
30- R22 AD6 R1035 1 24.7K_5%

PCI Express
PEG_RXP(4) PCIE_TX4P DVPDATA_22
PEG_RXN(4) 30- P22 AB8 R1032 1 24.7K_5%
PCIE_TX4N DVPDATA_23
PEG_RXP(5) 30- P23
PCIE_TX5P
PEG_RXN(5) 30- N23 AA2 R142 1 2 OPEN +V3S
PCIE_TX5N DVPCNTL_0
PEG_RXP(6) 30- N21 AA3 R143 1 2 OPEN 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,29-
STRAPS PIN DESCRIPTION OF RECOMMENDED SETTINGRECOMMENDED PCIE_TX6P DVPCNTL_1
R144 1 2 OPEN
PEG_RXN(6) 30- M21 AB2
PCIE_TX6N DVPCNTL_2 R1051 2 R1050 2
PEG_RXP(7) 30- M22 AC1 R145 1 2 OPEN 1 1
PCIE_TX7P DVPCNTL_3
PEG_RXN(7) 30- L22
TX_PWRS_ENB GPIO0 Full swing 1 PCIE_TX7N 499_1% 499_1%
PEG_RXP(8) 30- L23 W4
PCIE_TX8P VREFG
PEG_RXN(8) 30- K23
PCIE_TX8N
Transmitter de-emphasis enable 30- K21
TX_DEEMPH_EN GPIO1 0 PEG_RXP(9) PCIE_TX9P
-tx de-emphasis disabled for mobile PEG_RXN(9) 30- J21
PCIE_TX9N
PEG_RXP(10) 30- J22
PCIE_TX10P
Strap to set the debug muxes to bring out 30- H22
DEBUG_ACCESS GPIO4 0 PEG_RXN(10) PCIE_TX10N
debug signals even if registers are inaccessible PEG_RXP(11) 30- H23
PCIE_TX11P
PEG_RXN(11) 30- G23
Force chip to get to compliance state PCIE_TX11N
0 PEG_RXP(12) 30- G21
FORCE_COMPLIANCE GPIO8 PCIE_TX12P
quickly for tester purposes PEG_RXN(12) 30- F21
PCIE_TX12N
PEG_RXP(13) 30- F22
PCIE_TX13P
GPIO No Rom,with 128M frame buffer 0 0 0 X PEG_RXN(13) 30- E22
PCIE_TX13N
ROMIDCFG(3:0) 30- E23
(9,13,12,11) No Rom,with 64M frame buffer
PEG_RXP(14) PCIE_TX14P
0 1 0 X PEG_RXN(14) 30- D23
PCIE_TX14N
PEG_RXP(15) 30- C22
PCIE_TX15P
Samsung 8M*32 1.8V F die K4D553235F-GC2A 0 0 0 0 PEG_RXN(15) 30- B22
PCIE_TX15N

Hynix 8M*32 1.8V HY5DS573222F-28 0 0 0 1 +V1.2S

DVPDATA 15- AA22
VRAM_ID(0:3)
CLK_R_PCIE_REFCLK PCIE_REFCLKP
(20,21,22,23) Hynix 8M*32 1.8V HY5DS573222F-33 0 0 1 0 CLK_R_PCIE_REFCLK#
31-,13-,10- 15- Y22
PCIE_REFCLKN

Hynix 16M*32 1.8V HY5DS113222FM-28 0 0 1 1 1 2 Y20

PCIE_CALRP
R1087 1 2 560_0.5% V19
PCIE_CALRN
Hynix 16M*32 1.8V HY5DS113222FM-33 0 1 0 0 R1089 1 2 2K_1% W19 AD20 R225 1 2 10K_5%

SS
PCIE_CALI SSOUT
R1088 1.5K_1% AE19 R224 1 2 10K_5%
SSIN
1 2 AA21
PCIE_TEST
R1082 10K_5%
W20 AF9
PWRGD_MASK TX0M
PCIE_RST# 40- Y21 AE9
PWRGD TX0P
AE10
TX1M
+V3S AE11
TX1P
2 R1083 1 AD17 AF11

TMDS
R2SET TX2M
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,29- AF12
715_1% TX2P
SVID_CHROMA 36- AE18 AF8
C_R_PR TXCM
1 1 36- AF17 AE8
SVID_LUMA Y_G TXCP
+V3S VIDEO_COMP 36- AF18
R1084 R1085 COMP_B_PB
AA9 37- LCM_DDCPCLK
4.7K_5% 4.7K_5% DDC2CLK
DAC2

66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,29- AE20 AA10 37- LCM_DDCPDATA

H2SYNC DDC2DATA
OPEN 2 2 AF20
R141 V2SYNC
1 2 29- AF6 1 2
GPIO9 HPD1
OPEN AC18 R147 100K_5%
R138 DDC3CLK
1 2 29- AC19 AF23 60-
GPIO11 DDC3DATA R CRT_R
OPEN AE23 60- CRT_G
R137 G
1 2 29- AE22 60-
GPIO12 B
2
CRT_B
OPEN 1
R1056 1 2 29- AE21 36-
DAC1

GPIO13 HSYNC CRT_HSYNC R1118 75_5%

OPEN AF21 36- 1 2
R140 2 R228 2
VSYNC CRT_VSYNC
1 29- 29- 1 AF24
GPIO8 XTALIN XTALIN R1117 75_5%
OPEN AD22 1 2 1 2
R139 1 2
121_1% 1 RSET
29- GPIO8 XTALOUT 29- AF25 R1120 75_5%
R226 XTALOUT R1119
AC21 36- CRT_DDCDATA499_1%
71.5_1% R11161 DDC1DATA
21K_5%
2
R10571
R134 1
21K_5%
21K_5%
AD23
E5
E3
TESTEN
TEST_YCLK
DDC1CLK
AB20

AB18
36- CRT_DDCCLK
INVENTEC
CLK

TEST_MCLK GPIO_AUXWIN
AB21 TITLE
PLLTEST
R10811 210K_5% AD21 THERM AB7 20-
TIANSHAN
STEREOSYNC DPLUS DPLUS ATI-M52-T-1
AA7 20-,16- THERM_MINUS
DMINUS
SIZE CODE DOC. NUMBER REV
ATI_M52_T_BGA_565P A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 29 OF 74
 +VGAVCC
U19
C1113 0.1UF_16V 31-,9-
PEG_RXP(0) 29- 21- PEG_C_RXP(0) Part 6 of 6
1 2 L11
VDDC_1
29- C1117 0.1UF_16V 21- L12
PEG_RXN(0) PEG_C_RXN(0) VDDC_2
C1118 1 2 0.1UF_16V
L16
VDDC_3
PEG_RXP(1) 29- 21- PEG_C_RXP(1) M11
VDDC_4
C1119 1 2 0.1UF_16V
M12
VDDC_5
PEG_RXN(1) 29- 21- PEG_C_RXN(1) M13
VDDC_6
1 2 M15

CENTER ARRAY
C1121 0.1UF_16V VDDC_7
PEG_RXP(2) 29- 21- PEG_C_RXP(2) N12
VDDC_8
C1123 1 2 0.1UF_16V
N13
VDDC_9
PEG_RXN(2) 29- 21- PEG_C_RXN(2) N14
VDDC_10
C1124 1 2 0.1UF_16V
P13
VDDC_11
PEG_RXP(3) 29- 21- PEG_C_RXP(3) P14
VDDC_12
1 2 P15
VDDC_13
29- C1125 0.1UF_16V 21- R12
PEG_RXN(3) PEG_C_RXN(3) VDDC_14
C1126 1 2 0.1UF_16V
R14
VDDC_15
PEG_RXP(4) 29- 21- PEG_C_RXP(4) R15
VDDC_16
C1127 1 2 0.1UF_16V R16
VDDC_17
PEG_RXN(4) 29- 21- PEG_C_RXN(4) T11
VDDC_18
1 2 T15
VDDC_19
29-
C1128 0.1UF_16V 21- T16
PEG_RXP(5) PEG_C_RXP(5) VDDC_20
1 2 W9
VDDC_21 VDDCI_1
L14
29- C1129 0.1UF_16V 21- W11 N16
PEG_RXN(5) PEG_C_RXN(5) VDDC_22 VDDCI_2
C1130 1 2 0.1UF_16V Y9 P11
VDDC_23 VDDCI_3
PEG_RXP(6) 29- 21- PEG_C_RXP(6) Y11 T13
VDDC_24 VDDCI_4

29-
C1131 1 2 0.1UF_16V
21- ATI_M52_T_BGA_565P
PEG_RXN(6) PEG_C_RXN(6)
1 2
29- C1132 0.1UF_16V 21-
PEG_RXP(7) PEG_C_RXP(7)
1 2 0.1UF_16V
29- C1133 21-
PEG_RXN(7) PEG_C_RXN(7)
29-
C1134 1 2 0.1UF_16V
21-
PEG_RXP(8) PEG_C_RXP(8)
1 2
29- C1135 0.1UF_16V 21-
PEG_RXN(8) PEG_C_RXN(8)
29-
C1136 1 2 0.1UF_16V 21-
PEG_RXP(9) PEG_C_RXP(9)
29-
C1137 1 2 0.1UF_16V
21-
PEG_RXN(9) PEG_C_RXN(9)
1 2
29-
C1138 0.1UF_16V 21-
PEG_RXP(10) PEG_C_RXP(10) U19
1 2
29- C1139 0.1UF_16V 21- AB16 37-
PEG_RXN(10) PEG_C_RXN(10) Part 2 of 6 TXCLK_UP LVDS_TXCU+
C1140 1 2 0.1UF_16V AB15 37- LVDS_TXCU-
TXCLK_UN
PEG_RXP(11) 29- 21- PEG_C_RXP(11)
C1141 1 2 0.1UF_16V
AC16
TXOUT_U3P
PEG_RXN(11) 29- 21- PEG_C_RXN(11) AC15
TXOUT_U3N
1 2 +LPVDD
29- C1142 0.1UF_16V 21- AA15 37-
PEG_RXP(12) PEG_C_RXP(12) TXOUT_U2P LVDS_TXDU2+
C1143 1 2 0.1UF_16V
31- AA14 37-
TXOUT_U2N LVDS_TXDU2-
PEG_RXN(12) 29- 21- PEG_C_RXN(12)
C1144 1 2 0.1UF_16V
AE17 37- LVDS_TXDU1+
TXOUT_U1P
PEG_RXP(13) 29- 21- PEG_C_RXP(13) AE16 37- LVDS_TXDU1-
TXOUT_U1N
1 2
29- C1145 0.1UF_16V 21- 1 C1065 AD15 AE15 37-
PEG_RXN(13) PEG_C_RXN(13) LPVDD TXOUT_U0P LVDS_TXDU0+
C1146 1 2 0.1UF_16V 2 1UF_6.3V AE14 37- LVDS_TXDU0-
TXOUT_U0N
PEG_RXP(14) 29- 21- PEG_C_RXP(14) AD14
+V2.5S LPVSS

29-
C1147 1 2 0.1UF_16V
21- 31-,24-,13-,10-
PEG_RXN(14) PEG_C_RXN(14)
1 2 L17 AA11
LVDDR_1 TXCLK_LP
AC13 37- LVDS_TXCL+
29-
C1149 0.1UF_16V 21- 1 2 AB11 AC12 37-
PEG_RXP(15) PEG_C_RXP(15) LVDDR_2 TXCLK_LN LVDS_TXCL-
1 2 ACM321611
29- C1151 0.1UF_16V 21- 1 C127 1 C126 AF14
PEG_RXN(15) PEG_C_RXN(15) TXOUT_L3P
1 2 2 1UF_6.3V 2 1UF_6.3V AA12
LVDDR_3 TXOUT_L3N
AF15
AA13
LVDDR_4
AB13 37- LVDS_TXDL2+
TXOUT_L2P
Place to near Graphic TXOUT_L2N
AB12 37- LVDS_TXDL2-
AE13 37- LVDS_TXDL1+
TXOUT_L1P
AB14 AE12 37- LVDS_TXDL1-
1 C128 1 C1066 LVSSR_1 TXOUT_L1N
AC11
LVSSR_2
2 1UF_6.3V 2 1UF_6.3V AC14 AD12 37- LVDS_TXDL0+
LVSSR_3 TXOUT_L0P
AD13 AD11 37- LVDS_TXDL0-
LVSSR_4 TXOUT_L0N

AC8 37- LCM_3S_VDDEN

DIGON
AA8 1 2 43-,37-
BLON INV_PWM_3
R1048 0_5%
ATI_M52_T_BGA_565P 1 2
R1086 10K_5%

INVENTEC
TITLE
TIANSHAN
ATI-M52-T-2
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 30 OF 74
 +V1.8S
34-,32-,13-,31-
U19
A3 Part 4 of 6
VDDR1_1
A6
VDDR1_2
C1148 A9
1 C192 1 1 C1088 1 C1023 1 C1086 1 C1089 1 C1024 1 C1021 VDDR1_3
A12
VDDR1_4
A15
2 10UF_6.3V 22UF_4V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V VDDR1_5 +V2.5S
T6
VDDR1_6
D19 30-,24-,13-,10-,31-
VDDR1_7
C1 H11
VDDR1_8 VDD25_1
D5 H14
VDDR1_9 VDD25_2
D8 H19
VDDR1_10 VDD25_3 1 C1083 1 C1079 1 C1087
D11 K8
VDDR1_11 VDD25_4
D13 P8 2 1UF_6.3V 2 1UF_6.3V 2 10UF_6.3V
VDDR1_12 VDD25_5
A18 T19
VDDR1_13 VDD25_6
D17 U8
VDDR1_14 VDD25_7
A21 W16
E1
VDDR1_15 VDD25_8 +V3S
VDDR1_16
H8 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-
VDDR1_17
F20 V8
VDDR1_18 VDDR3_1
E4 W7
VDDR1_19 VDDR3_2
G9 W15 C125
VDDR1_20 VDDR3_3 1 C1067 1 C1020 1
G15 W17
VDDR1_21 VDDR3_4
G18 W18 2 1UF_6.3V 2 1UF_6.3V 22UF_4V
+V2.5S L1004 +LPVDD H1
VDDR1_22 VDDR3_5
Y15
VDDR1_23 VDDR3_6
30-,24-,13-,10-,31-
ACM321611 30- J8 Y17
1 2 D15
VDDR1_24 VDDR3_7 +V3S
VDDR1_25
H9 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-
VDDR1_26
H12 Y6
1 C1063 1 C1062 VDDR1_27 VDDR4_1
H15 AA5
VDDR1_28 VDDR4_2
2 1UF_6.3V 2 100PF_50V H18 AA6
VDDR1_29 VDDR4_3 1 C1071 1 C89 1 C1073
G4 AD3
VDDR1_30 VDDR4_4
L1 2 1UF_6.3V 2 10UF_6.3V2 1UF_6.3V
+V2.5S L1002 J4
VDDR1_31
VDDR1_32
30-,24-,13-,10-,31-
BLM11A121S G12 N20
VDDR1_33 PCIE_VDDR_12_1
1 2 L8
VDDR1_34 PCIE_VDDR_12_2
P20
L4 T20
VDDR1_35 PCIE_VDDR_12_3 +V1.2S
N8 U20
1 C1019 1 C1060 1 C1061 VDDR1_36 PCIE_VDDR_12_4
R1 K20 29-,13-,10-,31-
VDDR1_37 PCIE_VDDR_12_5
R7 J20
2 10UF_6.3V 2 1UF_6.3V 2 100PF_50V VDDR1_38 PCIE_VDDR_12_6
R8 L19
VDDR1_39 PCIE_VDDR_12_7 1 C248 1 C193 1 C194 1 C1114 1 C1085 1 C1082 1 C1077 1
+V1.8S N4
VDDR1_40 PCIE_VDDR_12_8
L20 C247
PCIE_VDDR_12_9
M19 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 22UF_4V
34-,32-,13-,31- N19
PCIE_VDDR_12_10
P19
PCIE_VDDR_12_11 +V1.2S
K19
PCIE_VDDR_12_12
J19 29-,13-,10-,31-
1 C1022 1 C1150 PCIE_VDDR_12_13
R19
PCIE_VDDR_12_14
2 1UF_6.3V 2 10UF_6.3V 1 C1182 1 C1115 1 C1116 1 C1183
AE25 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V
+V2.5S L18
PCIE_VDDR_12_15
AC24
PCIE_VDDR_12_16
30-,24-,13-,10-,31-
BLM11A121S AC25
PCIE_VDDR_12_17 +V1.2S
1 2 PCIE_VDDR_12_18
AD25 L1007
ACM321611 29-,13-,10-,31-
PCIE_PVDD_12__1
AA24 1 2
1 C1070 1 C130 AB24
PCIE_PVDD_12__2 1 C1110 1 C1111 1 C1122 1 C1120
2 1UF_6.3V AB23
2 10UF_6.3V PCIE_PVDD_12__3 +V1.2S
AC23 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V
PCIE_PVDD_12__4
29-,13-,10-,31-
+V2.5S L23
30-,24-,13-,10-,31-
BLM11A121S
VDDPLL
W13 2 L1005 1
1 2 BLM11A121S
I/O POWER
1 C1069
1 C156 1 C160 AD9 AD8 2 1UF_6.3V
TPVDD TPVSS
2 1UF_6.3V 2 10UF_6.3V
AB9 AC9
TXVDDR_1 TXVSSR_1
AB10 AC10
+V2.5S L1003
TXVDDR_2 TXVSSR_2
AD10
TXVSSR_3 +VGAVCC
BLM11A121S
30-,24-,13-,10-,31-
1 2 L7
VDDRH1 VSSRH1
J7 30-,9-,31-

1 C1064 1 C1057 AA16 AC17

A2VDD_1 A2VSSN_1
2 1UF_6.3V AB17 AD16 C1055
2 10UF_6.3V A2VDD_2 A2VSSN_2 1 C1081 1 C1058 1 C1076 1 C1078 1 C1068 1 C1059 1
AB19 AC20 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 22UF_4V
+V2.5S L1006
NC_A2VDDQ A2VSSQ
BLM11A121S AD19 AD18
30-,24-,13-,10-,31- AVDD AVSSN
1 2
Y18
AVSSQ
C1056
1 C1112 1 C1109 AA19 AA20 1 C1074 1 C1084 1 C1075 1 C1080 1 C1017 1 C1018 1
VDD1DI VSS1DI
2 1UF_6.3V AA18 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V 2 1UF_6.3V
2 10UF_6.3V VDD2DI 22UF_4V
AA17
VSS2DI
+VGAVCC L16 AD24 AE24
PVDD PVSS
30-,9-,31-
BLM11A121S
1 2 B2
MPVDD MPVSS
C2

ATI_M52_T_BGA_565P
1 C124 1 C123
2 1UF_6.3V 2 10UF_6.3V

INVENTEC
TITLE
TIANSHAN
ATI-M52-T-3
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 31 OF 74
VM_ADB(63:0) 34- U19 34- VM_AB(13:0)
VM_ADB(0) F16
DQB_0 Part 3 of 6 MAB_0
D10 VM_AB(0)
VM_ADB(1) E20
DQB_1 MAB_1
B8 VM_AB(1)
VM_ADB(2) E16
DQB_2 MAB_2
E9 VM_AB(2)
VM_ADB(3) E19
DQB_3 MAB_3
C8 VM_AB(3)
VM_ADB(4) F19
DQB_4 MAB_4
B10 VM_AB(4)
VM_ADB(5) E17
DQB_5 MAB_5
B7 VM_AB(5)
VM_ADB(6) E15
DQB_6 MAB_6
C7 VM_AB(6)
VM_ADB(7) F18
DQB_7 MAB_7
E7 VM_AB(7)
VM_ADB(8) F14
DQB_8 MAB_8
G6 VM_AB(8)
VM_ADB(9) F13
DQB_9 MAB_9
F9 VM_AB(9)
VM_ADB(10) E14
DQB_10 MAB_10
E8 VM_AB(10)
VM_ADB(11) E13
DQB_11 MAB_11
F8 VM_AB(11)
VM_ADB(12) F10
DQB_12 MAB_12
C6 VM_AB(12)
VM_ADB(13) E10
DQB_13 MAB_13
F7 VM_AB(13)
VM_ADB(14) F11 H7
DQB_14 MAB_14
VM_ADB(15) E11
DQB_15
34- VM_BDQM(7:0)
VM_ADB(16) C20
DQB_16 DQMBb_0
F17 VM_BDQM(0)
VM_ADB(17) B19
DQB_17 DQMBb_1
F12 VM_BDQM(1)
VM_ADB(18) B20
DQB_18 DQMBb_2
B18 VM_BDQM(2)
VM_ADB(19) C19
DQB_19 DQMBb_3
B13 VM_BDQM(3)
VM_ADB(20) C16
DQB_20 DQMBb_4
J5 VM_BDQM(4)
VM_ADB(21) C17
DQB_21 DQMBb_5
J2 VM_BDQM(5)
VM_ADB(22) B16
DQB_22 DQMBb_6
P5 VM_BDQM(6)
VM_ADB(23) B17
DQB_23 DQMBb_7
P2 VM_BDQM(7)
VM_ADB(24) B12
DQB_24
34- VM_BDQS(7:0)
VM_ADB(25) C15
DQB_25 QSB_0
E18 VM_BDQS(0)
VM_ADB(26) C11
DQB_26 QSB_1
E12 VM_BDQS(1)
VM_ADB(27) B15
DQB_27 QSB_2
C18 VM_BDQS(2)
VM_ADB(28) C14
DQB_28 QSB_3
C13 VM_BDQS(3)
VM_ADB(29) B11 J6 VM_BDQS(4)

MEMORY INTERFACE
DQB_29 QSB_4
VM_ADB(30) B14
DQB_30 QSB_5
H3 VM_BDQS(5)
VM_ADB(31) C12
DQB_31 QSB_6
P6 VM_BDQS(6)
VM_ADB(32) F5
DQB_32 QSB_7
P3 VM_BDQS(7)
VM_ADB(33) G5
DQB_33
VM_ADB(34) H6 C5 34- DDR_RASB#
DQB_34 RASBb
VM_ADB(35) H5
DQB_35
VM_ADB(36) K6
DQB_36 CASBb
E6 34- DDR_CASB#
VM_ADB(37) K5
DQB_37
VM_ADB(38) L6
DQB_38 WEBb
C4 34- DDR_WEB#
VM_ADB(39) L5
DQB_39
VM_ADB(40) F2
DQB_40 CSBb_0
B5 34- DDR_CSB0#
VM_ADB(41) G2
DQB_41
VM_ADB(42) H2
DQB_42 CSBb_1
F6 34- DDR_CSB1#
VM_ADB(43) G3
DQB_43
VM_ADB(44) K2
DQB_44 CKEB
B6 34- DDR_CKEB
VM_ADB(45) L2
DQB_45
VM_ADB(46) J3
DQB_46 CLKB0
C9 34-,33- DDR_CLKB0_R +V1.8S
VM_ADB(47) K3
DQB_47 CLKB0b
B9 34-,33- DDR_CLKB0#_R
VM_ADB(48) M5
DQB_48 34-,31-,13-
VM_ADB(49) M6
DQB_49 CLKB1
B4 34-,33- DDR_CLKB1_R 1
VM_ADB(50) N6
DQB_50 CLKB1b
A4 34-,33- DDR_CLKB1#_R
VM_ADB(51) N5 R1059
DQB_51 100_1%
VM_ADB(52) R6
DQB_52
VM_ADB(53) U5
DQB_53 2
VM_ADB(54) R5
DQB_54
VM_ADB(55) T5
DQB_55 MVREFD
C3
VM_ADB(56) M2
DQB_56 MVREFS
B3
1
VM_ADB(57) M3
DQB_57 R1058 1 C1025
VM_ADB(58) N2
DQB_58 +V1.8S
VM_ADB(59) N3 100_1%
DQB_59 +V3S 2 1UF_6.3V
VM_ADB(60) R2 34-,31-,13-
DQB_60 2
VM_ADB(61) R3
DQB_61 1
VM_ADB(62) T2 Y5 1 R1055 2
DQB_62 ROMCSb R132
VM_ADB(63) T3
DQB_63 OPEN
D3 100_1%
NC_MEMVMODE_0
D2
NC_MEMVMODE_1 2
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-
E2
MEMTEST
1 1
ATI_M52_T_BGA_565P
R135 R133 1 C122
243_1% 100_1%
2 1UF_6.3V
2 2

INVENTEC
TITLE
TIANSHAN
ATI-M52-T-4
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 32 OF 74
 U19
A2
VSS_1 Part 5 of 6
A7
VSS_2
H10
VSS_3
A13
VSS_4
D20
VSS_5
B21
VSS_6
B1
VSS_7
G13
VSS_8
L3
VSS_9
G8
VSS_10
D14
VSS_11
D6
VSS_12
D9
VSS_13 CORE GND
D12
VSS_14
D18
VSS_15
A19
VSS_16
C21 H20
VSS_17 PCIE_VSS_1
E21 G24
VSS_18 PCIE_VSS_2
D4 B26 DDR_CLKB1#_R 34-,32-,33- 34-,32-,33- DDR_CLKB1#_R
VSS_19 PCIE_VSS_3
T4 C23
VSS_20 PCIE_VSS_4
F1 D22
VSS_21 PCIE_VSS_5
F4 G22
VSS_22 PCIE_VSS_6
D16 A25
VSS_23 PCIE_VSS_7
G10 W23
VSS_24 PCIE_VSS_8
G19 D25 DDR_CLKB1_R 34-,32-,33- 34-,32-,33- DDR_CLKB1_R
VSS_25 PCIE_VSS_9
D21 H21
VSS_26 PCIE_VSS_10
H4 F23
VSS_27 PCIE_VSS_11 R93 R94
A16 L24 1 2 1 2
VSS_28 PCIE_VSS_12
H13 J24
VSS_29 PCIE_VSS_13 56_5% 56_5%
H16 Y24
VSS_30 PCIE_VSS_14 1 C84
H17 C24
VSS_31 PCIE_VSS_15
J1 M24 2 470PF_50V
VSS_32 PCIE_VSS_16
G16 H24
VSS_33 PCIE_VSS_17
A10 L21 Layout Note: place these
VSS_34 PCIE_VSS_18
K4 J23 resisters near the VIDEO_RAM
VSS_35 PCIE_VSS_19
L13 K25
VSS_36 PCIE_VSS_20
L15 B24
VSS_37 PCIE_VSS_21
M1 K22
VSS_38 PCIE_VSS_22
M7 AC22
VSS_39 PCIE_VSS_23
M8 G25 DDR_CLKB0#_R 34-,32-,33- 34-,32-,33- DDR_CLKB0#_R
VSS_40 PCIE_VSS_24
M14 VSS_41 E24
PCIE_VSS_25
M16 M20
VSS_42 PCIE_VSS_26
N11 P21
VSS_43 PCIE_VSS_27
N15 VSS_44 N22
PCIE_VSS_28
P1 M23
VSS_45 PCIE_VSS_29
P4 P24 DDR_CLKB0_R 34-,32-,33- 34-,32-,33- DDR_CLKB0_R
VSS_46 PCIE_VSS_30
P7 VSS_47 T22
PCIE_VSS_31
P12 F24
VSS_48 PCIE_VSS_32 R1091 2 R1090 2
P16 N24 1 1
VSS_49 PCIE_VSS_33
R11 R20
VSS_50 PCIE_VSS_34 56_5% 56_5%
R13 R23
VSS_51 PCIE_VSS_35 1 C1091
T8 R24
VSS_52 PCIE_VSS_36
T12 VSS_53 T24 2 470PF_50V
PCIE_VSS_37
T14 D24
VSS_54 PCIE_VSS_38
U3 K24
VSS_55 PCIE_VSS_39
U6 U24
VSS_56 PCIE_VSS_40
U7 V20
VSS_57 PCIE_VSS_41
W8 U21
VSS_58 PCIE_VSS_42
W10 V23
VSS_59 PCIE_VSS_43
W12 V24
VSS_60 PCIE_VSS_44
W14 VSS_61 W22
PCIE_VSS_45
Y8 Y23
VSS_62 PCIE_VSS_46
Y12 N25
VSS_63 PCIE_VSS_47
Y14 VSS_64 T25
PCIE_VSS_48
AC5 AB25
VSS_65 PCIE_VSS_49
AC7 W24
VSS_66 PCIE_VSS_50
AE1 VSS_67 AB22
PCIE_VSS_51
AF2 W25
VSS_68 PCIE_VSS_52
D7 AC26
VSS_69 PCIE_VSS_53
C10 VSS_70
M4
VSS_71
R4
VSS_72
F3 AA23
VSS_73 PCIE_PVSS
F15
VSS_74

ATI_M52_T_BGA_565P

INVENTEC
TITLE
TIANSHAN
ATI M52-T-5/VGA DAMPING
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 33 OF 74
 32-,34- U25 32- 32-,34- U12 32-
VM_AB(13:0) VM_ADB(31:0) VM_AB(13:0) VM_ADB(63:32)
VM_AB(12) N4 BA0 DQ31 E13 VM_ADB(31) VM_AB(12) N4 BA0 DQ31 E13 VM_ADB(63)
VM_AB(13) M5 BA1 DQ30 B8 VM_ADB(30) VM_AB(13) M5 BA1 DQ30 D12 VM_ADB(62)
DQ29 D13 VM_ADB(29) DQ29 D13 VM_ADB(61)
VM_AB(11) M7 A11 DQ28 C13 VM_ADB(28) VM_AB(11) M7 A11 DQ28 C13 VM_ADB(60)
VM_AB(10) L6 A10 DQ27 B10 VM_ADB(27) VM_AB(10) L6 A10 DQ27 B10 VM_ADB(59)
VM_AB(9) M8 A9 DQ26 D12 VM_ADB(26) VM_AB(9) M8 A9 DQ26 C9 VM_ADB(58)
VM_AB(8) N11 A8_AP DQ25 B9 VM_ADB(25) VM_AB(8) N11 A8_AP DQ25 B9 VM_ADB(57)
VM_AB(7) N10 A7 DQ24 C9 VM_ADB(24) VM_AB(7) N10 A7 DQ24 B8 VM_ADB(56)
VM_AB(6) N9 A6 DQ23 J3 VM_ADB(23) VM_AB(6) N9 A6 DQ23 K3 VM_ADB(55)
VM_AB(5) M9 A5 DQ22 K2 VM_ADB(22) VM_AB(5) M9 A5 DQ22 K2 VM_ADB(54)
VM_AB(4) N8 A4 DQ21 J2 VM_ADB(21) VM_AB(4) N8 A4 DQ21 J2 VM_ADB(53)
VM_AB(3) N7 A3 DQ20 K3 VM_ADB(20) VM_AB(3) N7 A3 DQ20 J3 VM_ADB(52)
VM_AB(2) M6 A2 DQ19 G2 VM_ADB(19) VM_AB(2) M6 A2 DQ19 G2 VM_ADB(51)
VM_AB(1) N6 A1 DQ18 F2 VM_ADB(18) VM_AB(1) N6 A1 DQ18 G3 VM_ADB(50)
VM_AB(0) N5 A0 DQ17 G3 VM_ADB(17) VM_AB(0) N5 A0 DQ17 F2 VM_ADB(49)
DQ16 F3 VM_ADB(16) DQ16 F3 VM_ADB(48)
C4 NC DQ15 J12 VM_ADB(15) C4 NC DQ15 J13 VM_ADB(47)
C11 NC DQ14 J13 VM_ADB(14) C11 NC DQ14 K13 VM_ADB(46)
H4 NC DQ13 K13 VM_ADB(13) H4 NC DQ13 K12 VM_ADB(45)
H11 NC DQ12 K12 VM_ADB(12) H11 NC DQ12 J12 VM_ADB(44)
L12 NC DQ11 F12 VM_ADB(11) L12 NC DQ11 G13 VM_ADB(43)
+V1.8S L13 F13 VM_ADB(10) +V1.8S L13 F12 VM_ADB(42)
NC DQ10 NC DQ10
32-,31-,13-,34- M3 NC DQ9 G13 VM_ADB(9) 32-,31-,13-,34- M3 NC DQ9 G12 VM_ADB(41)
1 DDR_CSB1# 32-,34- M4 NC_CS1# DQ8 G12 VM_ADB(8) 1 DDR_CSB1# 32-,34- M4 NC_CS1# DQ8 F13 VM_ADB(40)
N3 NC DQ7 E2 VM_ADB(7) N3 NC DQ7 C6 VM_ADB(39)
R223 C6 VM_ADB(6) R131 B7 VM_ADB(38)
1K_1% DQ6 1K_1% DQ6
M13 MCL DQ5 B5 VM_ADB(5) M13 MCL DQ5 B5 VM_ADB(37)
2 DQ4 C2 VM_ADB(4) 2 DQ4 B6 VM_ADB(36)
N13 VREF DQ3 D3 VM_ADB(3) N13 VREF DQ3 E2 VM_ADB(35)
1 DQ2 B6 VM_ADB(2) 1 DQ2 C2 VM_ADB(34)
M10 RFU DQ1 D2 VM_ADB(1) M10 RFU DQ1 D3 VM_ADB(33)
1 C151 R222 1 C152 B7 VM_ADB(0) 1 C120 R130 1 C121 D2 VM_ADB(32)
1K_1% DQ0 1K_1% DQ0
2 10UF_6.3V 2 0.1UF_16V L9 RFU 2 10UF_6.3V 2 0.1UF_16V L9 RFU
2 VDDQ C3 2 VDDQ C3
DDR_CLKB0#_R 33-,32- M12 CLK# VDDQ C5 DDR_CLKB1#_R 33-,32- M12 CLK# VDDQ C5
VDDQ C7 VDDQ C7
DDR_CSB0# 32-,34- N2 CS0# VDDQ C8 DDR_CSB0# 32-,34- N2 CS0# VDDQ C8
VDDQ C10 VDDQ C10
DDR_RASB# 32-,34- M2 RAS# VDDQ C12 DDR_RASB# 32-,34- M2 RAS# VDDQ C12
E3 +V1.8S E3
VDDQ VDDQ +V1.8S
DDR_CASB# 32-,34- L2 CAS# VDDQ E12 32-,31-,13-,34- DDR_CASB# 32-,34- L2 CAS# VDDQ E12
VDDQ F4 VDDQ F4 32-,31-,13-,34-
DDR_WEB# 32-,34- L3 WE# VDDQ F11 DDR_WEB# 32-,34- L3 WE# VDDQ F11
VDDQ G4 VDDQ G4
VM_BDQM(3) 32- B12 DM3 VDDQ G11 VM_BDQM(7) 32- B12 DM3 VDDQ G11
J4 C187 J4 C86
VDDQ 1 VDDQ 1
VM_BDQM(2) 32- H3 DM2 VDDQ J11 VM_BDQM(6) 32- H3 DM2 VDDQ J11
K4 C1152 0.1UF_16V K4 C1028 0.1UF_16V
VDDQ 47UF_4V VDDQ 47UF_4V
VM_BDQM(1) 32- H12 DM1 VDDQ K11 1 2 VM_BDQM(5) 32- H12 DM1 VDDQ K11 1 2
VDD D7 VDD D7
32- B3 DM0 D8 C208 0.1UF_16V 32- B3 DM0 D8 C1030 0.1UF_16V
VM_BDQM(0) VDD +V1.8S VM_BDQM(4) VDD +V1.8S
VDD E4 1 2 VDD E4 1 2
DDR_CLKB0_R 33-,32- M11 CLK VDD E11 32-,31-,13-,34- DDR_CLKB1_R 33-,32- M11 CLK VDD E11 32-,31-,13-,34-
L4 C190 0.1UF_16V L4 C1033 0.1UF_16V
VDD VDD
DDR_CKEB 32-,34- N12 CKE VDD L7 1 2 DDR_CKEB 32-,34- N12 CKE VDD L7 1 2
VDD L8 VDD L8
L11 C1154 0.1UF_16V L11 C1027 0.1UF_16V
VDD VDD
VM_BDQS(3) 32- B13 DQS3 VSSQ B4 1 2 VM_BDQS(7) 32- B13 DQS3 VSSQ B4 1 2
VSSQ B11 VSSQ B11
32- H2 DQS2 D4 C1153 0.1UF_16V 32- H2 DQS2 D4 C1031 0.1UF_16V
VM_BDQS(2) VSSQ VM_BDQS(6) VSSQ
VSSQ D5 1 2 VSSQ D5 1 2
VM_BDQS(1) 32- H13 DQS1 VSSQ D6 VM_BDQS(5) 32- H13 DQS1 VSSQ D6
D9 C189 0.1UF_16V D9 C1029 0.1UF_16V
VSSQ VSSQ
VM_BDQS(0) 32- B2 DQS0 VSSQ D10 1 2 VM_BDQS(4) 32- B2 DQS0 VSSQ D10 1 2
VSSQ D11 VSSQ D11
VSSQ E6 VSSQ E6
F6 TH_GND VSSQ E9 F6 TH_GND VSSQ E9
F7 F5 C188 0.1UF_16V F7 F5 C1032 0.1UF_16V
TH_GND VSSQ TH_GND VSSQ
F8 TH_GND VSSQ F10 1 2 F8 TH_GND VSSQ F10 1 2
F9 TH_GND VSSQ G5 F9 TH_GND VSSQ G5
G6 G10 C153 0.1UF_16V G6 G10 C1035 0.1UF_16V
TH_GND VSSQ TH_GND VSSQ
G7 TH_GND VSSQ H5 1 2 G7 TH_GND VSSQ H5 1 2
G8 TH_GND VSSQ H10 G8 TH_GND VSSQ H10
G9 J5 C191 0.1UF_16V G9 J5 C1034 0.1UF_16V
TH_GND VSSQ TH_GND VSSQ
H6 TH_GND VSSQ J10 1 2 H6 TH_GND VSSQ J10 1 2
H7 TH_GND VSSQ K5 H7 TH_GND VSSQ K5
H8 K10 C1157 0.1UF_16V H8 K10 C85 0.1UF_16V
TH_GND VSSQ TH_GND VSSQ
H9 TH_GND VSS E5 1 2 H9 TH_GND VSS E5 1 2
J6 TH_GND VSS E7 J6 TH_GND VSS E7
J7 E8 C1156 0.1UF_16V J7 E8 C1090 0.1UF_16V
TH_GND VSS TH_GND VSS
J8 TH_GND VSS E10 1 2 J8 TH_GND VSS E10 1 2
J9 TH_GND VSS K6 J9 TH_GND VSS K6
K7 C1155 0.1UF_16V K7 C1026 0.1UF_16V
VSS VSS
VSS K8 1 2 VSS K8 1 2
VSS K9 VSS K9
VSS L5 VSS L5
VSS L10 PLACE IN MEMORY SECTION VSS L10 PLACE IN MEMORY SECTION
SAM_K4D553235F_VC33_FBGA_144P SAM_K4D553235F_VC33_FBGA_144P

INVENTEC
TITLE
TIANSHAN
VIDEO RAM
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 27-Sep-2003 SHEET 34 OF 74
BLANK

INVENTEC
TITLE
TIANSHAN
BLANK
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 35 OF 74
 60-
VGA_R_R
60-
VGA_R_G +V5A
60- CLOSE TO VGA CONN
VGA_R_B +V5S
53-,48-,41-,37-,14-,13-,12-,9-,8-,7-,36-
+V5A
126_VCC 60-,52-,51-,50-,48-,47-,46-,45-,41-,39-,20-,14-,13-,11-,10-,5-
53-,48-,41-,37-,14-,13-,12-,9-,8-,7-,36- D1002

1
CHENKO_LL4148_2P 36-
1 C2 1 C1

2 1

3
2 0.1UF_16V2 10UF_10V
CRT_HSYNC 29- D4 D3 D1
C1002 1 C1001 1
1
0.1UF_16V 2 0.22UF_6.3V 2

2
R1018
10K_5% U1000 CHENMKO_BAV99 CHENMKO_BAV99 CN1
1 8 1 1
2 1OE Vcc
2 7 CHENMKO_BAV99 2 2
1A 2OE R1001 3
3 6 1 2 3
2Y 1Y 4
4
GND 2A
5 0_5% 126_VCC 4
29- 5 5
CRT_VSYNC PHP_74LVC2G126DP_TSSOP_8P 1 R1016 2 60- 36- 6
1 CRT_BUF_HSYNC 6
1 1 7 7
R1017 33_5% 8
R1000 R1004 8
10K_5% 9 9
1 R1002 2 2.2K_5% 2.2K_5% 10
2 +V3S 10
11 11
0_5% 2 2 12 12 G G1
C2 C1 13 13 G G2
14 14
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,36-
1 R1003 2 60- 15 15
1 1 1
A CRT_BUF_VSYNC
R1015 R1014 D1001 33_5%
R1012
2.2K_5% 2.2K_5% 2.2K_5% CHENMKO_CHPZ6V2_3P
2 2 2 Q1004
29- S D 1 R1011 2 60-
CRT_DDCDATA S D CRT_Q_DDCDATA SUYIN_070912FR015S200ZU_15P
0_5%
SSM3K17FU G
G
Q1005
29- S D 1 R1013 2 60-
CRT_DDCCLK S D CRT_Q_DDCCLK
0_5%
SSM3K17FU G
G
C2 C1

D1000
CHENMKO_CHPZ6V2_3P
CLOSE TO VGA CHIP A

SHOULD BE LOCATED CLOSE TO SVIDEO CONN

60- SVID_LUMA_DOCKING

(10/5) (10/5)
29- 1 L21 2
SVID_LUMA
LS_1MH_1.8U
+V3S
1
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,36-
R172 1 C155 1 C157
75_1%

1
2 82PF_50V 2 82PF_50V
2 D1004
CN4

3
CHENMKO_BAV99
1
1
2
2
SVIDEO CN
3

2
3
4
4
5
5
60- VIDEO_COMP_DOCKING 7 G1
7 G1
6 G2
6 G2
(10/5) (10/5)
VIDEO_COMP 29- 1 L22 2
LS_1MH_1.8U SUYIN_030107FR007T110ZU_7P
+V3S
1
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,36-
R173 1 C154 1 C158
75_1%
2 82PF_50V 2 82PF_50V

1
2
D1005
3 CHENMKO_BAV99

60- SVID_CHROMA_DOCKING

(10/5) (10/5)
SVID_CHROMA 29- 1 L24 2
LS_1MH_1.8U +V3S

1 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,36-
R174 1 C159 1 C161
1

75_1%
2 82PF_50V 2 82PF_50V
2 D1006

INVENTEC
3

CHENMKO_BAV99

TITLE
2

TIANSHAN
CRT& SVIDEO CONN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 36 OF 74
 Place closed to connector
+V5A
53-,48-,41-,36-,14-,13-,12-,9-,8-,7-,37-
+V3A

SLP_S3_5R 13- 65-,64-,63-,60-,58-,44-,41-,40-,39-,16-,14-,13-,9-,7-

1
R1021
SSM3K7002F 2 47K_5%
S

LCM_3S_VDDEN 30-
2
1G +V3S
D
(20/5)
Q1008 3 1 R1020 2
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,37-
1 C1007 3
G
6
47K_5% 1 1
2 100PF_50V 5
1 C1006 2
C1005
2
C1004
2 10UF_6.3V

2 1
S D 0.1UF_16V
2 0.01UF_16V 4 1 C11
Q1007 1 1 1 0.1UF_16V
FDC638P R1019 R4 R5
100_5% 4.7K_5% 4.7K_5%
2 2 2
(20/5) Q1006 3 CN3
1
1G
D
(20/5) 2
1
2
3
SSM3K7002F S 3
2 4
4
5
5
6
6
7
7
LCM_DDCPCLK 29- 8
8
9
9
LCM_DDCPDATA 29- 10
10
30- 11
LVDS_TXDL0- 11
30- 12
LVDS_TXDL0+ 12
30- 13
LVDS_TXDL1- 13
30- 14
LVDS_TXDL1+ 14
30- 15
LVDS_TXDL2- 15
30- 16
LVDS_TXDL2+ 30- 16
17
LVDS_TXCL- 30- 17
18
LVDS_TXCL+ 18
19
19
20
20
30- 21
LVDS_TXDU0- 21
30- 22
LVDS_TXDU0+ 22
30- 23
LVDS_TXDU1- 23
30- 24
LVDS_TXDU1+ 24
30- 25
LVDS_TXDU2- 25
30- 26
LVDS_TXDU2+ 26
30- 27
+V5A LVDS_TXCU- 27
30- 28
LVDS_TXCU+ 28
53-,48-,41-,36-,14-,13-,12-,9-,8-,7-,37- 29
29
30
30
31
C1003 31
32
1 32
33
33
34
22UF_6.3V 35
34
35
INV_PWM_3 43-,30- 36
36
37 G1
37 G
38 G2
38 G
39
39
40
1 40
R6007 1 C8 1 C14 1 C7 ACES_88307_4001_40P
OPEN
2 OPEN 2 1000PF_50V 2 0.1UF_16V
2

+V3S

65-,39- 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,37-
LID_SW#_3
1
R6008
47K_5%
1 2

D6007 3
BAT54A

29- 1 R6009 2
LCM_3S_BKLTEN
0_5%_OPEN
INVENTEC
TITLE
TIANSHAN
LCD CONN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 37 OF 74
 +V3AL +V_RTC
66-,57-,47-,45-,43-,14-,7-,6-,5- 43-,41-

1 C1274
2 1UF_6.3V

2
D1021 1 R1277 2
BAT54C

3
20K_1%
1 D6006 C357 18PF_50V

1
1
1 2
2 40V_3A_1W_OPEN 1 C1275 R1276
2 1UF_6.3V OPEN
1 1 2 1 1
RTCBAT 2
R1321 R1275 R341
1K_5% 1M_5% X3 10M_5%
CN20 2 2 3 4 2
C358
4 G 2 2 18PF_50V
3 G 1 1 U36
JST_BM2B_SRSS 1 2 32.768KHZ_VAIL20 AB1
RXTC1 LAD0
AA6 63-,57-,46-,43- LPC_3S_AD(0)
AB2 AB5 63-,57-,46-,43- LPC_3S_AD(1)
RXTC2 LAD1

RTC

LPC
AC4 63-,57-,46-,43- LPC_3S_AD(2)
LAD2
AA3
RTCRST# LAD3
Y6 63-,57-,46-,43- LPC_3S_AD(3) Close to ICH7
Y5 AC3 46- LPC_3S_DRQ0#
INTRUDER# LDRQ0# +VCCP
1 2 W4 AA5
INTVRMEN LDRQ1#_GPIO23
R1279 332K_1% 41-,25-,24-,22-,21-,18-,17-,16-,15-,9-,38-
W1 AB3 63-,57-,46-,43- LPC_3S_FRAME#
1 EE_CS LFRAME#
Y1
R1281 EE_SHCLK
Y2 AE22 43- EC_3S_A20GATE
OPEN EE_DOUT A20GATE
W3 AH28 16-
H_A20M#
EE_DIN A20M# Close to ICH7 1
2
V3 AG27 1 R338 2 22-,17- R337
LAN_CLK CPUSLP# H_CPUSLP# 56_5%
OPEN
U3 AF24 1 2 17-,11-
LAN_RSTSYNC TP1_DPRSTP# H_DPRSTP# 2
AH25 17- H_DPSLP# R1264 0_5%
R343 TP2_DPSLP#
47- 1 2 U5
AC97_3S_BITCLK_MDC LAN_RXD0

LAN
V4 AG26 16- H_FERR#
39_5% LAN_RXD1 FERR#
T5
R375 2 LAN_RXD2
47- 1 AG24 17- 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,38-
AC97_3S_SYNC_MDC GPIO49_CPUWRGD H_PWRGD
U7 +V3S
39_5% LAN_TXD0
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,38- V6
R376 2 LAN_TXD1
47- 1 V7 AG22 16-
+V3S AC97_3S_RST#_MDC LAN_TXD2 IGNNE# H_IGNNE#
AG21 TP787
R1282 1 2 39_5% 39_5% INIT3_3V#
1 R336 2
AC97_3S_BITCLK 48- U1 AF22 16- H_INIT#
ACZ_BIT_CLK INIT#
AC97_3S_SYNC 48- R1292 1 2 39_5% R6
ACZ_SYNC INTR
AF25 16- H_INTR 10K_5% 41-,25-,24-,22-,21-,18-,17-,16-,15-,9-,38-

AC-97/AZALIA

CPU
48- R1290 1 2 39_5% R5 AG23 43-
+VCCP
1 AC97_3S_RST# ACZ_RST# RCIN# PM_3S_KBCCPURST#
R1271 48- T2 AH24 16-
10K_5% AC97_3S_SDIN0 ACZ_SDIN0 NMI H_NMI 1
AC97_3S_SDIN1 47- T3 AF23 16- H_SMI#
ACZ_SDIN1 SMI# R1263
2 AC97_3S_SDOUT_MDC 47- R1280 1 2 39_5% T1
ACZ_SDIN2
AH22 16- 56_5%
R342 1 2 39_5% STPCLK# H_STPCLK#
AC97_3S_SDOUT 48- T4
ACZ_SDOUT 2 21-,20-,16-
AF26 1 R1262 2
THERMTRIP# PM_THRMTRIP#
LED_3S_SATA# 47- AF18
SATALED# 24.9_1%
SATA_C_RXN0 51- AF3 AB15 52- PIDE_3S_D(0)
SATA0RXN DD0
SATA_C_RXP0 51- AE3 AE14 52- PIDE_3S_D(1)
C362 3300PF_50V SATA0RXP DD1
SATA_C_TXN0 51- SATA_TXN0 AG2
SATA0TXN DD2
AG13 52- PIDE_3S_D(2)
SATA_C_TXP0 51- 1 2 SATA_TXP0 AH2
SATA0TXP DD3
AF13 52- PIDE_3S_D(3)
C361 1 2 3300PF_50V AD14 52-
DD4 PIDE_3S_D(4)
AF7 AC13 52- PIDE_3S_D(5)

SATA
SATA2RXN DD5
AE7 AD12 52- PIDE_3S_D(6)
SATA2RXP DD6
CLOSE TO ICH7 AG6
SATA2TXN DD7
AC12 52- PIDE_3S_D(7)
AH6 AE12 52- PIDE_3S_D(8)
SATA2TXP DD8
AF12 52- PIDE_3S_D(9)
DD9
CLK_R_SATA1# 15- AF1 AB13 52- PIDE_3S_D(10)
SATA_CLKN DD10
CLK_R_SATA1 15- AE1 AC14 52- PIDE_3S_D(11)
SATA_CLKP DD11
AF14 52- PIDE_3S_D(12)
DD12
AH10 AH13 52- PIDE_3S_D(13)
SATARBIASN DD13
AG10 AH14 52- PIDE_3S_D(14)
SATARBIASP DD14
AC15 52-
DD15 PIDE_3S_D(15)
52- AF15 AH17 52-
PIDE_3S_IOR# DIOR# DA0 PIDE_3S_A(0)
52- AH15 AE17 52-
PIDE_3S_IOW# DIOW# IDE DA1 PIDE_3S_A(1)
52- AF16 AF17 52-
1 PIDE_3S_DACK# DDACK# DA2 PIDE_3S_A(2)
52- AH16
R331 PIDE_3S_IRQ IDEIRQ
PIDE_3S_IORDY 52- AG16 AE16 52- PIDE_3S_CS#(0)
24.9_1% IORDY DCS1#
52- AE15 AD16 52-
PIDE_3S_DREQ DDREQ DCS3# PIDE_3S_CS#(1)
2
ITL_ICH7_MBGA_652P

INVENTEC
TITLE
TIANSHAN
ICH7-1
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 38 OF 74
 U36
F26 V26 21- DMI_RXN(0)
PERn1 DMI0RXN
F25 V25 21- DMI_RXP(0)
PERp1 DMI0RXP
E28 U28 21- DMI_TXN(0)
PETn1 DMI0TXN
E27 U27 21- DMI_TXP(0)
PETp1 DMI0TXP CHENMKO_BAT54_3P
C1286 57- H26 Y26 21-
0.1UF_16V PCIE_C_RXN2 PERn2 DMI1RXN DMI_RXN(1) D27
57- H25 Y25 21- 60-,48-,39- 60-,59-
57- 2 1 PCIE_C_RXP2 PERp2 DMI1RXP DMI_RXP(1) ISO_PREP# 1 3 PREP#
PCIE_TXN2 G28 W28 21-
PCIE_C_TXN2 2 1 PETn2 DMI1TXN DMI_TXN(1)

Direct Media Interface

57- PCIE_TXP2 G27 W27 21-
PCIE_C_TXP2 PETp2 DMI1TXP DMI_TXP(1)
C1285 ISOLATION
0.1UF_16V K26
PERn3 DMI2RXN
AB26 21- DMI_RXN(2)
K25 AB25 21- DMI_RXP(2)
PERp3 DMI2RXP

PCI-Express
J28 AA28 21- DMI_TXN(2)
PETn3 DMI2TXN
J27 AA27 21- DMI_TXP(2)
PETp3 DMI2TXP
60- C1287 M26 AD25 21-
PCIE_C_RXN4 0.1UF_16V PERn4 DMI3RXN DMI_RXN(3)
60- M25 AD24 21- +V1.5S
PCIE_C_RXP4 PERp4 DMI3RXP DMI_RXP(3)
60- 2 1 PCIE_TXN4 L28 AC28 21- DMI_TXN(3)
PCIE_C_TXN4 PETn4 DMI3TXN
60- 2 1 PCIE_TXP4 L27 AC27 21- DMI_TXP(3) 57-,41-,25-,24-,21-,18-,10-,8-
PCIE_C_TXP4 PETp4 DMI3TXP
C1288 1
0.1UF_16V P26 AE28 15- CLK_R_PCIE_ICH#
PERn5 DMI_CLKN R1296
P25 AE27 15- CLK_R_PCIE_ICH
PERp5 DMI_CLKP 24.9_1%
N28
PETn5
N27 C25
PETp5 DMI_ZCOMP DMI_IRCOMP_R 2
D25
DMI_IRCOMP
T25
PERn6
T24 F1 64- Close to ICH6
PERp6 USBP0N USB_P1-
R28 F2 64- USB_P1+
PETn6 USBP0P
R27 G4 57- USB_P2-
PETp6 USBP1N
G3 57- USB_P2+
R373 47_5% USBP1P
44- 1 2 R2 H1 TP790
SPI_CLK SPI_CLK USBP2N
SPI_CE# 44- P6 H2 TP791
SPI_CS# USBP2P
P1 J4 53- USB_P3-
SPI_ARB USBP3N

SPI
J3 53- USB_P3+
R1293 1 47_5% USBP3P
44- 2 P5 K1 53-
SPI_SI SPI_MOSI USBP4N USB_P4-
44- P2 K2 53-

USB
SPI_SO SPI_MISO USBP4P USB_P4+
+V3A L4 53- USB_P5-
2 2 2 USBP5N
+V3A D3 L5 53- USB_P5+
OC0# USBP5P
65-,64-,63-,60-,58-,44-,41-,40-,37-,16-,14-,13-,9-,7-,39- 10K_5% 10K_5% 10K_5% C4 M1 60- USB_P6-
OC1# USBP6N
R1291 R377 R374 65-,64-,63-,60-,58-,44-,41-,40-,37-,16-,14-,13-,9-,7-,39- D5 M2 60- USB_P6+
1 OC2# USBP6P
1 1 1 D4 N4 60- USB_P7-
OC3# USBP7N
R369 E5
OC4# USBP7P
N3 60- USB_P7+
10K_5% C3
OC5#GPIO29
A2 D2
2 OC6#GPIO30 USBRBIAS# R380
B3 D1 USB_RBIAS_PN 1 2
OC7#GPIO31 USBRBIAS
22.6_1% 1 1 1 1
ITL_ICH7_MBGA_652P R1270 R333 R334 R1269
Place within 500 mils of ICH 8.2K_5% OPEN 8.2K_5% 8.2K_5%
U36 2 2 2 2
ICH_3A_SMCLK 39- C22 AF19
SMBLCK GPIO21_SATA0GP 47-

SATA
39- B22 AH18

GPIO
ICH_3A_SMDATA SMBDATA GPIO19_SATA1GP HDD_HALTED

SMB
ICH_3A_LINKALERT# 39- A26 AH19 TP703
LINKALERT# GPIO36_SATA2GP
ICH_3A_ALERT_CLK 39- B25 AE19 TP702
SMLINK0 GPIO37_SATA3GP
ICH_3A_ALERT_DAT 39- A25
SMLINK1 15-
AC1
CLK14 CLK_R3S_ICH14

Clocks
39- A28 B2 15-
PM_RI# TP708
RI# CLK48 CLK_R3S_ICH48
A_3S_ICHSPKR 48- A19 C20 TP580
SPKR SUSCLK
SUS_STAT# 63-,50- A27
2 0_5%
SUS_STAT# R391
16- A22 B24 1 60-,58-,43-,13-,12-
XDP_DBRESET# SYS_RST# SLP_S3# SLP_S3#_3R
SLP_S4#
D23 OPEN 2 1R1299
60-,53-,47-,12-,8-
BM_BUSY# 21- AB18
GPIO0_BM_BUSY# SLP_S5#
F22 0_5% 2 1R1297
SLP_S5#_3R
2
OCP_OC# 5-,39- B23 AA4 TP704 43-,21-,11- PM_PWROK R1278
GPIO11_SMBALERT# PWROK
1
PCISTOP#_3 15- AC20 AC22 21-,11- PM_DPRSLPVR 10K_5%
GPIO18_STPPCI# GPIO16_DPRSLPVR
CPUSTOP#_3 15- AF21
GPIO20_STPCPU#
C21 TP705
TP0_BATLOW# 1

SYS GPIO
TP2 A21
PULL-DOWN FOR GMCH A0

Power MGT
GPIO26
PWRBTN#
C23 65- PWR_SWIN2#_3 R1265
B21 OPEN
40- TP762 E23
GPIO27 OPEN FOR GMCH A1
VGA_RST# GPIO28
1 R1303 2 63-,57-,52-,46-,40- 2
C19 BUF_PLT_RST#
LAN_RST#
PCI_3S_CLKRUN# 63-,58-,47-,46-,43-,39- AG18
GPIO32_CLKRUN# 0_5%
Y4 43-,7- RSMRST#
RSMRST# CHENMKO_BAT54_3P D1019
AC19 +V3A 43- LOW_BAT#_3
TP788 U2
GPIO33_AZ_DOCK_EN#
E20 1
R1302 2 OPEN 65-,44-,40- 1 3
TP789
GPIO34_AZ_DOCK_RST# GPIO9 ACCEL_INT R1323 2 1
10K_5%
A20
GPIO10 TP765
PCIE_WAKE# 57-,39- F20 F19 65-,64-,63-,60-,58-,44-,41-,40-,37-,16-,14-,13-,9-,7-,39-
WAKE# GPIO12
PCI_3S_SERIRQ 63-,47-,46-,43-,39- AH21 E19 65-,37- LID_SW#_3
SERIRQ GPIO13
THERM_SCI# 40-,20- AF20 R4 59-,40- LED_LANLINK#
THRM# GPIO14
E22
TP699
+V3A
GPIO15
11- AD22 R3 57-
SB_3S_VRMPWRGD VRMPWRGD GPIO24
64-
XMIT_OFF# ISOLATION 2 R1301 1
D20 BT_OFF
GPIO25
43-,40- AC21 AD21 46-,43-
RUNSCI0#_3 GPIO6 GPIO35 R1267 2 NPCI_RESET# 8.2K_5%
60-,48-,39- AC18 AD20 1 60-
ISO_PREP# GPIO7 GPIO GPIO38 DOCK_ADP_ID 65-,64-,63-,60-,58-,44-,41-,40-,37-,16-,14-,13-,9-,7-,39-
E21 AE20
TP706
GPIO8 GPIO39 OPEN +V3S +V3A 65-,64-,63-,60-,58-,44-,41-,40-,37-,16-,14-,13-,9-,7-,39-
+V3A 1
ITL_ICH7_MBGA_652P
65-,64-,63-,60-,58-,44-,41-,40-,37-,16-,14-,13-,9-,7-,39- R1274 +V3S 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,39-
1 1 1 2 1
100K_5%
39- R396 1 2 10K_5% R428 R395 R1266 R388 R1298
PM_RI# 2 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,39-
2.2K_5% OPEN 10K_5%
5-,39- R390 1 2 10K_5% 2.2K_5% 10K_5%
OCP_OC# 60-,52-,51-,50-,48-,47-,46-,45-,41-,36-,20-,14-,13-,11-,10-,5-
ICH_3A_LINKALERT# 39- R394 1 2 10K_5% 57-,44-,27-,26-,20-,15- 2 2 2 1 2
ICH_3A_ALERT_CLK 39- R393 1 2 10K_5% +V5S
39- R392 1 2 10K_5% ICH_3S_SMCLK
ICH_3A_ALERT_DAT
2 SSM3K7002F
S

PCIE_WAKE# 57-,39- R1285 1 2 1K_5%

D
G
1
3 Q1039

66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,39-
+V3S ICH_3A_SMCLK
ICH_3A_SMDATA
39-
39-
R13001
R389 1
2 33_5%
2 33_5%

3 D Q57
INVENTEC
TITLE
63-,58-,47-,46-,43-,39- R332 1 2 8.2K_1%
G 1 TIANSHAN
PCI_3S_CLKRUN# S ICH7-2
63-,47-,46-,43-,39- R335 1 2 8.2K_5% 2 SSM3K7002F
PCI_3S_SERIRQ 57-,44-,27-,26-,20-,15-
SIZE CODE DOC. NUMBER REV
ICH_3S_SMDATA A3 CS Model_No A02
CHANGE by Ho,Thomas SHEET 39 OF 74
 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,40-

PCI_3S_AD(31:0) +V3S 60-,15- CPPE#

47-,58- U36
E18 D7 58-,40- PCI_3S_REQ#(0)
AD0 REQ0# 1
C18 E7 58- PCI_3S_GNT#(0)
AD1 GNT0# R1313
A16 C16 40- PCI_3S_REQ#(1)
AD2 REQ1# 10K_5%
F18 D16
AD3 PCI GNT1#
E16 C17 47-,40- PCI_3S_REQ#(2) 2
AD4 REQ2#
A18 D17 47- PCI_3S_GNT#(2)
AD5 GNT2#
E17 E13 40- PCI_3S_REQ#(3)
AD6 REQ3#
A17 F13
AD7 GNT3#
A15 A13 40- PCI_3S_REQ#(4)
AD8 REQ4#_GPIO22 TP709
C14
AD9 GNT4#_GPIO48
A14 R1312 0_5%
E14 C8 1 2
AD10 GPIO1_REQ5#
D14 D8 ALS_EN# 1 2
AD11 GPIO17_GNT5#
B12 R1317
AD12 10K_5%
C13 B15 58-,47- PCI_3S_CBE#(0)
AD13 C_BE0#
G15 C12 58-,47- PCI_3S_CBE#(1)
AD14 C_BE1#
G13 D12 58-,47- PCI_3S_CBE#(2)
AD15 C_BE2#
E12 C15 58-,47- PCI_3S_CBE#(3)
AD16 C_BE3#
C11
AD17
D11 A7 58-,47-,40- PCI_3S_IRDY#
AD18 IRDY#
A11 E10 58-,47- PCI_3S_PAR
AD19 PAR
A10 B18
AD20 PCIRST#
F11 A12 58-,47-,40- PCI_3S_DEVSEL#
AD21 DEVSEL#
F10 C9 58-,47-,40- PCI_3S_PERR#
AD22 PERR#
E9 E11 40- PCI_3S_LOCK# 58-,47- PCI_3S_RST#
AD23 PLOCK#
D9 B10 58-,47-,43-,40- PCI_3S_SERR#
AD24 SERR#
B9 F15 58-,47-,40- PCI_3S_STOP#
AD25 STOP#
A8 F14 58-,47-,40- PCI_3S_TRDY#
AD26 TRDY#
A6 F16
AD27 FRAME# PCI_3S_FRAME#
C7 58-,47-,40-
AD28
B6 C26 21- PLT_RST#
AD29 PLTRST#
E6 A91, 0.5 15- CLK_R3S_ICHPCI +V3A
AD30 PCICLK
D6 B19 58-,47- 65-,64-,63-,60-,58-,44-,41-,39-,37-,16-,14-,13-,9-,7-,40-
AD31 PME# PCI_3S_PME#
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,40-
Interrupt I/F
PCI_3S_INTA# 58-,40- A3 G8 40- PCI_3S_INTE#
PIRQA# GPIO2_PIRQE# +V3S 5
PCI_3S_INTB# 40- B4 F7 40- PCI_3S_INTF# U39
PIRQB# GPIO3_PIRQF# 63-,57-,52-,46-,39-
PCI_3S_INTC# 47-,40- C5
PIRQC# GPIO4_PIRQG#
F8 47-,40- PCI_3S_INTG# 2 4 BUF_PLT_RST#
47-,40- B5 G7 R1287 1 2 OPEN
PCI_3S_INTD# PIRQD# GPIO5_PIRQH#
2 0_5% 65-,44-,39-
R1288 1
ACCEL_INT 3 PHP_74LVC1G17_SOT753_5P
TP627 AE5
MISC AE9
RSVD1 RSVD6 TP632
TP628 AD5 AG8
RSVD2 RSVD7 TP633 1
TP629 AG4 AH8 +V3A
RSVD3 RSVD8 TP634
TP630 AH4
RSVD4 RSVD9
F21
TP635
R402
TP631 AD9
RSVD5 MCH_SYNC#
AH20 21- MCH_ICH_SYNC# 65-,64-,63-,60-,58-,44-,41-,39-,37-,16-,14-,13-,9-,7-,40- 20K_5%
2
ITL_ICH7_MBGA_652P
U38 5 1
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,40-
29- 1 R429 2 4
PCIE_RST#
+V3S 330_5% 2
NC7SZ08M5 3
58-,47-,40- R13061 2 8.2K_5%
PCI_3S_FRAME#
58-,47-,40- R384 1 2 8.2K_5%
PCI_3S_IRDY#
58-,47-,40- R13081 2 8.2K_5%
PCI_3S_TRDY#
58-,47-,40- R13071 2 8.2K_5%
PCI_3S_STOP#
58-,47-,43-,40- R385 1 2 8.2K_5%
PCI_3S_SERR#
58-,47-,40- R386 1 2 8.2K_5%
PCI_3S_DEVSEL#
VGA_RST# 39-
58-,47-,40- R13111 2 8.2K_5%
PCI_3S_PERR#
40- R13101 2 8.2K_5%
PCI_3S_LOCK#
58-,40- R13151 2 8.2K_5%
PCI_3S_REQ#(0)
40- R13051 2 8.2K_5%
PCI_3S_REQ#(1)
47-,40- R13041 2 8.2K_5%
PCI_3S_REQ#(2)
40- R13091 2 8.2K_5%
PCI_3S_REQ#(3)
58-,40- R381 1 2 8.2K_5%
PCI_3S_INTA#
40- R382 1 2 8.2K_5%
PCI_3S_INTB#
47-,40- R13181 2 8.2K_5%
PCI_3S_INTC#
47-,40- R383 1 2 8.2K_5%
PCI_3S_INTD#
40- R13161 2 8.2K_5%
PCI_3S_INTE#
40- R13191 2 8.2K_5%
PCI_3S_INTF#
47-,40- R13141 2 8.2K_5%
PCI_3S_INTG#
RUNSCI0#_3

THERM_SCI#
43-,39-

39-,20-
R12731

R12681
2 8.2K_5%

2 8.2K_5%
65-,64-,63-,60-,58-,44-,41-,39-,37-,16-,14-,13-,9-,7-,40-

+V3A
INVENTEC
TITLE
PCI_3S_REQ#(4) 40- R387 1 2 8.2K_5% TIANSHAN
59-,39- R12891 2 8.2K_5%
ICH7-3
LED_LANLINK#
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 40 OF 74
 +V3S
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,41-
D1018
1 3
+V5S +VCCP
CHENMKO_BAT54_3P
U36 38-,25-,24-,22-,21-,18-,17-,16-,15-,9-,41-
2 R1286 1 G10 L11
V5REF1 VCC1_05_1
L12
60-,52-,51-,50-,48-,47-,46-,45-,39-,36-,20-,14-,13-,11-,10-,5- 100_5% VCC1_05_2 C1269
AD17 L14
C1295 1 V5REF2 VCC1_05_3 1 C1268 1 C1290 1
L16
VCC1_05_4
+V3A F6 L17
0.1UF_16V 2 V5REF_SUS VCC1_05_5 2 0.1UF_16V 2 1UF_6.3V 220UF_2V_15mR_Panasonic
65-,64-,63-,60-,58-,44-,40-,39-,37-,16-,14-,13-,9-,7-,41- L18
VCC1_05_6
AA22 M11
D1020 VCC1_5_B1 VCC1_05_7
AA23 M18
VCC1_5_B2 VCC1_05_8
1 3 AB22 P11
VCC1_5_B3 VCC1_05_9
+V5A CHENMKO_BAT54_3P AB23 P18
VCC1_5_B4 VCC1_05_10
AC23 T11
VCC1_5_B5 VCC1_05_11
AC24 T18
VCC1_5_B6 VCC1_05_12
2 R1320 1 AC25 U11
VCC1_5_B7 VCC1_05_13
AC26 U18 +V3S
10_1% VCC1_5_B8 VCC1_05_14
AD26 V11
C1301 1 VCC1_5_B9 VCC1_05_15
53-,48-,37-,36-,14-,13-,12-,9-,8-,7- AD27 V12 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,41-
VCC1_5_B10 VCC1_05_16
AD28 V14
0.1UF_16V 2 VCC1_5_B11 VCC1_05_17
D26 V16
VCC1_5_B12 VCC1_05_18
D27 V17
VCC1_5_B13 VCC1_05_19 1C368
D28 V18
VCC1_5_B14 VCC1_05_20
57-,39-,25-,24-,21-,18-,10-,8-,41- E24 2 0.1UF_16V
VCC1_5_B15 +V3S
+V1.5S E25 V5
VCC1_5_B16 VCCSUS3_3_VCCLAN3_3_1
E26 V1
VCC1_5_B17 VCCSUS3_3_VCCLAN3_3_2
F23 W2
L37 VCC1_5_B18 VCCSUS3_3_VCCLAN3_3_3
F24 W7 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,41-
VCC1_5_B19 VCCSUS3_3_VCCLAN3_3_4 1 C1299
1 2 G22
VCC1_5_B20
G23 U6
+VCCP
KC_FBM_11_160808_101_T_2P 1 1 C1289 1 C1267 1 C1266 VCC1_5_B21 VCC3_3_VCCHDA 2 0.1UF_16V
C369 H22 38-,25-,24-,22-,21-,18-,17-,16-,15-,9-,41-
VCC1_5_B22
220UF_2.5V 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V H23 R7
VCC1_5_B23 VCCSUS3_3_VCCSUSHDA
J22
VCC1_5_B24
J23 AE23
VCC1_5_B25 V_CPU_IO_1
K22 AE26
VCC1_5_B26 V_CPU_IO_2 1 C365 1 C1263 1 C1264
K23 AH26
VCC1_5_B27 V_CPU_IO_3
L22 2 4.7UF_6.3V 2 0.1UF_16V 2 0.1UF_16V
VCC1_5_B28
L23 AA7
VCC1_5_B29 VCC3_3_3
M22 AB12
VCC1_5_B30 VCC3_3_4
+V1.5S M23 AB20
VCC1_5_B31 VCC3_3_5
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,41- N22 AC16
VCC1_5_B32 VCC3_3_6
57-,39-,25-,24-,21-,18-,10-,8-,41- N23 AD13 +V3S
VCC1_5_B33 VCC3_3_7
+V3S P22 AD18
VCC1_5_B34 VCC3_3_8
P23 AG12 66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,41-
VCC1_5_B35 VCC3_3_9
R22 AG15
R339 L36 VCC1_5_B36 VCC3_3_10
1 2 1 2 R23
VCC1_5_B37 VCC3_3_11
AG19
BLM11A121S R24
1_1% VCC1_5_B38
R25 A5
1 1 VCC1_5_B39 VCC3_3_12 1 C1293 1 C1271 1 C1294 1 C1270
R26 B13
C367 C366 T22
VCC1_5_B40 VCC3_3_13
B16
2 2 VCC1_5_B41 VCC3_3_14 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V
10UF_6.3V 0.01UF_16V T23 B7
VCC1_5_B42 VCC3_3_15
T26 C10
1 VCC1_5_B43 VCC3_3_16
T27 D15
C1306 T28
VCC1_5_B44 VCC3_3_17
F9
+V1.5S 2 0.1UF_16V VCC1_5_B45 VCC3_3_18
U22 G11
VCC1_5_B46 VCC3_3_19 +V_RTC
57-,39-,25-,24-,21-,18-,10-,8-,41- U23 G12
VCC1_5_B47 VCC3_3_20
V22 G16 43-,38-
VCC1_5_B48 VCC3_3_21
V23
VCC1_5_B49
W22 W5
VCC1_5_B50 VCCRTC
W23
VCC1_5_B51
Y22 P7
1 C1291 VCC1_5_B52 VCCSUS3_3_1 1 C1273 1 C1272
Y23
VCC1_5_B53
2 0.1UF_16V A24 2 0.1UF_16V 2 0.1UF_16V
VCCSUS3_3_2
B27 C24
VCC3_3_1 VCCSUS3_3_3
D19
+V1.5S_GPLL_ICH AG28
VCCSUS3_3_4
D22
VCCDMIPLL VCCSUS3_3_5
G19 +V3A
VCCSUS3_3_6
+V1.5S AB7
VCC1_5_A1
57-,39-,25-,24-,21-,18-,10-,8-,41- AC6 K3 65-,64-,63-,60-,58-,44-,40-,39-,37-,16-,14-,13-,9-,7-,41-
VCC1_5_A2 VCCSUS3_3_7
AC7 K4
L35 VCC1_5_A3 VCCSUS3_3_8
1 2 AD6
VCC1_5_A4 VCCSUS3_3_9
K5
BLM11B121SB AE6
VCC1_5_A5 VCCSUS3_3_10
K6
AF5 L1
1 VCC1_5_A6 VCCSUS3_3_11
C360 C359 1 AF6
VCC1_5_A7 VCCSUS3_3_12
L2 1
C1302
1
C1297
1
C1298
1
C1303
AG5 L3
10UF_6.3V 2 0.1UF_16V 2 VCC1_5_A8 VCCSUS3_3_13 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V
AH5 L6
VCC1_5_A9 VCCSUS3_3_14
+V3S L7
VCCSUS3_3_15
AD2 M6
VCCSATAPLL VCCSUS3_3_16
66-,63-,58-,57-,52-,48-,47-,46-,44-,43-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,41- M7
VCCSUS3_3_17
AH11 N7
VCC3_3_2 VCCSUS3_3_18
+V1.5S
C364 1 AB10 AB17 +V1.5S
VCC1_5_A10 VCC1_5_A_19
0.1UF_16V 2 AB9
VCC1_5_A11 VCC1_5_A_20
AC17 57-,39-,25-,24-,21-,18-,10-,8-,41-
57-,39-,25-,24-,21-,18-,10-,8-,41-
AC10
VCC1_5_A12
AD10 T7
VCC1_5_A13 VCC1_5_A_21
AE10 F17
1 C363 VCC1_5_A14 VCC1_5_A_22
AF10 G17
VCC1_5_A15 VCC1_5_A_23
2 1UF_6.3V AF9
+V3A VCC1_5_A16
AG9 AB8
VCC1_5_A17 VCC1_5_A_24 1 1
65-,64-,63-,60-,58-,44-,40-,39-,37-,16-,14-,13-,9-,7-,41- AH9 AC8 C1292
VCC1_5_A18 VCC1_5_A_25 C1296
2 0.1UF_16V 2 0.1UF_16V
E3 K7
VCCSUS3_3_19 VCCSUS1_05_1
C1300 1 C1 C28
VCCUSBPLL VCCSUS1_05_2
G20
0.1UF_16V 2 VCCSUS1_05_3
AA2
VCCSUS1_05_VCCLAN1_05_1
Y7 A1
VCCSUS1_05_VCCLAN1_05_2 VCC1_5_A_26
H6
VCC1_5_A_27
H7
VCC1_5_A_28
+V1.5S J6
VCC1_5_A_29
57-,39-,25-,24-,21-,18-,10-,8-,41-
VCC1_5_A_30

ITL_ICH7_MBGA_652P
J7
INVENTEC
1 TITLE
C372 TIANSHAN
0.1UF_16V 2 ICH7-4
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 41 OF 74
 U36
A4 P28
VSS1 VSS98
A23 R1
VSS2 VSS99
B1 R11
VSS3 VSS100
B8 R12
VSS4 VSS101
B11 R13
VSS5 VSS102
B14 R14
VSS6 VSS103
B17 R15
VSS7 VSS104
B20 R16
VSS8 VSS105
B26 R17
VSS9 VSS106
B28 R18
VSS10 VSS107
C2 T6
VSS11 VSS108
C6 T12
VSS12 VSS109
C27 T13
VSS13 VSS110
D10 T14
VSS14 VSS111
D13 T15
VSS15 VSS112
D18 T16
VSS16 VSS113
D21 T17
VSS17 VSS114
D24 U4
VSS18 VSS115
E1 U12
VSS19 VSS116
E2 U13
VSS20 VSS117
E4 U14
VSS21 VSS118
E8 U15
VSS22 VSS119
E15 U16
VSS23 VSS120
F3 U17
VSS24 VSS121
F4 U24
VSS25 VSS122
F5 U25
VSS26 VSS123
F12 U26
VSS27 VSS124
F27 V2
VSS28 VSS125
F28 V13
VSS29 VSS126
G1 V15
VSS30 VSS127
G2 V24
VSS31 VSS128
G5 V27
VSS32 VSS129
G6 V28
VSS33 VSS130
G9 W6
VSS34 VSS131
G14 W24
VSS35 VSS132
G18 W25
VSS36 VSS133
G21 W26
VSS37 VSS134
G24 Y3
VSS38 VSS135
G25 Y24
VSS39 VSS136
G26 Y27
VSS40 VSS137
H3 Y28
VSS41 VSS138
H4 AA1
VSS42 VSS139
H5 AA24
VSS43 VSS140
H24 AA25
VSS44 VSS141
H27 AA26
VSS45 VSS142
H28 AB4
VSS46 VSS143
J1 AB6
VSS47 VSS144
J2 AB11
VSS48 VSS145
J5 AB14
VSS49 VSS146
J24 AB16
VSS50 VSS147
J25 AB19
VSS51 VSS148
J26 AB21
VSS52 VSS149
K24 AB24
VSS53 VSS150
K27 AB27
VSS54 VSS151
K28 AB28
VSS55 VSS152
L13 AC2
VSS56 VSS153
L15 AC5
VSS57 VSS154
L24 AC9
VSS58 VSS155
L25 AC11
VSS59 VSS156
L26 AD1
VSS60 VSS157
M3 AD3
VSS61 VSS158
M4 AD4
VSS62 VSS159
M5 AD7
VSS63 VSS160
M12 AD8
VSS64 VSS161
M13 AD11
VSS65 VSS162
M14 AD15
VSS66 VSS163
M15 AD19
VSS67 VSS164
M16 AD23
VSS68 VSS165
M17 AE2
VSS69 VSS166
M24 AE4
VSS70 VSS167
M27 AE8
VSS71 VSS168
M28 AE11
VSS72 VSS169
N1 AE13
VSS73 VSS170
N2 AE18
VSS74 VSS171
N5 AE21
VSS75 VSS172
N6 AE24
VSS76 VSS173
N11 AE25
VSS77 VSS174
N12 AF2
VSS78 VSS175
N13 AF4
VSS79 VSS176
N14 AF8
VSS80 VSS177
N15 AF11
VSS81 VSS178
N16 AF27
VSS82 VSS179
N17 AF28
VSS83 VSS180
N18 AG1
VSS84 VSS181
N24 AG3
VSS85 VSS182
N25 AG7
VSS86 VSS183
N26 AG11
VSS87 VSS184
P3 AG14
VSS88 VSS185
P4 AG17
VSS89 VSS186
P12 AG20
VSS90 VSS187
P13 AG25
VSS91 VSS188
P14 AH1
VSS92 VSS189
P15 AH3
VSS93 VSS190
P16 AH7
VSS94 VSS191
P17 AH12
VSS95 VSS192
P24 AH23
VSS96 VSS193
P27 AH27
VSS97 VSS194

ITL_ICH7_MBGA_652P

INVENTEC
TITLE
TIANSHAN
ICH7-5
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 42 OF 74
 +V3S
+V3AL
66-,63-,58-,57-,52-,48-,47-,46-,44-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-
66-,57-,47-,45-,38-,14-,7-,6-,5-,43-

1 C142 1 C141 1 C1099 1 C143 1 C1042 1 C1043 1 C114

2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V

U1005

11
67
81
94

30
38
47
45-

VCC1
VCC1
VCC1
VCC1

VCC2
VCC2
VCC2
SCAN_3S_OUT(11:0)
+V3AL
SCAN_3S_OUT(0) 17 99 7-
KSO0 OUT0 KBC_PW_ON 66-,57-,47-,45-,38-,14-,7-,6-,5-,43-
SCAN_3S_OUT(1) 16 KSO1 OUT1_IRQ8# 100 47-
+V3AL 15
BAT_GRNLED#
SCAN_3S_OUT(2) KSO2
SCAN_3S_OUT(3) 14 KSO3 OUT7_SMI# 98 6-
66-,57-,47-,45-,38-,14-,7-,6-,5-,43- 13
BATSELB 1
SCAN_3S_OUT(4) KSO4 OUT8_KBRST 97 TP684 38-
PM_3S_KBCCPURST# R1104

General Purpose I/O Interface

SCAN_3S_OUT(5) 12 KSO5 OUT9_PWM2 96 1 2 37-,30-
10
INV_PWM_3 8.2K_5%

Keyboard/Mouse Interface
1

SCAN_3S_OUT(6) KSO6 OUT10_PWM0 95 R170 OPEN 20-

PWM_3S_FAN#
SCAN_3S_OUT(7) 9 KSO7 OUT11_PWM1 93 6-,5-
R1099 SCAN_3S_OUT(8) 7
CHGCTRL_3 2
KSO8
100K_5% SCAN_3S_OUT(9) 6 62 66-,65-,60-
KSO9 GPIO2 PWR_SWIN#_3
SCAN_3S_OUT(10) 5 KSO10 GPIO3 63 39-
LOW_BAT#_3
2

SCAN_3S_OUT(11) 4 KSO11 GPIO4_KSO14 64

45- TP1 3 66 66-
SCAN_3S_IN(7:0) KSO12 GPIO5_KSO15 SCAN_3S_OUT(15)

SMSC_KBC1021_TQFP_100P_VAIL20
2 KSO13_GPIO18 1 2 39-,7-
1 2
RSMRST#
GPIO7_PWM3 68 R6010 0_5%
SCAN_3S_IN(0) 25 KSI0 GPIO8_RXD 69 R1103 10K_5%
SCAN_3S_IN(1) 24 KSI1 GPIO9_TXD 70
SCAN_3S_IN(2) 23 KSI2
SCAN_3S_IN(3) 22 KSI3
SCAN_3S_IN(4) 21 KSI4 GPIO11_AB2A_DATA 71 6- BATCON
SCAN_3S_IN(5) 20 KSI5 GPIO12_AB2A_CLK 72 14- ADP_PS1
SCAN_3S_IN(6) 19 KSI6 GPIO13_AB2B_DATA 73 58-,7-,6-,5- ADP_PRES
SCAN_3S_IN(7) 18 KSI7 GPIO14_AB2B_CLK 74 6- THM_TRAVEL# +V3AL
GPIO15_FAN_TACH1 75 58-,47-,40-
PCI_3S_SERR#
IM_5S_CLK 45- 26 IMCLK GPIO16_FAN_TACH2 76 6- 66-,57-,47-,45-,38-,14-,7-,6-,5-,43-
45- 27 77 38-
THM_MAIN# 1 R166 2
IM_5S_DATA IMDAT GPIO17_A20M
60- 29
EC_3S_A20GATE
KB_5S_CLK KCLK 100K_5%
KB_5S_DATA 60- 31 KDAT GPIO20_PS2CLK 78 LED_3_NUM#
60- 32 EMCLK 80 60-,58-,39-,13-,12- 66-,57-,43-
EM_5S_CLK GPIO21_PS2DAT SLP_S3#_3R
EM_5S_DATA 60- 33 EMDAT

Access Bus Interface

Power Mgmt
86 6- SDA_MAIN
63-,58-,47-,46-,39- AB1A_DATA
PCI_3S_CLKRUN# 44 CLKRUN# AB1A_CLK 87 6- SCL_MAIN

SIRQ
63-,47-,46-,39- 46 SER_IRQ
PCI_3S_SERIRQ
15-
1, 0.5 43 PCI_CLK 84 6- SDA_MBAY
CLK_R3S_KBPCI AB1B_DATA
40-,39- 59 EC_SCI# 85 6- SCL_MBAY
RUNSCI0#_3 AB1B_CLK
+V3AL 66-,57-,47-,45-,38-,14-,7-,6-,5-,43- 63- CLK_TPM
63-,57-,38-,46-
+V3AL
LPC_3S_AD(3:0)
LPC_3S_AD(3) 40 LAD3 56 50-
GPIO25 A_SD 66-,57-,47-,45-,38-,14-,7-,6-,5-,43-
LPC Bus

LPC_3S_AD(2) 39 LAD2 GPIO01

82 R1065 1 2 0_5%
1
LPC_3S_AD(1) 37 LAD1 83 R168 1 2 10K_5%
GPIO26
R1061 LPC_3S_AD(0) 35 48 R169 1 2 1K_1% 15-

Miscellaneous
LAD0 CLOCK CLK_R3S_KBC14
10K_5% 58 14-,43-
32KHZ_OUT
R1102 1 2 0_5% 39-,21-,11- ADP_EN
LPC_3S_FRAME# 63-,57-,46-,38- 41 LFRAME# 49 PM_PWROK
2 nRESET_OUT
NPCI_RESET# 46-,39- 42 LRESET# PWRGD
61 R126 1 2 0_5% 14-
1 R1062 2 PWR_GOOD_KBC 1 R1101 2 14-
ADP_EN 34 LPCPD# VCC1_PWRGD 60
VCC1_POR#_3
50 14- 1K_5%
14-,43- OPEN GPIO19 ADP_ID
1
GPIO24
57 R1100 1 2 10K_5% 50-,48-
GPIO27 A_EAPD
53 XTAL1 R1063 1 2 10K_5%
RTC

54 XTAL2 91 14-
X1000 nDMS_LED ADP_PS0
51 VCC0 BAT_LED# 88 47-
32.768KHZ_VAIL20 BAT_AMBERLED#
52 TEST_PIN 90 66-,60-,57-,47-
4 1 TP576 PWR_LED#_8051TX STBY_LED# +V3AL
89 66-,57-
55 AGND

FDD_LED#_8051RX LED_3_CAPS# 66-,57-,47-,45-,38-,14-,7-,6-,5-,43-

GND
GND
GND
GND
GND
GND
GND

3 2 CN1002
+V_RTC 1 1
8
92
79
65
45
36
28

1
41-,38- R1064 2 2
1 C1045 1 C1044 10K_5% 66-,57-,43- 3 3 G 7
LED_3_NUM# 4
2 15PF_50V 2 15PF_50V 2 4 G 8
5 5
6 6
1 C1046
2 0.1UF_16V MLX_67451_0006

INVENTEC
TITLE
TIANSHAN
KBC
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 26-May-2006 SHEET 43 OF 74
 +V3S
66-,63-,58-,57-,52-,48-,47-,46-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,44-

1
R287
10K_5%_OPEN +V3S
2 66-,63-,58-,57-,52-,48-,47-,46-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,44-

U32
ACCEL_INT 65-,40-,39- 6 3
RDY_INT Vdd
9 19
SDO Vdd 1 C313 1 C329
57-,39-,27-,26-,20-,15- 10
ICH_3S_SMDATA SDA_SDI_SDO
57-,39-,27-,26-,20-,15- 12 11
ICH_3S_SMCLK SCL_SPC Vdd_IO 2 10UF_6.3V_OPEN2 0.1UF_16V_OPEN
13
CS
16
CK
20
Reserved
1 18
NC Reserved
7 4
1 NC Reserved
8
R291 NC
14 2
10K_5%_OPEN 15
NC GND
5 1 C312
NC GND
21 17 2 0.1UF_16V_OPEN
2 NC GND
22
NC
23
NC
24 27
NC NC
25 28
NC NC
26
NC

ST_LIS3LV02DQ_QFN_28P_OPEN

HARDDRIVE PROTECTION

65-,64-,63-,60-,58-,41-,40-,39-,37-,16-,14-,13-,9-,7-,44-

+V3A

65-,64-,63-,60-,58-,41-,40-,39-,37-,16-,14-,13-,9-,7-,44-
U1013
+V3A SPI_CE# 39- 1 8
CE# VDD

39-
R372 1 2 47_5% 2 7
R370 1 2 3.3K_5%
SPI_SO SO HOLD#
R371 1 2 3.3K_5% 3 6 39-
WP# SCK SPI_CLK 1 C370
4 5 39- 2 0.1UF_16V
VSS SI SPI_SI
SST_25LF080A_SOP_8P

INVENTEC
TITLE
TIANSHAN
FWH/SPI/HDD PROTECTION
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 44 OF 74
 CN11 ROHM_UMP11_SSOP_6P
1 1
2 2 45- 43-,45-
3 KSCAN_3S_IN(4) SCAN_3S_IN(4)
3 4 3
SCAN_3S_OUT(9) 4 4
KSCAN_3S_IN(9) 66-,45- 5 5 66-,45-
66-,45- 6 KSCAN_3S_IN(12)
KSCAN_3S_IN(11) 6 5
66-,45- 7 43-,45- 45-
KSCAN_3S_IN(13) 7 SCAN_3S_IN(5) KSCAN_3S_IN(5)
SCAN_3S_IN(7) 43-,45- 8 8 6 2
KSCAN_3S_IN(6) 45- 9 9
KSCAN_3S_IN(5) 45- 10 10 66-,45-
SCAN_3S_OUT(1) 11 KSCAN_3S_IN(13)
11 1
SCAN_3S_OUT(10) 12 12
SCAN_3S_OUT(6) 13 13
SCAN_3S_OUT(7) 14 14
U8
SCAN_3S_OUT(4) 15 15
SCAN_3S_OUT(8) 16 16
SCAN_3S_OUT(3) 17 17
KSCAN_3S_IN(3) 45- 18 18
45- 19 19
KSCAN_3S_IN(1) ROHM_UMP11_SSOP_6P
KSCAN_3S_IN(2) 45- 20 20 45-
45- 21 KSCAN_3S_IN(6)
KSCAN_3S_IN(4) 21
KSCAN_3S_IN(0) 45- 22 22 45- 43-,45-
66-,45- 23 KSCAN_3S_IN(0) SCAN_3S_IN(0) 1
KSCAN_3S_IN(10) 23 4 3
KSCAN_3S_IN(12) 66-,45- 24 24
KSCAN_3S_IN(8) 66-,45- 25 25 66-,45- 3 43-,45-
45- 26 KSCAN_3S_IN(8) SCAN_3S_IN(6)
KSCAN_3S_IN(14) 26 5 D20
SCAN_3S_OUT(5) 27 27 43-,45- 45-
SCAN_3S_OUT(2) 28 SCAN_3S_IN(1) KSCAN_3S_IN(1) DAP202K
28 6 2 2
SCAN_3S_OUT(0) 29 29
SCAN_3S_OUT(11) 30 30 66-,45- 45-
KSCAN_3S_IN(9) KSCAN_3S_IN(14)
1
ACES_85203_30021_30P
U6
43-
SCAN_3S_OUT(11:0)

+V5S
60-,52-,51-,50-,48-,47-,46-,41-,39-,36-,20-,14-,13-,11-,10-,5-

1 R319 2
0_5%
+5VS_IM
C351 1
1 1
680PF_50V 2
R1261 R1260
+V3AL 4.7K_5% 4.7K_5%
2 2
66-,57-,47-,43-,38-,14-,7-,6-,5- (15/5) CN16
1 1
5 1 2 3 4 43- 2 2
IM_5S_DATA
IM_5S_CLK
43- 3
4
3 G 5 TOUCH PAD
RS1 4 G 6
ROHM_UMP11_SSOP_6P
47K_5%
JST_BM4B_SRSS
45- 43-,45-
7 8 9 6 10
KSCAN_3S_IN(2) SCAN_3S_IN(2)
4 3
66-,45-
KSCAN_3S_IN(10)
5
43-,45- 45-
SCAN_3S_IN(3) KSCAN_3S_IN(3)
6 2
66-,45-
KSCAN_3S_IN(11)
1
SCAN_3S_IN(0)
SCAN_3S_IN(1)
SCAN_3S_IN(2) U7
SCAN_3S_IN(3)
SCAN_3S_IN(4)
SCAN_3S_IN(5)
SCAN_3S_IN(6)
SCAN_3S_IN(7)

43-,45-
SCAN_3S_IN(7:0)
INVENTEC
TITLE
TIANSHAN
INT.KBC/POINT DEVICES
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 45 OF 74
 +V5S
60-,52-,51-,50-,48-,47-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-
CHENMKO_BAT54_3P D23
1 3
2 R48 1 2 R45 1

4.7K_5% 4.7K_5%
2 R46 1 2 R44 1
1 1 1 1
R51 R56 R58 R60 4.7K_5% 4.7K_5%
4.7K_5% 4.7K_5% 4.7K_5% 4.7K_5% 2 R49 1 2 R43 1
+V3S
2 1 2 1 2 1 2 4.7K_5% 4.7K_5%
R53 R57 R59 2 R47 1 2 R42 1 66-,63-,58-,57-,52-,48-,47-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,46-

4.7K_5% 4.7K_5% 4.7K_5%

4.7K_5% 4.7K_5%
2 2 2
60- LPT_5S_PD(7:4)
60- LPT_5S_PD(7)
LPT_5S_SLCT 60- 1 C199 1 C182 1 C198
LPT_5S_PE LPT_5S_PD(6)
60- LPT_5S_PD(5)
LPT_5S_BUSY 60-
2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V
LPT_5S_ACK# LPT_5S_PD(4)
60-
LPT_5S_ERROR#

66-,63-,58-,57-,52-,48-,47-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,46-
60-
LPT_5S_ALF#

66-,63-,58-,57-,52-,48-,47-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,46-
60-
LPT_5S_STRB#
UART_3S_RXD 60-
60-
UART_3S_TXD
60- +V3S
UART_3S_DSR#

1 1
R234 R233 +V3S
4.7K_5% 4.7K_5%

64
63
62
61
60
59
58
57
56
55
52
53
51
50
49
54
2 2

NDSR1
TXD1
RXD1
NSTROBE
NALF
NERROR
NACK
BUSY
PE
SLCT
VSS
PD7
PD6
PD5
PD4
VCC
66-,63-,58-,57-,52-,48-,47-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,46-

UART_3S_RTS# 60- 1 45 60- LPT_5S_PD(3:0)

NRTS1 VCC
+V3S UART_3S_CTS 60- 2 48 LPT_5S_PD(3)
NCTS1 PD3
UART_3S_DTR# 60- 3
NDTR1 PD2
47 LPT_5S_PD(2)
UART_3S_RI 60- 4
NRI1 PD1
46 LPT_5S_PD(1)
UART_3S_DCD# 60- 5 44 LPT_5S_PD(0)
NCDCD1 PD0
TP620 6 42 60-
IO_PME# NSLCTIN
60- LPT_5S_SLCTIN#
7
VTR U27 NINIT
41
LPT_5S_INIT#
8 SMSC_LPC47N217_JV_STQFP_64P GP23 40 60- EXPCRD_RST#
VSS
LPC_3S_AD(3:0) 63-,57-,38-,43- CLK_R3S_SIO14 15- 9 43
CLOCKI VSS
LPC_3S_AD(0) 10
VAD0 IRMODE_IRRX3
39
1 1
11 38
LPC_3S_AD(1) 12
VCC IRTX2
37
R1179 R1178
LPC_3S_AD(2) 13
LAD1 IRRX2
36 46- 10K_5% OPEN
LAD2 GP14_IRQIN2
46- GP14_IRQIN2
LPC_3S_AD(3) 14
LAD3 GP13_IRQIN1
35
GP13_IRQIN1 2 2
63-,57-,43-,38- 15 PCI_RESET# 34 1 R250 2
LPC_3S_FRAME# LFRAME# GP12_IO_SMI# 46-
CLKRUN#
38- 16 33

SER_IRQ
LPC_3S_DRQ0#
PCI_CLK
LDRQ#
LPCPD#
GP11_SYSOPT SYSOPT 47K_5%
+V3S

GP40
GP41
GP42
GP43
GP44
GP45
GP46
GP47
GP10
VCC
VSS
66-,63-,58-,57-,52-,48-,47-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,46-
17
18
19
20
21
26
22
23
24
25
27
28
29
30
31
32
63-,58-,47-,43-,39-

R231
63-,47-,43-,39-

1 2 46-
43-,39- 2 R254 GP14_IRQIN2
1
NPCI_RESET# 10K_5%
46- GP10
0_5%
1 R253 2 46-
15-

46-

46-
46-
46-
46-

63-,57-,52-,40-,39- 2 R235 1
AUDIO_SHUTDOWN
1, 0.5 60- SER_SHD
BUF_PLT_RST# 10K_5%
OPEN
PCI_3S_CLKRUN#

PCI_3S_SERIRQ

AUDIO_SHUTDOWN

GP43
GP44
GP45
GP46
CLK_R3S_SIOPCI

+V3S
66-,63-,58-,57-,52-,48-,47-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,46-

46- RS2
3 10
R255 GP10 46- 2
2 1 9 46-
SYSOPT 46- GP43
4 6
GP46
1

10K_5% 46- 8 7 46-

GP44 GP45
R251 +V3S 5 1
47K_5%
66-,63-,58-,57-,52-,48-,47-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,46-
10K_5%
2
1

66-,63-,58-,57-,52-,48-,47-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,46-

+V3S +V3S
R252 66-,63-,58-,57-,52-,48-,47-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,46-
2

47K_5%

GP13_IRQIN1
46- 2

10K_5%
R232 1
+V3S INVENTEC
66-,63-,58-,57-,52-,48-,47-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,46- TITLE
TIANSHAN
SUPER I/O
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 46 OF 74
 +V5S
+V3S
60-,52-,51-,50-,48-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-
66-,63-,58-,57-,52-,48-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5- CN22
1 2
+V3AL
3 4 66-,57-,45-,43-,38-,14-,7-,6-,5-
5 6
7 8
CLK_R3S_CBPCI 15-
1, 0.5 9 10 15-
CLK_R3S_CARD48
11 12
58-,40- 13 14 40-
PCI_3S_CBE#(3) PCI_3S_INTC#
58-,40- 15 16 40-
PCI_3S_CBE#(2) PCI_3S_INTD#
58-,40- 17 18 40-
PCI_3S_CBE#(1) PCI_3S_INTG#
58-,40- 19 20 40-
PCI_3S_CBE#(0) PCI_3S_REQ#(2)
58-,40- 21 22 40-
PCI_3S_RST# 63-,46-,43-,39-
PCI_3S_GNT#(2)
58-,40- 23 24
PCI_3S_PERR# PCI_3S_SERIRQ
58-,40- 25 26 63-,58-,46-,43-,39-
PCI_3S_PAR PCI_3S_CLKRUN#
58-,40- 27 28 48-
PCI_3S_FRAME# A_3S_PCSPKR
29 30
58-,40- 31 32 58-,40-
PCI_3S_TRDY# PCI_3S_AD(30)
58-,40- 33 34 58-,40-
PCI_3S_IRDY# PCI_3S_AD(28)
PCI_3S_STOP# 58-,40- 35 36 58-,40- PCI_3S_AD(26)
58-,40- 37 38 58-,40-
PCI_3S_DEVSEL# 58-,40-
PCI_3S_AD(24)
39 40 58-,40- PCI_3S_AD(22)
PCI_3S_PME# 58-,43-,40- 41 42 58-,40-
PCI_3S_SERR# PCI_3S_AD(20)
60-,53-,39-,12-,8- 43 44 58-,40-
SLP_S5#_3R PCI_3S_AD(18)
45 46 58-,40- PCI_3S_AD(16)
47 48
58-,40- 49 50 58-,40-
PCI_3S_AD(31) PCI_3S_AD(14)
58-,40- 51 52 58-,40-
PCI_3S_AD(29) PCI_3S_AD(12)
58-,40- 53 54 58-,40-
PCI_3S_AD(27) PCI_3S_AD(10)
58-,40- 55 56 58-,40-
PCI_3S_AD(25) PCI_3S_AD(8)
58-,40- 57 58 58-,40-
PCI_3S_AD(23) PCI_3S_AD(6)
58-,40- 59 60 58-,40-
PCI_3S_AD(21) PCI_3S_AD(4)
58-,40- 61 62 58-,40-
PCI_3S_AD(19) PCI_3S_AD(2)
58-,40- 63 64 58-,40-
PCI_3S_AD(17) PCI_3S_AD(0)
65 66
58-,40- 67 68 64-
PCI_3S_AD(15) 57- LED_BLUETOOTH
58-,40- 69 70
PCI_3S_AD(13) 66-,65- LED_WLAN_LINK#
58-,40- 71 72
PCI_3S_AD(11) WLN_BT_LED#
58-,40- 73 74 66-,60-,57-,43-
PCI_3S_AD(9) 52- STBY_LED#
58-,40- 75 76
PCI_3S_AD(7) 38- MBDASP#_5
58-,40- 77 78
PCI_3S_AD(5) LED_3S_SATA#
58-,40- 79 80 39-
PCI_3S_AD(3) 43- HDD_HALTED
PCI_3S_AD(1) 58-,40- 81 82
83 84 43- BAT_AMBERLED#
38- 85 86
BAT_GRNLED#
AC97_3S_SDOUT_MDC
AC97_3S_SYNC_MDC 38- 87 88 38- AC97_3S_RST#_MDC
AC97_3S_SDIN1 38- 89 90 38- AC97_3S_BITCLK_MDC
G1 G2
G3 G4
G5 G6

ACES_88034_907N_90P

INVENTEC
TITLE
TIANSHAN
DAUGHTER BOARD CONN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 47 OF 74
 +V5A
53-,41-,37-,36-,14-,13-,12-,9-,8-,7-
66-,63-,58-,57-,52-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-

+V3S AVDD AUDIO_VCC 1 C18 1 1 C20

C19
48- 50-,49-,48- 2100PF_50V 10UF_6.3V 2 1UF_16V
(20/5)
1 L43 2 1 L44 2
BLM11A121S BLM11A121S 60-,52-,51-,50-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-

U3
1 C40 1
C112 IN +V5S
10UF_6.3V 5
1 1 C111 1 C109 1 C39 1 C73 OUT
1 GND 2
2 0.1UF_16V_OPEN 2 0.1UF_16V_OPEN 2 0.1UF_16V 2 0.1UF_16V 4
10UF_6.3V C37 BYP
3 1 R1 2
0.1UF_16V 2 SHDN
1 C38 10K_5%
AUDIO_VCC GMT_G916_475T1Uf_SOT23_5P
2
50-,49-,48- 0.01UF_16V
1
1 R30 2
R110
10K_5% 0_5%

Q33 3
D

A_3S_PCSPKR
47- 1G
S

SSM3K7002F 2 U11

25
38
1
9
C110

DVDD
DVDD

AVDD
AVDD
AUDIO_VCC 2 1 2 R115 1 27
VREF_FILT
50-,49-,48- OPEN OPEN
AC97_3S_SDOUT 38- 5 39 49- HP_OUT_L
SDATA_OUT PORT_A_L
1
38- 6 41 49- 1 C41 1 C42
R107 AC97_3S_BITCLK 1 2
BIT_CLK PORT_A_R
C70 1 2 1UF_10V 49-
HP_OUT_R
10K_5% AC97_3S_SDIN0 38- 8
SDATA_IN PORT_B_L
21
C69 1 2 1UF_10V
A_MIC1 2 OPEN 2 0.1UF_16V
38- R114 39_5% 10 22 49-
AC97_3S_SYNC SYNC PORT_B_R A_MIC2
AC97_3S_RST# 38- 11 28
2 RESET# MIC_BIAS_B

50-,48- 1 2 43 16 C103 1 2 1UF_10V 49-

HPSENSE 1 2
GPIO_0_JS_1 PORT_F_L
C104 1 2 1UF_10V INT_MIC
R1047 OPEN 44
GPIO_1_JS_0 PORT_F_R
17
R1046 OPEN 1 2 2 30
GPIO_2 MIC_BIAS_F
60-,39- 1 2 R117 10K_5% 3
ISO_PREP# GPIO_3
C71 1UF_16V 1 R81 2
R116 OPEN 23 60- A_LINEINL
PORT_C_L
31 24 C72 1UF_16V 1 2
Q28 3 C106 NC PORT_C_R 4.7K_5%
33 29 1 2
D
R113 NC MIC_BIAS_C AUDIO_VCC
A_3S_ICHSPKR 39- 1G 2 1 2 1 40
NC 1
45 35 50- LINE_OUT_L 50-,49-,48-
0.1UF_16V 150K_1%
S NC PORT_D_L
R80
SSM3K7002F 2
46 36 50- LINE_OUT_R
NC PORT_D_R

2
C107 C108 32 4.7K_5%
MIC_BIAS_D
2 1 2 R112 1 18 R31
CD_L 2
2 1 19 14 100K_5%
0.1UF_16V 100K_1% 1
0.1UF_16V 20
CD_GND PORT_E_L
15 3D Q11
CD_R PORT_E_R

1
R111 1C105 AVDD G 1

10K_5% 2 0.01UF_16V 12
PCBEEP MONO_OUT
37
R37 48- S
47 13 1 2 2 SSM3K7002F
2 EAPD SENSE_A_SRC_B R79
48 34 1 2 1 2 60-
S_PDIF_OUT SENSE_B_SRC_A AVDD 2.67K_1% A_LINEINR
50-,48-
DVSS
DVSS

AVSS
AVSS

1 R36 2
R83 1 R34 2
HPSENSE 4.7K_5%
2.2K_1% 48-
1 OPEN 1 39.2K_1% 1
26
42
4
7

AD_1981HD_LQFP_48P R38 R82 1 R32 2 R78

OPEN OPEN 4.7K_5%
50-,43-
20K_1% AVDD
A_EAPD 2 2 2
1 R33 2
48-
10K_1% 1 AUDIO_VCC
Q12 R14
C43 50-,49-,48-
1 SSM3K7002F OPEN
LAYOUT NOTES 1 : R30 MUST BE PLACE ACROSS DIGITAL AND ANALOG GROUND. 3D 1
LAYOUT NOTES 2 : R30 IS NEEDED TO PLACE RIGHT AT CODEC 2 OPEN 2
1 60- R13
G
LINE_IN_SENSE 3 D Q4 47K_5%
S
2 1 C44 1 49-
G
2 MIC_SENSE
1 2 0.1UF_16V S
2 SSM3K7002F C21
R35 1
100K_5% 0.1UF_16V
2
2

INVENTEC
TITLE
TIANSHAN
AZALIA CODEC
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 48 OF 74
 C28 100PF_50V
1 2
AUDIO_VREF 1 R20 2
49- AUDIO_VCC 100K_5%
C31 150PF_50V LAYOUT NOTES : C30 CLOSE TO U4097 PIN_6
50-,48-,49-
1 2 C30 1
L4083~L4085 WILL BE CHANGE TO 100NH
R23 100PF_50V 2
1 2 4
10 + U2
100K_5% C24 8 48-
AUDIO_VREF AUDIO_VCC 49- 1 R500 2 1 R21 2 9 - OUT A_MIC1
EXT_MIC1 MAX4492AUD
LAYOUT NOTES: C33 CLOSE TO U4097-PIN2 49- 50-,48-,49- 1 2 0_5% 10K_5%
0.22UF_10V 11
L6 WILL BE CHANGE TO 100NH
1 C1010
1 C33 1 C27
49- 2 0.1UF_16V
INT_MIC_CN 2 100PF_50V 2 68PF_50V
AUDIO_VCC 4 C26 100PF_50V
3 + U2 1 2
50-,48-,49-
1 ANAGND 48-
R27 R28 C36 1 R501 R26 OUT INT_MIC R19
1 2 1 2 2 1 2 2 - 1 2
MAX4492AUD
3K_5% 3K_5% 1 2 0_5% 10K_5%
0.22UF_16V 11 AUDIO_VREF 100K_5%
1 C68 1 C35
49-
2 4.7UF_6.3V 2 68PF_50V AUDIO_VCC
50-,48-,49-
C29 1
100PF_50V 2
4
0.22UF_10V 12 + U2
14 48-
49- C59 1 R502 2 2 R72 1 13 - OUT A_MIC2
EXT_MIC2 MAX4492AUD
1 2 0_5% 10K_5% 11
AUDIO_VCC
L9 WILL BE CHANGE TO 100NH LAYOUT NOTES : C29 CLOSE TO U4097 PIN_9
50-,48-,49- AUDIO_VCC
1
50-,48-,49-
R25 1 C61
47K_5% 2 68PF_50V
AUDIO_VCC 4
2 U2
50-,48-,49-
5 +
7 MAX4492AUD AUDIO_VREF
1
6 - OUT 1 R22 2
49-
1 1 R24 1 C34
R73 R18 47K_5% 11 100_5%
470_5% 470_5% 2 10UF_6.3V 1 C32
2
2 2 2 4.7UF_6.3V

1 C60 1 1 1 C58 1 C25

R71 R17 CN5
2 10UF_6.3V 3.9K_1% 3.9K_1% 2 470PF_50V 2 10UF_6.3V
2 2 1 1 49- INT_MIC_CN
2 2
KNOWLES_MB6022APB_1_2P
1
C23
2 470PF_50V

L4 1 JACK3
49-
BLM21A121S
EXT_MIC1 1 2 2
49- 1 2 6
EXT_MIC2
L10 3
BLM21A121S 4
48- 5
MIC_SENSE
AMP_1720003_1_6P EARPHONE

PR_AOUTL 60-,50-
L2
BLM11A121S
48- C15 100UF_6.3V 1 2 1 2 1 JACK2
HP_OUT_L
1 R3 16_1% L3 2
BLM11A121S 6
48- C22 100UF_6.3V 1 2 1 2 3
HP_OUT_R 60-
PR_AOUTR 1 4
R7 16_1% 5
C9 1 C101 AMP_1720003_1_6P
C6007 0.1UF_16V 1 1
R8 R9 2 2
1 2 470PF_50V 470PF_50V
1K_5% 1K_5%
C6005 0.1UF_16V
2 2
1 2
LOCATE AT JACK
C6004 0.1UF_16V
1 2
C57 0.1UF_16V
1 2

INVENTEC
TITLE
TIANSHAN
EQ&MIC JACK
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 49 OF 74
 +V5S
U5 60-,52-,51-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-,50-
C63 0.047UF_10V
LINE_OUT_L
48- 5 LIN- VDD 16
2 1 9 LIN+
1 2 PVDD 15
C65 0.47UF_6.3V PVDD 6
C67 10UF_6.3V_OPEN19 1 C1016 1 C100 1 C97 1 C102 1 C99
SHUTDOWN#
10 BYPASS 2 0.1UF_16V 2 1000PF_50V 2 0.1UF_16V2 4.7UF_6.3V 2 4.7UF_6.3V
LOUT- 8
1 2 50-
C66 0.47UF_6.3V SPK_OUT_L-
17 RIN- LOUT+ 4 50-
SPK_OUT_L+
1 2
C96 0.047UF_10V
LINE_OUT_R 48- 7 RIN+ ROUT- 14 50- SPK_OUT_R-
1 2 ROUT+ 18 50- SPK_OUT_R+
2 1 20
2 GAIN0 GND 13
C101 0.47UF_6.3V GND 11
3 GAIN1 GND
60-,52-,51-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-,50- 12 NC 1
3 1 GND 21
D
R29 +V5S GND
1G R74
OPEN TI_TPA6017A2_PWP_20P
1 OPEN 2
S
Q60 2 2
SSM3K7002F_OPEN

66- 1 R2 2 60-,52-,51-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-,50-
MUTE#
0_5% +V5S
R77
63-,39- 1 R106 2 1 0_5% 2
SUS_STAT#
47K_5% 1 1
R75 R76
3 0_5% OPEN
D
43- 1G Q27
A_SD SSM3K7002F 2 2
S
2 R105
1 OPEN 2

D
3
48-,43- 1G Q14
A_EAPD
S SSM3K7002F
2

INTERNAL SPEAKER AUDIO_VCC

49-,48-,50-

(LEFT) CN17 2
50- 1 1
SPK_OUT_L- 50- 2
SPK_OUT_L+ 2 R12
3 3 G 5
4 100K_5%
4 G 6 1
1 C64 1 C62
2 100PF_50V 2 100PF_50V JST_BM4B_SRSS

PR_HPSENSE# 60- 48- HPSENSE

1 C17
2 OPEN

AUDIO_VCC
3
49-,48-,50- D
1G Q3
2 SSM3K7002F
(RIGHT) S
2
50- R10
SPK_OUT_R- 50-
SPK_OUT_R+ 100K_5%
1
D
3
1 C98 1 C95 60-,49- 1 R11 2 1G Q2
PR_AOUTL
2 100PF_50V 2 100PF_50V 100K_5% S SSM3K7002F
1 C16 2
2 2.2UF_6.3V

INVENTEC
TITLE
TIANSHAN
AUDIO AMP & HP JACK
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 50 OF 74
 CN19
1
GND
SATA_C_TXP0 38- 2
A+
SATA_C_TXN0 38- 3
A-
4
38-
C1305 3300PF_50V SATA_RXN0 5
GND
SATA_C_RXN0 SATA_RXP0 B-
SATA_C_RXP0 38- 1 2 6
B+
C1304 1 2 3300PF_50V 7
GND
8
CLOSE TO SATA CONN 9
V3.3
V3.3
+V5S 10
V3.3
11
GND
60-,52-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5- 12
GND
13
GND
14
V5
15
V5
16
V5
17
GND
18
RESERVED
19
GND
20
V12
21 G1
V12 G
22 G2
V12 G

SYN_10_0739_LN05_22P

INVENTEC
TITLE
TIANSHAN
HDD CONN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 51 OF 74
 CN18
1
R379 1
63-,57-,46-,40-,39- 1 2 2
BUF_PLT_RST# 2
3
0_5% 3
4
4
38- 5
PIDE_3S_D(15:0) 5
PIDE_3S_D(8) 6
6
PIDE_3S_D(7) 7
7
PIDE_3S_D(9) 8
8
PIDE_3S_D(6) 9
9
PIDE_3S_D(10) 10
10
PIDE_3S_D(5) 11
11
PIDE_3S_D(11) 12
12
PIDE_3S_D(4) 13
13
PIDE_3S_D(12) 14
14
PIDE_3S_D(3) 15
66-,63-,58-,57-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5- 15
PIDE_3S_D(13) 16 16
+V3S PIDE_3S_D(2) 17
17
PIDE_3S_D(14) 18
18
PIDE_3S_D(1) 19 19
PIDE_3S_D(15) 20
20
PIDE_3S_D(0) 21
1 21
38- 22
1 R1295 PIDE_3S_DREQ 22
23
4.7K_5% 23
R1294 38- 24
PIDE_3S_IOR# 24
10K_5% 38- 25
2 PIDE_3S_IOW# 25
26
2 26
38- 27
PIDE_3S_IORDY 27
38- 28
PIDE_3S_DACK# 28
+V5S 38- 29
29
PIDE_3S_IRQ
30
30
60-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-,52- PIDE_3S_A(1) 38- 31
31
32
1 32
PIDE_3S_A(0) 38- 33 33
R6006 38- 34
10K_5% PIDE_3S_A(2) 38- 34
35
PIDE_3S_CS#(0) 38- 35
2 36 36
47-
PIDE_3S_CS#(1)
MBDASP#_5 37
37
+V5S 38
38
39 39
60-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-,52- 40
40
(20/5) 41
41
42
42
43
43
44
44
45
1 C1277 1 C1276 1 45
C371 46
46
47UF_6.3V 47 G1
2 0.1UF_16V 2 0.1UF_16V 47 G
48 G2
48 G
49
49
50
50

1
R340 SYN_800032MR050S1XXZU_50P
0_5%
2

INVENTEC
TITLE
TIANSHAN
ODD CONN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 52 OF 74
 +V5A
48-,41-,37-,36-,14-,13-,12-,9-,8-,7-,53- USB_5_VCC1
53-

(20/5)
U1012
(20/5) 1 8
GND OUT
2 7
1 C1193 IN OUT

3 6 1
2 0.01UF_50V IN OUT C1212
R1185 0.1UF_16V 2
1
60-,47-,39-,12-,8-,53- 2 4 5
SLP_S5#_3R EN OC#
0_5%
GMT_G548B1P8U_MSOP_8P USB_5_VCC1
53-

C1210
1 C1211 1 C1233 1
NOTES: 2 0.1UF_16V 2
L2000,L1008,L30(Option for EMI test) 1000PF_50V 100UF_6.3V
Install Chock (Default)
Install 0 ohm

L30
39- 1 2 USB_L_P5-
USB_P5-

39- 4 3 USB_L_P5+
USB_P5+
WCM_2012_900T
CN15
Close to USB CON 1
1
2
2
3
3
4
4
5 G1
5 G
6 G2
6 G
L1008 7 7 G G3
39- 1 2 USB_L_P4- 8 G4
USB_P4- 8 G

TYCO_25_126A_8P
39- 4 3 USB_L_P4+
USB_P4+
WCM_2012_900T
Close to USB CON

USB_5_VCC2
53-
USB_5_VCC2
53-
PAD2000
1
1 C2000 1 C2001 1 C2002

+V5A 47UF_6.3V 2 0.1UF_16V 2 1UF_10V

53- CN2000
USB_P3+_UDB 2
1
48-,41-,37-,36-,14-,13-,12-,9-,8-,7-,53-
CN21 VCC
U40 2 D-
(20/5) 1
D+ G G1
1 8 1 53- USB_G USB_G USB_G 3
GND OUT 2 USB_P3-_UDB 3
4 G2
USB_P3+ 39- 2 G G
(20/5) 2 7 39- 3 3 G 5
IN OUT USB_P3- 4 4 G 6 4 SYN_020133MR004S524ZL_4P
3 6
IN OUT
JST_BM4B_SRSS PAD5.55X4.3_4P
C383 1 60-,47-,39-,12-,8-,53-
1 R430 2 4 5
SLP_S5#_3R EN OC#
0.1UF_16V 2 0_5% USB_G S48 USB_G
GMT_G548B1P8U_MSOP_8P
USB_G SCREW2.8_6_5P

L2000
53- 4 3 USB_L_P3-
USB_P3-_UDB

53- 1 2 USB_L_P3+
USB_P3+_UDB
WCM_2012_900T
USB_G
Close to USB CON

USB DAUGHTER BOARD INVENTEC

TITLE
TIANSHAN
USB CONN/USB(DB)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 53 OF 74
BLANK

INVENTEC
TITLE
TIANSHAN
BLANK
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 54 OF 74
BLANK

INVENTEC
TITLE
TIANSHAN
BLANK
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 55 OF 74
BLANK

INVENTEC
TITLE
TIANSHAN
BLANK
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 56 OF 74
 +V3S +V1.5S
66-,63-,58-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5- 41-,39-,25-,24-,21-,18-,10-,8-

1 C1050 1 C113 1 C1009 1 C1049 1 C45 1 C1014

2 0.1UF_16V 22UF_4V 2 0.1UF_16V 2 0.1UF_16V 22UF_4V 2 0.1UF_16V

CN10
PCIE_WAKE# 39- 1 2
WAKE# 3.3V
WLAN_PRIORITY 64- 3
CH_DATA GND
4 Place resister as close to LPC signal as possible to minimize stub length for LPC bus
BT_PRIORITY 64- 5
CH_CLK 1.5V
6
0_5%
(will be NI for FCS)
CLK_R_REQD# 15- 7
CLKREQ# LPC_FRAME#
8 R1027 1 2 63-,46-,43-,38- LPC_3S_FRAME#
9 10 R1026 1 2 0_5% 63-,46-,43-,38- LPC_3S_AD(3)
GND LPC_AD3
CLK_R_PCIE_MINI1# 15- 11 12 R1030 1 2 0_5% 63-,46-,43-,38- LPC_3S_AD(2)
REFCLK- LPC_AD2
CLK_R_PCIE_MINI1 15- 13
REFCLK+ LPC_AD1
14 R1029 1 2 0_5% 63-,46-,43-,38- LPC_3S_AD(1)
15
LPC_AD0
16 R1028 1 2 0_5% 63-,46-,43-,38- LPC_3S_AD(0)
63-,52-,46-,40-,39-,57- R10251 2 0_5% 17
GND
18
+V3_LAN
BUF_PLT_RST# LPC_DEBUG_RST# GND
CLK_R3S_LPCPCI 15- 19 20 39- XMIT_OFF# 59-,58-
LPC_PCI_CLK W_DISABLE#
21 22 R1031 1 2 0_5%
GND PERST# BUF_PLT_RST#
39- 23 24 63-,52-,46-,40-,39-,57-
PCIE_C_RXN2 PERn0 +3.3Vaux
PCIE_C_RXP2 39- 25 26
PERp0 GND
27 28 C1015
29
GND 1.5V
30 44-,39-,27-,26-,20-,15- 1 C1013 1
GND SMB_CLK ICH_3S_SMCLK
PCIE_C_TXN2 39- 31 32 44-,39-,27-,26-,20-,15- ICH_3S_SMDATA 2 0.1UF_16V 22UF_4V
PETn0 SMB_DATA
PCIE_C_TXP2 39- 33 34
35
PETp0 GND
36 USB_R_P2- 1 R1043 2 OPEN 39- USB_P2-
GND USB_D-
37
USB_D+
38 USB_R_P2+1 2 OPEN 39- USB_P2+
Reserved
39 40
41
Reserved GND
42
R1045
+V3AL Reserved LED_WWAN#
66-,47-,45-,43-,38-,14-,7-,6-,5- 43 44 R1044 1 2 0_5% 47- LED_WLAN_LINK#
Reserved LED_WLAN#
R123 1 2 0_5% 45
+V3AL LED_WPAN#
46
STBY_LED# 66-,60-,47-,43- R121 1 2 0_5% 47 48
PWR_LED# 1.5V
LED_3_NUM# 66-,43- R120 1 2 0_5% 49 50
NUM_LED# GND
LED_3_CAPS# 66-,43- R122 1 2 0_5% 51
CAPS_LED# 3.3V
52
G1 G2
G G

FOX_AS0B226_S68N_7N_52P

INVENTEC
TITLE
TIANSHAN
MINICARD CONN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 57 OF 74
 +V3S
1 66-,63-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-

PCI_3S_AD(0:31) 47-,40-,58- U37 R427

PCI_3S_AD(0) N7 A7 0_5%
M7 AD00 VDDIO_PCI10 E1
PCI_3S_AD(1) AD01 VDDIO_PCI01 2
PCI_3S_AD(2) P6 AD02 VDDIO_PCI03 P2
PCI_3S_AD(3) P5 G1 1 C1320 1 C1313 1 C377 1 C378 1 C1312 1 C1311 1 C1319 1 C380
N5 AD03 VDDIO_PCI02 C5
PCI_3S_AD(4) AD04 VDDIO_PCI07 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 10UF_6.3V
PCI_3S_AD(5) M5 AD05 VDDIO_PCI08 N6
PCI_3S_AD(6) P4 AD06 VDDIO_PCI09 E4
PCI_3S_AD(7) N4 B3
AD07 VDDIO_PCI04 +V3_LAN
PCI_3S_AD(8) P3 AD08 VDDIO_PCI05 K3
PCI_3S_AD(9) N3 AD09 VDDIO_PCI06 L4 59-,57-,58-
PCI_3S_AD(10) N2 AD10
PCI_3S_AD(11) M1 AD11 VDDIO_01 A11
PCI_3S_AD(12) M2 F11 1 C1332 1 C1345 1 C1337 1 C1330 1 C386
AD12 VDDIO_02
PCI_3S_AD(13) M3 AD13 VDDIO_03 K12 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 10UF_6.3V
PCI_3S_AD(14) L1 AD14 VDDIO_04 L12
+V3_LAN
PCI_3S_AD(15) L2
AD15
PCI_3S_AD(16) K1 AD16 59-,57-,58-
PCI_3S_AD(17) E3 AD17
PCI_3S_AD(18) D1
AD18 3
PCI_3S_AD(19) D2 B11 1 C382 1 C1346
AD19 REGSUP25 C11 1 E
Q58
PCI_3S_AD(20) D3 AD20 REGCTL25 C10 B
2 10UF_6.3V 2 0.1UF_16V
PCI_3S_AD(21) C1 BCP69
AD21 REGSEN25 C C
PCI_3S_AD(22) B1 AD22 4 2 +V3_LAN +V3_LAN
PCI_3S_AD(23) B2 +V2.5_3.3_LAN
B4 AD23
PCI_3S_AD(24) AD24 1 59-,57-,58- 59-,57-,58-
PCI_3S_AD(25) A5 AD25
PCI_3S_AD(26) B5 Q59 R426
B6 AD26 B9 3 BCP69 1 C392 1 C1339 0_5%
PCI_3S_AD(27) AD27 REGSUP12 B10
PCI_3S_AD(28) C6 1 E +V1.2_1.8_LAN 1 C1309
AD28 REGCTL12
B
2 10UF_6.3V 2 0.1UF_16V 2
PCI_3S_AD(29) C7 AD29 REGSEN12 A9 C C
0.1UF_16V 2 0.1UF_16V
PCI_3S_AD(30) A8 AD30 4 2
PCI_3S_AD(31) B8 1 C1318
AD31 1 C393 1 C1343 1
2 R1327
PCI_3S_CBE#(0:3) 47-,40-
VESD_1 P1 2 10UF_6.3V 2 0.1UF_16V 1 1 1K_5%
PCI_3S_CBE#(0) M4 CBE0# VESD_2 G2
PCI_3S_CBE#(1) L3 A1 R1328 R1326
CBE1# VESD_3 1K_5% 1K_5% 2
U1014
PCI_3S_CBE#(2) F3 CBE2#
PCI_3S_CBE#(3) C4 CBE3# 2 2
8 VCC A0 1
P10 7 2
47-,40- J1 PAR EEDATA M10 6 WP A1 3
PCI_3S_PAR EECLK SCL A2
5 SDA GND 4
47-,40-,58- 1 R424 2 100_5% A4 H12
PCI_3S_AD(30)
CLK_R3S_LANPCI 15-
1, 0.5 A3 IDSEL
PCI_CLK
GPIO0 K13
GPIO1 J13 ATM_AT24C64A_SOIC_8P
GPIO2
PCI_3S_INTA# 40- H2 INTA#
PCI_3S_RST# 47-,40- C2 PCI_RST# NC_01 L14
PCI_3S_GNT#(0) 40- J3 GNT# NC_02 J11
C3 R432
NC_03 L11
40- 1 2
PCI_3S_REQ#(0) REQ#
PCI_3S_FRAME# 47-,40- F2 FRAME# OPEN
PCI_3S_IRDY# 47-,40- F1 IRDY#
PCI_3S_TRDY# 47-,40- G3 TRDY# P7
+V3_LAN 47-,40- H3 NC M6
PCI_3S_DEVSEL# DEVSEL# VSS
59-,57-,58- PCI_3S_STOP# 47-,40- H1 STOP#
PCI_3S_PERR# 47-,40- J2 PERR#
PCI_3S_SERR# 47-,43-,40- A2
SERR# C12
TCK B12
A10 TDO A12
C9 NC TMS D11 1 R1342 2
NC TRST# 65-,64-,63-,60-,44-,41-,40-,39-,37-,16-,14-,13-,9-,7-,58-
TDI D12 4.7K_5%
1 R1333 2 J12 +V3A +V3_LAN
4.7K_5% F4 VAUX_PRSNT N1 59-,57-,58-
A6 M66EN
PME#
VSS_01
VSS_02 E2
1 R425 2 F8 1 R1322 2
VSS_21 D8
OPEN VSS_19 OPEN
Q1043 2 VSS_22 G8
PCI_3S_PME# 47-,40-
VSS_20 E8
Q1041
D

3 SSM3K7002F VSS_23 D9
CHENMKO_BAT54_3P E9 4 S D 1
VSS_24 2 1
G

1 F9
D1023 VSS_25 D4 5 1 C1307 1 C1308 1 C381 R1325
3 1 VSS_04 K2 3 6 100_5%
VSS_03 G 2 0.1UF_16V2 0.1UF_16V2 10UF_6.3V
58- 1 R1331 2 G6
LAN_ON_3 VSS_13 FDC638P 2
1M_5% 1 C1321 VSS_14 L6
D7
VSS_15 G4
2 3300PF_50V VSS_05
VSS_06 D5 1
E5
VSS_07 F5 R1324
VSS_08 G5 +V3A 220K_5%
VSS_09 D6
VSS_10 5 65-,64-,63-,60-,44-,41-,40-,39-,37-,16-,14-,13-,9-,7-,58-
2
E6 SLP_S3#_3R 60-,43-,39-,13-,12- 1 U1016 Q1038 3
VSS_11 F6 4 1 5 U1015
VSS_12 G7 R1329 2 2 1G
D

VSS_18 ADP_PRES 43-,7-,6-,5- 1 4

E7 220K_5% TC7S32F 2
VSS_16 F7 3 NC7SZ00M5
S

VSS_17 3 SSM3K7002F 2

G11
NC E10
NC E11
J4 NC H11 58-
NC_04 NC LAN_ON_3
63-,47-,46-,43-,39- H4 +V2.5_3.3_LAN
PCI_3S_CLKRUN# CLK_RUN# P11
K4 VDDP_01 L13
NC_06 VDDP_02 K14 1 C1334 1 C1326 1 C1324
L7
NC_07
VDDP_03
2 0.01UF_16V 2 0.01UF_16V 2 0.1UF_16V INVENTEC
TITLE
BCM_BCM5788_FBGA_196P TIANSHAN
LAN INTERFACE-1
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 58 OF 74
 +V3_LAN +V3_LAN
58-,57-,59- R1005 2 58-,57-,59-
+V1.2_1.8_LAN 1

1 100K_5%
1 L40 2 R1006
BLM11A601S 100K_5%
1 C1347 1
C1348 2 Q1001 3 BSS84_3P
2 0.1UF_16V2 0.1UF_16V D S
2
PREP# 60-,39- 1G
S 1G D
+V2.5_3.3_LAN SSM3K7002F 2 Q1000 3 CN2
9 Y1 Y2 10
L38
1 2 RJ45_TD+ 60-,59- 1 TX+
BLM11A601S RJ45_TD- 60-,59- 2 TX-
1 C1336 1 60-,59- 3 RX+ G G1
C387 RJ45_TC+
2 0.1UF_16V2 0.1UF_16V RJ45_TB+ 60-,59- 4 P4
RJ45_TB- 60-,59- 5 P5
RJ45_TC- 60-,59-
1, 0.5 6 RX- G G2
RJ45_TA+ 60-,59- 7 P7
RJ45_TA- 60-,59- 8 P8
11 G1 G2 12

TYCO_1770074_1_RJ45_12P
+V1.2_1.8_LAN LED_3S_LANLINK# 59-

LED_3S_LANACT# 59-
U37

R1341 2

R1340 2

R1339 2

1 R1337 2

R1336 2

R1338 2

R1335 2

1 R1334 2
1 1 1 1

49.9_1%

49.9_1%

49.9_1%

49.9_1%

49.9_1%

49.9_1%

49.9_1%

49.9_1%
K5 C1349 C1340 C1341 C1344
L5 VDDC_03 AVDDL_01 F12
F13
2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V
1 C379 1 C1323 1 C1322 1 C1325 1 C1327 1 C1329 H6 VDDC_04 AVDDL_02
VDDC_05

1
2 10UF_6.3V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V J6 VDDC_06 +V2.5_3.3_LAN
K6 VDDC_07 AVDD_01 A13
H7 VDDC_08 AVDD_02 F14
J7 U30
K7 VDDC_09 1 24
VDDC_10 TCT1 MCT1
H8 TRD0-
J8 VDDC_11 TRD0M B14
B13
3 TD1- MX1- 22 60-,59- RJ45_TD-
VDDC_12 TRD0P TRD0+ 2 TD1+ MX1+ 23 60-,59- RJ45_TD+
K8 VDDC_13 4 TCT2 MCT2 21
1 C1333 1 C1315 1 C1338 1 C1328 1 C1316 P8 C14 TRD1- 6 TD2- MX2- 19 60-,59-
VDDC_14 TRD1M C13 RJ45_TC-
2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V J9 TRD1+ 5 TD2+ MX2+ 20 60-,59- RJ45_TC+
K9 VDDC_15 TRD1P 7 18
VDDC_16 TCT3 MCT3
J10 VDDC_17 D14
TRD2M D13 TRD2- 9 TD3- MX3- 16 60-,59- RJ45_TB-
K10 TRD2+ 8 TD3+ MX3+ 17 60-,59- RJ45_TB+
L10 VDDC_18 TRD2P 10 15
VDDC_19 TCT4 MCT4
E12 TRD3-
P12 VDDC_20 TRD3M E14
E13 TRD3+
12
11
TD4- MX4- 13
14
60-,59-
60-,59-
RJ45_TA-

75_1%R1236

75_1%R1237
75_1%R1235

75_1%R1238
VDDC_21 TRD3P TD4+ MX4+ RJ45_TA+
P13 VDDC_22
1 C1331 1 C388 1 C1314 1 C1317 1 C1335 M14 VDDC_23 BIASVDD A14 +V2.5_3.3_LAN BOTH_GST5009_SOP_24P

2
2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V H5 VDDC_01
J5 VDDC_02
N14 VDDC_24 RDAC D10
1 R1343 2 1 L39 2
P14 VDDC_25 1.18K_1% BLM11A601S
1 C1232 1 C1231 1 C1230 1 C1229

1
1 1
C389 C1342
2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V2 0.1UF_16V
C8 1 C1245
NC
+V2.5_3.3_LAN 2 2200PF_2000V

1 C396
2 0.1UF_16V
H10 NC_08 K11
NC
N9
NC
M9
J14 NC
N11 XTALVDD
XTALI LOW_PWR M11
1 R1332 2

R431 4.7K_5%
1 2 N10 XTALO P9
N13 NC
X5 200_5% XTAL_VSS M8
1 2 NC
L8
NC
25MHZ
N8
NC
+V1.2_1.8_LAN
G10 VSS_27 40-,39- LED_LANLINK#
1 C390 1 C391 F10 1 L41 2
M12 VSS_26
2 27PF_50V 2 27PF_50V VSS_28 BLM11A601S
N12 1 C395 1 C394
G9 VSS_29
VSS_30 2 0.1UF_16V2 2.2UF_16V
H9 VSS_31
L9 VSS_32 PLLVDD2 H14 SSM3K7002F 2
B7 VSS_33 +V3_LAN S

GPHY_PLL2_VSS M13 1G
R1009 2 58-,57-,59- D
G13 1
Q1003 3
59- LED_3S_LANLINK#
LED_LNK# H13 60-
LED_100# 470_5% LED_LANLINK#_DOCK
G12 60- LED_LANACT#_DOCK
LED_1000# G14 1 R1008 2 59- 1 R1007 2
LED_ACT# LED_3S_LANACT# Q1002 3
470_5% 10K_5% D
1G
S

BCM_BCM5788_FBGA_196P SSM3K7002F 2
INVENTEC
TITLE
TIANSHAN
LAN RJ45 CONN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 59 OF 74
 +VADP
0805CS_111XJBC_110NH
14-,5-
L1000 L1001 29-
CRT_R_B 60- 1 2 1 2
1 C54 1 C53 0805CS_390XJBC_39NH CRT_B
52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-,60- +V5S
100PF_50V C52 2 0.1UF_25V 2 100PF_50V 1C1012
U1001
2 1 VGA_R_B 36- 1
A Vcc
5 2 18PF_50V
CN1000
G1 P1 2
GND 18.5V B

PWR_SWIN#_3 66-,65-,43- 1 83 60- DETECT1# 3 4 48-,39-,60- ISO_PREP#

NBSWON# DETECT1# GND OE
2 84
RJ45_GND RJ45_GND
LED_LANLINK#_DOCK 59-
RJ45_TB+ 59- 3
RJ45_C+ RJ45_D+
85 59- RJ45_TA+ FAIR_FSA66P5X_SC70_5P
RJ45_TB- 59- 4
RJ45_C- RJ45_D-
86 59- RJ45_TA- 0805CS_111XJBC_110NH
5 87
RJ45_GND RJ45_GND L13 L8 29-
RJ45_TD+ 59- 6
RJ45_TX_A+ RJ45_RX_B+
88 59- RJ45_TC+ CRT_R_G 60- 1 2 1 2
1 C51 59- 7 89 59-1, 0.5 RJ45_TC-
CRT_G
RJ45_TD- RJ45_TX_A- RJ45_RX_B- +V5S 0805CS_390XJBC_39NH
2 100PF_50V 8 90 52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-,60-
RJ45_GND RJ45_GND 1
LED_LANACT#_DOCK 59- 9
RJ45_ACTLED# PWRLED
91 60- LED_3_PWR U4 C56
10 92 1 2 53-,47-,39-,12-,8- 36- 1 5
RJ45LILED# S5# SLP_S5#_3R VGA_R_G A Vcc 2 18PF_50V
11 93 R91 0_5%
36- GND GND
CRT_BUF_VSYNC 12 94 2
36- CRTVS DVI_DDC_CLK B
CRT_BUF_HSYNC 13 95
36- CRTHS DVI_DDC_DATA
14 96 3 4 48-,39-,60-
CRT_Q_DDCDATA 36- CRT_DDC_DATA GND GND OE ISO_PREP#
CRT_Q_DDCCLK 15 97
CRT_DDC_CLK GND
16
HPD DVI_D2-
98 FAIR_FSA66P5X_SC70_5P
17
AGND UNUSABLE
99 0805CS_111XJBC_110NH
60- 18 100
CRT_R_R 60- CRT-R DVI_D2+ L12 L11 29-
19
CRT-G
101 CRT_R_R 60- 1 2 1 2
CRT_R_G 60- 20
GND
102 CRT_R
CRT_R_B CRT-B GND 52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-,60- 0805CS_390XJBC_39NH
21 103 +V5S
AGND DVI_D1- 1
36- 22 104 C90
VIDEO_COMP_DOCKING TV_COMP UNUSABLE
36- 23
TV_CHROMA DVI_D1+
105 U9 2 18PF_50V
SVID_CHROMA_DOCKING 36- 24 106 36- 1 5
SVID_LUMA_DOCkING TV_LUMA GND VGA_R_R A Vcc 1
25
GND GND
107 C1011
26
1394TPAP1 DVI_CLK-
108 2
B 0.1UF_16V 2
48- 27 109
LINE_IN_SENSE 28
UNUSABLE UNUSABLE
110 3 4 48-,39-,60-
1394TPAN1 DVI_CLK+ GND OE ISO_PREP#
14- 29 111
ACOCP_EN# 30
GND GND
112 FAIR_FSA66P5X_SC70_5P
1394TPBP1 GND
31 113
UNUSABLE DVI_D0-
32 114 +V3A
1394TPBN1 UNUSABLE
33 115
GND DVI_D0+
46- 34 116
UART_3S_DCD# PR_DCD# GND 65-,64-,63-,58-,44-,41-,40-,39-,37-,16-,14-,13-,9-,7-
46- 35 117 1 2 14-,5-
UART_3S_RI PR_RI RFU LIMIT_SIGNAL 2
UART_3S_DTR# 46- 36 118 39- DOCK_ADP_ID
PR_DTR# RFU
46- 37 119 R61 1K_5% +V5S R62
UART_3S_CTS PR_CTS RFU
UART_3S_RTS# 46- 38
PR_RTS# RFU
120 10K_5%
46- 39 121
UART_3S_DSR# 46- 40
PR_DSR# RFU
122
52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-,60-
60-
1
UART_3S_TXD PR_SOUT RFU LED_3_PWR
46- 41 123 Q13
UART_3S_RXD 42
PR_SIN RFU
124 3D
GND RFU
46- 43 125 G 1 66-,57-,47-,43-
LPT_5S_STRB# PPT_STB# RFU STBY_LED#
46- 44 126

1K_1%
LPT_5S_ALF# SSM3K7002F

1K_1%

1K_1%
1K_1%
PPT_AFD# RFU S
46- 45 127 2
LPT_5S_ERROR# PPT_ERR# RFU
1 1 1 1 58-,43-,39-,13-,12-
46- 46 128
LPT_5S_ACK# 46- 47
PPT_ACK# RFU
129
SLP_S3#_3R
LPT_5S_BUSY 46- 48
PPT_BUSY RFU
130
46-
LPT_5S_PE 46- 49
PPT_PE RFU
131
LPT_5S_SLCT PPT_SLCT 2 2 2 2

R55
LPT_5S_PD(7:0) RFU

R54

R50
R52
LPT_5S_PD(7) 50
PPT_PD7 RFU
132
LPT_5S_PD(6) 51
PPT_PD6 GND
133
LPT_5S_PD(5) 52 134 43-
PPT_PD5 PR_KB_DATA 43- KB_5S_DATA
LPT_5S_PD(4) 53
PPT_PD4 PR_KB_CLK
135
LPT_5S_PD(3) 54 136 40-,15- KB_5S_CLK
PPT_PD3 CLKREQ# CPPE# 43-
LPT_5S_PD(2) 55
PPT_PD2 PR_MS_DATA
137
LPT_5S_PD(1) 56 138 43- EM_5S_DATA
PPT_PD1 PR_MS_CLK EM_5S_CLK
LPT_5S_PD(0) 57
PPT_PD0 PR_HPSENSE#
139 50- PR_HPSENSE#
46- 58 140 C50 470PF_50V
LPT_5S_SLCTIN# PPT_SLIN# AUDIO_AGND
LPT_5S_INIT# 46- 59
PPT_INIT# LINEIN-L
141 1 2 48- A_LINEINL
60 142 48- A_LINEINR
GND LINEIN-R
61 143
RFU AUDIO_AGND
62 144 50-,49-
RFU LINEOUT-L PR_AOUTL 1 C81
63 145 49-
RFU LINEOUT-R PR_AOUTR
64 146 2 100PF_50V
RFU AUDIO_AGND 1
65 147 C49
RFU GND
66 148 2 470PF_50V
RFU GND
67 149 39- PCIE_C_TXP4
RFU PCIEXP-TX1+
68 150
RFU NC
69 151 39- PCIE_C_TXN4
RFU PCIEXP-TX1-
70 152
RFU GND
71 153
GND GND
USB_P7- 39- 72 154 39- PCIE_C_RXP4
USB4- PCIEXP-RX1+
73 155
UNUSABLE NC
USB_P7+ 39- 74 156 39- PCIE_C_RXN4
USB4+ PCIEXP-RX1-
75 157
GND GND
USB_P6- 39- 76 158
USB3- GND
77 159 15- CLK_R_DOCK_REF
UNUSABLE REFCLK+
USB_P6+ 39- 78 160
USB3+ NC
79 161 15- CLK_R_DOCK_REF#
GND REFCLK-
SER_SHD 46- 80 162
RESERVED GND
EXPCRD_RST# 46- 81 163 59-,39- PREP#
PCIEXP_RESET# PREP#
DETECT1# 60- 82 164
DETECT2# VA_ON#

G2 P2 C48
GND +5VS 1
RING 60- R
RING TIP
T 0.01UF_16V
60- TIP R41 1
G3 G9 150_1% 2 52-,51-,50-,48-,47-,46-,45-,41-,39-,36-,20-,14-,13-,11-,10-,5-,60-
G3 G9
G4 G10 2 +V5S
G4 G10
G5 G11
G5 G11
CN7 G6 G12
1 G6 G12
TIP 60- 1 G7
G7 G13
G13
2
RING 60-
3
4
2
3
4
G G1
G G2
G8
G8

JAE_SP03_14588_PCL03_164P
G14
G14
INVENTEC
1 C46 1 C47 TITLE
ACES_87212_0400_4P TIANSHAN
2 1UF_10V 2 0.1UF_16V DOCKING CONN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 60 OF 74
S12 S13 S14 S15 S26 S27 S28
SCREW2.8_6_8_5P SCREW2.8_6_5P SCREW2.8_8_6_1P SCREW2.8_6_8_5P
SCREW1.1_5_2.4_1P SCREW1.1_5_2.4_1P SCREW1.1_5_2.4_1P

S16 S17 S18

S29 S30
SCREW2.8_6_5P SCREW2.8_6_5P SCREW2.8_8_5P
SCREW2_5.1_3_1P SCREW2_5.1_3_1P

S19
SCREW2.8_6_11_5P S35
SCREW2.8_9_11_1P

S20 S21 S22 S23

SCREW3.8_6_1P SCREW3.8_6_1P SCREW3.8_6_1P SCREW3.8_6_1P

S24
SCREW2.8_6_8_5P

FIX35 FIX36

FIX_MASK FIX_MASK

FIX37 FIX38

FIX_MASK FIX_MASK

FIX40 FIX39

FIX_MASK FIX_MASK

FIX41 FIX42

FIX_MASK FIX_MASK

FIX43 FIX44

FIX_MASK FIX_MASK

INVENTEC
TITLE
TIANSHAN
SCREW
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 61 OF 74
BLANK

INVENTEC
TITLE
TIANSHAN
BLANK
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 62 OF 74
 +V3A
65-,64-,60-,58-,44-,41-,40-,39-,37-,16-,14-,13-,9-,7-

1 C134
2 0.1UF_16V_OPEN

+V3S
U13
66-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,63-
LPC_3S_AD(0) 57-,46-,43-,38- 26 5
LAD0 VSB
LPC_3S_AD(1) 57-,46-,43-,38- 23
LAD1
LPC_3S_AD(2) 57-,46-,43-,38- 20 10
LAD2 VDD 1 C165 1 C132 1 C133
LPC_3S_AD(3) 57-,46-,43-,38- 17 19
LAD3 VDD
24 2 0.1UF_16V_OPEN 2 0.1UF_16V_OPEN 2 0.1UF_16V_OPEN
VDD
CLK_R3S_FWHPCI 15- 21
LCLK
4
GND
LPC_3S_FRAME# 57-,46-,43-,38- 22 11
LFRAME# GND
18
57-,52-,46-,40-,39- 1 R175 2 16
GND
25
BUF_PLT_RST# LRESET# GND
0_5%_OPEN
SUS_STAT# 50-,39- 28 7
66-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5-,63- LPCPD# PP
1
47-,46-,43-,39- 27
NC
3 1 R176 2 43-
+V3S PCI_3S_SERIRQ SERIRQ NC CLK_TPM
PCI_3S_CLKRUN# 58-,47-,46-,43-,39- 15 12
CLKRUN# NC OPEN
9 13
C167 10PF_50V_OPEN
TESTBI_BADDR XTALI
XTALO
14 1 2
8 6

1
TESTI GPIO 1
2
GPIO2
R177 X1
INF_SLB9635TT_TSSOP_28P_OPEN 10M_5%_OPEN 32.768KHZ_OPEN

4
2
C166 10PF_50V_OPEN
1 2

INVENTEC
TITLE
TIANSHAN
TPM V1.2
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 63 OF 74
 +V3A
65-,63-,60-,58-,44-,41-,40-,39-,37-,16-,14-,13-,9-,7- BLUETOOTH_VCC

Q56

2
R423 4 S D 1
10K_5% 2
5 1 C384 1 C385

1
39- 1 R421 2 3 6
BT_OFF G 2 10UF_6.3V 2 0.1UF_16V
220K_5% FDC638P

CN23
1
2 1
2
3
4 3
USB_P1+ 39-
5 4
5
6 G G1
7 6
USB_P1- 39-
7 G G2
8 8
ACES_87212_0800_8P
LED_BLUETOOTH 47-

57- 1 R420 2
WLAN_PRIORITY
100_5%

57- 1 R422 2
BT_PRIORITY
100_5%

INVENTEC
TITLE
TIANSHAN
BLUETOOTH
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 64 OF 74
 +V3A
64-,63-,60-,58-,44-,41-,40-,39-,37-,16-,14-,13-,9-,7-,65-

+V3A 1
G Q1040
64-,63-,60-,58-,44-,41-,40-,39-,37-,16-,14-,13-,9-,7-,65-
PWR_SWIN#_3 66-,60-,43- D S 39- PWR_SWIN2#_3
39-,37- LID_SW#_3 3 2
1 SSM3K7002F

D1003 3
CHENMKO_BAV99
+V3A
2
64-,63-,60-,58-,44-,41-,40-,39-,37-,16-,14-,13-,9-,7-,65-
66-,47- WLN_BT_LED#
SW1 R1010 2
1
3

100K_1% Q1042 3
D
44-,40-,39-
D1022 2G
1 C1000 ACCEL_INT 1 3 1
4

1 C1310 R1330 S
2 0.1UF_16V
BAT54_30V_0.2A_OPEN OPEN 2N7002_OPEN 1
2 OPEN
2
LID SWITCH
SW_DT006_PT11ABH_E

INVENTEC
TITLE
TIANSHAN
BUTTON&SWITCH&LED
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 65 OF 74
 +V3AL
57-,47-,45-,43-,38-,14-,7-,6-,5-

CN6
1
2 1
2
PWR_SWIN#_3 65-,60-,43- 3
4 3
SCAN_3S_OUT(15) 43-
5 4
KSCAN_3S_IN(8) 45-
5
KSCAN_3S_IN(9) 45- 6
7 6
KSCAN_3S_IN(10) 45-
8 7
KSCAN_3S_IN(11) 45-
8
KSCAN_3S_IN(12) 45- 9
10 9
KSCAN_3S_IN(13) 45-
11 10
63-,58-,57-,52-,48-,47-,46-,44-,43-,41-,40-,39-,38-,37-,36-,32-,31-,29-,27-,26-,24-,21-,20-,15-,14-,13-,11-,10-,9-,5- LED_3_NUM# 57-,43- 11
+V3S MUTE# 50- 12
13 12
STBY_LED# 60-,57-,47-,43-
14 13
14
15
16 15
16
LED_3_CAPS# 57-,43- 17 17
WLN_BT_LED# 65-,47- 18
19 18
19
20
20
ACES_85203_20421_20P

INVENTEC
TITLE
TIANSHAN
LED/SWITCH CONN
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 66 OF 74
 +V3AL_LEDB
FIX31 FIX32 67-
S4 S7 S8 S10 S11
SCREW2.8_6_5P SCREW2.8_6_5P SCREW2.8_6_5P SCREW2.8_6_5P SCREW2.8_6_5P
FIX_MASK FIX_MASK
D6000
67- 1 R6000 2
STBY_LED#_LEDB 1 2
FIX29 FIX33 270_5%
EVL_YG_19_21_G6C_BM2P1B_3T
FIX_MASK FIX_MASK
POWER_LED
+V3AL_LEDB 67-
SWGND SWGND SWGND SWGND SWGND
PWR_SWIN#_3_LEDB
FIX30 FIX34 67-
SW6000
1 R6001 2 1 4
FIX_MASK FIX_MASK 2 5
100K_5% 6
+V3AL_LEDB 3
1 C6000
SW6006
4
VOLUM UP 2 1000PF_50V
3
67- SWTT_TC017_PS11BT

1
67- 2 5 67-
SCAN_3S_OUT(15)_LEDB 6 KSCAN_3S_IN(9)_LEDB
3 SWGND SWGND
2 1
SWTT_TC017_PS11BT

D6001
POWER SWITCH
SWGND SWGND CHENMKO_BAV99
SWGND

+V3AL_LEDB
SW6005
4
VOLUM DN
1
67- 67- 2 5 67-
KSCAN_3S_IN(10)_LEDB
SCAN_3S_OUT(15)_LEDB 3 6
SWTT_TC017_PS11BT
+V3AL_LEDB
SWGND SWGND 67-
1 C6001 1 C6002
2 0.1UF_16V 2 0.1UF_16V
SW6003 PRESENTATION D6004
1 4 EVL_YG_19_21_G6C_BM2P1B_3T
67- 2 5 67-
SCAN_3S_OUT(15)_LEDB 6 KSCAN_3S_IN(13)_LEDB R6004 2
3 LED_3_NUM#_LEDB 67- 1
1 2
PAD6000 1 SWTT_TC017_PS11BT
270_5%
2 SWGND
3
4
5
67-
67-
67-
PWR_SWIN#_3_LEDB
SCAN_3S_OUT(15)_LEDB SWGND SWGND
NUM_LOCK LED
KSCAN_3S_IN(8)_LEDB
6
7
67-
67-
KSCAN_3S_IN(9)_LEDB
KSCAN_3S_IN(10)_LEDB
SW6002 WIRELESS & BLUETOOTH D6003
8 67- 1 4
KSCAN_3S_IN(11)_LEDB 5 EVL_YG_19_21_G6C_BM2P1B_3T
9 67- KSCAN_3S_IN(12)_LEDB 67- 2 67-
KSCAN_3S_IN(11)_LEDB
10 67-
SCAN_3S_OUT(15)_LEDB 3 6 67- 1 R6003 2
KSCAN_3S_IN(13)_LEDB LED_3_CAPS#_LEDB 1 2
11 67- LED_3_NUM#_LEDB +V3S_LEDB 270_5%
12 67- SWTT_TC017_PS11BT

13
14
67-
MUTE_LEDB#
STBY_LED#_LEDB 67- CAP LED +V3S_LEDB
15 67-
16 SWGND SWGND
17
18
67-
67-
LED_3_CAPS#_LEDB
1
SW6001
4
QUICK_LOOK D6002
WLN_BT_LED#_LEDB 5 R6002 2
19
SCAN_3S_OUT(15)_LEDB
67- 2 67-
WLN_BT_LED#_LEDB 67- 1
20 3 6 KSCAN_3S_IN(12)_LEDB 1 2
EVL_19_21_B7C_ZQ1R2_3T_2P 270_5%
SMDPAD0.7X2.7_20P SWTT_TC017_PS11BT

WLAN_BLUETOOTH_LED
SWGND
SWGND
SW6004
4
MUTE D6005
1 R6005
SWGND 67- 2 5 67- 67- 1 2 2 1
SCAN_3S_OUT(15)_LEDB 6 KSCAN_3S_IN(8)_LEDB MUTE_LEDB#
3
EVL_21SUYC 330_5%
SWTT_TC017_PS11BT

MUTE & MUTE LED

SWGND SEGND

SWITCH BUTTON BOARD

INVENTEC
TITLE
TIANSHAN
LED/SWITCH BUTTON BOARD
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 67 OF 74
+V3S_DB +V5S_DB
73-,72-,71-,70-,69- 70-,69-
CN4003
1 2
+V3AL_DB
3 4 73-
5 6
7 8
69- 9 10 69-
CLK_R3S_CBPCI_DB CLK_R3S_CARD48_DB
11 12
69- 13 14 69-
PCI_3S_CBE#_DB(3) PCI_3S_INTC#_DB
69- 15 16 69-
PCI_3S_CBE#_DB(2) PCI_3S_INTD#_DB
69- 17 18 69-
PCI_3S_CBE#_DB(1) PCI_3S_INTG#_DB
69- 19 20 69-
PCI_3S_CBE#_DB(0) 69-
PCI_3S_REQ#_DB(2)
21 22 69- PCI_3S_GNT#_DB(2)
PCI_3S_RST#_DB 69- 23 24 69-
PCI_3S_PERR#_DB PCI_3S_SERIRQ_DB
69- 25 26 69-
PCI_3S_PAR_DB PCI_3S_CLKRUN#_DB
69- 27 28 69-
PCI_3S_FRAME#_DB A_3S_PCSPKR_DB
29 30
69- 31 32 69-
PCI_3S_TRDY#_DB PCI_3S_AD_DB(30)
69- 33 34 69-
PCI_3S_IRDY#_DB PCI_3S_AD_DB(28)
69- 35 36 69-
PCI_3S_STOP#_DB PCI_3S_AD_DB(26)
69- 37 38 69-
PCI_3S_DEVSEL#_DB 69-
PCI_3S_AD_DB(24)
39 40 69- PCI_3S_AD_DB(22)
PCI_3S_PME#_DB
69- 41 42 69-
PCI_3S_SERR#_DB PCI_3S_AD_DB(20)
70- 43 44 69-
SLP_S5#_3R_DB PCI_3S_AD_DB(18)
45 46 69- PCI_3S_AD_DB(16)
47 48
69- 49 50 69-
PCI_3S_AD_DB(31) PCI_3S_AD_DB(14)
69- 51 52 69-
PCI_3S_AD_DB(29) PCI_3S_AD_DB(12)
PCI_3S_AD_DB(27) 69- 53 54 69- PCI_3S_AD_DB(10)
69- 55 56 69-
PCI_3S_AD_DB(25) PCI_3S_AD_DB(8)
69- 57 58 69-
PCI_3S_AD_DB(23) PCI_3S_AD_DB(6)
69- 59 60 69-
PCI_3S_AD_DB(21) PCI_3S_AD_DB(4)
69- 61 62 69-
PCI_3S_AD_DB(19) PCI_3S_AD_DB(2)
69- 63 64 69-
PCI_3S_AD_DB(17) PCI_3S_AD_DB(0)
65 66
69- 67 68 73-
PCI_3S_AD_DB(15) LED_BLUETOOTH_DB
69- 69 70 73-
PCI_3S_AD_DB(13) 73- LED_WLAN_LINK#_DB
69- 71 72
PCI_3S_AD_DB(11) 73- WLN_BT_LED#_DB
PCI_3S_AD_DB(9) 69- 73 74
69- 75 76 73- STBY_LED#_DB
PCI_3S_AD_DB(7) 73- MBDASP#_5_DB
PCI_3S_AD_DB(5) 69- 77 78
69- 79 80 73- LED_3S_SATA#_DB
PCI_3S_AD_DB(3) HDD_HALTED_DB
69- 81 82 73-
PCI_3S_AD_DB(1) 73- BAT_AMBERLED#_DB
83 84
72- 85 86
BAT_GRNLED#_DB
AC97_3S_SDOUT_MDC_DB
AC97_3S_SYNC_MDC_DB 72- 87 88 72- AC97_3S_RST#_MDC_DB
72- 89 90 72-
AC97_3S_SDIN1_DB AC97_3S_BITCLK_MDC_DB
G1 G2
G3 G4
G5 G6

ACES_88029_907N_90P

DBGND DBGND

DAUGHTER BOARD

INVENTEC
TITLE
TIANSHAN
DAUGHTER BOARD CONN(DB)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 68 OF 74
 ACARDVCC +V3S_DB
70- 73-,72-,71-,70-,68-,69-
+V3S_DB
73-,72-,71-,70-,68-,69-
1 C4019 1 C4006 1 C4000 1 C4022 1 C4021
1
U4000 2 4.7UF_6.3V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V R4015
A15 10K_5%
VCCB +V3S_DB
J19
VCCB 2
W12
TP792 DBGND DBGND DBGND DBGND DBGND U4000 73-,72-,71-,70-,68-,69-
NC
C10 70- W8 J5
B_CAD31 ACARD_3S_AD31 VCCP SUSPEND#
A10 70- 68-,69- P1
B_CAD30 ACARD_3S_AD30 PCI_3S_AD_DB(31:0) VCCP 1 1
F11 70-
ACARD_3S_AD29 B9 70- S_DATA
B_CAD29 DATA R4026 R4025
E11 70- PCI_3S_AD_DB(31) M1 A9 70-
B_CAD28 ACARD_3S_AD28 PCI_3S_AD_DB(30) M2
AD31 CLOCK S_CLOCK 10K_5% 10K_5%
C11 70-
ACARD_3S_AD27 C9 70- S_LATCH
B_CAD27 AD30 LATCH
V12
TP793 B13 70- PCI_3S_AD_DB(29) M3
NC B_CAD26 ACARD_3S_AD26 AD29 2 2
C13 70- PCI_3S_AD_DB(28) M6 H3 68-
B_CAD25 ACARD_3S_AD25 AD28 SPKOUT A_3S_PCSPKR_DB
A14 70- PCI_3S_AD_DB(27) M5
B_CAD24 ACARD_3S_AD24 PCI_3S_AD_DB(26) N1
AD27 1
B14 70- G1 68-
B_CAD23 ACARD_3S_AD23 AD26 MFUNC0 PCI_3S_INTC#_DB R4018
B15 70- PCI_3S_AD_DB(25) N2 H5 68-
B_CAD22 ACARD_3S_AD22 PCI_3S_AD_DB(24) N3
AD25 MFUNC1 PCI_3S_INTD#_DB 150_5%
E14 70- ACARD_3S_AD21 H2 68- PCI_3S_INTG#_DB
B_CAD21 AD24 MFUNC2
A16 70- PCI_3S_AD_DB(23) P3 H1 68-
B_CAD20 ACARD_3S_AD20 AD23 MFUNC3 PCI_3S_SERIRQ_DB R4024 2 2
D19 70- PCI_3S_AD_DB(22) R1 J1 1
B_CAD19 ACARD_3S_AD19 PCI_3S_AD_DB(21) R2
AD22 MFUNC4
U12 E17 70- J2
NC B_CAD18 ACARD_3S_AD18 PCI_3S_AD_DB(20) P5
AD21 MFUNC5 OPEN
F15 70- J3 68-
B_CAD17 ACARD_3S_AD17 AD20 MFUNC6 PCI_3S_CLKRUN#_DB
H19 70- PCI_3S_AD_DB(19) R3
B_CAD16 ACARD_3S_AD16 PCI_3S_AD_DB(18) T1
AD19
DBGND
J17 70- F1 68-
B_CAD15 ACARD_3S_AD15 PCI_3S_AD_DB(17) T2
AD18 CLK_48 CLK_R3S_CARD48_DB
J15 70-
B_CAD14 ACARD_3S_AD14 AD17
J18 70- PCI_3S_AD_DB(16) W4 E10 TP795
B_CAD13 ACARD_3S_AD13 PCI_3S_AD_DB(15) W7
AD16 A_USB_EN
K15 70-
B_CAD12 ACARD_3S_AD12 AD15
K17 70- PCI_3S_AD_DB(14) R8
B_CAD11 ACARD_3S_AD11 PCI_3S_AD_DB(13) U8
AD14
TP794
E5 K18 70- ACARD_3S_AD10
NC B_CAD10 AD13
L15 70- PCI_3S_AD_DB(12) V8
B_CAD9 ACARD_3S_AD9 AD12 R4027 220_5%
L18 70- PCI_3S_AD_DB(11) W9 G2 1 2
+V3S_DB B_CAD8 ACARD_3S_AD8 PCI_3S_AD_DB(10) V9
AD11 SCL
1 2
L19 70- ACARD_3S_AD7 G3
B_CAD7 AD10 SDA
73-,72-,71-,70-,68-,69- M17 70- PCI_3S_AD_DB(9) U9
B_CAD6 ACARD_3S_AD6 AD9 R4020 220_5%
M18 70- PCI_3S_AD_DB(8) R9
B_CAD5 ACARD_3S_AD5 PCI_3S_AD_DB(7) V10
AD8
N19 70- ACARD_3S_AD4
B_CAD4 AD7 C4005 0.1UF_16V
M15 70- PCI_3S_AD_DB(6) U10 K19
B_CAD3 ACARD_3S_AD3 AD6 VR_PORT C4024 0.1UF_16V DBGND
N17 70- PCI_3S_AD_DB(5) R10 K1 1 2
B_CAD2 ACARD_3S_AD2 PCI_3S_AD_DB(4) W11
AD5 VR_PORT
B_CAD1
N18 70- ACARD_3S_AD1 AD4 VR_EN#
K2 1 2
P19 70- PCI_3S_AD_DB(3) V11
B_CAD0 ACARD_3S_AD0 AD3
PCI_3S_AD_DB(2) U11
AD2
E13 70- PCI_3S_AD_DB(1) P11 F3
1C4013 1C4011 1 C4016 B_CBE3# ACARD_3S_CBE3# PCI_3S_AD_DB(0) R11
AD1 SC_CD#
E18 70- ACARD_3S_CBE2#
B_CBE2# AD0
2 0.1UF_16V 2 0.1UF_16V 20.1UF_16V H18 70- ACARD_3S_CBE1# E2
B_CBE1# SC_CLK
L17 70- ACARD_3S_CBE0# PCI_3S_CBE#_DB(3) 68- P2 E1
B_CBE0# C_BE3# SC_DATA
PCI_3S_CBE#_DB(2) 68- U5
C_BE2#
H14 70- ACARD_3S_PAR PCI_3S_CBE#_DB(1) 68- V7 E3
B_CPAR C_BE1# SC_FCB
PCI_3S_CBE#_DB(0) 68- W10
C_BE0#
DBGND E19 70-
B_CFRAME# ACARD_3S_FRAME#
G15 70- ACARD_3S_TRDY# PCI_3S_PAR_DB 68- U7 G5
C4017 B_CTRDY# PAR SC_PWR_CTL
C4012 F17 70-
0.1UF_16V 0.1UF_16V B_CIRDY# ACARD_3S_IRDY#
P6 G18 70- ACARD_3S_STOP# PCI_3S_FRAME#_DB 68- R6
VCC B_CSTOP# FRAME#
P8 F19 70- ACARD_3S_DEVSEL# PCI_3S_TRDY#_DB 68- W5 F2 TP796
1 1 1 1 VCC B_CDEVSEL# TRDY# SC_OC#
P10 H15 70- ACARD_3S_BLOCK# PCI_3S_IRDY#_DB 68- V5 D1 +V5S_DB
VCC B_CBLOCK# IRDY# SC_RFU
2 2 2 2 L6 PCI_3S_STOP#_DB 68- V6 F5
VCC STOP# SC_RST
L14 G19 70- ACARD_3S_PERR# PCI_3S_DEVSEL#_DB 68- U6 70-,68-
VCC B_CPERR# DEVSEL#
C4018 C4014 J6 C12 70- 68-,69- 1 2 N5
0.1UF_16V VCC B_CSERR# ACARD_3S_SERR# PCI_3S_AD_DB(22) IDSEL R4013 2 1K_5%
0.1UF_16V 1
J14
VCC R4017 100_5% SC_VCC_5V
G6
F6 C14 70- ACARD_3S_REQ# PCI_3S_PERR#_DB 68- R7
VCC B_CREQ# PERR#
DBGND F9 G17 70- 68- W6
VCC B_CGNT# ACARD_3S_GNT# PCI_3S_SERR#_DB SERR#
R4012 2 220_5%
F12 P12 1
VCC TEST0
F14 A12 70- ACARD_3S_STSCHG PCI_3S_REQ#_DB(2) 68- L3
VCC B_CSTSCHG REQ#
A11 70- ACARD_3S_CLKRUN# PCI_3S_GNT#_DB(2) 68- L2 +V3S_DB
B_CCLKRUN# GNT#
P7 F18 70- ACARD_3S_CLK M19 70- ACARD_3S_D(14)_RFU
GND B_CCLK RSVD
P9 68- L1 H17 70- DBGND
GND CLK_R3S_CBPCI_DB PCLK RSVD
2
ACARD_3S_A18_RFU 73-,72-,71-,70-,68-,69-
N6 E12 70- 68- K3 C4 1
GND B_CINT# ACARD_3S_INT# PCI_3S_RST#_DB 1 2
PRST# RSVD
M14 K5 B10 70- ACARD_3S_D(2)_RFU
GND GRST# RSVD
DBGND K6 C15 70-
GND B_CRST# ACARD_3S_RST# R4023 0_5% R4019 43K_5%
K14 L5
GND R4022 2 RI_OUT#_PME#
H6 B12 70- 70- 1
GND B_CAUDIO ACARD_3S_AUDIO GRST#
G14
GND 0_5% TI_PCI6612_PBGA_216P +V3S_DB
F7 N15 70- ACARD_3S_CD1#
F10
GND B_CCD1#
B11 70-
PLL3_3V
B_CCD2# ACARD_3S_CD2# 73-,72-,71-,70-,68-,69-
F13
GND
A13 70- 1 R4016 2
GND B_CVS1 ACARD_3S_VS1# L4001
B_CVS2
B16 70- ACARD_3S_VS2# 0_5% 1 2
U4000 BLM21A121S
1 C4007 1 C4010 1 C4009
TI_PCI6612_PBGA_216P R12
CPS AVDD
P13
P14
AVDD 2 10UF_6.3V 2 0.01UF_16V 2 1UF_6.3V
U15
AVDD
R18
XO
68- DBGND
PCI_3S_PME#_DB U19
VDDPLL_33
DBGND
+V3S_DB
R19 P15
XI VDDPLL_15
R17 73-,72-,71-,70-,68-,69-
VSSPLL R4009 2 0_5% L4000
1 1 2
R14
AGND R0
T18 BLM11A121S
U13 1 C4002 1 C4003 1 C4004
AGND
U14 T19 2 0.1UF_16V 2 0.1UF_16V 2 0.1UF_16V
AGND R1

W17 R13
TPBIAS1 TPBIAS0 C4008 0.1UF_16V
DBGND V16 V14 1 2
TPA1+ TPA0+
W16 W14 DBGND
TPA1- TPA0-
DBGND

DAUGHTER BOARD
V15
W15
TPB1+
TPB1-
TPB0+
TPB0-
V13
W13

P17 1 R4011 2
PLL3_3V
INVENTEC
PHY_TEST_MA TITLE
4.7K_5% TIANSHAN
TI_PCI6612_PBGA_216P CARDBUS CONTROLLER(DB)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 69 OF 74
 CN4000 ACARDVCC
ACARD_3S_AD0 69- 2 69-,70-
D3-CAD0
ACARD_3S_AD1 69- 3 17
D4-CAD1 VCC
ACARD_3S_AD3 69- 4 51
D5-CAD3 VCC
ACARD_3S_AD5 69- 5
D6-CAD5
ACARD_3S_AD7 69- 6
D7-CAD7
ACARD_3S_CBE0# 69- 7
CE1-CCBE0
ACARD_3S_AD9 69- 8
A10-CAD9
ACARD_3S_AD11 69- 9
OE-CAD11
ACARD_3S_AD12 69- 10
A11-CAD12
ACARD_3S_AD14 69- 11
A9-CAD14
ACARD_3S_CBE1# 69- 12
A8-CCBE1 ACARDVPP
ACARD_3S_PAR 69- 13
A13-CPAR
ACARD_3S_PERR# 69- 14 70-
A14-CPERR
ACARD_3S_GNT# 69- 15 18
WE_PGM-CGNT VPP1
ACARD_3S_INT# 69- 16 52
RDY_BSY-IRQ-INT VPP2
69- 1 2 19
ACARD_3S_CLK A16-CCLK
69- 20
R4010 ACARD_3S_IRDY# A15-CIRDY
47_5%ACARD_3S_CBE2# 69- 21
A12-CCBE2
ACARD_3S_AD18 69- 22
A7-CAD18
+V3S_DB +V5S_DB ACARD_3S_AD20 69- 23
ACARDVPP A6-CAD20
ACARD_3S_AD21 69- 24
A5-CAD21
73-,72-,71-,69-,68- 70- ACARD_3S_AD22 69- 25
69-,68- A4-CAD22
ACARD_3S_AD23 69- 26
A3-CAD23
ACARD_3S_AD24 69- 27
A2-CAD24
ACARD_3S_AD25 69- 28
A1-CAD25
ACARD_3S_AD26 69- 29
U4001 A0-CAD26
ACARD_3S_AD27 69- 30
1 C4001 D0-CAD27
24 1 ACARD_3S_AD29 69- 31
NC 5V D1-CAD29
23 2 2 0.1UF_16V ACARD_3S_D(2)_RFU 69- 32
NC 5V D2-RFU
22 3 69- S_DATA ACARD_3S_CLKRUN# 69- 33
68- NC DATA WP-IOIS16-CKRUN
SLP_S5#_3R_DB 21 4 69- S_CLOCK ACARD_3S_CD1# 69- 36
SHDN CLOCK CD1-CCD1
20 5 69- S_LATCH ACARD_3S_AD2 69- 37
NC LATCH ACARDVCC D11-CAD2
19 6 ACARD_3S_AD4 69- 38
NC NC D12-CAD4
18 7 DBGND 69- 39
NC 12V 69-,70- ACARD_3S_AD6 D13-CAD6
17 8 ACARD_3S_D(14)_RFU 69- 40
NC AVPP D14-RFU
16 9 ACARD_3S_AD8 69- 41
NC AVCC D15-CAD8
15 10 ACARD_3S_AD10 69- 42
OC AVCC CE2-CAD10
14 11 ACARD_3S_VS1# 69- 43
NC GND 1 C4020 RFSH-VS-1-CVS1
GND

13 12 69- 1 C4023 69- 44 34

3.3V RESET GRST# ACARD_3S_AD13 IORD-CAD13 GND
2 0.1UF_16V 2 0.1UF_16V ACARD_3S_AD15 69- 45 35
IOWR-CAD15 GND
TI_TPS2220BPWPR_HTSSOP_24P 69- 46 1
25

ACARD_3S_AD16 A17-CAD16 GND

ACARD_3S_A18_RFU 69- 47 68
A18-RFU GND
ACARD_3S_BLOCK# 69- 48 G1
A19-CBLOCK GND
ACARD_3S_STOP# 69- 49 G2
A20-CSTOP GND
DBGND DBGND 69- 50 G3
ACARD_3S_DEVSEL# A21-CDEVSEL GND
ACARD_3S_TRDY# 69- 53 G4
A22-CTRDY GND
ACARD_3S_FRAME# 69- 54
A23-CFRAME
ACARD_3S_AD17 69- 55
A24-CAD17
DBGND DBGND 69- 56
ACARD_3S_AD19 A25-CAD19
DBGND
ACARD_3S_VS2# 69- 57
NC-CVS2
ACARD_3S_RST# 69- 58
RESET-CRST
ACARD_3S_SERR# 69- 59
WAIT-CSERR
ACARD_3S_REQ# 69- 60
INPACK-CREQ
ACARD_3S_CBE3# 69- 61
REG-CCBE3
ACARD_3S_AUDIO 69- 62
BVD2-SP-CAUDIO
ACARD_3S_STSCHG 69- 63
BVD1-STSCHG-C
ACARD_3S_AD28 69- 64
D8-CAD28
ACARD_3S_AD30 69- 65
D9-CAD30
ACARD_3S_AD31 69- 66
D10-CAD31

DAUGHTER BOARD ACARD_3S_CD2# 69- 67

CD2-CCD2

SANTA_130603_2_68P

INVENTEC
TITLE
TIANSHAN
PC CARD SLOT(DB)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 70 OF 74
 VCC_SD VCC_SD
71- 71-

+V3S_DB VCC_SD
73-,72-,70-,69-,68- 71-
Q4002
4 1 1 1 1 1
S D
2 R4029 R4014 R4021 R4028
5 100K_5% 22K_5% 100K_5% 100K_5%
3 G
6
2 2 2 2
1 C4026 FDC638P
2 0.01UF_16V 1 C4025 1 C4027 U4000
2 0.01UF_16V SD_3S_PWREN# 71- C8 E9 71- SD_3S_CD#
2 10UF_10V MC_PWR_CTRL0 SD_CD#
TP15 F8 A4 TP9
MC_PWR_CTRL1 SD_CLK
C5 TP10
SD_CMD
TP16 A8
MS_CD#
SD_3S_CLK 71- A7 C6
1 1 MS_CLK SD_DAT0 1 C4015
SD_3S_CMD 71- E8 A5 TP12
R4033 R4031 MS_BS SD_DAT1
B5 TP13 2 100PF_50V
47K_5% 47K_5% SD_DAT2
E6 TP14
SD_DAT3
DBGND DBGND 71- B6 E7 71-
2 2 SD_3S_DAT3 MS_DATA3 SD_WP SD_3S_WP
SD_3S_DAT2 71- A6
MS_DATA2

SD CARD POWER SD_3S_DAT1

SD_3S_DAT0
71-
71-
C7
B7
MS_DATA1
MS_DATA0
SM_CD#
B8

B4
TP17

TP18
DBGND

SM_CLE
SD_3S_PWREN# 71- A3
SM_PHYS_WP

TI_PCI6612_PBGA_216P

VCC_SD
71-

1 1
R4032 R4030
OPEN OPEN
2 2

CN4002
SD_3S_WP 71- 13 GND 14
71- 10 WP 11
SD_3S_CD# CD GND
71- 1 GND 12
SD_3S_DAT3 CD_DAT3 9
SD_3S_CMD 71- 2 DAT2 71-
3 CMD 8 SD_3S_DAT2 DBGND
VSS1 DAT1 71-
SD_3S_DAT1
4 DAT0 7 71-
R4034 2 VDD 6 SD_3S_DAT0
SD_3S_CLK 71- 1 5 CLK VSS2
33_5%
MLX_67913_0001_14P
1 C4028
2 10PF_50V

DBGND DBGND DBGND

DAUGHTER BOARD

INVENTEC
TITLE
TIANSHAN
SD CARD CONN(DB)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 71 OF 74
 +V3S_DB
CN4001 73-,71-,70-,69-,68-
1 2
GND REVERSED
68- 3 4
AC97_3S_SDOUT_MDC_DB SDO REVERSED L4002
5 6 2 1
GND 3.3VDUAL
AC97_3S_SYNC_MDC_DB 68- 7 8 ICB_1206_3.0A
SYNC GND
AC97_3S_SDIN1_DB 68- 9 10
SDI GND
AC97_3S_RST#_MDC_DB 68- 11 12 68- AC97_3S_BITCLK_MDC_DB
RST# BCLK
G1 G4
G G 1 C4029 1
G2 G5 C4030
G3
G G
G6 1 C6006 2 0.1UF_16V
G G 22UF_4V
2 10PF_50V
ACES_88019_1210_12P

DBGND
DBGND DBGND

DBGND

DAUGHTER BOARD

INVENTEC
TITLE
TIANSHAN
MDC1.5 CONN(DB)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 72 OF 74
 +V3S_DB
72-,71-,70-,69-,68-,73-

2
D4000 +V3S_DB
EVL_19_21_B7C_ZQ1R2_3T_2P
1 72-,71-,70-,69-,68-,73-

R4000
330_5%
2

68- WLN_BT_LED#_DB 2 1
1
R4006 R4008
3 270_5% 270_5% R4007 68-
68- 1G
D
Q4000 OPEN MBDASP#_5_DB
LED_BLUETOOTH_DB 1 2
1 S SSM3K7002F 2 1
2
R4001 2 2
D4003 D4005 3 D4007
100K_1% EVL_21SUYC BAT54A
2 1 1 EVL_YG_19_21_G6C_BM2P1B_3T

2
DBGND DBGND 68-
LED_3S_SATA#_DB
3 D Q4001
68- G 1 68-
LED_WLAN_LINK#_DB 1 2 SCS_751V_40_2P HDD_HALTED_DB
D4001 S
2 SSM3K7002F

WLAN_BLUETOOTH LED HDD & MBAY LED

+V3AL_DB DBGND
+V3AL_DB 68-,73-
68-,73-
+V3AL_DB
1 68-,73-

R4003
10K_5% D4002
EVL_YG_19_21_G6C_BM2P1B_3T
2
68- R4002 1 2 270_5%
STBY_LED#_DB D4004 EVL_21SUYC R4004 1 270_5%
1 2 BAT_AMBERLED#_DB 68- 2
1 2
POWER / STANDBY LED BAT_GRNLED#_DB 68- D4006
1
EVL_YG_19_21_G6C_BM2P1B_3T
2
R4005 1 2 270_5%

BATTERY-CHARGE LED

DAUGHTER BOARD

INVENTEC
TITLE
TIANSHAN
BUTTON&SWITCH&LED(DB)
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 73 OF 74
 FIX1 FIX2

FIX_MASK FIX_MASK

FIX3 FIX4

FIX_MASK FIX_MASK

S36 S37
SCREW2.8_6_5P SCREW2.8_6_5P

DBGND DBGND

S38 S39
SCREW2_3_5_1P SCREW2_3_5_1P

DBGND DBGND

S40 S41
SCREW4.5_6_8_1P SCREW4.5_6_8_1P

DBGND DBGND

INVENTEC
TITLE
TIANSHAN
CARDBUS BOARD SCREW
SIZE CODE DOC. NUMBER REV
A3 CS Model_No A02
CHANGE by Ho,Thomas 25-May-2006 SHEET 74 OF 74