(vicom pM9621 USB2.0 to Fast Ethernet Controller DAVICOM Semiconductor, Inc. DM9621 = USB2.0 to 10/100M Fast Ethernet Controller DATA SHEET Version: DM9621-DS-P02 February 23, 2011DM9621 >} USB2.0 to Fast Ethernet Controller CONTENT 1, Features: 1.1 System Description 2. Block Diagram and Block Description 3. Pin Configuration: 3.1 48- Pin QFN. 3.2 48-pin description 10 3.3 strap pins table... ee 4. Vendor Control and Status Register Set 13 4.1 Network Control Register (00H)... seventies 4 4.2 Network Status Register (01H) .....cscsminustntneienusttistneneseeeses 15 4.3 TX Control Register (02H) 16 4.4 RX Control Register ( O5H ) 16 4.5 RX Status Register ( 06H ) 17 4.6 Receive Overflow Counter Register (O7H ).....c0ecnesnrnnnnnnnennanens 17 4.7 Back Pressure Threshold Register (08H) 18 4.8 Flow Control Threshold Register ( 09H ) 18 4.9 RX/TX Flow Control Register ( OAH ).. 4.10 EEPROM & PHY Control Register ( OBH ).. eesenstntnntnneniensee 4.11 EEPROM & PHY Address Register ( CH ) 20 4.12 EEPROM & PHY Data Register ( EE_PHY_Lm 0DH EE_PHY_Hi OEH ).... 20 4.13 Wake Up Control Register ( OFH )... fevcstnnenentnntniensaniennneesee 20 4.14 Physical Address Register ( 10H~15H ) 20 4.15 Multicast Address Register ( 16H~1DH ) 2 4.16 General purpose control Register ( 1EH ) 24 4.17 General purpose Register ( 1FH ). 24 4.18 Vendor ID Register (28H~29H)... 2 4.19 Product ID Register (24H~2BH) a4 4.20 Chip Revision Register (2CH).... 21 4.21 TX Special Control Register (20H). . sevstetenenstntesees 22, 4.22 Extemal PHY Force Mode Control Register (25H). 22 4.23 Transmit Check Sum Control Register (31H) .-.ccccocessnenrnnnntnnnnenennenes 22 4.24 Receive Check Sum Control Status Register (32H) ...c.c:snssnntnensennnes 23 4.25 External PHY ceiver Address Register (33H) 23 Painvary 2 Version DNBG21 1405-602 any 23 2011(vicom 4.26 General Purpose Control Register 2 (34H) 4.27 General Purpose Register 2 (35H) .-ccecncrnns 4.28 General Purpose Control Register 3 (36H)... 4.29 General Purpose Register 3 (37H) 4.30 EEPROM and PHY Control Register (3AH). 4.31 Pause Packet Control/Status Register (3DH)....... 4.32 Transmit Packet Counter (81H) 4.33 USB Packet Error Counter (82H) 4.34 Ethernet Receive Packet CRC Error Counter (83H). 4.36 Ethernet Transmit Excessive Collision Counter (84H)... 4.36 Ethernet Transmit Collision Counter (85H) ...c.cesneeus 4.37 Ethernet Transmit Late Collision Counter (86H) 4.38 RX Header Control/Status Register (91H) 4.39 USB Squelch Control (95H) .....ssee 4.40 USB Address (96H) 4.41 USB Device Address Register (FOH). 4.42 Receive Packet Counter Register (F1H 4.43 Transmit Packet Counter/UUSB Status Register (F2H) 4.44 USB Control Register (F4H) 5. EEPROM Format: 6. PHY Register Description .. 6.1 Basic Mode Control Register (BMCR) ~ OOH. 6.2 Basic Mode Status Register (BMSR) - 01H 6.3 PHY ID Identifier Register #1 (PHYID1) - 02H.......... 6.4 PHY Identifier Register #2 (PHYID2) - 03H 6.5 Auto-negotiation Advertisement Register(ANAR) ~ O4H 6.6 Auto-negotiation Link Partner Ability Register (ANLPAR) — O5H.... 6.7 Auto-negotiation Expansion Register (ANER)- 06H .. 6.8 DAVICOM Specified Configuration Register (OSCR) — 10H 6.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 11H 6.10 10BASE-T Configuration/Status (10BTCSR) - 12H 6.11 Power down Control Register (PWDOR) - 13H . 6.12 (Specified config) Register - 14H...... 6.13 DSP Control (DSP_CTRL) - 1BH DM9621 USB2.0 to Fast Ethernet Controller 23 23 2 24 24 24 2 24 24 25 25 25 2. 25 25 25 26 26 .. 26 26 26 26 27 .. 28 29 30 31 231 31 wovee 32, 33 33 35 36 36 37 38 Peinray Version DNBG21 1405-602 any 23 2011(> Com pM9621 USB2.0 to Fast Ethernet Controller 6.14 Power Saving Control Register (PSCR) - 1DH 38 7. Functional description ....-ccecenreronennenn 39 7.1 USB Functional description .......c:nsstsnunttinnnsieninetnnnrennseesee 9D 7.1.1 USB Standard Command 39 7.1.2 Vendor ComMANAS .....cocsnenennnnnntnnnnnnsnananennanaseneeeense 40 7.1.2.1 Register Type. eee) 7.1.2.2 Memory Type a 7.1.3 Interface 0 Configuration 42 7.1.4 Descriptor Values 43 7.1.5 Descriptors of string/1/2/3 are loaded from EEPROM... 48 7.2 Ethernet Functional Description.......ss-nstueseniunesene 49 7.2.1 Serial Management Interface 49 7.2.2 100Base-TX Operation. . 50 7.2.3 4B5B ENCOder «cscs . . eevee seve 50 7.2.4 Scrambler 50 7.2.5 Parallel to Serial Converter. 50 7.2.6 NRZ to NRZI Encoder... . eeectenstneeeeese 50 7.2.7 MLT-3 Converter 50 7.2.8 MLT-3 Driver 50 7.2.9 4B5B Code Group 51 7.2.10 100Base-TX Receiver . 52 7.2.11 Signal Detect... 52 7.2.12 Adaptive Equalization 52 7.2.13 MLT-3 to NRZI Decoder... - 52 7.2.14 Clock Recovery Module... 52 7.2.15 NRZI to NRZ. 52 7.2.16 Serial to Parallel . 52 7.2.17 Descrambler..... sessttnstnsetnnstseenntsseessteeneeneteneteneesee seve 82 7.2.18 Code Group Alignment 53 7.2.19 4B5B Decoder 53 7.2.20 10Base-T Operation 53 7.2.21 Collision Detection . 53 7.2.22 Carrier Sense... eesseeneene sesstersessstensennatnsetseesseesnsenseees 8B 7.2.23 Auto-Negotiation. 53 Peinray 4 Version DNBG21 1405-602 any 23 2011(> com pm9621 USB2.0 to Fast Ethernet Controller 7.2.24 Auto-Negotiation (continued) 53 8, DC and AC Electrical Characteristics .... octencnninnmnnnennnnnnnenensense Bf 8.1 Absolute Maximum Ratings (25°C ) 54 8.1.1 Operating Conditions 54 8.2 DC Electrical Characteristics (VDD = 3.3V)..... 55 8.3 AC Electrical Characteristics & Timing Waveforms ... sosntnnensenestesee BS 8.3.1 TP Interface 55 8.3.2 Oscillator/Crystal Timing 56 9. AC Timing waveform 87 9.1 Power On Reset Timing. ..57 9.2 EEPROM timing... 58 9.3 RMII TX timing 59 9.4 RMII RX timing ...... soseeeeassannnnen . 59 10. Magnetic and Crystal Selection Guide. . seessennstnsesseteseee seve 60 10.1 Magnetic Selection Guide. 60 10.2 Crystal Selection Guide 60 11. Application Circut..... 62 12. Package Information 65 13. Ordering Information 66 Peinray Version DNBG21 1405-602 any 23 2011(> 1. Features: COM DM9621 USB2.0 to Fast Ethernet Controller @ USB Interface USB2.0 Device Supports 12Mbps Full-Speed operation Supports 480Mbps High-Speed operation Supports suspend mode and remote wake-up Resume Supports USB standard commands Supports vendor specific commands Efficient TX/RX FIFO auto management. Supports 4 endpoints (Control, interrupt, Bulk_IN, Bulk_OUT) Supported Classes2._ USB Common Class / USB Communications Class - Ethernet Support |EEE802.3u 100BASE-TX and with IEEE802.3 10BASE-T standards ‘Support IEEE802.3x flow control function for 100BASE-TX and 10BASET. Built-in 10/100Mbps Fast-Ethernet PHY with Auto-MDIX Supports RMIl interface or 8 pins GPIO Support Auto-negotiation function Back Pressure Mode for half-duplex mode flow Control PAUSE frame for full-duplex flow control Supports GPIO, wakeup frame, link status change and Magic packet events for remote wake-up Support TCP / UDP / IP checksum offload checking and generating @ EEPROM Interface Supports 128/256/512 bytes (93C46/93C56/93C66) of serial EEPROM(for storing USB Descriptors) 93C46/93C56/93C66 auto-detection © LED Indications Ethemet — Link / Act indication Ethemet - Speed (10M / 100M) indication USB speed indication (full / high speed + traffic modes) © Clock Single 25MHz / 30 ppm crystal or oscillator Optional 12MHz crystal for USB Peinray Version DNBG21 1405-602 uy 23(> GaN pMg621 USB2.0 to Fast Ethernet Controller © Power Input + Low-Power, Single-Supply 3.3V, 0.18um CMOS Technology . Built in 3.3V to 1.8V regulator @ = Miscellaneous + Very Low Power Consumption in suspend mode . Power Reduced mode (cable detection), and Power Down mode = Compatible with 5.0V tolerant /O 1.4 System Description The DIM9621 USB to 10/100Mbps Fast Ethernet controller is a high performance and highly integrated ASIC with embedded SSRAM for packet buffering. It enables low cost and affordable Fast Ethernet network connection to desktop, notebook PC, and embedded system using popular USB ports. Ithas an USB interface to communicate with USB host controller and is compliant with USB specification V1.0, V1.1 and V2.0. It implements 10/100Mbps Ethernet LAN function based on IEEE802.3, and IEEE802.3u standards. M9621 integrates an on-chip 10/100Mbps Ethernet PHY to simplify system design and provides an optional Reduce media-independent interface (RMI). Peinray 7 Version DNBG21 1405-602 uy 23COM DM9621 USB2.0 to Fast Ethernet Controller 2. Block Diagram and Block Description Br eure (5 oaeax N EO FIFO hat usa, SE sRaM Ethernet pay NI Bulk ™ a umMt oot ee FEO EEPROM interface T EEPROM Peinray Version DNBG21 1405-602 any 23 2011USB2.0 to Fast Ethernet Controller (vicom pM9621 3. Pin Configuration: 3.1 48- Pin QFN. z= Zz. 889. Sno ,w@FEaaagg avbSaiee ess SxesSkePs G5 aa Soe VCC3A i vec3 GND CLK50M RREF EECS DM EECK DP EEDIO VCC33_PLL - DM9621NP Molo GND_PLL MDC VCCOUT RXDV veces GND x2 RXDO x1 RXD1 GND TXDO Oe ekooeebhus SRR ER EZ Ar ARR o92 xX a oF ooo er 8 Zz z & k Panay Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 3.2 48-pin description |= Input, _O= Output__\/O = Input / Output,_O/D = Open Drain, _P = Power. Pin No. Pin Name Type Description " JPEN ° ISPIO2_0 in GPIO mode 12,13 |TXD[1:0] © = |TXD[1] as GPIO2_1 in GPIO mode [TXD[O] es GPIO2_2 in GPIO mode 7 pe (Ear moe JEEPROM Interface |USB Interface Spo Ee or aaa internal PLL, detail see 3.3 strap pins table(Page 12) Version DNBG21 1405-602 any 23 201(Sv COM [CED intertace DM9621 USB2.0 to Fast Ethernet Controller USB LED lActive low for USB HS mode 27 JUSB_LED © |Ficating for USB FS mode Fash if traffic on USB ISPEED LED 28 |spo_ep © |Active low for Ethernet 100M Floating for Ethernet 10M Link LED lActive low for Ethernet link 29 [LNK_LED © Floating for Ethernet noncink Flash if traffic on Ethernet [107100 PHY 1 [BGGND P__ [Band gap ground 2 [BGRES WO _ [Bandgap pin. Connect 6.88K 196 resister to GND. 3__[RXVODOUT © _[f8V power out for RX a (Re | [TPRXinput 5 RX 1 [TP RX input @ __|RXGND P__|RXgrouna 7__[TXGND P__|Tx ground 8 (ie © [TP Tx output ei © [TP Tx output 10 |TxvDDOUT © _ [1.8 power out for TX power Miscellaneous [Serial Management Interface Data 25 [SMLD VO [Tie to ground in application [Serial Management Interface Clock. 26 {suck VO [Tie to ground in application [This pin can also as a GPIO wakeup event defined in register OFH. IVEUS input $2 \veus_IN | Tie to high in bus power mode 33__ [wou © _ [issue @ wake-up signal when wake-up event happens. : Hardware Reset Ss RSTe | Ipctive low signal to initiate the DM9621 31_[rest2 |__|Test Mode 2, tie to ground in application [Define Pint1-15, 17-18 mode 30 {rest 1 fo Rv {i GPIO controlled by registers 34H~35H Power 2445 (VCC3 P__ [Distal voc 3.3 1648 [GND P__ [Digital GND Pamrasy 1" Version DNBG21 1405-602 any 23 2011(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 3.3 strap pins table 4 pul-high 1K=10K,_0: default floating PinNo. | __ PinName Description 2 TROT] [0 EEPROM type auto-detection 1: EEPROM force to 0348 type 3 TXDIO] [RX packet header format 0: S-byte Ethemet RX packet header mode! ‘The 3 bytes in Ethemat RX packet header are RX_status, byte_etr_low, ‘and byte_ctt_high respectively 1: 4doyte Ethemet RX header mode The 4 bytes in Ethernet RX packet header are RX _flag, RX_status, byte_ctr_low, and byte_ctr_high respectivel 2 EECS _[0: 12MHz clock from internal PLL 11: 12MHz clock from external crystal Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 4. Vendor Control and Status Register Set ‘The DME621 implements several contol and status values by hardware or softare reset unless othenvise registers, which can be accessed by he USB vendor specifed register ype commands. Al ORs are set to their defeut Register Description ontset Peraurrvaue NGR__| Network Conrel Register OOH OH NSR | Network Status Register O1H OOH TR | TX Conte! Register 2H OOH RR | RX Control Register 05H OOH RSR | RX Status Register 06H Oot ROCR | Receive Overfow Counter Register o7H OOH BPTR | Back Pressure Threshold Rogster 03H 37H FCTR | Flow Control Threshold Registor 08H 3H FOR | RX Flow Contol Register OAH OOH EPCR | EEPROM & PHY Control Register oBH oH EPAR | EEPROM & PHY Aderess Register ocH 40H EPORL | EEPROM & PHY Low Byie Dota Ragiior oDH Unicow EPORH | EEPROM & PHY High Byte Dela Register O=H Unicow WER Wake Up Control Register OFH OH PAR | Physeal Address Register 70-16H Determined by EEPROM WAR | Wuticast Adress Register TaD ‘c000000000000 080 (SPOR | General Purpese Cone Reaister a) OH GPR | General Purpose Register FH nineamn Vib | Vendor iD 23H. 26H (OAASH PID__| Product DAH-2BH 21H CHER | CHP revision 2cH OH TSCR | TX Special Contel Register 20H OOH TCSCR__| Transmit Check Sum Control Register 3H OOH RCSCSR | Receive Check Sum Control Status Regisior 32H OOH ‘GPCRO| General Purpose Contol Resistor? 3H OOH ‘GPRO__| General Purpose Registor2 3H OOH EEP_CTRL_| EEPROM and PHY Control Register SAH OOH PECER _ | Pause Packet Cont Siatus Register 30H aH TXGTR__| Transmit Pecket Counter 3iH (OOH UPERR | USS Packet ror Courter aH OOH GRC_CTR_| Ethemet Receive Packet ORG Ero’ Counter 33H OOH EXCOL_CTR | Etheme! Transmit Excessive Colson Courter aah OOH COL GTR _| Ethemet Transmit Calision Counter aH OOH LCOL_CTR_| Ethemet Transmit Late Colison Counter 35H OOH MODE CTL_| Mode Conte 3H (OOH SQUELCH | USB squelch Gontel 35H oH USE_ADR [USS Address 35H OH Peinvery 8 Version DNBG21 1405-602 any 23 2011(Sv COM DM9621 USB2.0 to Fast Ethernet Controller USBDA | USB deviee address register FOH, (00H RXC____| Received packet counter register FAH, (0H TXCIUSBS_| Transmit packet counter"USB status register FH 10H USBC | USB contol register FAH (00H Key to Defautt Inthe register description that follows, the defaut coluran fault value from EEPROM takes the form: fefauit value from strap pin , Access Type>: Where RO=Read only column takes the form RO = Read only Reset Value>, «Access Type> / RW = Read/Write Where Reset Value> SC = Seif clearing 4 Bit set to logic one P = Value permanently set 0 Bit set to logic zero LL = Latehing low x No default value LH = Latching high (PIN#) Value latched in from pin # at reset Pawnee % Version DNBG21 1405-602 any 23 2011DM9621 USB2.0 to Fast Ethernet Controller Mode Control Register (BMCR) - 00H SitName — [Default Desergion Reset Sctvare reset isc |@=Nermel eperaion 15 | Reset / 0, RWISC |Fri Sr ete the satus and contol the PHY registers to ther éotut states The bt which seltclenring, wl Keep returning & Salus of one ul he fset process's complied Loopback: [sop back contr registr {ST sop-tack enabled 14 Loopback 0,RW [0 = Normal operation nenin oohops operation mode, sting is it may cause the eescrambler to xe syrenvonzaon end produce a 1S0cme "end Sm’ befor any all data appear a he hl receive outputs Speed select: 1 = 100Mbps- a= toubpe 13 | Speed selection | 1, RW [Py Speed maybe selected ether by this itor by autonagotiaion Wnen avto-negctation enabled and bi 12 sel, te vl tum fautonegetaton slcted media {pe Auto-negotiation eneie: 12 [Avtoregotaion! 5 ay |f'tautesnagstiaionseneled bit @ and 13 wil bein autownegataton tats Power Down: nie inthe pover-dovn eae, the PHY should respond to Inenegomentansactone. During the tension to power doom 11 | Ponerdoon | 0, Ww |stte sna uni inthe power-down sate, the PHY shoud not Generate spunovs signals on he Ml over don osha! operation isolate 10 | twoite | omw. [ts ecletes Resened) [a= Norma! eperaton Restart automegotaion ['cRester aulosegotaton, Reiss the auo-nagoteton process When autonegotaton Is dsebld (ot 12 of i egster Restart |cleared), this bit has no function and it should be cleared. This bit is 2 | sueRett gn | ORWISC [settclearng and wilkoupreumng avalue of unt auto-negehaton riteod by the PRY. The sprain of the auto-negetion process vil tbe afocted bythe management erty tat oar tne Bt 6 Normal eperaon uplex mods: } aru plex operation, Ouplx selection is alowed when Astomegotaton o deabled bt 12 of ne eptei cteared). Vth 8 | Duplexmede | RW [AU regoltion enabled, ths i reflects the duplex capably selected by auto-negotiation Normal eperaion Collision est 7 | cotsiontest | ow [1 Colison est enabled. When se, this bit wil cause the COL signals bo asserted in vesponce tothe asseten of EN Pane 2 tron Cec. s208202 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller I= Normal operation Reserved: 60 | RESERVED | ORO [rite as 0, ignore on read 6.2 Basic Mode Status Register (BMSR) ~ 01H Bit BitName | Default Description TOOBASE-Té capable: 18 | 100BASE-T4 | O.ROIP |1=Able to perform in 100BASE-T4 mode 10 = Not able to perform in 100BASE-T4 mode : 00BASE-TX full duplex capable: 14 | TOBASET™ | 1ROIP |1 = Able to perform 100BASE-TX in full duplex mode [0 = Not able to perform 100BASE-TX in full duplex mode 100BASE-TX half duplex capable: 13 | 1POBASE"TX | 1.ROIP |1 = Able to perform 100BASE-TX in half duplex mode Pl 0 = Not able to perform 100BASE-TX in half duplex mode 10BASE-T full duplex capable: 12 Hirassox | ROMP |1'= Able to perform 10BASE-T in full duplex mode Pl |0 = Not able to perform 10BASE-TX in full duplex mode TOBASET 0BASE-T half duplex capabl 1" fatdape | bROIP |1 = Able to perform 10BASE-T in half duplex mode Pl 10 = Not able to perform 10BASE-T in half duplex mode Reserved: 107 | RESERVED | ORO _livrite as 0, ignore on read Hl frame preamble suppression: MF preamble 1 = PHY will accept managoment frames with preamble suppressed 8 suppression | RO |o = Hy will not accept management frames with preamble suppressed ‘ation ‘Auto-negotiation complete: 5 |Avtgnegetiaton | oq | S'automegetiaton process completed er 0 = Auto-negotiation process not completed Remote fault: 11 = Remote fault condition detected (cleared on read or by a chip im reset), Fault criteria and detection method is PHY implementation ‘ Remote fault | OROMH | pccifc. This bitwill set after the RF bitin the ANLPAR (bit 13, register address 05) is set [0 = No remote feult condition detected ‘Auto configuration ability: 3 [Attenegotaton | yom {sable teperorm eutonegotiion [0 = Not able to perform auto-negotiation Link status: /1 = Valid link is established (for either 10Mbps or 100Mbps loperation) |O= Link is not established 2 Link status | OROILL Irie ink status itis implemented with a latching function, so that the occurrence of a ink failure condition causes the link status bit to be cleared and remain cleared until its read via the management interface Relay, Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller Jabber detect, O.RO/LH Wabber detect: 1 = Jabber condition detected (0 = No jabber ‘This bit is implemented with a latching function. Jabber conditions |will set this bit unless it is cleared by a read to this ragister through @ management interface or a PHY raset. This bit works only in OMbps mode Extended capability 1,ROIP Extended capability: 11 = Extended register capable lo asic register capable on) 6.3 PHY II D Identifier Register #1 (PHYID1) - 02H The PHY Identifier Registers #1 and #2 work togather in a single identifier of the DM9621. The Identifier consists, of @ concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00806E. Bit Bit Name, Default Description (OUI most significant bits: 150 | umes | , [OUl least significant bits: 1610 | OULLSB ROD [Bit 19 to 24 of the OUI (00806E) are mapped to bit 18 to 10 of this register respective \Vendor model number: 8-4 | VNDR_MDL | <001011>, | six bits of vendor mode! number mapped to bit 9 to 4 (most ROP |significant bitto bit 9) occa», [Model revision number: 3.0 | MDL_REV Roe’ [Four bts of vendor model revision number mapped to bit 3 10 0 (most significant bit to bit 3) 6.5 Auto-negoti n Ad ivertisement Register(ANAR) ~ 04H This register contains the advertised abilities of this DM8621 device as they will be transmitted to its link partner during Auto-negotiation, Bit BitName, Default Description [Next page indication: yp [0 =Nonext page available 15 NP ORO |1 = Next page available ‘The PHY has no next page, so this bit is permanently set to 0 Acknowledge: 1 = Link partner ability data reception acknowledged JO = Not acknowledged 14 ACK ORO |The PHY’s auto-negotiation state machine will automatically, control this bit in the outgoing FLP bursts and sett at the appropriate time during the auto-negotiation process. Software should not attempt to write to this bit. Peinray 3 Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 13 RF Remote fault: 1 = Local device senses a fault condition 10 = No fault detected 12-41 RESERVED Reserved: Write as 0, ignore on read 10 Fos Flow control support: 1 = Controller chip supports flow control ability [0 = Controller chip doesn't support flow control abit 14 0, ROP 400BASE-T4 support: 1 = 100BASE-Té is supported by the local davice 0 = 100BASE-T4 is not supported ‘The PHY does not support 100BASE-T4 so this bit is permanently [set to 0 TX_FDX 1,RW 100BASE-TX full duplex support: 1 = 100BASE-TX full duplex is supported by the local device 0 = 100BASE-TX full duplex is not supported TX_HDX 1, RW 100BASE-TX suppor 1 = 100BASE-TX is supported by the local device. 0 = 100BASE-TX is not supported 10_FDX 1.RW 10BASE-T full duplex support: 1 = 10BASE-T full duplex is supported by the local device 0 = 10BASE-T full duplex is not supported 10_HDX 1,RW 10BASE-T support: 1 = 10BASE-T is supported by the local device 0 = 10BASE-T is not supported 4-0 6.6 Auto-1 Selector <00001>, RW negotiation Link Partner Abil This ragister contains the advertised abilities of the link partner when received during Auto-negotiation Protocol selection bits: ‘These bits contain the binary encoded protocol selector supported by this node. }<00001> indicates that this device supports IEEE 802.3 CSMAICD. lity Register (ANLPAR) - 05H Bit Bit Name, Default Description, 15 NP 0,RO Next page indication: JO = Link partner, no next page available 1 = Link partner next page available 14 ACK 0,RO Acknowledge: 1 = Link partner abilty data reception acknowledged JO = Not acknowledged The PHY’s auto-nagotiation state machine will automatically [control this bit from the incoming FLP bursts. Software should not attempt to write to this bit. 13 RF 0,RO Remote Fault: 1 = Remote fauit indicated by link partner 10.= No remote fault indicated by link partner 12-11 RESERVED X,RO Reserved Write as 0. ignore on read 10 Fos oRW Flow control support: 411= Controller chip supports flow control ability by link partner Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethemet Controller (0 = Controller chip doesn't support flow control abilty By Ink partner 9 14 0,RO 100BASE-T4 support: 1 = 100BASE-Té is supported by the link partner 0 = 100BASE-Ts is not supported by the link partner 8 TX_FDX 0,RO 00BASE-TX full duplex support: 1 = 100BASE-TX full duplex is supported by the link partner [0 = 100BASE-TX full duplex is not supported by the link partner 7 TX_HOX 0,RO 400BASE-TX support 1 = 100BASE-TX half duplex is supported by the link partner 0 = 100BASE-TX half duplex is not supported by the link partner 6 10_FOX 0,RO 10BASE-T full duplex support: 1 = 10BASE-T full duplex is supported by the link partner 0 = 10BASE-T full duplex is not supported by the link partner 5 10_HDX 0,RO 10BASE-T support: 1 = 10BASE-T half duplex is supported by the link partner 0 = 10BASE-T half duplex is not supported by the link partner 4 Selector 6.7 Auto-negotiation Ex <00000>, RO Link partner's binary encoded protocol selector ansion Register (ANER)- 06H Protocol selection bits: Bit Bit Name Default, Description, Reserved 158 |_RESERVED X/RO__|Write as 0, ignore on read Local device parallel detection fault 4 POF ©. ROILH ‘A fault detacted via perallel detection function ): No fault detected via parallel detection function Link partner next page able: 3 | LPLNPLABLE| 0,RO —|LP_NP_ABLE = 1 : Link partner, next page available LP_NP_ABLE = 0 : Link partner, no next page Local device next page able: 2 NP_ABLE OROIP |NP_ABLE = 1 : next page available NP“ABLE = 0 : no next page New page received: 1 PAGE_RX | 0,ROJLH [Anew link code word page received. This bit wll be automatically cleared when the register (register 6) is read by management. Link partner auto-negotiation able’ 0 | LPLAN_ABLE} 0,RO_—_|A“1"in this bit indicates that the link partnar supports |Auto-nagotiation, 6.8 DAVICOM Specified Configuration Register (OSCR) - 10H Bit__| BitName | Default Description’ [Bypass 4858 encoding and 5B4B decoding : 15 BP_ABSB O,RW — |1= 4858 encoder and 5848 decoder function bypassed 0 = Normal 4B58 and SB4B operation Bypass scrambler/descrambler function 14 BP_SCR o.RW — |1= Scrambler and descrambler function bypassed (0 = Normal scrambler and descrambler operation 3 |e Rw _ [Bypass symbol alignment functio 1 = Receive functions (descrambler, symbol alignment and Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller [symbol decoding functions) bypassed. Transmit functions | symbol encoder and scrambler) bypassed 10. = Normal operation BYPASS ADPOK Force signal detector (SD) active. This register is for debug only, 12 | 8P_ADPOK 0, RW |not release to customer. 1=Force SD is OK, [O=Normal operation Reserved: " RESERVED 9. RO Write as 0. ignore on read. OOBASE-TX or FX mode control: 10 1% 4,RW |= 100BASE-TX operation 0 = 100BASE-FX operation 9 RESERVED 0, RO Reserved Reserved: 8 RESERVED 0.RO_|\Write as 0, ignore on read Force good link in 100Mbps: Jo = Normal 100Mbps operation 7 FLLINK_100 ORW 1 = Force 100Mbps good link status his bit is useful for diagnostic purposes 5 Reserved: 8 RESERVED ORO Write as 0, ignore on read. 5 RESERVED 0,RO Reserved: Write as 0. ignore on read. Reduced power down control enable: This bit is used to enable automatic reduced power down, 0: Disable automatic reduced power down. 1: Enable automatic reduced power down, Reset state machine: 3 SMRST 0, RW [When writes 1 to this bit, all state machines of PHY will be reset. This bit is selfclear after reset is completed. MF preamble suppression control: Mil frame preamble suppression control bit 4 | RPDCTREN | 1,RW 2 MFPS ‘RW /1 = MF preamble suppression bit on 0= ME preamble suppression bit of Sleep mode: Writing a 1 to this bit will cause PHY entering the Sleep mode and 4 SLEEP fo, rw _ |Powerdowm all cireuit except oscilator and clock generator circuit When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset 0 Reserved CRW [Reserved Force to 0 in application Peinray Version DNBG21 1405-602 any 23 201(vicom DM9621 USB2.0 to Fast Ethernet Controller 6.9 DAVICOM Specified Configuration and Status Register (DSCSR) ~ 11H Bit Bit Name, Default Description, 15 100FDX 4, RO 700M full duplex operation mode: |After auto-negotiation is completed, results will be writen to this bit. If this bit is 1, it means the operation 1 mode is @ 100M full duplex mode. The software can read bit{15:12] to see which mode is selected after auto-negotiation. This bit is invalid when itis not in Ithe auto-nagotiation mode, 14 100HDX 1, RO 100M half duplex operation mode: |After auto-negotiation is completed, results will be writen to this bit. I this bit is 1, it means the operation 1 mode is a 100M half duplex mode. The software can read bit{15:12] to see which mode is selected after auto-negotiation. This bit is invalid when itis not in the auto-negotiation mode, 13 10FDX 4, RO 10M full duplex operation mode: |After auto-negotiation is completed, results will be written to ths bit. I this bit is 1, it means the operation 1 mode is a 10M Full Duplex mode, The software can read bit{15:12] to see which mode is. selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode. 12 10HOX 4, RO '10M half duplex operation mode: |After auto-negotiation is completed, results will be writen to this bit. If this bit is 1, it means the operation 1 mode is a 10M half duplex mode. The software can read bit{15:12] to see which mode is selected after auto-negotiation. This bit is invalid when itis not in Ithe auto-nagotiation mode, RESERVED 0, RO Reserved: Write as 0, ignore on read PHYADR(4:0] (PHYADR), RW PHY address Bit 4:0: [The first PHY address bit transmitted or raceived is the MSB of the address (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY. 3.0 ANMB[3:0] 0.RO 'Auto-negotiation monitor bits: [These bits are for debug only. The auto-negotiation status will be lwrittan to these bits. 3 TRIDLE state ‘Ability match “Acknowledge match ‘Acknowledge match fail Consistency match Consistency match fail Parallel detects signal_ link ead) Parallel detects signal_link_ready fail ‘Auto-negotiation completed successful Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 6.10 10BASE-T Configuration/Status (10BTCSR) - 12H Bit_| BitName | Default Description 5 Reserved: 18 | RESERVED | 0.RO | write as 0. ignore on read Link pulse enable: 1 = Transmission of link pulses enabled 0 = Link pulses disabled, good link condition forced This bit is valid only in 1OMbps operation. Heartbeat enable: 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the PHY is configured for fll duplex operation, this bit wll be ignored (the colision/heartbeat function is invalid in full duplex mode), ‘Squelch enable = 12 | squeLcn 4,RW | 1 =normal squeich 0-= low squelch Jabber Enable: Enables or disables the Jabber function when the PHY is in 1“ JABEN 4, RW | 10BASE-T full duplex or 10BASE-T traneceiver leopback mode 4 = Jabber function enabled 0 = Jabber function cisabled Reserved: CRO | Write as 0. ignore on read Polarity reversed: o.Ro | When this bitis set to 1, it ingicates that the 10Mbps cable polarity is reversed. This bit is set and cleared by 10BASE-T module automatically 6.14 Power down Control Register (PWDOR) ~ 13H 14 LPLEN 1. RW 13 HEE RW 401 | RESERVED 0 POLR Bit__| BitName | Default Description 15 | Reserved 0,RO |Reserved 2 Read as 0. ignore on witite 8 PD10DRV | 0, RW__|Vendor power down control test z PptoopL_| 0, RW _|Vendor power down control test 6 PDchip 0, RW__|Vendor power down control test 5 PDcom O.RW__|Vendor power down control test 4 PDaeq 0, RW__|Vendor power down control test 3 PDdrv 0, RW__|Vendor power down control test 2 PDedi 0, RW__|Vendor power down control test 1 PDedo 0, RW__|Vendor power down control test o PD10 O.RW__|Vendor power down control test * When selected, the power down value is control by Register 14H Peinray Version DNBG21 1405-602 any 23 2011(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 6.12 (Specified config) Register ~ 14H Bit Bit Name Defautt Description 15 TSTSE1 O.RW __|Vendor test select control 14 TSTSE2 O.RW _|Vendor test select control 13 |FoRCE_TxsD| oRW — |Force Signal Detect 1: force SD signal OK in 100M (0: normal SD signal 12__| Force Fer | _o.Rw _|Vendor test select control Preamble Saving Control 11 | PREAMBLEX | RW Jo: when bit 10 is set, the 10BASE-T transmit preamble count is reduced, When bit 11 of register 1DH is set, 12-bit preamble is reduced; otherwise 22-bit preamble is reduced. 4: transmit preamble bit count is normal in 10BASE-T mode 1OBASE-T mode Transmit Power Saving Control 10° | TX1OM_PWR | RW |: enable transmit power saving in 10BASE-T mode 0: disable transmit power saving in 10BASE-T mode [Auto-negotiation Power Saving Control 8 | NWAY_PWR | ORW Ih" disable pover saving during auto-negotiation period (0: enable power saving during auto-negotiation period 8 Reserved ORW [Reserved 7 MDIX_CNTL |MDIMDIX,RO| The polarity of MDIMDIX value 1: MDIX mode lO: MDI_mode 6 | AutoNeg_Ipbk | O,RW | Auto-negotiation Loop-back 1: test internal digital auto-negotiation Loop-back (0: normal. 6 | Mdixfx Value} 0, RW | MDIX_CNTL force value: When Mdix_down = 1, MDIX_CNTL value depend on the register valus. 4 |Mdixdown|” ORW |MDIX Down Manual force MDI/MDIX. 1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5 (0: Enable HP Auto-MDIX 3 MonSelt O.RW _|Vendor moniter select 2 MonSeld O.RW _|Vendor monitor select 1 Reserved oRW _|Reserved Peinray 9 Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller [Force to 0. in application. 0 PD_value O.RW — |Power down control value Decision the value of each field Register 13H 1: power down 0: normal 6.13 DSP Control (DSP_CTRL) - 1BH Bit_| BitName | Default Description 18-0 | DSP_cTRL| 0.RW [DSP CONTROL For internal testing onl 6.14 Power Saving Control Register (PSCR) - 1DH Bit Bit Name Default Description. 15-12 _| RESERVED ORO [RESERVED 11 | PREAMBLEX | O,RW [Preamble Saving Control lwhen both bit 10and 11 of register 14H are set, the 10BASE-T transmit preamble count is reduced, 41: 12-bit preamble is reduced. 0: 22-bit preamble is reduced. 10 | AMPLITUDE ORW [Transmit Amplitude Control Disabled 4: when cable is unconnected with link partner, the TX amplitude is reduced for power saving 0: disable Transmit amplitude reduce function 3 TK PWR ORW _ |Transmit Power Saving Control Disabled 1: when cable is unconnected with link partner, the driving current| lof transmit is reduced for power saving. 0: disable transmit driving power saving function &0 | RESERVED ORO [RESERVED Peinray Version DNBG21 1405-602 any 23 201(vicom DM9621 USB2.0 to Fast Ethernet Controller 7. Functional description 7.4 USB Functional description 7.4.4 USB Standard Command 1. Supported Standard Command Setup Stage Data Stage BmRegType BRequest wValue windex _|_wLength Data ‘00000008 Zero Feature oogso0018 | CLEAR_FEATURE Interface Zero None a | Selector. [— 000000108, Endpoint 400000008 |GET CONFIGURATION] Zero Zero One _| Configuration value Descriptor 100000008 | GET_DESCRIPTOR ZerolLID | Length Descriptor typerindex. 100000018 | _GET_INTERFACE Zero Interface One | Alternate Interface 100000008 Zero 100000018 GET_STATUS Zero Interface Two Status 100000108 Endpoint 000000008 SET_ADDRESS _|Device address| Zero Zero None Configuration ooaca0008 | SET_CONFIGURATION ' Zero Zero None Descriptor ooeaen908 | SeT_DEScRIPTOR | ZeroiLiD | Length Descriptor ppelindex. 000000008 f Zero eature 000000018, SET_FEATURE Interface Zero None Selector 00000108 Endpoint Alternate ooacc0018 | SET_INTERFACE Interface Zero None setting 100000108 | SYNCH FRAME: Zero Endpoint Two Frame Number Peinray % Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 2. Not Supported Standard Commands + Clear_Feature (Interface) + Set_Feature (Interface) * Set_Descriptor () * Sync_Frame () 7.4.2 Vendor commands ‘There are two types of vendor's command. We can access internal register maximum 64 bytes, 7.4.24 Register Type READ_REGISTER() and can access internal memory. Setup Stage BmReqType __bReq Wvalue windex wLength ByteO Byte Byte? | ByteS ——Byled Byte Bytes Byte 7 COW QOH _00H_| 00H __RegOfise{7:0)_00H__BCI7:0]_ OOH WRITE_REGISTER() Setup Stage BmRegType| bReq | wvalue wingex wiengin | Byteo | eyte1 | Byte2 | Bytes | Byted | Bytes| Bytes| Byte 7 40H iH | ooh | coh | RegOfisey7:0)/ OOH | BCI7:0| 00H WRITE1_REGISTER( ) Setup Stage BmReqType _bReq Wvalue windex wlength ByteO Byte 1 40H OSH Byte2 Byte 3 Data{7:0]__ 00H Byte4 Byte Byte Byte7 RegOffset{7:0] 00H ‘00004 Peinray Version DNBG21 1405-602 any 23 201DM9621 USB2.0 to Fast Ethernet Controller (Sv COM 7.1.2.2 Memory Type ‘Theses kind of commands are valid! when the bit respond with request error when receiving these 'MEM_MODE “is set, otherwise device will commands READ_MEMORY() Setup Stage BmReqtype|_Breq wvalue Windex wLength ByteO | Byte1 | Byte2 Bytes Byted ByteS | Bytes Byte 7 CoH 02H 00H 00H__MemOrii7-0]__ Memori{1s:8) | BC{7:0)_ 00H WRITE_MEMORY() Setup Stage IBmReqType| BReq __ WValue Windex wlength, Byto0 | Byte1 Byte2 Byte3 Byted Byte 5 Byte6 Byte 7 40H OSH OOK 00H __MemOfi{7.0)_ Memoft5.8)_BC(7-0)__ OOH WRITE1_MEMORY() Setup Stage Emre Bre wvalue windex wLength Byie0 _|Byte1| Byte? | Bytes | Bytes Byte 5 Byte | Byte7 40H | o7H |Datei7-0)|_ 00H | Memor7-0) | Memonq15:8) (0000H Relay, 4 Version DNBG21 1405-602 any 23 201(Sv COM 7.1.3 Interface 0 Configuration Definition: len-byte is 64-byte in full speed mode and 256-byte in high speed mode, 4. Endpoint 4 DM9621 USB2.0 to Fast Ethernet Controller Type: Bulk In Packet Padioad: len-byte When host accessing EP1 I IN-FIFO is full, device will send len-byte data. IFIN-FIFO isn't full and Ethernat packet isn't end, device will send a NAK IFIN-FIFO isn't full and Ethernet packet is end, device will send the surplus data in IN-FIFO. Data Format For 3-byte header mode Fist byte Ethemet Receive Packet Status, the bit format is same as register 6 (RSR) Second byte: Ethemet Receive Packet byte count low Third byte Ethernet Receive Packet byte count high The others: Ethernet Receive Packet Data For 4-byte header mode (if pin GPIO2_2 is pull-high) Fist byte Second byte Ethernet Receive Packet Status, the bit format is same as register 8 (RSR) Third byte: Ethernet Receive Packet byte count low Fourth byte: Ethernet Receive Packet byte count high The others: Ethemet Receive Packet Data Ethemat Receive Packet Checksum Status, the bit{7:2] format is same as register 32H (RCSCSR) 2. Endpoint 2 Type: Bulk Out Packet Padload: len-byte When host accessing EP2, If OUT-FIFO isn't full, host sends data, device response ACK, If OUT-FIFO is full, host sends data, device response NAK If host sends data less len-byte or zero byte, it means Ethernet packet end Data Format First byte Ethernet Transmit Packet byte count | Second byte: Ethernet Transmit Packet byte count high The others: Ethernet Transmit Packet data 3. Endpoint 3 Type: Interrupt In Packet Load: 8-byte When host accessing EP3, Hf no interrupt condition, device response NAK. interrupt condition, device will send content back to hest. Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller Data Format ‘Offset | Name Description ByteO | _NSR Network status register Byte? | TSR Reserved Byte2 | TSR2 Reserved Byte3 | _RSR RX status ragister Byte 4 | ROCR Received overflow counter register Byte5 | RXC Received packet counter Byte6 | TXC Transmit packet counter Byte7 | GPR Reserved 7.4.4 Descriptor Values All descriptors are stored in i’s default values, Values which are "7" in the table below are under define Device Descriptor/18-Byte Offset Field Size Value Description 0 _[bLenath 1| 12H _|size of descriptor in bytes 1 _bDescristorType ___1__O1M_DEVICE Descriptor Type 2 beeuse. 2 | 0200H USB BCD version pDevieeClass 1 | 00H Class code, assign by USB Zero: No device level class OTH-FEH : Valid davice class FFH : Vender-specifc 5 _bDeviceSubCiass ___1___O0H SubClass code. assign by USB 6 bDeviceProtecol 1 OOH Protocol code, assign by USB 7_bMaxPacketSizeO 1 08H Maximum PL for EPO(@,16,32,64) 8 idVender 2 OABH Vendor ID(0A46) (fm EEP) 10 idProduce 2 goat Podustl® 9621H, RX header is 4-byte mode 12 [bedDevice 2 O101H Device release number 14 _|iMemufacturer 1 | 01H __Index of string descriptor for manufacturer 18 Product 1_| 02H _ Index of string descriptor for product 16 _iSerialNumber 1 03H _ Index of string descriptors for serial number 17 _bNumConfigurations _1_O1H_ Number of configurations Painvary g Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller Configurationo Descriptor/9-Byte Offset Field Size_Value Description 0 _bLength 1__08H Size of descriptors 1 __bDescriptorType 1 02H_ CONFIGURATION Descriptor Type. 2__\wTotalLength 2 0027H Total descriptor length 4 _bNuminterfaces 1 01H Number of interfaces 5 _bConfigurationVelue 1 | O1H Value of this configuration 6 _iConfiguration 1___00H _Index of string descriptor for configuration 7__bmAttributes 1__A(8)0H (Configuration characteristics D7-Reserved (set to 1) D6: Selt-powered DS: Remote WakeUp 0: f REGOOH bits is “0 4:f REGOOH bit 6 is “1” Dd: Reserved ( reset to 0) MaxPower 3CH__Maximum power, 2mA units (fm EEP) Interface0 Descriptor/9-Byte Offset Field Size Value Description, 0 _blength 1___09H __ Size of this descriptor 1 bDescriptorType 1 Q4H INTERFACE Descriptor Type 2__binterfaceNumber 1 00H Number of interface 3__bAlternateSetting 1___00H Value used to select alternate setting 4__bNumEndpoints 1___03H__Number of ednpoints 5 _bbinterfaceClass 1 | 00H Class code. 6 _binterfaceSubClass 1 OOH _SunClass code 7 _ binterfaceProtocol 1 00H Protocol code 8 interface 1 00H _ Index of string for this interface. Peinray 4 Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller Endpointt Descriptor/6-Byte loftset Field Size_Value Description, 0 |btengtn 1___O7H Size of this descriptor 1 |bDescriptorType 1 | OSH ENDPOINT Descriptor Type 2 |bEndpointAddress 1 81H Address of the endpoint Bit3~0:_ The endpoint number Bit 6~4: Reserved(0) Bit7 : Direction(Control EP exclude) 0= OUT endpoint 1.=IN endpoint 3 lbmAttributes 1 02H EP's attributes Biti~0: Transfer Type 00 = Centro} 01 = Isochronous 10 = Bulk terrupt Maximum packet size of this EP (0200H for high speed) 4 |wMaxPacketSize 2 0040H 6 |binterval 1 00H _ Interval for poling (periodical pipe) (fm EEP) Interrupt Tpye = ~ 255 (ms) Isochronoous Type = 1 (ms) Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller Endpoint 2 Descriptori6-Byte lortset| Field Size Value Description © lbtength 1 | 07H Size ofthis descriptor 1_[bDeseriptorType 15H ENDPOINT Deseriptor Type 2 _|bEndpointAddress_1 | 02H Address of the endpoint Bit3~0:_ The endpoint number Bit 6~4: Reserved(0) Bit7 : Direction(Control EP exclude) o te UT endpoint IN endpoint 3 |bmAttributes 1_02H EP's attributes Bit1~0: Transfer Type 00. ‘ontrol 01 = Isochronous 10 = Bulk 11 = Interrupt Maximum packet size of this EP (0200H for high speed) 6 _|binterval 1 00H _ Interval for poling (periodical pipe) (fm EEP 4 |\wMaxPacketsize —-2-—»0040H Interrupt Tpye = 1 ~ 255 (ms) Isochronoous Type = 1 (ms) Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller Endpoint3 Descriptor/6-Byte loftset Field Size_Value Description, 0 |btengtn 1___O7H Size of this descriptor 1 |bDescriptorType 1 | OSH ENDPOINT Descriptor Type 2 |bEndpointAddress 1 83H Address of the endpoint Bit3~0:_ The endpoint number Bit 6~4: Reserved(0) Bit7 : Direction(Control EP exclude) 0= OUT endpoint 1.=IN endpoint 3 lbmAttributes 1 03H EP's attributes Biti~0: Transfer Type 00 = Centro} 01 = Isochronous 10 = Bulk terrupt lwMaxPacketSize 2 | OO08H Maximum packet size ofthis EP interval 1 01H _ Interval for polling (periodical pipe) Interrupt Tpye = 1 ~ 255 (ms) Isochronoous Type = 1 (ms) StringO DescriptoriCode array Offset ield size |_Value Description 0 blength 1 04H Size of tis descriptor 1__bDescriptorType | 1 | 03H ___ STRING Descriptor Type 2 wLANGIDIH) 2 | 0408H_LANGID code(Eng.) Painveny a Version DNBG21 1405-602 any 23 201DM9621 (Buicom USB2.0 to Fast Ethernet Controller 7.1.5 Descriptors of string/1/2/3 are loaded from EEPROM String! Descriptor/UNICODE String Offset Field Size__Value Description 0 _bLength 1 Descriptor length loading from EEPROM 1__[bDescriptorType, 1 03H __|STRING Descriptor Type. 2x _bStrin fn Manufacture ‘String2 Descriptor/UNICODE String Offset Field __—Size_ Value Description 0 _bLengtn 1 Descriptor length loading from EEPROM 1 bDescriptorType_1 03H __|STRING Descriptor Type 2+ _bSting 5 Product ‘String3 Descriptor/UNICODE String Offset___Field Size Value Description 0 _bLength 1 Descriptor length loading from EEPROM 1 _bDescriptorType| 1 03H __STRING Descriptor Type 2+ lbString 2 Serial Number Descriptors of string/1/2/3 if no EEPROM exist. String? Descriptor/UNICODE String Offset Field Size__Value Description 0 _blength 1___04H _Deseriptor length 1 bDescriptorType 1 03H __|STRING Descriptor Type 2s _bString 200204 |Manutacture ‘String? Descriptor/UNICODE String Offset Field Size__Value Description 0 _blength 1 10H Descriptor length 1 bDescriptorType, 1 03H __ [STRING Descriptor Type. 2x _bString 14 155 00 53 00 42 00 20.00 45 00 74 0068.00 Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller ‘String3 Descriptor/UNICODE String Offset Field Size__Value Description 0 _blength 1___04H Descriptor length 1_bDescriptorType| 1 03H __ [STRING Descriptor Type 2s bString 2 0031H Serial Number 7.2 Ethernet Functional Description 7.2.4 Serial Management Interface DM9621 li SMI mpc ———> mpc PHY MDIO +——> MDIO Extemal PHY can be accessed via the MDC, MDIO SMI - Reed Frame Structure Peinray #@ Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 7.2.2 100Base-TX Operation ‘The block diagram in figure 3 provides an overview of the functional blocks contained in the transmit section. ‘The transmitter section contains the following functional blocks: - 4B5B Encoder = Scrambler - Parallel to Serial Converter - NRZ to NRZI Converter = NRZI to MLT-3 = MLT-3 Driver 7.2.3 4B5B Encoder ‘The 4858 encoder converts 4-bit (48) nibble data generated by the MAC Reconciliation Layer into a Sebit (5B) code group for transmission, reference Table 1. This conversion is required for control and packet data to be combined in code groups. The ‘4B5B encoder substitutes the first 8 bits of the MAC. preamble with a JK code-group pair (11000 10001) pon transmit. The 4858 encoder continues to replace subsequent 4B preamble and data nibbles ‘with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of the Transmit Enable signal from the MAC Reconciliation layer, the 4858 encoder injects the T/R code-group pair (01101 00111) indicating endl of frame. After the TR code-group pair, the 4B58 encoder continuously injects IDLEs into the transmit data stream until ‘Transmit Enable is asserted and the next transmit packet is detected ‘The DM9621 includes a Bypass 4358 conversion option within the 100Base-TX Transmitter for support of applications like 100 Mbps repeaters which do not require 4B58 conversion. 7.2.4 Scrambler ‘The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX operation By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies related to repeated 5B sequences like continuous transmission of IDLE symbols. The scrambler output is combined with the NRZ 58 data from the code-group encoder via an XOR logic function, The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. 7.2.5 Parallel to Serial Converter, ‘The Parallel to Serial Converter receives parallel 6B scrambled data from the scrambler and serializes it (converts it from a parallel to a serial data stream). ‘The serialized data stream is then presented to the NRZ to NRZI Encoder block 7.2.6 NRZ to NRZI Encoder After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable 7.2.7 MLT-3 Converter ‘The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two binary data streams with alterately phased logic one events. 7.2.8 MLT-3 Driver ‘The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver which converts these streams to current sources and alternately drives either side of the transmit transformer primary winding resulting in @ minimal current MLT-3 signal. Refer to figure 4 for the block diagram of the MLT-3 converter. Peinray Version DNBG21 1405-602 any 23 2011(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 7.2.9 4B5B Code Group Meaning Data 0 '0000" Data 1 ‘0001 Data 2 (0010 Data 3 ‘0011 Data 4 ‘0100 Data 5 ‘0101 Data 6 O10 Data 7 ont Data 6 1000 Data & 1001 Data A 1010 Data 8 1011 Data C 1100 Data D 1101 Data E 1110 oO 1 2 3 4 5 8 7 3 2 A & c D E F Data F 111 Tale undefined SFO 101 SFD (2) ‘101 ESD (1 undefined ESD (2 undefined x2] 5}x[e|— Error undefined Invalid undefined Invalid undefined, Invalid undefined! Invalid undefined Invalid Undefined Invalid undefined Invalid undefined Invalid undefined Invalid undefined <|<|<\<|<|<]<]<|<|< Invalid undefined Tablet Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 7.2.10 100Base-Tx Receiver ‘The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data that is then provided to the Mil ‘The receive section contains the following functional blocks: = Signal Detect, = Digital Adaptive Equalization - MLT-3 to Binary Decoder = Clock Recovery Module - NRZI to NRZ Decoder + Serial to Parallel - Descrambler + Code Group Alignment - 4B58 Decoder 7.2.11 Signal Detect ‘The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX Standards for both voltage thresholds and timing parameters, 7.2.12 Adaptive Equalization When transmitting data at high speeds over copper twisted pair cable, attenuation based on frequency becomes a concem. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomnass of the scrambled data stream This variation in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will be over-kill in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore, the compensation cr equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length 7.2.13 MLT-3 to NRZI Decoder The DIMG621 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZi data, The relationship between NRZI and MLT-S data is shown in figure 4. 7.2.14 Clock Recovery Module ‘The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125Mhz reference clock. The extracted and synchronized clock and date are prasented to the NRZI to NRZ Decoder. 7.2.15 NRZI to NRZ. ‘The transmit data stream is required to be NRZI encoded in for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the Clock Recovery Module and converts it to 2 NRZ data stream to be presented to the Serial to Parallel conversion block. 7.2.16 Serial to Parallel ‘The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter, and converts the data stream to parallel data to be presented to the descrambler. 7.247 Descrambler Because of the scrambling process required to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The descrambler receives scrambled parallel data streams from the Serial to Parallel converter, descrambles the data streams, and presents the data streams to the Code Group alignment block, Peinray Version DNBG21 1405-602 any 23 2011(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 7.2.18 Code Group Alignment ‘The Code Group Alignment block receives un-aligned 5B deta from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the JIK is detected, and subsequent data is aligned on a fixed boundary. 7.2.19 4B5B Decoder ‘The 4B5E Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data. When receiving a frame, the first 2 5-bit code groups received are the start-of-frame delimiter (J/K symbols). The JIK symbol pair is stripped and two nibbles of preamble pattern are substituted. The last ‘two code groups are the end-of-frame delimiter (T/R. symbols) The T/R symbol pair is also stripped from the nibble presented to the Reconciliation layer 7.2.20 10Base-T Operation ‘The 10Base-T transceiver is IEEE €02.3u compliant. ‘When the DM8621 is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented to the Ml interface in nibble format, converted to a serial bit stream, then Manchester encoded. When receiving, the Manchester encoded bit stream is decoded and converted into nibble format for presentation to the Mil interface. 7.2.21 Collision Detection For haif-duplex operation, a collision is detected ‘when the transmit and raceive channels are active simultaneously. When a collision has been detected, it will be reported by the COL signal on the Mil interface. Collision detection is disabled in Full Duplex operation, 7.2.22 Carrier Sense Carrier Sense (CRS) is asserted in half-duplex ‘operation during transmission or reception of data. During full-duplex mode, CRS is asserted only during receive operations. 7.2.23 Auto-Negotiation ‘The objective of Auto-negotiation is to provide a means to exchange information between segment linked devices and to automatically configure both devices to take maximum advantage of their abilities, Itis important to note that Auto-negotiation does not test the link segment characteristics. The Auto-Negotiation function provides a means for a device to advertise supported modes of operation to @ remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation, This allows devices on both ends of a segment to establish a link atthe best common mode of operation. If more than ‘one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function. 7.2.24 Auto-Negotiation (continued) ‘Auto-negotiation also provides a parallel detection, function for devices that do not support the Auto-negotiation feature. During Parallel detection there is no exchange of configuration information, instead, the receive signal is exemined. Ifitis discovered that the signal matches a technology that the receiving device supports, a connection will be automatically established using that technology. This allows devices that do not support Auto-negotiation but support a common mode of operation to establish alink. Peinray Version DNBG21 1405-602 any 23 2011(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 8. DC and AC Electrical Characteristics 8.1 Absolute Maximum Ratings (25°C ) ‘Symbol Parameter Min. Max. Unit Conditions Dv00 [Supply Voltage 03 36 Vv 4 VN IDC Input Vettage (IND asf ss [Vv 2 Vout ]D€ Output Vetage(vOUT) “03 [ 36 Vv 2 Ts [Storage Temperature range EJ +150 °C a Tr [Ambient Temperature ne oe : L lead Temperature ~ | 260 | 36 t (Lr, soldering, 10 sec.) “TPowerpn 20pm 8.1.1 Operating Conditions symbol Parameter Min, Typ. | Max. | Unit | Conditions Dvoo _|Supply Voltage 3.135 | 3300 _| 3465 |v Po | 100BASE-TX = 170 _ mA. 3.3 (Power 1OBASE-T TX _ 190 = mA, 3.3V) Dissipation) |10BASE-T idle - 100 _ ma | 3.3V.power saving JUSB suspend mode = 2.48 = mA. 3.3V Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 8.2 DC Electrical Characteristics (VDD = 3.3V) Symbol Parameter Min. | Typ. | Max. | Unit Conditions Inputs Vit__| input Low Vokage - | - | os |v Vi Input High Voltage 2.0 - - Vv is Input Low Leakage Current 1 - - uA VIN = 0.0V. tis | Input High Leakage Current -|- 1 [a VIN=3.3V outputs Vou _| output Low Voltage - | - [oa [iv 1OL= ama, vou _| output High Voltage 2a | - - tv IOH = -dma Receiver view] RX#IRX- Common Mode Input - fray. dv 100.9 Termination Voltage Across Transmitter vroro | 1007X+/: Differential Output 19 | 20 ] 21] v Peak to Peak Voltage vroio_| 10TX+/-Ditferential Output Voitage | 44 | 6 | 56 | v Peak to Peak rroso0 | 1007X4/- Differential Output 119] | [20 | [21] | ma Absolute Value Current 10TX#/- Diferential Output Current Absolute Value 8.3 AC Electrical Characteristics & Timing Waveforms TP interface symbol Parameter min__| typ. |Max._| unit | Conditions tree _| 100TX+/ Differential Rise/Fall Time so | - | 50 | ne tm | 1007X+s Diferential Rise/Fall Time 0 - | os | ns Mismatch troc_ | 100TX+/ Differential Output Duty Cycle ° - | 05 | ns Distortion Tut | 100TX+/ Differentil Output Peakto-Peak | 0 - | 14 | ons Jitter Pamrasy % Version DNBG21 1405-602 any 23 2011(Sv COM USB2.0 to Fast Ethernet Controller xost_| 100Tx. % 8.3.2 OscillatoriCrystal Timing symbol Parameter min. | Typ] Max.) Unit ) Conditions Tox | OSC Clock Cycle Bosses | 40) 400012 | ne ppm Tewh | OSC Pulse Width High : 20 : ns Tewt__| OSC Pulse Width Low 20 z As Peinray Version DNBG21 1405-602 any 23 201(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 9. AC Timing waveform: 9.1 Power On Reset Timing n — n —4 PWRST# an ——— a Tt fe acs nA State Parameter Power on reset time 15 T2 PWRST# Low Period 5 - - ms: 13 Strap pin setup time with PWRST#| 40 - - nS - Ta ‘Strap pin hold time with PWRST# | 40 : 5 nS : TS PWRST# high to EEOS high = 1 : us : 76 PWRST# high to EECS burstend | __- =| 735 [ms i Peinray 7 Version DNBG21 1405-602 any 23 2011(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 9.2 EEPROM timing " EEK $4 L 1 1 be EEDIO [J = nm as ‘Symbol Parameter Min.) Typ.) Max. Unit Ti__EEOS Hold Time 42 us 2 EECK Frequency 5.12 us 13 EEDIO Hold Time in output state 42 us T4__EEDIO Setup Time in input state 8 ns 75 EEDIO Held Time in input state 1 ns Painveny Version DNBG21 1405-602 any 23 201COM (> 9.3 RMII TX timing DM9621 USB2.0 to Fast Ethernet Controller cuKsoM 56 L ve [$$ —— oft re. $$ ‘Symbol Parameter Min. | Typ. | Max. [Unit Ti XE TxD 1-0 Delay Time Z ns. 9.4 RMII RX timing cLKsoM $6 L mxov $$ m R ae | 72 RX0_1-0 $$ ‘Symbol Parameter Min. Typ.) Max. [Unit Ti RXDV|AXD_1=0 Setup Time 3 ns. 12 RXDV.RXD_1~0 Hold Time 2 ns Peinray Version DNBG21 1405-602 uy 23(Sv COM DM9621 USB2.0 to Fast Ethernet Controller 10. Magnetic and Crystal Selection Guide 10.1 Magnetic Selection Guide Refer to Table 1 for transformer requirements. Transformers, meeting these requirements, are available from a variety of magnetic manufacturers Designers should test and qualify all magnetic before using them in an application. The transformers listed in Table 1 are electrical equivalents, but may not be pin-to-pin equivalents. Designers should test and qualify all magnetic specifications before using them in an application. RoHS regulations, please contact with your magnetic vendor, this table only for you reference Manufacturer Part Number DELTA LFE8505-DC , LFE8S63-DC, LFE8583-DC MAGCOM HS9016, HS9024 Halo TG110-SO50N2, TG110-LC50N2 Bel Fuse $558-5999-W2 Table 1 10.2 Crystal Selection Guide A crystal can be used to generate the 25MHz reference clock instead of an oscillator. The crystal must be a fundamental type, and series-resonant. Connects to pins X1 and X2, and shunts each crystal lead to ground with a 15pf capacitor (see figure 10-1). PARAMETER ‘SPEC Type Fundamental, series-resonant Frequency 25.000 MHz +/- 30ppm Equivalent Series Resistance | 25 ohms max Load Capacitance 22 BF typ. Case Capacitance T pF max. Power Dissipation mW max. Peinray Version DNBG21 1405-602 any 23 201