L4973

3.5 A step down switching regulator

Datasheet - production data

• Thermal shutdown
• Output over voltage protection
• Soft-start function

SO-20 (12+4+4)
Description
The L4973 is a step down monolithic power
Features switching regulator delivering 3.5 A at fixed
voltages of 3.3 V or 5.1 V and using a simple
• Up to 3.5 A step down converter external divider output adjustable voltage up to 50
• Operating input voltage from 8 V to 55 V V. Realized in BCD mixed technology, the device
uses an internal power D-MOS transistor (with a
• 3.3 V and 5.1 V (±1 %) fixed output, and
typical RDS(on) of 0.15 Ω) to obtain very high
adjustable outputs from:
efficiency and very fast switching times.
– 0.5 V to 50 V (3.3 type) Switching frequency up to 300 kHz are
– 5.1 V to 50 V (5.1 type) achievable (the maximum power dissipation of
• Frequency adjustable up to 300 kHz the packages must be observed).
A wide input voltage range between 8 V to 55 V
• Voltage feed forward
and output voltages regulated from 3.3 V to 40 V
• Zero load current operation (min. 1 mA) cover the majority of the today applications.
• Internal current limiting (pulse by pulse and Features of this new generation of DC-DC
HICCUP mode) converter includes pulse by pulse current limit,
hiccup mode for output short circuit protection,
• Precise 5.1 V (1.5%) reference voltage
voltage feed forward regulation, soft-start,
externally available
input/output synchronization, protection against
• Input/output synchronization function feedback loop disconnection, inhibit for zero
• Inhibit for zero current consumption (100 mA current consumption and thermal shutdown.
typ. at VCC = 24 V) Package available is SO-20 (12+4+4) for SMD
assembly.
• Protection against feedback disconnection

Figure 1. Application circuit

9&& 9WR9
  &%227

526& 

 / 92 9RU9

&,1 &  /

   

5&203
&26& &66 ' &287

&&203

',1$

May 2024 DocID1546 Rev 19 1/25

This is information on a product in full production. www.st.com
Contents L4973

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2/25 DocID1546 Rev 19

L4973 Block diagram

1 Block diagram

Figure 2. Block diagram

,1+ 9 9&& 9&&

   
&%227
&+$5*(

=(52&855(17 95() ,17(51$/

,17(51$/ 9
,1+,%,7 *22' 9 6833/<
5()(5(1&(
9


62)7 +,&&83&855(17
66
67$57 /,0,7,1*

&203
7+(50$/ &855(17
6+87'2:1 /,0,7,1*
9 %227
9  5 4 
($ 
9)%  3:0 6 4
 

6<1& 26&,//$725

'5,9(5

   

26& *1' 287 287 ',1%

DocID1546 Rev 19 3/25

25
Pin settings L4973

2 Pin settings

2.1 Pin connection

Figure 3. Pin connection (top view)

OSC 1 20 SYNC
OUT 2 19 SS
OUT 3 18 V5.1
GND 4 17 GND
GND 5 16 GND
GND 6 15 GND
GND 7 14 GND
VCC 8 13 VFB
VCC 9 12 COMP
BOOT 10 11 INH
D94IN163A

SO20 (12+4+4)

4/25 DocID1546 Rev 19

L4973 Pin settings

2.2 Pin description

Table 1. Pin description

N° Pin Name Description

12 COMP E/A output to be used for frequency compensation

A logic signal (active high) disables the device (sleep mode operation).
11 INH If not used it must be connected to GND; if floating the device is
disabled.
A capacitor connected between this pin and the output allows to drive
10 BOOT
the internal D-MOS.
20 SYNC Input/Output synchronization.
8,9 VCC Unregulated DC input voltage
2,3 OUT Stepdown regulator output.
Stepdown feedback input. Connecting the output directly to this pin
results in an output voltage of 3.3 V for the L4973V3.3 and 5.1 V for
L4973V5.1. An external resistive divider is required for higher output
13 VFB
voltages. For output voltage resistive divider is required for higher
output voltages. For output voltage less than 3.3 V, see Note: and
Figure 30.
18 V5.1 Reference voltage externally available.
4,5,6,7
GND Signal ground
14,15,16,17
An external resistor connected between the unregulated input voltage
1 OSC and Pin 1 and a capacitor connected from Pin 1 to ground fixes the
switching frequency. (Line feed forward is automatically obtained)

Note: The maximum power dissipation of the package must be observed.

DocID1546 Rev 19 5/25

25
Electrical data L4973

3 Electrical data

3.1 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

V9,V8 Input voltage 58 V

Output DC voltage -1 V
V2,V3
Output peak voltage at t = 0.1 µs f = 200 kHz -5 V
I2,I3 Maximum output current int. limit.
V10-V8 14 V
V10 Bootstrap voltage 70 V
V12 Analogs input voltage (VCC = 24 V) 12 V
V19 Analogs input voltage (VCC = 24 V) 13 V
6 V
V13 (VCC = 20 V)
-0.3 V
5.5 V
V20 (VCC = 20 V)
0.3 V
VCC V
V11 Inhibit
-0.3 V
Ptot Power dissipation a Tpins = 90 °C 4 W
TJ,TSTG Junction and storage temperature -40 to 150 °C

3.2 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

RthJP Maximum thermal resistance junction-pin 15 °C/W

RthJA Maximum thermal resistance junction-ambient 80 (1) °C/W
1. Package mounted on board

6/25 DocID1546 Rev 19

L4973 Electrical characteristics

4 Electrical characteristics

Table 4. Electrical characteristics

(Refer to the test circuit,VCC = 24 V; TJ = 25 °C, COSC = 2.7 nF;
ROSC = 20 kΩ; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit

Dynamic characteristics
Input voltage range (1) VO = VREF to 40 V; IO = 3.5A (2)
8 55 V
IO = 1 A 5.05 5.1 5.15 V
Output voltage
IO = 0.5 A to 3.5 A VCC = 8 V 5.00 5.1 5.20 V
L4973V5.1
to 55 V (2) 4.95 5.1 5.25 V
IO = 1 A 3.326 3.36 3.393 V
Output voltage
IO = 0.5 A to 3.5 A VCC = 8 V 3.292 3.36 3.427 V
L4973V3.3
to 40 V (2) 3.26 3.36 3.46 V
0.15 0.22 Ω
RDS(on ) VCC = 10.5 V IO = 3.5 A
(2)
0.35 Ω
(2)
Maximum limiting 3.8 4.5 5.5 A
VCC = 8 V to 55 V
current 4 4.5 5.5 A
VO = 5.1 V; IO = 3.5 A 90 %
η Efficiency
VO = 3.3 V; IO = 3.5 A 85 %
(2)
Switching frequency 90 100 110 kHz
Supply voltage ripple Vi = VCC+2 VRMS VO = Vref;
60 dB
rejection IO = 1 A; fripple = 100 Hz
Switching frequency
∆fsw stability vs., supply VCC = 8 V to 55 V 2 5 %
voltage
Reference section

Iref = 0 to 20 mA; 5.025 5.1 5.175 V

Reference voltage
VCC = 8 to 55 V (2) 4.950 5.1 5.250 V
Iref = 0 mA;
Line regulation 5 10 mV
VCC = 8 to 55 V
Vref = 0 to 5 mA; 2 10 mV
Load regulation
VCC = 0 to 20 mA 6 25 mV
Short circuit current 30 65 100 mA

DocID1546 Rev 19 7/25

25
Electrical characteristics L4973

Table 4. Electrical characteristics (continued)

(Refer to the test circuit,VCC = 24 V; TJ = 25 °C, COSC = 2.7 nF;
ROSC = 20 kΩ; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit

Soft-start
Soft-start charge current 30 45 60 µA
Soft-start discharge
15 22 30 µA
current
Inhibit
(2)
High level voltage 3.0 V
(2)
Low level voltage 0.8 V
Isource high level VINH = 3 V (2) 10 16 50 µA
Isource low level VINH = 0.8 V (2) 10 15 50 µA
DC characteristics
Total operating
Duty cycle = 50 % 4 6 mA
quiescent current
Quiescent current Duty cycle = 0 2.7 4 mA

Total stand-by quiescent VCC = 24 V; VINH = 5 V 100 200 µA

current VCC = 55 V; VINH = 5 V 150 300 µA
Error amplifier
High level output voltage 11.0 V
Low level output voltage 0.65 V
Source bias current 1 2 3 µA
Source output current 200 300 600 µA
Sink output current 200 300 µA
VCOMP = VFB
Supply voltage ripple
CREF = 4.7 µF 1-5 mA load 60 80 dB
rejection
current
DC open loop gain RL = ∞ 50 60 dB
Icomp = -0.1 to 0.1 mA;
Transconductance 2.5 mS
Vcomp = 6 V
Oscillator section
Ramp valley 0.78 0.85 0.92 V
VCC = 8 V 1.9 2.1 2.3 V
Ramp peak
VCC = 55 V 9 9.6 10.2 V
Maximum duty cycle 95 97 %

8/25 DocID1546 Rev 19

L4973 Electrical characteristics

Table 4. Electrical characteristics (continued)

(Refer to the test circuit,VCC = 24 V; TJ = 25 °C, COSC = 2.7 nF;
ROSC = 20 kΩ; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit

Duty cycle = 0%;

Maximum frequency 300 kHz
ROSC =13 kΩ; COSC = 820 pF;
Sync function
High input voltage VCC = 8 V to 55 V 3.5 V
Low input voltage VCC = 8 V to 55 V 0.9 V
Slave sink current 0.15 0.25 0.45 mA
Master output amplitude Isource = 3 mA 4 4.5 V
Output pulse width No load, Vsync = 4.5 V 0.20 0.35 µs
1. Pulse testing with a low duty cycle
2. Specifications referred to TJ from -40 °C to 125 °C.

DocID1546 Rev 19 9/25

25
Application circuit L4973

5 Application circuit

Figure 4. Application circuit (D5.1)

9&& ,1+ 6<1&

5 
  
&

 /'
& & & / 9R
  
  

& & & ' [ &

5 &
&

',1$

Figure 5. Application circuit (D3.3)

9&& ,1+ 6<1&

5 
  
&

 /'
& & & / 9R
  
  

& & & ' [ &

5 &
&

',1$

10/25 DocID1546 Rev 19

L4973 Typical characteristics

6 Typical characteristics

Figure 6. Quiescent drain current vs. Figure 7. Quiescent drain current vs.
input voltage (0% duty cycle) junction temperature

Ibias D97IN633A Ibias D97IN634

(mA) (mA)
200KHz-R2=22K 200KHz-R2=22K
C7=1.2nF C7=1.2nF
5.0
Tamb=25˚C
0% DC
4.0
4.5
100KHz-R2=20K
4.0 C7=2.7nF
100KHz-R2=20K
C7=2.7nF
3.5
0% DC
3.5 VCC = 35V

0Hz
3.0
3.0
0Hz

2.5

2.0 2.5
0 10 20 30 40 50 VCC(V) -50 0 50 100 Tj(˚C)

Figure 8. Stand by drain current vs. input Figure 9. Reference voltage vs. junction
voltage temperature (pin 16)

Ibias D97IN635A VREF D97IN637

(µA) (V)

Vinh = 5V Pin 16

5.15
150

Vcc=35V
25˚C
5.1
100
125˚C

5.05
50

5.0
0 10 20 30 40 50 VCC(V) -40 -20 0 20 40 60 80 100 Tj(˚C)

DocID1546 Rev 19 11/25

25
Typical characteristics L4973

Figure 10. Reference voltage vs. Figure 11. Reference voltage vs.
input voltage (pin 16) reference input current

VREF D97IN636A VREF D97IN638

(V) (V)

Tj=25˚C
Pin 16
5.15 5.2

Vcc=40V

5.1 5.1
Vcc=10V

5.05 5.0
Tj=25˚C

5.0 4.9
0 10 20 30 40 50 VCC(V) 0 10 20 30 40 50 IREF(mA)

Figure 12. Inhibit current vs. inhibit Figure 13. Line regulation (see Figure 4)
voltage (pin 10)

Iinh D97IN651 VO D97IN639A

(µA) (V)

Vcc=35V Tj=0˚C
Pin 10
100 5.12
Tj=125˚C

˚C
25
Tj=

5.1 Tj=25˚C
50

Tj=125˚C

0 5.08
IO = 1A

-50 5.06
0 5 10 15 Vinh(V) 0 10 20 30 40 50 VCC(V)

12/25 DocID1546 Rev 19

L4973 Typical characteristics

Figure 14. Load regulation (see Figure 4) Figure 15. Line regulation (see Figure 5)

VO D97IN640 VO D97IN660A
(V) (V)

VCC = 35V 3.35

5.15
Tj=125˚C
3.34
Tj=125˚C
Tj=25˚C
5.1 3.33
Tj=25˚C

3.32
5.05 IO = 1A
3.31

5.0 3.3
0 1 2 3 IO(A) 0 10 20 30 40 50 VCC(V)

Figure 16. Load regulation Figure 17. Switching frequency vs.

R2 and C7

VO D97IN661 fsw D97IN630

(V) (KHz)
VCC = 35V 500 Tamb=25˚C
3.35
0.8
2nF
200
3.34 1.2
Tj=125˚C nF
100
2.2
3.33 nF

50 3.3n
F
Tj=25˚C
3.32
4.7n
20 F
5.6n
F
3.31
10

3.3 5
0 1 2 3 IO(A) 0 20 40 60 80 R2(KΩ)

DocID1546 Rev 19 13/25

25
Typical characteristics L4973

Figure 18. Switching frequency vs. Figure 19. Switching frequency vs.
input voltage junction temperature

fsw D97IN631 fsw D97IN632

(KHz) (KHz)

Tamb=25˚C

105 105

100 100

95 95

90 90
0 10 20 30 40 50 VCC(V) -50 0 50 100 Tj(˚C)

Figure 20. Dropout voltage between pin Figure 21. Efficiency vs. output voltage
7,8 and 2,3

∆V D97IN643 η D97IN641
(V) (%)

Tj=125˚C
98
100KHz
C
0.6 5˚
Tj
=2 96

94
200KHz
0.4 92
Tj=0˚C

90
0.2 IO = 3A
88 VCC = 50V

86
0
0 1 2 3 IO(A) 0 10 20 30 40 VO(V)

14/25 DocID1546 Rev 19

L4973 Typical characteristics

Figure 22. Dropout voltage between pin Figure 23. Efficiency vs. output voltage
7,8 and 2,3

∆V D97IN643 η D97IN641
(V) (%)

Tj=125˚C
98
100KHz
C
0.6 5˚
Tj=2 96

94
200KHz
0.4 92
Tj=0˚C

90
0.2 IO = 3A
88 VCC = 50V

86
0
0 1 2 3 IO(A) 0 10 20 30 40 VO(V)

Figure 24. Efficiency vs. output voltage Figure 25. Efficiency vs. output current
(Diode STPS745D) (see Figure 4)

η D97IN642 η D97IN645
(%) (%)

98 VO = 5.1V
100KHz fsw = 100KHz
96 95
Vcc=12V

94 200KHz

90 Vcc=24V
92

90
Vcc=48V
IO = 3A
85
88 VCC = 35V

86
80
0 5 10 15 20 25 30 VO(V) 0 1 2 3 IO(A)

DocID1546 Rev 19 15/25

25
Typical characteristics L4973

Figure 26. Efficiency vs. output current Figure 27. Efficiency vs. output current
(see Figure 4) (see Figure 5)

η D97IN646 η D97IN644
(%) (%)

Vcc=12V VO = 3.3V
fsw = 100KHz
90 90
Vcc=24V Vcc=12V

85 85 Vcc=24V

Vcc=48V

80 80 Vcc=48V
VO = 5.1V
fsw = 200KHz

75 75
0 1 2 3 IO(A) 0 1 2 3 IO(A)

Figure 28. Efficiency vs. output current Figure 29. Power dissipation vs. input
(see Figure 5) voltage (device only)
(see Figure 4)

η D97IN662 Pdiss D97IN647A

(%) (W)
VO = 5.1V
fsw = 100KHz
VO = 3.3V
90 fsw = 200KHz
1.5
Vcc=12V
IO=3.5A

85
IO=3A
Vcc=24V
1.0
80
IO=2.5A
Vcc=48V

0.5 IO=2A
75

70 0
0 0.5 1 1.5 2 2.5 3 3.5 IO(A) 0 10 20 30 40 50 Vcc(V)

16/25 DocID1546 Rev 19

L4973 Typical characteristics

Figure 30. Power dissipation vs. output Figure 31. Pulse by pulse limiting current
voltage (device only) vs. junction temperature

Pdiss D97IN648 Ilim D97IN652

(W) (A)

3.0 5.2
VCC = 35V IO=3.5A
fsw = 100KHz
2.5
5
2.0 IO=3A

4.8
1.5 IO=2.5A Vcc=35

4.6
1.0 IO=2A

0.5 IO=1A 4.4

0 4.2
0 5 10 15 20 25 30 VO(V) -40 -20 0 20 40 60 80 100 120 Tj(˚C)

Figure 32. Load transient Figure 33. Line transient

IO D97IN649 VCC D97IN650

(A) (V)
3 30

2 20

1 10
T
VO VO
2 1
(mV) (mV)
200µs/DIV
IO = 1A
100 fsw = 100KHz
100
T
1 0 2 0

VCC = 35V -100 -100

fsw = 100KHz 1ms/DIV

Figure 34. Source current rise and fall Figure 35. Soft-start capacitor selection
time, pin 2, 3 vs. inductor and VCC max (ref. AN938)

Lomax D97IN653
(µH)
Css=1µF
Css=820nF
300
fsw = 100KHz

250
Css=680nF

200

Css=470nF
150

100 Css=220nF

50 Css=100nF

0
25 30 35 40 45 50 Vi(V)

DocID1546 Rev 19 17/25

25
Typical characteristics L4973

Figure 36. Soft-start capacitor selection Figure 37. Open loop frequency and
vs. inductor and VCC max (ref. AN938) phase of error amplifier

Lomax D97IN654 GAIN D97IN663

(dB) Phase
(µH)

8nF

F
6n
s=6

5
s=
fsw = 200KHz 50

Cs
Cs
GAIN
150
0

nF
0

47
s=
Cs
100 -50 45
3nF
s =3
Cs
-100 90
50 nF Phase
22
s=
Cs -150 135

0 -200
15 20 25 30 35 40 45 50 Vi(V) 10 102 103 104 105 106 107 108 f(Hz)

18/25 DocID1546 Rev 19

L4973 Application ideas

7 Application ideas

Figure 38. 3.5 A at VO < 3.3 V

93 5 5
 . .
 . . 5
9&& ,1+ 6<1& 92 x
 . . 5
 . .
5 
  
&  . .

 /' / 9R

& & & 
   

5 5
' [
& & 5 &
&
&

',1$

Figure 39. 12 V to 3.3 V high performance buck converter (fsw = 200 kHz)
,1+ 6<1&

9&& 5
9“   & K
N  
Q) 

&  /' /

Q)
 
&  
X)9    9R 9
&
+)4 ,R $ 
Q)
3DQDVRQLF & & &
Q) X) S) 5 '
& 
N
X)9
& +)4 
Q) 3DQDVRQLF


/ .RRO0P7XUQVPP 
        ,R $
' 6736 ',1$

Figure 40. Synchronization example

9&& 9 && 9 &&

   

 
 /   /  
/ /
   
    

',1

DocID1546 Rev 19 19/25

25
Application ideas L4973

Figure 41. Multi output not isolated (pin out referred to DIP12+3+3)

9&& ,1+ 6<1&

& ' 9R

5
   

 / Q
& & & / 9R
  
   Q

& & &

5
' & & &
&

Q Q
92 92
Q ',1$

3232

20/25 DocID1546 Rev 19

L4973 Package mechanical data

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

Table 5. SO-20 mechanical data

mm. inch
Dim.
Min Typ Max Min Typ Max
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.200
C 0.23 0.32 0.009 0.013
D (1) 12.60 13.00 0.496 0.512
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.0 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
k 0° (min.), 8° (max.)
ddd 0.10 0.004

DocID1546 Rev 19 21/25

25
Package mechanical data L4973

Figure 42. Package dimensions

22/25 DocID1546 Rev 19

L4973 Order code

9 Order code

Table 6. Order code

Part number Package Packaging

L4973D3.3-013TR, E-L4973D3.3-TR SO-20 Tape and reel

L4973D5.1-013TR SO-20 Tape and reel

DocID1546 Rev 19 23/25

25
Revision history L4973

10 Revision history

Table 7. Document revision history

Date Revision Changes

12-Sep-2001 13 First Issue

Updated the Layout look & feel.
07-May-2005 14
Changed name of the D1 on the fig. 5.
14-Dec-2005 15 Added the ECOPACK part numbers in the Table 1. Order Codes.
06-Dec-2006 16 The document has been reformatted, and order codes updated
07-May-2007 17 New data on Table 4.
26-Feb-2009 18 Updated Section5: Evaluation board on page 10.
03-May-2024 19 Updated Table 6.

24/25 DocID1546 Rev 19

L4973

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2024 STMicroelectronics – All rights reserved

DocID1546 Rev 19 25/25

25