DF Question Bank Nljiet

New L J Institute of Engineering and Technology Semester: III (2023)
Subject Name: Digital Fundamentals

Subject Code: 3130704
Faculties: Dhara Pomal, Pinak Deb
Sr. MODULE 1: FUNDAMENTALS OF DIGITAL SYSTEMS Marks
No
AND LOGIC FAMILIES
TOPIC:1 Digital signals, digital circuits, AND, OR, NOT, NAND, NOR
and Exclusive-OR operations
SHORT QUESTIONS (1 Mark) / MCQ / True-False/Fill in the blanks
1 Which gates are called as universal gates? What are its advantages?(May-2016-NEW) 01
[NLJIET] Answer: NAND , NOR gates . Because we can construct all gates using them.
2 Do as directed :Find the logic required at R input.(May-2015-NEW)[NLJIET] 01
Answer : R=1
3 Bubbled OR is also called.(Dec-2015- NEW) [NLJIET] Answer : NAND 01
4 Which gates are also known as controlled NOT gate? (Dec-2015- NEW) [NLJIET] 01
Answer : XOR,XNOR
5 Define the following terms: Universal gate (Nov-2013-OLD) [NLJIET] 01
6 Select the most appropriate option(Dec-2014- NEW) [NLJIET] 03
(i) If a 3-input NOR gate has eight input possibilities, how many of those possibilities will (01
result in a high output? Marks
(A) 1 (B) 2 (C) 7 (D) 8 Answer: (C) Each)
(ii) If a signal passing through a gate is inhibited by sending a LOW into one of the inputs,
and the output is HIGH, the gate is a(n):
(A) AND (B) NAND (C) NOR (D) OR Answer: (B)
(iii) When used with an IC, what does the term “QUAD” indicate?
(A) 2 circuits (B) 4 circuits (C) 6 circuits (D) 8 circuits Answer: (B)
7 Bubbled OR gate is also called. (Jan-2017- NEW) [NLJIET] Answer : NAND 01
8 Design a NOT gate using a two input Ex-OR gate(Jan-2017-NEW)[NLJIET] 01
Answer:NOT gate is designed by connecting any one input terminal to ‘1’ or ‘Vcc’ of
Ex-OR gate
9 The output of a ____ gate is only 1 when all of its inputs are 1 (Jun-2017-NEW) [NLJIET] 01
(a) NOR (b) XOR (c) AND (d) NOT Answer : (c)
10 Which gate equivalent is to bubbled OR gate? (Jun-2017-NEW) [NLJIET] 01
(a) AND (b) XOR (c) NOT (d) NAND Answer : (d)
11 A NOT gate has (Jun-2017-NEW) [NLJIET] 01
(a) Two inputs and one output (b) One input and one output
(c) One input and two outputs (d) none of above Answer : (b)
DESCRIPTIVE QUESTIONS
1 What is signal? Explain different types of signal. (Jul-2022-NEW)[NLJIET] 04
2 Explain various logic gates. (Jul-2022-NEW)[NLJIET] 07
Draw and explain two input (i) AND (ii) OR and (iii) EX-OR gates.(Jun-2015-OLD) 07
[NLJIET]
With neat logical diagram and truth table explain all the basic gates including NAND, NOR, 07
EX-OR, EX-NOR gate(Nov-2017-OLD)[NLJIET]
Draw the logic symbol and construct the truth table for each of the following gates. (Mar- 07
2010-OLD)[NLJIET]
[1]Two input NAND gate [2]Three input OR gate [3]Three input X-NOR gate [4]NOT gate
Digital Fundamentals (3130704) 2023 Page 1

Answer the following (May-2011-OLD)[NLJIET] 07

Draw symbol and construct the truth table for three input Ex-OR gate. 02
Explain with neat logic diagram and truth table the functioning of basic logic gates. (Jan- 07
2017-OLD) [NLJIET]
Write the truth table of 3-input XOR gate. (Feb-2022-OLD) [NLJIET] 03
3 Implement NOR, AND, & OR gates using NAND gates only.(Feb-2023-NEW) [NLJIET] 03
Why NAND and NOR gates are called universal gates? Explain with appropriate example. 07
(Aug-2023-NEW) [NLJIET]
Explain NAND gate as a Universal Gate. (Jul-2022-NEW) [NLJIET] 04
Implement EX-NOR using NAND gate. (Feb-2022-NEW) [NLJIET] 03
Generate AND & EX-OR gates using NOR gate. (Feb-2022-NEW) [NLJIET] 03
List out three basic logic operations. Realize these operations using NOR gates only. (Nov- 04
2020-NEW) [NLJIET]
Realize AND, OR and NOT gate using NAND gates only.(Mar-2021-NEW)[NLJIET] 03
Generate AND, OR, NOT, EXOR and EX-NOR gate using NAND as a universal gate.(Jun- 07
2019-NEW) [NLJIET]
Discuss Universal gates. Obtain AND, OR gate using NAND and NOR gates.(Nov-2017- 07
NEW) [NLJIET]
Implement AND, OR, & EX-OR gates using NAND & NOR gates. (Dec-2019-NEW) 07
[NLJIET]
Implement NOT, AND, & OR gates using NAND gates only. (May-2018-NEW) 03
[NLJIET] 04
Discuss NAND gate as universal gate (implement NOT, AND OR & NOR gate using
NAND gate). (May-2015-NEW) [NLJIET] 04
Explain NAND and NOR as an universal gates.(May-2011-OLD) [NLJIET] 07
Explain with figures how NAND gate and NOR gate can be used as Universal gate. (Dec-
2010-OLD) [NLJIET] 07
Justify the statement: “NAND and NOR gates are universal gates.”(Jan-2017-OLD)
[NLJIET] 07
Explain how NAND and NOR gates can be utilized as universal gates to implement all the
basic gates.(Nov-2017-OLD) [NLJIET] 04
Implement Boolean expression for Ex-OR gate using NAND gates only. (May-2011-OLD)
[NLJIET] 06
Draw symbol and truth table for four input EX-OR gate. Explain NAND and NOR as an
universal gate.(Dec-2011-OLD) [NLJIET] 07
Draw the logic diagrams of NAND & NOR gates & explain why they are called as universal
gates.(Dec-2015-OLD) [NLJIET] 04
Why NAND gate is known as universal gate? (Jan-2017-NEW) [NLJIET] 04
Prove that NAND gate as Universal gate (Jun-2017-NEW) [NLJIET] 07
Generate AND, OR, NOT, EXOR and EX-NOR gate using NAND as a universal gate(Jul-
Implement NOT, AND and OR gate using NAND gates. (Feb-2022-OLD) [NLJIET]
4 Implement NOT gate using XOR gate. (Feb-2022-OLD) [NLJIET] 03
5 Show that 07
Also construct the corresponding logic diagrams.(May-2016-NEW) [NLJIET]
6 Given Boolean function, F = xy + x’y’ + y’z, 1. Implement it with only OR & NOT gates 05
2.Implement it with only AND & NOT gates (May-2012-OLD) [NLJIET]
(1) Draw the logic circuit for following using only NAND gates: (Nov-2013-OLD) 07
[NLJIET]
F = ABC+A’B+AC’D’
(2) Draw the logic circuit for following using only NOR gates:
F = ABC’ + AB(C+D)
Implement the Boolean functions. (a) xyz+x’y+xyz’ (b) (A+B)’(A’+B’)’ and (c) F= 07
xy+xy’+y’z with logic gates. (May-2013-OLD) [NLJIET]
7 Define: Integrated Circuit and briefly explain SSI, MSI, LSI and VLSI.(Mar-2010-OLD) 07
[NLJIET]
8 Answer the following questions (Dec-2014-OLD) [NLJIET] 05
Find out Y, if B=1 and A=Square wave
TOPIC:2 Boolean Algebra, examples of IC gates

1 State the associative property of Boolean algebra (May-2016-NEW) [NLJIET] Answer: 01
(A*B)*C = A*(B*C) , (A+B)+C = A+(B+C)
2 Write D’Morgan’s Theorems (Dec-2014-NEW) [NLJIET] Answer : (A B )’ = A’ + B’, 01
(A+B)’ = A’ B’
3 State the distributive property of Boolean algebra (Jan-2017-NEW) [NLJIET] Answer: 01
A(B+C) = AB + AC , A+BC = (A+B) (A+C)
1 Write the boolean expression for the logic diagram given below and simplify it as much as 04
possible and draw the logic diagram that implements the simplified expression.(Feb-2023-
NEW) [NLJIET]
04
Find the Boolean Equation for following circuit and simplified Boolean equation.(Jun-
2019-NEW) [NLJIET]
2 Prove following using the Boolean algebraic theorems: 03

1. A + A’B + AB’ = A + B 2. AB + A’B + A’B’ = A’ + B (Nov-2020-NEW) [NLJIET]
Reduce the expression F = A [ B + C’ (AB + AC’)’].(Dec-2019-NEW) [NLJIET] 04
Simply Boolean Function : F=A'B'C+A'BC+AB'.(Jun-2019-NEW) [NLJIET] 03
Simplify the Boolean function F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’(Dec-2019- 03
NEW) [NLJIET]
i. Using laws of Boolean algebra prove that, AB + BC + A'C = AB + A'C. 07
ii. Minimize the logic function X = A(B' + C')(A + D).
Also realize the reduced function using NOR gates only.(May-2018-NEW) [NLJIET]
Simplify the following Boolean functions to a minimum numbers of literals. 1. x + x’y 2. x 04
(x’+y) 3. x’y’z + x’yz + xy’ 4. xy + x’z +yz (Dec-2018-NEW) [NLJIET]
Show that (A + C) (A + D) (B + C) (B + D) = AB + CD (Jan-2017-NEW) [NLJIET] 03
Simplify Using Boolean laws and draw the logic diagram for the simplified expression.F = 04
(ABC)’+(AB)’C+A’BC’+A(BC)’+AB’C (Jun-2017-NEW) [NLJIET]
Show that AB’C + B + BD’+ ABD’ +A’C = B+C.(Nov-2017-NEW) [NLJIET] 03

Reduce the expression F = ((AB)’+A’+AB)’ (May-2016-NEW) [NLJIET] 03
Reduce following Boolean function and then realize the reduced one using NOR gate only. 04
X = A (B'+C') (A+D) (Dec-2015-NEW) [NLJIET]
Minimize the following Boolean expressions. (Dec-2015-NEW) [NLJIET] 04
1. X = ( (A'B'C')' + (A'B)' )' 2. Y = AB + ABC' + A'BC + A'BC'
Simplify using Boolean laws and draw the logic diagram for the given expression. 07
F = (ABC)’ + (AB)’ C + A’ B C’ + A (BC)’ + A B’ C (Dec-2014-NEW) [NLJIET]
Simplify 1. A’B + A’BC’ + A’BCD + A’BC’D’E 2. (P+Q+R) (P’+ Q’+ R’) P(May-2014 - 08
OLD) [NLJIET]
Prove that: 1. ((A’B+ABC)’ + A (B+AB’))’ = 0 2. AB’C + A’BC + ABC = AC + AB 07
(May-2014-OLD) [NLJIET]
Simplify the following Boolean function to minimum numbers of literals. 07
(a) xyz+x’y+xyz’ and (b) (A+B)’(A’+B’)’ (May-2013-OLD) [NLJIET]
Prove the following Boolean identities.(Dec-2014-NEW) [NLJIET] 07
(i) XY + YZ + Y’ Z = XY + Z (ii) AB + A’B + A’B’ = A’ + B
Prove that (i) A[B+C(AB+AC)’] = AB (ii) AB’ (C+BD) + A’ B’= B’C(Dec-2015-OLD) 08
[NLJIET]
Find the complement of the following Boolean function and reduce to a minimum number 07
of literals. B’D + A’BC’ + ACD + A’BC (Jan-2013-OLD) [NLJIET]
Reduce the expression: (1)A+B(AC+(B+C’)D) (2) (A+(BC)’)’(AB’+ABC) (Dec-2010- 07
OLD) [NLJIET]
Simplify the Boolean function, F= A’B’C’+B’CD’+A’BCD’+AB’C’(Jun-2016-OLD) 07
[NLJIET]
Simplify the Boolean function, F= A’C+A’B+AB’C+BC. (Jun-2016-OLD) [NLJIET] 07
Minimize the following Boolean expressions using Boolean algebra, X = AB + (A+B)(A’ 04
+B) (Feb-2022-OLD) [NLJIET]
3 Obtain the truth table of the function: F= xy + xyʹ + yʹz. (Jan-2017-NEW) [NLJIET] 03
4 State and Prove D’Morgan Theorem using truth-tables (Mar-2021-NEW) [NLJIET] 04
State and Prove D’Morgan Theorem for three variables (Jun-2017-NEW) [NLJIET] 3.5
State and explain De Morgan’s theorems with truth tables (May-2016-NEW) [NLJIET] 04
State & prove De Morgan’s theorems with the help of truth tables.(May-2018-NEW) 04
[NLJIET]
State and explain De Morgan’s theorems with truth tables.(Jun-2019-NEW) [NLJIET] 04
State and explain De Morgan’s theorems with truth tables.(Dec-2019-NEW) [NLJIET] 04
State & explain Demorgan’s theorem (Dec-2015-OLD) [NLJIET] 07
State and Prove D’Morgan Theorem (Jun-2017-NEW) [NLJIET] 02
State and Prove D’Morgan Theorem (Nov-2017-NEW) [NLJIET] 04
State and prove DeMorgan Theorem.(Dec-2018-NEW) [NLJIET] 03
Demonstrate by means of truth tables the validity of the following Theorems of Boolean 3.5
algebra : De Morgan’s theorems for three variables (Dec-2009-OLD) [NLJIET]
Answer the following: What is the principle of Duality Theorem?(May-2011-OLD) 02
[NLJIET]
State De-Morgan’s theorems and prove with the help of truth table.(May-2015-NEW) 04
[NLJIET]
State and prove De-Morgan’s Theorems with the help of Truth tables. (Nov-2013-OLD) 07
[NLJIET]
State DeMorgan’s theorems & prove with the help of truth table. (Feb-2013-OLD) 03
[NLJIET]
5 Show that the dual of the exclusive-OR is equal to its compliment.(May-2013-OLD) 07
[NLJIET]

6 List out and explain the most common postulates used to formulate various algebraic 07
structures. (Jun-2016-OLD) [NLJIET]
TOPIC:3 Number systems-binary, signed binary, octal hexadecimal
number, binary arithmetic, one’s and two’s complements arithmetic,
codes, error detecting and correcting codes
1 Define Nibble. (May-2016-NEW) [NLJIET] 01
2 1 Kb corresponds to _______ (Jun-2017 -NEW) [NLJIET] 01
(a) 1024 bits (b) 1000 bytes (c)210 bytes (d) 210 bits Answer : (a)
3 Convert decimal number (43)10 to binary. (Dec-2015-NEW) [NLJIET]Answer : (101011)2 01
(32)10 = (?)2 (Jan’2017 NEW) [NLJIET] Answer : (100000)2 01
4 Convert octal number (234)8 to hexadecimal. (Dec-2015-NEW) [NLJIET]Answer : (9C)16 01
5 Do as directed : (May-2016-NEW) [NLJIET] 03
I. Given that (16)10 = (100)x, find the value of x. Answer : 4 (01
II. Add (6E)16 and (C5)16 Answer : (133)16 Marks
III. (4433)5 = ( )10 = ( )2 Answer : (1118)10 , (10001011110)2 Each)
6 Select the most appropriate option(Dec-2014-NEW) [NLJIET] 03
(i) Convert the decimal number 187 to 8-bit binary. (01
(A) 101110112 (B) 110111012 (C) 101111012 (D) 101111002 Answer : (A) Marks
(ii) Convert the binary number 1001.00102 to decimal. Each)
(A) 90.125 (B) 9.125 (C) 125 (D) 12.5 Answer : (B)
(iii) The 2’s complement of the number 1101110 is
(A) 0010001. (C) 0010010. (C) 0000000 (D) None. Answer : (B)
7 (56)16 = (?)10 (Jan-2017-NEW) [NLJIET] Answer : (86)10 01
8 The digit F in Hexadecimal system is equivalent to —— in decimal system 01
(a)16 (b)15 (c)17 (d) 8 (Jun-2017-NEW) [NLJIET] Answer : (b)
9 (734)8 = ( )16 (Jun-2017-NEW) [NLJIET] 01
(a) C1D (b) DC1 (c) 1CD (d) 1DC Answer : (d)
10 Convert the following numbers to decimal(Dec-2009-OLD) [NLJIET] 07
(i) (1001.101)2 Answer : (17.625)10 (ii) (101011.11101)2 Answer : (43.90625)10 (01
(iii) (0.365)8 Answer : (0.47851563)10 (iv) A3E5 Answer : (41957)10 Marks
(v) CDA4 Answer : (52644)10 (vi) (11101.001)2 Answer : (29.125)10 Each)
(vii) B2D4 Answer : (126)10
11 Do as directed (Jan-2017-OLD) [NLJIET] 07
(i) (645.65625)10 = ( )2 Answer : (1000000000.10101)2 (01
(ii) (FACE.25)16 = ( )10 Answer : (64206.14453125)10 Marks
(iii) (11011)Gray = ( )10 Answer : (18)10 Each)
(2) Subtract (45)10 from (93)10 using 1’s Complement Method Answer : (48)10
(v) (ABC.555)16 = ( )8 Answer : (5274.2525)8
(vi) (2493)10 = ( )Excess-3 CodeAnswer : (0101011111000110) Excess-3 Code
(vii) (1525)10 = ( ) Gray codeAnswer : (11100001111) Gray code
12 Convert the following nos (Nov-2017-New) [NLJIET] 04
(i) (52)10 = ( )2 Answer : (110100)2 (01
(ii) (436)8 = ( )16 Answer : (8F0)16 Marks
(iii) (5C7)16 = ( )10 Answer : (1479)10 Each)
(iv) (11011.101)2 = ( )10 Answer : (27.625)10
13 Do as directed : (May-2016-NEW) [NLJIET] 04
I. (1011011101101110)2 = ( )16 Answer : (B76E)16 (01
II. Subtract (45)8 from (66)8 Answer : (21)8 Marks
III. Covert the Gray code 1101 to binary Answer : (1001)2 Each)
IV. Find the XS-3 code of 37 Answer : (01101010)XS3
1 Do as directed: (Feb-2023-NEW) [NLJIET] 07
1. Convert (75.75) 10 = (___) 8 = (___)16
2. Convert (101.10)16 = (__)8
3. Add (17)10 and (-25)10 using 8-bit 2’s complement
Convert the following number to the given base:(i) (62)10 = (?)2 = (?)8 (ii) (AFB)16 = (?)2 = 04
(?)8(Aug-2023-New) [NLJIET]
Do as directed: (Mar-2021-New) [NLJIET]
07
(a) (1111.11)2 = ( ? )8 = ( ? )10
(b) 23 – 48 using 2’s complement method
(c) (396)10 = ( ? )BCD = ( ? ) EX-3
(d) (11111)2 = ( ? )Gray
04
Convert the decimal Number 250.5 to base 4 and base 8. (Jul-2022-NEW) [NLJIET]
Convert the decimal number 225.225 to octal & hexadecimal.(Feb-2022-NEW) [NLJIET] 04
Convert the following numbers form given base to the base indicates. (Dec-2018-NEW) 03
[NLJIET]
1. (AEF2.B6)16 = (_______)2
2. (674.12)8 = (________)10
3. (110110.1011)2 = (________)16
Convert 1000 0110 (BCD) to decimal, binary & octal.(May-2018-NEW) [NLJIET] 03
Do as directed. (Jun-2019 New) [NLJIET] 07
i. Find 8 bit representation of (-1)10=(_________)2
ii. Find A+A'B =__________.
iii. _____ and _______ can work as universal gates.
iv Define term: Propagation Delay
v. By keeping one input HIGH, NAND gate can work as Inverter to second input. (T/F)
vi. Convert (FFFF)16=(________)10.
Do as Directed : (Dec-2019-NEW) [NLJIET] 03
1. Given that (16)10 = (100)x. Find the value of x.
2. Add (6E)16 and (C5)16.
3. (1011011101101110)2 = (_____)8 = (_____)16.
Convert (125.625)10=(________)2.
Do as directed(May-2015-NEW) [NLJIET] 02
(i) Convert (75)10 = (____________)2 (ii) Convert (101011)2 = (_____)10
Convert (10101101)2 = (_____)16 = (______)8 02
Convert the following Hexadecimal numbers to Octal. (Dec-2015-OLD) [NLJIET] 02
(a) 4F7.A8 (b) BC70.OE (c) 42FD
Convert following 1. (4E7.2)16 = (?)8 2. (521.3)8 = (?)2 (May-2014-OLD) [NLJIET] 06
Convert the decimal number 225.225 to binary, octal and hexadecimal(May-2011-OLD) 06
[NLJIET]
Convert the decimal number 225.225 to binary, octal and hexadecimal (Dec-2011- 06
OLD)[NLJIET]
Convert following numbers.(Jun-2015-OLD) [NLJIET] 03
(a)(4021.2)5 = ( )10. (b) (B65F)16= ( ) 10. (c) (630.4)8 = ( ) 10. (d) (41) 10 = ( )
Convert the following numbers as directed:(Nov-2013-OLD) [NLJIET] 07
(1) (130)10 = ( )2
(2) (1011011)2 = ( )10
(3) (1011101111)2 = ( )8
(4) (110111011101111011)2 = ( )16
Convert the following Numbers as directed : (Dec-2010-OLD) [NLJIET] 04
(1) (52)10 =( )2 (2) (101001011)2 = ( )10
(3) (11101110)2 =( )8 (4) (68)10 =( )16
Convert following Hexadecimal Number to Decimal:B28, FFF, F28(Mar-2010-OLD) 04

[NLJIET]
Do as Directed: (Nov-2017-OLD) [NLJIET] 07
(i)(673.124)8 = ( )2 (ii) (4522.25)10 = ( )2 (iii) (FACE)16 = ( )10
(iv) (10101010)2 = ( )8 = ( )16 (vi) (10101101)2 = ( )gray
(v)Substract using 2’s complement method. (10010)2 – (10011)2
(vii) (8620)10 = ( )BCD =( )2421
Convert 4BAC16 = ( )8 = ( )4 = ( )2 = ( )10. Show all steps of conversion (May-2017-OLD) 07
[NLJIET]
Convert octal number (354)8 into binary. (Feb-2022-OLD) [NLJIET] 03
Convert the decimal number (45.5)10 to binary(Feb-22-OLD) [NLJIET] 03
Convert the decimal number 250.5 to base 3, base 4, base 7 and base 16 (May-2012- 07
OLD)[NLJIET]
Convert the decimal number 250.5 to base 3, base 4, base 7 and base 16(May-2013- 07
OLD)[NLJIET]
Convert the decimal number 250.5 to base 3, base 4, base 7 and base 16 (Jan-2013-OLD) 07
[NLJIET]
Convert the decimal number 250.5 to base 3, base 4, base 7 and base 8 (Jun-2017-NEW) 07
[NLJIET]
1.Convert the binary number (1101110.0110) to Hexadecimal 03
2. Find 2’s Complement Representation of (-45)10.
3. Convert (FFFF)16 = (________)8 (Jul-2022-OLD) [NLJIET]
2 Represent following numbers in 8 Bit Binary representation: (i) (126)10 (ii) (79)10 03
(iii)(-128)10 (Jun-2019- NEW) [NLJIET]
3 Convert 33.4510 to binary. Result should be accurate to within 0.0110. (May-2018-NEW) 03
[NLJIET]
Convert decimal number (0.252)10 to binary with an error less than 1 %. (Dec-2015-NEW) 03
[NLJIET]
4 Explain Arithmetic addition and arithmetic subtraction. (May-2012-OLD) [NLJIET] 04
5 Do as directed: (Feb-2023-NEW) [NLJIET] 04
1. Add 25+17 in BCD
2. Add 37 +28 in XS-3
6 Perform addition in BCD format (79)BCD + (16)BCD(May-2015-NEW) [NLJIET] 03
7 Add the two numbers (A3E5)16 + ( CDA4)16 (Dec-2014-OLD ) [NLJIET] 02
8 Perform subtraction of (78)10 – (58)10 using 2’s complement addition method. (May-2015- 03
NEW) [NLJIET]
9 Explain r’s complement with example in detail.(Jun-2016-OLD) [NLJIET] 07
10 Explain (r-1)’s complement with example in detail.(Jun-2016-OLD) [NLJIET] 07
11 Find the 10’s complement of the following:(1)(935)11 (2)(6106)10(Jan-2017- 04
NEW)[NLJIET]
12 (i) Using 10’s complement, subtract : (72532-3250) 10(Jun-2015-OLD)[NLJIET] 07
(ii) Using 10’s complement, subtract : (3250-72532) 10
(iii) Using 2’s complement, subtract : (1010100-1000100) 2
13 1. Do subtraction using 12-bit two’s complement addition method, 27.125 – 79.625 07
2. Do BCD addition for given numbers, 679.6 + 536.8 (Dec-2014-OLD) [NLJIET]
14 Perform the subtraction with the following decimal numbers using 1’s compliment and 2’s 07
compliments: (a) 11010-1101 , (b) 10010-10011(May-2013-OLD) [NLJIET]
15 Perform the operation of subtractions with the following binary number using 2’s 07
complement(Dec-2009-OLD) [NLJIET]
(i) 10010 – 10011 (ii) 100 – 110000 (iii) 11010 – 10000

16 Perform the binary subtraction using 2’s complement (0111)2 - (1101)2 (Jul-2022-NEW) 03
[NLJIET]
Perform following operation using 2’s complement method. 03
(11010)2 – (1000)2 (Feb-2022-NEW) [NLJIET]
Perform the operation of subtractions with the following binary number using 2’s 03
complement (11010)2 – (10000)2 (Nov-2017-NEW)[NLJIET]
17 Do as directed: (Nov-2020-NEW) [NLJIET] 07
1. Express decimal number 60.875 into binary form.
2. One 8421 code word is transmitted in Hamming code with even parity checking. The
received word is 0101000. Find out the correct code word and write decimal equivalent.
18 List and explain in detail Binary codes with example. (Feb-2023-NEW) [NLJIET] 04
19 Explain Excess 3 code and 2421 code in detail. (Jun-2016-OLD) [NLJIET] 07
20 Represent the decimal number 8620 in BCD, Excess-3, and Gray code (Dec-2011-OLD) 03
[NLJIET]
Convert (96)10 to its equivalent Gray code and EX-3 code.(May-2015-NEW) [NLJIET] 03
Convert decimal 8620 into BCD, excess-3 and Gray code.(May-2011-OLD) [NLJIET] 04
21 Write a brief note on Gray codes. Also discuss methods for conversion from gray to binary 07
code and vice versa.(May-2014-OLD) [NLJIET]
22 Construct Hamming code for BCD 0110. Use even parity (Mar-2021-NEW)[NLJIET] 04
23 What are the different types of the codes used in digital systems? Explain them.(May-2016- 04
NEW)[NLJIET]
Explain error detection codes and the reflected code with examples.(Jun-2015-OLD) 07
[NLJIET]
Explain error detecting & correcting codes with the help of a suitable example.(Dec-2015- 07
OLD) [NLJIET]
TOPIC:4 Characteristics of digital Ics, digital logic families, TTL,
Schottky TTL & CMOS logic, interfacing CMOS & TTL, Tri-state logic
1 Define Negative Logic: (Jan-2017- NEW) [NLJIET] 01
Define Fan-out. (May-2016-NEW) [NLJIET] 01
Define Fan-out. (Dec-2015-NEW)[NLJIET] 01
Define: Fan in (Jan-2017-NEW) [NLJIET] 01
Define: Noise Margin (Jan-2017-NEW) [NLJIET] 01
2 Which logic family is the fastest logic family? (Jan-2017-NEW) [NLJIET] Answer : TTL 01
3 Which logic family consumes the less power?(Jan-2017-NEW)[NLJIET]Answer: 01
CMOS
4 Which TTL logic gate is used for wired ANDing? (May-2016-NEW) [NLJIET]Answer 01
:Open collector output
5 Define the followings. Totem Pole output (Dec-2014-NEW) [NLJIET] 01
6 The digital logic family which has minimum power dissipation is (Jun-2017-NEW) 01
[NLJIET](a) TTL (b) RTL (c) DTL (d) CMOS Answer : (d)
7 Select the most appropriate option(Dec-2014-NEW) [NLJIET] 01
Which TTL logic gate is used for wired ANDing
(A) Open collector output (B) Totem Pole (C) Tri state output (D) ECL gatesAnswer:(A)
8 Which circuit is used to eliminate chattering? (Dec-2015-NEW) [NLJIET] 01
Answer : RC Low pass Filter or Shift register based debouncing switch
1 List out various logic families. Also list characteristics of digital IC.(Jul-2022-NEW) 03
[NLJIET]
Define the logic family properties: (i) fan in (ii) propagation delay (iii) power 03
dissipation(Aug-2023-NEW) [NLJIET]
Define following:1. Figure of merit 2.Noise margin 3.Power dissipation. (Mar-2021-NEW) 03

[NLJIET]
Define (i)Fan in (ii)Noise Margin (iii)Propagation delay.(Nov-2017-NEW) [NLJIET] 03
Define: Noise margin , Propagation delay (May-2011-OLD) [NLJIET] 02
Define the followings.(May-2016-NEW) [NLJIET] 04
(i)Propagation delay (ii) Fan in (iii) Noise Margin (iv) Negative Logic
Define the followings.(Dec-2014-NEW) [NLJIET] 04
(i)Propagation delay (ii) Fan in (iii) Noise Margin (iv) Negative Logic
Define the followings: (May-2016- NEW) [NLJIET] 02
(i) Noise Margin (ii) Negative Logic
List out various logic families. Also list the characteristics of digital ICs.(May-2018-NEW) 03
[NLJIET]
Give classification of logic families. Also list the characteristics of digital IC(Jan-2017- 03
NEW) [NLJIET]
Explain following terms w.r.t Digital Logic Family.(Dec-2018-NEW) [NLJIET] 03
1. Fan-in 2.Noise Margin 3. Power Dissipation
Define the following terms (Jun-2017-NEW) [NLJIET] 05
1. Positive Logic 2. Negative Logic 3. Fan In 4. Fan out 5. Noise Margin
What is positive and negative logic? Explain in detail. (Jun-2016-OLD) [NLJIET] 07
Define and explain (i) fan out (ii) power dissipation and (iii) Propagation delay. (Jun-2015- 07
OLD) [NLJIET]
Explain the digital IC Parameters.(Dec-2014-OLD) [NLJIET] 07
1. Fan in, Fan out 2. Propagation Delay 3. Power Dissipation 4. Noise Margin
Describe briefly TTL fanin, fanout & noise margin with suitable sketches (Dec-2015-OLD) 07
[NLJIET]
Define followings with respect to logic families.(May-2015-NEW) [NLJIET] 04
1) Fan in 2) Fan out 3) Noise Margin 4) Propagation delay
Explain briefly: propagation delay, fan out(May-2015-NEW) [NLJIET] 02
Explain briefly: propagation delay, fan out(Dec-2011-OLD) [NLJIET] 02
Explain following terms w.r.t Digital Logic Family. (Jul-2022-OLD) [NLJIET] 03
1. Fan-in 2. Noise Margin 3. Power Dissipation
Define followings (Feb-2022-OLD)[NLJIET] 03
(i) Fan out (ii) Noise Margin (iii) Propogation delay
2 Explain two input CMOS NAND gate.(May-2016-NEW) [NLJIET] 07
3 Compare TTL, ECL, & CMOS logic families. (Feb-2023-NEW)[NLJIET] 03
Compare TTL, ECL, & CMOS logic families. (May-2018-NEW)[NLJIET] 04
Compare the following in every aspect. TTL and CMOS (Nov-2017-NEW)[NLJIET] 03
Give comparison of TTL and CMOS family. (Jun-2019-NEW)[NLJIET] 03
Compare the following in every aspect. TTL and CMOS(Dec-2014-NEW)[NLJIET] 03
Compare TTL, ECL, & CMOS logic families. (Dec-2015-NEW)[NLJIET] 07
Give classification of Logic Families and compare CMOS and TTL families.(Mar-2010- 03
OLD)[NLJIET]
Tabled the compare of TTL, CMOS, and ECL logic families based on speed, fan-in, fan-
out, noise immunity, power dissipation, and application.(Feb-2022-OLD)[NLJIET] 07
1. Give comparison for TTL and CMOS family. 2. Implement basic gates using DTL
logic.(Dec-2014-OLD)[NLJIET] 07
4 Discuss the advantages & disadvantages of TTL Logic Family.(Dec-2018-NEW) 03
[NLJIET] 04
Discuss advantages and drawbacks of TTL logic family(Jul-2022-OLD)[NLJIET]
5 Give classification of logic families and compare CMOS and TTL.(Feb-2022-NEW) 07
[NLJIET]

MODULE 2: COMBINATIONAL DIGITAL CIRCUITS

TOPIC:1 Standard representation for logic functions, K-map
representation, and simplification of logic functions using K-map,
minimization of logical functions, Don’t care conditions, Q-M method of
function realization
1 What are called Don’t care conditions? (May-2016-NEW) [NLJIET] 01
Answer: Don’t care conditions for a function is an input-sequence (a series of bits) for
which the function output does not matter.
2 What is prime implicant? (May-2016-NEW) [NLJIET] 01
Answer : The prime implicant is a group of minterms which can’t be combined with
any other groups.
3 Define: combinational logic circuit(Nov-2013-OLD) [NLJIET] 01
1 Explain Minterm and Maxterm. (Jul-2022-NEW) [NLJIET] 07
Explain briefly: SOP & POS, minterm & maxterm, canonical form(Dec-2011-OLD) 03
[NLJIET]
Define the following terms: (1) Literal (2) Minterm (3) Maxterm(Nov-2013-OLD) 03
[NLJIET] 04
Answer the following(May-2011-OLD) [NLJIET]
(i) Explain briefly: standard SOP and POS forms. (ii) What are Minterms and Maxterms?
2 List out various methods of simplifying a given Boolean function. Solve F = AB + AB’ 03
using any two methods. (Nov-2020-NEW) [NLJIET]
3 Simply Boolean Function: F=(B+BC)(B+B’C)(B+D) (Jul-2022-OLD) [NLJIET] 03
4 Obtain the truth table of the function: F = xy+yz+zx . (Feb-2022-NEW)[NLJIET] 03
5 Convert F(A,B,C) = BC+A into standard minterm form. (Feb-2022-NEW)[NLJIET] 03
(1) Convert Y = AB + AC’ + BC into canonical SOP form.
(2) Convert Z=(A+B)(A+C)(B+C’) into canonical POS form.(Nov-2020-NEW) [NLJIET] 04
Express Boolean function F =AB+A’C in a product of maxterm.(Nov-2017-NEW) [NLJIET] 04
Express Boolean function F=A+B’C in a sum of minterms.(Dec-2019-NEW) [NLJIET] 07
Obtain canonical Sum of Product form of following function: F=AB+ACD.(Jun-2019-NEW) 03
[NLJIET]
Convert F(A, B, C) = BC + A into standard minterm form.(May-2015-NEW) [NLJIET] 03
Attempt following: Convert into Sum-of-Minterms: A’ + B + CA, Convert into Product-of- 07
Maxterms: A(A’+B)(C’) (May-2014-OLD) [NLJIET]
Convert the expression Y=A+BC into the standard SOP form (Jun-2017-NEW) [NLJIET] 03
Express following Function in Product of Maxterms F(x,y,z)=( xy + z) (y + xz)(May-2012 03
-OLD) [NLJIET]
Express the Boolean function F=A+B’C a sum of minterms and in sum of max terms. (Jun- 07
2015-OLD) [NLJIET]
Convert F (A, B, C) = (B+C) A into standard maxterm form. (Feb-2022-OLD) [NLJIET] 04
6 Reduce the expression Σ (2, 3, 6,7,8,10,11,14) using K-map.(Feb-2023-NEW)[NLJIET] 03
Simplify Boolean function using K-MAP
F(A, B, C, D)=ABC’D’ + ABC’D + ABCD’ + AB’CD’ (Jul-2022-NEW) [NLJIET] 03
Simplify the Boolean expression: F(x,y,z) = ∑m (0,1,3,4,5,7) (Feb-2022-NEW) [NLJIET] 03
Minimize following Boolean function using K-map: Y(A,B,C,D) = Σ m(0, 1, 2, 3, 5, 7, 8, 03
9, 11, 14) (Mar-2021- NEW) [NLJIET]
Minimize following Boolean function using K-map: 07
X(A,B,C,D) = Σ m(0, 1, 2, 3, 5, 7, 8, 9, 11, 15) (Nov-2020-NEW) [NLJIET]
Simplify the Boolean function F(X, Y, Z) = ∑ (2, 4, 5, 6) using K – map. Explain groups. 03
(Jun-2015-OLD) [NLJIET]
Simplify the Boolean function F (w, x, y, z) = Σ m (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) (Dec- 07
2019-NEW)[NLJIET]
Simplify the Boolean function F (w, x, y, z) = Σ m (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) 07
(Jun’2019 NEW) [NLJIET]
Simplify the Boolean function, F=Σ(0,1,2,5,8,9,10). (Jun-2016-OLD) [NLJIET] 07
Simplify the Boolean Function with Karnaugh map: (Nov-2013-OLD) [NLJIET] 07
F(W,X,Y,Z) = ∑(0,1,2,4,5,6,8,9,12,13,14) and F = A’B’C’ + B’CD’ +A’BCD’ +AB’C’
Simplify the Boolean function: (Dec-2010-OLD)[NLJIET] 07
F(w,x,y,z) = ∑(0,1,2,4,5,6,8,9,12,13,14) (2) F(w,x,y) = ∑(0,1,3,4,5,7)
Simplify the Boolean function: (Nov-2017-OLD) [NLJIET] 07
F(w,x,y,z) = ∑(0,1,2,4,5,6,8,9,12,13,14) (2) F(w,x,y) = ∑(0,1,3,4,5,7)
Obtain the simplified expression in sum of product for the following Boolean functions. 07
F= ∑(0,1,4,5,10,11,12,14) and F= ∑(11,12,13,14,15).(May-2013-OLD) [NLJIET]
Obtain the simplified expressions in sum of products for the following Boolean functions 07
(i)F(A,B,C,D,E)=∑(0,1,4,5,16,17,21,25,29)(ii)A’B’CE’+A’BCD’+B’DE’+BCD’(Dec-
2009-OLD) [NLJIET]
7 Implement the following function with NAND and NOR Gate. F(a,b,c) = Σ (0,6) (Dec- 07
2018-NEW) [NLJIET]
Solve the following Boolean functions by using K-Map. Implement the simplified function 04
by using logic gates.F = (w,x,y,z) = Σ (0,1,4,5,6,8,9,10,12,13,14)(Dec-2018-NEW)
[NLJIET] 07
Reduce the expression F = ∑m(0,2,3,4,5,6) using K-map and implement using NAND gates
only. (May-2016-NEW) [NLJIET] 07
Implement the function F=Σ(0,6) with NAND gates only. (Jun-2016-OLD) [NLJIET] 07
Implement the function F=Σ(0,6) with NOR gates only. (Jun-2016-OLD)[NLJIET]
Implement the function F(a,b,c) = Σ (0,6) with 04
1.Only NAND Gates. 2. Only NOR Gates (Jul-2022-OLD)[NLJIET]
8 Minimized the boolean expression using K-map f (A, B, C, D) = ∑m (0, 1, 5, 6, 7, 8, 9) + d(10, 11, 04
12, 13, 14, 15) (Aug-2023-NEW)[NLJIET]
Minimize following Boolean function using K-map: 04
F(A,B,C,D) = Σ m(1, 3, 7, 11, 15) + d(0, 2, 5) (Mar-2021-NEW) [NLJIET]
Minimize the following logic function using K-map: 03
F(A,B,C,D) = Σ m(1, 3, 5, 8, 9, 11, 15) + d(2,13) (Nov-2020-NEW) [NLJIET]
Simplify Boolean function using K-Map F(W,X,Y,Z)=Σ(1,3,5,8,9,11,15) , d= Σ(2,13) 04
(Jun-2017-NEW) [NLJIET]
Minimize following multiple output functions using K-Map(Dec-2015-OLD) [NLJIET] 07
(i) F1 = Σm=(0,2,6,10,11,12,13) + d(3,4,5,14,15) (ii) F2 =πM(0,4,9,10,11,14,15)
Reduce using K-map Σ m (0, 2, 6, 10, 11, 12, 13) + d (4, 5, 14, 15) (Dec-2014-OLD) 07
[NLJIET] 07
Simply the Boolean Function: (Nov-2013-OLD) [NLJIET]
F(W,X,Y,Z) = ∑(1,3,7,11,15) and the Don’t care conditions : d(W,X,Y,Z) = ∑(0,2,5) 07
Implement the functions F=∑(1,3,7,11,15) with don’t care conditions d=∑(0,2,5). Discuss
the effect of don’t care conditions.(May-2013-OLD) [NLJIET] 04
Simply the Boolean Function using K-map : F(W,X,Y,Z) = ∑(1, 3, 7, 11, 15)with don’t care
conditions d(W,X,Y,Z) = ∑(0, 2, 5) (May-2011-OLD) [NLJIET] 07
Minimize the following function using K-map and implement the same.
F (w,x,y,z) = Σm (0,1,2,3,6,7,13,14) + Σd (8,9,10,12)(Jan-2017-OLD) [NLJIET] 07
Reduce the given function using K-map and implement the same using gates. F(A,B,C,D )
= Σm (1,3,7,11,15) + Σd (0, 2, 5) (Feb-2022-OLD) [NLJIET]
9 Minimize following Boolean function using K-map & design the simplified function using 07
logic gates. F = Σ m(1, 2, 4, 6, 7, 11, 15) + Σ d(0, 3) (Dec-2015-NEW) [NLJIET]

Reduce the given function using K-map and implement the same using gates. F(A,B,C,D ) 07
= Σm (0,1,3,7,11,15) + Σd ( 2,4) (May-2015-NEW) [NLJIET]
Minimize the following logic function using K-maps and realize using NAND and NOR
gates.F(A,B,C,D) =Σm(1,3,5,8,9,11,15) + d(2,13).(Dec-2014-NEW) [NLJIET] 07
Simplify Boolean function F ( w,x,y,z ) = ∑( 0,1,2,4,5,6,8,9,12,13,14 ) using K-map and
Implement it using (i) NAND gates only (ii) NOR gates only (Dec-2011-OLD) [NLJIET] 07
10 Minimize the logic function F (A,B,C,D) = π M (1, 2, 3, 8, 9, 10, 11, 14) . d (7, 15) Use 07
Karnaugh map. Draw the logic circuit for simplified function using NOR gates only. (Dec-
2014- NEW) [NLJIET]
Reduce the expression f=ΠM(0,1,2,3,4,7) using K Map and draw the circuit with NOR gates 07
only. (Jul-2022-OLD) [NLJIET]
11 Obtain set of prime implicants for Function F=∑m(1,2,3,5,6,7,8,9,12,13,15)(Feb-2023- 07
NEW) [NLJIET]
Obtain set of prime implicants for Σm(0,1,6,7,8,9,13,14,15)(Dec-2014-OLD) [NLJIET] 07
12 Obtain set of prime implicants for πM(2,3,8,12,13).d(10,14)(Dec-2014-OLD) [NLJIET] 07
13 Using K-map find the Boolean function and its complement for the following: F(A,B,C,D) 07
= ∑(1,2,3,4,6,8,9,10,11,12,14)(May-2014-OLD) [NLJIET]
14 Simplify the following Boolean function by using the tabulation method F (A, B, C, D) = 07
Σ m (0, 1, 2, 8, 10, 11, 14, 15).(Dec-2019-NEW) [NLJIET]
Simplify following Boolean function by using the tabulation method F(A,B,C,D) = 07
Σ(1,2,3,5,6,7,8,9,12,13,15) (Nov-2017-NEW) [NLJIET]
Simplify following Boolean function by using the tabulation method 07
F = Σ(0,1,3,7,8,9,11,15)(Jun-2017-NEW) [NLJIET]
Derive Boolean function using Tabulation Method for the following: F(P,Q,R,S) = 07
∑(0,1,3,4,5,7,10,13,14,15) (May-2014-OLD) [NLJIET]
Simplify the Boolean Function by using tabulation method: F = ∑(0,1,2,8,10,11,14,15) 07
(Dec-2011-OLD) [NLJIET]
Simplify the following Boolean function using tabulation Method and draw logic diagram 07
using NOR gates only F(w,x,y,z ) = ∑(0, 1,2,8,10,11,14,15) (May-2011-OLD)[NLJIET]
Simplify the following Boolean function by means of the tabulation method: 07
F(A,B,C,D,E,F,G) = ∑ (20,28,38,39,52,60,102,103,127) (Jan-2013-OLD) [NLJIET]
Determine the Prime Implicants of following Boolean Function using Tabulation Method. 07
F(A,B,C,D,E,F,G) = ∑(20,28,38,39,52,60,102,103,127) (May-2012-OLD) [NLJIET]
Use Tabulation method & Solve Σm (0,2,6,8) + d(12,13,14,15) (May-2017-OLD) [NLJIET] 07
15 Simplify the Boolean function:(1)F=A’B’C’+B’CD’+A’BCD’+AB’C’(2)F=A’B’D’+ 07
A’CD + A’BC, d=A’BC’D+ACD+AB’D’ Where “d” indicate Don’t care conditions. (Dec-
2010- OLD) [NLJIET]
Simplify the following Boolean function using K-Map.(May-2012-OLD) [NLJIET] 04
F = A’B’C’+B’CD’+A’BCD’+AB’C’
Obtain the simplified expressions in sum of products using K-map: 07
x’z + w’xy’ + w(x’y+xy’)(Jan-2013-OLD) [NLJIET]
Minimize the following function using K-map and implement the same. 07
F = A’B’C’ +B’CD’ + A’BCD’ + AB’C’ (Jan-2017-OLD) [NLJIET]
16 Convert the following to other canonical form.(Dec-2015-OLD)[NLJIET] 07
(i)F( x,y,z) = Σ( 1,3,7) (ii) F( A,B,C,D) = π ( 0,1,2,3,4,6,12)
17 Discuss canonical and standard forms in detail. (Jun-2016-OLD)[NLJIET] 07
18 Explain SOP and POS expression using suitable examples(Mar-2010-OLD) [NLJIET] 07
Explain SoP Expressions. How do they differ from PoS ? (May-2017-OLD) [NLJIET] 07
19 Using D as the VEM, reduce Y=AʹBʹCʹDʹ+AʹBʹCDʹ+ABʹCʹDʹ+ABʹCʹD+ABʹCDʹ+ABʹCD. 04
(Jan-2017-NEW)[NLJIET]
Using D as the VEM, reduce Y=AʹBʹCʹDʹ+AʹBʹCDʹ+ABʹCʹDʹ+ABʹCʹD+ABʹCDʹ+ABʹCD. 07
(Dec-2015-NEW) [NLJIET]
Simplify following Boolean function using VEM (Jun-2017-NEW) [NLJIET] 07

F = AB’CD + A’BC’D+AB’CD’+A’B’C’D
F = A’B’C’D+A’BC’D’+A’BC’D+AB’C’D’+AB’CD’+AB’CD+ABCD’
Using D & E as the MEV, Reduce F = A’B’C’ + A’B’CD + A’BCE’ + A’BC’E + AB’C + 07
ABC + ABC’D’. (Dec-2019-NEW) [NLJIET]
Using D as the MEV, reduce Y = A'B'C'D' + A'B'CD' + AB'C'D' + AB'C'D + AB'CD + 03
AB'CD'. (Feb-2022-OLD) [NLJIET]
20 Reduce the expressions in SOP and POS form using K-map. (Nov-2017-NEW) [NLJIET] 07
F(A,B,C,D)= Σm (1,5,6,12,13,14) + d(2,4)
Use K-map and Solve Σm (0,2,6,8) + d(12,13,14,15). Write answer in SoP and PoS form 07
21 (i) Reduced to simplest form using K-map: (May-2018-OLD) [NLJIET] 07
F (A, B, C, D) = Σ(0, 1, 2, 5, 8, 9, 10)
(ii) Using D as the MEV, reduce Y=𝐴̅𝐵̅ 𝐶̅ 𝐷 ̅ + 𝐴̅𝐵̅ 𝐶𝐷
̅ + 𝐴𝐵̅ 𝐶̅ 𝐷
̅ + 𝐴𝐵̅ 𝐶̅ 𝐷 + 𝐴𝐵̅ 𝐶𝐷 + 𝐴𝐵̅ 𝐶𝐷
̅
22 Express Boolean function F=A+B’C in a sum of minterms.(Dec-2019-NEW) [NLJIET] 03
23 Given a logic function: Z = ABC + BC’D + A’BC.(March-2021-NEW) [NLJIET] 07
(i) Make a truth table.
(ii) Simplify using K-map.
(iii)Realize simplified function using NAND gates only.
TOPIC:2 Multiplexer, De-Multiplexer/Decoders, Adders, Subtractors,
BCD arithmetic, carry look ahead adder, serial adder, ALU, elementary
ALU design, popular MSI chips, digital comparator, parity
checker/generator, code converters, priority encoders, decoders/drivers
for display devices
1 How many enable lines are there in 3X8 decoder IC 74138? (Dec-2015-NEW) [NLJIET] 01
Answer : 3
2 How many selection lines are required in 32X1 MUX? (Dec-2015-NEW) [NLJIET] 01
Answer : 5
3 How many inputs are required for a 1-of-16 decoder? (Jan-2017-NEW) [NLJIET] 01
(a) 2 (b) 4 (c) 8 (d) 12 Answer : (b)
1 Draw logic circuit of 4:1 MUX. (May’2018 NEW) [NLJIET] 03
What is Multiplexer? With logic circuit and function table explain the working of 4 to 1 07
multiplexer.(Nov-2013-OLD)[NLJIET]
multiplexer.(Jun-2017-New)NLJIET]
multiplexer.(Nov-2017-New) [NLJIET]
What is meant by multiplexer? Explain with diagram and truth table the Operation of 4 to1 04
line multiplexer(Dec-2011-OLD) [NLJIET]
Explain the working of multiplexer.(May-2016-NEW) [NLJIET] 03
Explain a 4 to 1 line multiplexer in detail.(May-2013-OLD) [NLJIET] 07
With logic diagram and function table explain the operation of 4 to 1 line multiplexer.(Dec- 07
2010-OLD)[NLJIET]
With logic diagram and function table explain the operation of 4 to 1 line multiplexer.(Nov- 07
2017-OLD) [NLJIET]
Design and explain 4x1 Multiplexer (Jan-2017-OLD) [NLJIET] 07
2 How to generate 8x1 MUX using 4x1 MUX.(Jun-2019-NEW)[NLJIET] 03
3 Implement the following Boolean function using MUX (Jul-2022-NEW)[NLJIET] 07
a) F(A,B,C) = ∑(1,3,6) b) F(A,B,C) = π(2,3,5)
Implement the following Boolean functions with a 3 x 1 multiplexer F (w, x, y, z) = Σ (2, 04

3, 5, 6, 11, 14, 15)(Feb-2023-NEW) [NLJIET]
Realize the expression Y(A, B, C, D) = Ʃ m(15, 7, 4, 6, 8, 9, 12, 14) using an 8:1 MUX. 07
(May-2018-NEW) [NLJIET]
Implement the following function using 8X1 MUX F (A, B, C, D) = Σ m (0, 1, 3, 4, 8, 9, 07
15)(Dec-2019-NEW)[NLJIET]
Implement following Boolean function using8:1multiplexer F = ∑(2,3,5,7,8,9,12,13,14,15) 07
Implement the given function using multiplexer. F (A, B, C) = Ʃ (1, 3, 5, 6) (Jan-2017- 04
NEW) [NLJIET]
Implement the given function using multiplexer F (A, B, C) = ∑m (1,2,4,7) (May-2016- 04
NEW) [NLJIET]
Implement following logic function using 8X1 MUX: F = Σ m(0,1,3,5,7,11,13,14,15) (Dec- 07
2015- NEW) [NLJIET]
Design a 8 to 1 multiplexer by using the four variable function given by F(A,B,C,D) = 07
∑m(0,1,3,4,8,9,15) (Dec-2014-NEW) [NLJIET]
Implement combinational logic using 8:1 line MUX for F(A,B,C,D) = Σm (0, 2, 4, 5, 7, 9, 07
12, 15)(Dec-2015-OLD) [NLJIET]
Implement F (A, B, C, D) = Σ m (0, 1, 3, 4, 8, 9, 15) using multiplexer, choose A as input
line.(Dec-2014-OLD) [NLJIET] 07
What is multiplexer? Implement the following function with a multiplexer F(A,B,C,D) =
∑(0, 1, 3, 4, 8, 9, 15)(May-2011-OLD) [NLJIET] 07
Implement following logic function using 8X1 MUX : F = Σ m(0,1,2,3,5,8,9,11,14) (May-
2015-New)[NLJIET] 07
Implement the Boolean function F(X,Y,Z)= ∑(0,2,3,4) using suitable multiplexer.(Jul-
Implement the given function using 8 X 1 Multiplexer 07
F (A,B,C,D) = Σm (2,4,5,7,10,14) (Feb-2022-OLD) [NLJIET]
4 With logic diagram and truth table, explain the working of 3 line to 8 line decoder. (Feb- 04
2022-New)[NLJIET]
Draw logic circuit of 2x4 Decoder. (Jun-2019-NEW) [NLJIET] 04
Explain Briefly 3 to 8 Line Decoder (Nov-2017-NEW)[NLJIET] 03
Draw logic diagram of 3-line to 8-line decoder. (May-2018-NEW)[NLJIET] 04
Explain 3 to 8 line decoder.(Jan-2017-OLD)[NLJIET] 07
Explain 3 to 8 line decoder.(Jun-2015-OLD) [NLJIET] 07
With logic circuit and truth table explain working of 3 to 8 line decoder. (Nov-2013-OLD) 07
[NLJIET]
What is meant by decoder? Explain 3-to-8 line decoder with diagram and truth table (Dec- 07
2011-OLD) [NLJIET]
With logic circuit and truth table explain working of 3 to 8 line decoder. (Dec-2010- 07
OLD)[NLJIET]
With logic circuit and truth table explain working of 3 to 8 line decoder.(Nov-2017-OLD) 07
[NLJIET]
Describe a block diagram for decoder circuit. Implement 3 to 8 Decoder Circuit (May- 07
2017-OLD) [NLJIET]
Draw the logic diagram of 3 to 8 line decoder. Explain its operation with truth table.(Dec- 07
2015-OLD) [NLJIET]
5 Give the applications of Decoder. (May-2016-NEW) [NLJIET] 03
6 Design 4 X 16 decoder using two 3 X 8 decoders. (Feb-2023-New)[NLJIET] 03
Design 4-to-16 Decoder from two 3-to-8 Decoders. (May-2016-NEW) [NLJIET] 04
Design 4 X 16 decoder using two 3 X 8 decoder.(May-2015-NEW)[NLJIET] 07
Design 4 X 16 decoder using two 3 X 8 decoder.(Jan-2013-OLD) [NLJIET] 07
Design a 4-to-16 decoder by using only 2-4 decoder circuits.(May-2014-OLD) [NLJIET] 07

Construct 4*16 Decoder with help of 2*4 Decoder.(May-2012-OLD) [NLJIET] 07
7 Implement the following Boolean functions with a multiplexer and Decoder. F(w, x, y, z) 07
= Σ (2, 3, 5, 6, 11, 14, 15) (Dec-2018-NEW)[NLJIET]
Implement following functions using 3x8 decoder & logic gates, F1 = Σ m(1, 3, 4, 6), F2 = 04
Σ m(2, 4, 5, 7) .(Feb-2022-OLD)[NLJIET]
8 Draw the logic diagram of 1-digit BCD adder.(Mar-2021-NEW) [NLJIET] 03
Design a BCD adder.(Jun-2015-OLD) [NLJIET] 07
Discuss 4 bit BCD adder in detail.(May-2012-OLD) [NLJIET] 05
Design BCD adder using binary parallel adder. (Jul-2022-OLD) [NLJIET] 07
9 Explain BCD adder using two 4-bit adder IC and a correction -detector circuit(Feb-2023- 04
NEW)[NLJIET]
10 Design 3-bit even parity generator circuit.(May-2015-NEW) [NLJIET] 07
Design 3-bit even parity generator circuit using X-OR gates only.(May-2018-NEW)
[NLJIET] 07
Design 3-bit parity generator circuit using even parity bit (Jan-2017-NEW) [NLJIET] 07
11 Write a brief note on parity checker/generator.(May-2014-OLD) [NLJIET] 05
Design and explain Odd parity generator (Jan-2017-OLD) [NLJIET] 07
Design and Implement 3-bit odd parity generator circuit (Nov-2017-OLD)[NLJIET] 07
12 Explain Look-ahead Carry generator(Jul-2022-NEW)[NLJIET] 04
13 Explain magnitude comparator (Jun-2017-NEW)[NLJIET] 03
Explain magnitude comparator (Nov-2017-NEW) [NLJIET] 03
14 Design a circuit which compare two binary number whether A>B, A=B or A<B.(Aug-2023- 07
NEW)[NLJIET]
Design one bit magnitude comparator. (Jan-2017-NEW) [NLJIET] 03
Design 1-bit magnitude comparator circuit. (May-2018-NEW) [NLJIET] 03
Design 1 - bit Magnitude Comparator.(Dec-2019-NEW) [NLJIET] 04
15 Draw truth table of 2-bit digital comparator. (Feb-2023-NEW)[NLJIET] 04
Implement 2-bit Magnitude comparator. (Jul-2022-NEW)[NLJIET] 07
Explain 2-bit comparator circuit(Feb-2022-NEW)[NLJIET] 03
Draw truth table of 2-bit digital comparator (Mar-2021-NEW)[NLJIET] 03
Design a circuit for 2-bit magnitude comparator.(May-2015-NEW)[NLJIET] 07
Draw logic circuit for 2-Bit Magnitude Comparator.(Jun-2019-NEW)[NLJIET] 04
Draw logic circuit for 2-Bit Magnitude Comparator. (Jul-2022-OLD) [NLJIET] 03
16 With logic circuit explain the working of 4-bit magnitude comparator.(Nov-2013-OLD) 07
[NLJIET]
Explain 4 bit Magnitude Comparator.(May-2012-OLD) [NLJIET] 07
Design 4-bit magnitude comparator in detail.(Dec-2009-OLD) [NLJIET] 07
Draw & explain in brief pin diagram of 7485 four-bit magnitude comparator.(Dec-2015- 04
NEW) [NLJIET]
17 Explain 4-bit parallel binary adder with neat & clean diagram.(Feb-2023-NEW) [NLJIET] 04
Explain 4 bit Binary Parallel Adder. (July-2022-NEW) [NLJIET] 04
Draw & explain the operation of 4 bit binary parallel adder (Dec-2015-OLD) [NLJIET] 07
Explain 4 – bit parallel adder.(Dec-2019-NEW) [NLJIET] 04
18 Explain Half Adder circuit with neat diagram (Jan-2017-NEW) [NLJIET] 04
Explain working of Half Adder circuit with diagram.(June-2019-NEW) [NLJIET] 03
19 Draw the truth table of full adder and implement using minimum number of logic 07
gates.(Nov-2017-New) [NLJIET]
Draw the truth table of full adder and implement using minimum number of logic 07
gates.(May-2015-NEW)[NLJIET]
With necessary sketch explain full adder in detail.(Dec-2009-OLD) [NLJIET] 07
Design a full adder circuit using two half adders and gates (May-2017-OLD) [NLJIET] 07
Explain Full Adder in detail. (Jun-2016-OLD) [NLJIET] 07

Design and explain with truth table the logic circuit for full adder (Jan-2017-OLD) [NLJIET] 07
Design Full Adder circuit. (Feb-2022-OLD) [NLJIET] 04
20 Design a 3 bit Full adder circuit and implement using a half adder circuit.(Nov-2017-OLD) 07
[NLJIET]
Design a full-adder using two half-adder and an OR gate(May-2011-OLD) [NLJIET] 07
21 Write short note on half adder and full adder. (May-2016-NEW) [NLJIET] 07
Explain half and full adder in detail.(May-2013-OLD) [NLJIET] 07
22 Compare Half adder and Full adder. (Jul-2022-NEW) [NLJIET] 03
23 Design full adder circuit using decoder and multiplexer. (Feb-2022-NEW) [NLJIET] 07
Explain full adder and design a full adder circuit using 3 to 8 decoder and two OR gates 07
(Jan-2017-NEW) [NLJIET]
Design a full adder and realize full adder using 3X8 Decoder and 2 OR gates.(Dec-2019- 07
NEW) [NLJIET]
Design a full adder using 3X8 decoder followed by gates. (Dec-2015-NEW) [NLJIET] 07
Design 1-Bit Full Adder using 3x8 Decoder.(Jun-2019-NEW)[NLJIET] 07
Implement Full Adder Circuit with the help of Decoder and logic gates.(Jul-2022-OLD) 04
[NLJIET]
24 Explain the half subtractor with logic circuit. (Aug-2023-NEW) [NLJIET] 03
25 Explain Full Subtractor with truth table and circuit diagram (Jun-2017-NEW) [NLJIET] 07
Draw the truth table of full subtractor and implement using minimum number of logic 07
gates.(May-2015-NEW) [NLJIET]
Design Full subtractor circuit. (Feb-2022-OLD) [NLJIET] 04
26 Draw logic circuit of Full Adder and Full Subtractor with truth table. (Jun-2019- 07
NEW)[NLJIET]
Explain design and functioning of half and full subtractors.(Jun-2015-OLD) [NLJIET] 07
27 Implement Full Subtractor Circuit with the help of Decoder and logic gates.(Jun-2017- 07
NEW) [NLJIET]
28 With logic circuit describe the function of (1) Full adder (2) Full subtractor Write the 07
simplified Boolean functions with their outputs. (Nov-2013-OLD) [NLJIET]
29 Write a brief note on full subtractor with the help of its TT. Also design full subtractor logic 07
circuit using 3 x 8 decoder and OR gates. Use X, Y, & Z as input variables and D & B as
output variables.(Nov-2020-NEW) [NLJIET]
30 Design converter to convert decimal 8,4,-2,-1 code to BCD.(Jun-2015-OLD) [NLJIET] 07
31 Design converter to convert decimal 2,4,2,1 code to 8,4,-2,-1 code.(Jun-2015-OLD) 07
[NLJIET]
32 Design BCD to excess-3 converter.(Aug-2023-NEW)[NLJIET] 07
Design BCD to Excess 3 code converter using minimum number of NAND gates(Feb- 07
2022-NEW)[NLJIET]
Derive and draw logic circuit for BCD to Excess-3 Code converter.(Jun-2019-NEW) 07
[NLJIET]
Design BCD to Excess-3 code convertor circuit (Jan-2017-NEW) [NLJIET] 07
Design BCD to excess -3 code converter.(Jun-2015-OLD) [NLJIET] 07
Design a BCD to Excess-3 code converter using minimum number of NAND gates(Dec- 07
2014-NEW) [NLJIET]
Design and implement BCD to excess 3 code converter.(May-2013-OLD) [NLJIET] 07
Design BCD to Excess-3 code converter using minimum number of NAND gates(Dec- 08
2011-OLD) [NLJIET]
Prepare BCD to excess 3 code converter. (Jun-2016-OLD) [NLJIET] 07
Design a BCD to excess 3 code converter and implement using various logic gates(Feb- 07
2022-OLD) [NLJIET]

33 Explain excess -3 code & gray code (Nov-2017-New)[NLJIET] 07

Explain excess -3 code & gray code (Dec-2015-OLD)[NLJIET] 07
34 Design 4 bit binary to BCD code converter (Mar-2010-OLD) [NLJIET] 07
Design 4 bit binary to BCD code converter and implement using EX-OR gates only(Nov- 07
2017-OLD)[NLJIET]
35 Design a 3-bit gray to binary code converter. Implement it using suitable PROM. Draw the 07
necessary diagrams and tables.(Dec-2018-NEW)[NLJIET]
Using suitable decoder & OR gates, design 4-bit binary to Gray code converter.(May-2018- 07
NEW) [NLJIET]
Design 4 bit binary to gray code converter. (May-2016-NEW) [NLJIET] 07
Design a circuit for binary to gray code conversion.Give Example(May-2017-OLD) 07
[NLJIET]
36 Design Combinational circuit for Binary to Xs-3 conversion(Feb-2023 NEW) [NLJIET] 07
A combinational circuit has 3 inputs A, B, C and output F. F is true for following input 07
combinations(Dec-2014 NEW) [NLJIET]
A is False, B is True
A is False, C is True
A, B, C are False
A, B, C are True
(i) Write the Truth table for F. Use the convention True = 1 and False = 0.
(ii) Write the simplified expression for F in SOP form.
(iii) Write the simplified expression for F in POS form.
(iii) Draw the logic circuit using minimum number of 2-input NAND gates.
Design a Combinational circuit that convert 8- 4 -2 -1 code to BCD.(Jul-2017 NEW) 07
[NLJIET]
Design a combinational circuit with four input lines that represent decimal digit in BCD and 07
four output lines that generates the 9’s Complement of the input digit.(Jun-2017 NEW)
[NLJIET]
Design a combinational logic circuit whose output is high only when majority of inputs (A, 04
B, C, D) are low.(Dec-2018-NEW)[NLJIET]
Design the Combinational Circuits for Binary to Gray Code Conversion.(May-2012-OLD) 05
[NLJIET]
Design a combinational circuits for a full adder.(May-2012-OLD) [NLJIET] 04
Design a combinational circuit that multiplies BCD inputs by 5. Show that output can be 07
obtained from the inputs without using any logic gates.(Dec-2014-OLD) [NLJIET]
Design a combinational circuit with the four input lines that represent a decimal digit in 07
BCD and four output line that generate the 9’s complement of the input digit.(Jan-2013-
OLD) [NLJIET]
Design a combinational circuit that generates the 9’s complement of BCD digit.(Dec-2009- 07
OLD) [NLJIET]
Design a combinational circuit that accepts a three bit binary number and generates an 07
output binary number equal to the square of the input number.(Dec-2009-OLD) [NLJIET]
Design a combinational circuit whose input is a four bit number and whose Output is the 08
2’s complement of the input number.(Dec-2011-OLD)[NLJIET]
Design a combinational circuit whose input is a four bit number and whose Output is the 07
2’s complement of the input number.(May-2011-OLD)[NLJIET]
37 Show how a full-adder can be converted to a full-subtractor with the help of addition of one 07
inverter circuit.(Jan-2013 OLD)[NLJIET]
38 With a neat block diagram explain the function of encoder. Explain priority encoder? (Feb- 07
2023-NEW)[NLJIET]
With a neat block diagram explain the function of encoder. Explain priority encoder? (Dec- 07
2018-NEW)[NLJIET]
What is encoder? With logic circuit and truth table explain the working of Octal to binary 07
Encoder.(Nov-2013-OLD)[NLJIET]
With a neat block diagram explain the function of encoder. Explain priority encoder? (Jul- 07
2022-OLD)[NLJIET]
39 Explain common cathode types seven segments displays.(May-2012-OLD)[NLJIET] 03
40 Write a brief note on BCD-to-7-segment decoder/driver. Set up a single 7-segement LED 07
display using 7447 BCD-to-7-segment decoder/driver. (Nov-2020-NEW) [NLJIET]
41 Explain the design of Arithmetic Logic Unit(Mar-2010-OLD) [NLJIET] 07
Draw & explain the block diagram of ALU. (Nov-2020-NEW) [NLJIET] 04
Draw & explain the logic diagram of ALU. (Dec-2011-OLD) [NLJIET] 08
42 Draw block diagram of a 4-bit arithmetic logic unit. Design an adder/subtractor circuit with 07
one selection variable S and two inputs A and B.when S = 0 circuit performs A+B, when S
= 1 circuit performs A – B by taking the 2’s complement of B.(May-2011-OLD) [NLJIET]
43 Define: [1] Comparator [2] Encoder [3] Decoder [4] Multiplexer [5] De-multiplexer 05
(Mar-2010-OLD) [NLJIET]
MODULE 3: SEQUENTIAL CIRCUITS AND SYSTEMS

TOPIC:1 A 1-bit memory, the circuit properties of Bistable latch, the
clocked SR flip flop, J- K-T and D types flip flops, applications of flip
flops
1 What is difference between latch and flip-flop? (May-2016-NEW) [NLJIET]Answer : 01
Latch is level triggered , Flipflop is edge triggered
2 Which latch is also known as transparent latch? (Dec-2015-NEW)[NLJIET]Answer : D 01
Latch
3 Which flip-flop is also known as ones-catching flip-flop? (Dec-2015-NEW)[NLJIET] 01
Answer : Master Slave Flipflop
4 What is the use of state diagram?(May-2016-NEW)[NLJIET]Answer :To give graphical 01
representation of state table
5 Define race around condition. (May-2016-NEW) [NLJIET] 01
6 What is a state equation?(May-2016-NEW)[NLJIET]Answer:It is the algebraic 01
equation of next state
7 Define the following terms: Flip Flop(Nov-2013-OLD) [NLJIET] 01
8 Define: sequential logic circuit(Nov-2013-OLD) [NLJIET] 01
9 Define: Flip-Flop(Mar-2010-OLD) [NLJIET] 01
10 What is the significance of the J and K terminals on the J-K flip-flop? 01
(a) There is no known significance in their designations.
(b) The J represents “jump,” which is how the Q output reacts whenever the clock goes
high and the J input is also HIGH.
(c) The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
(d) All of the other letters of the alphabet are already in use.(Jan-2017-NEW)[NLJIET]
Answer : (a)
11 Define: state table(May-2015-NEW) [NLJIET] 01
12 Calculate the number of state flip-flops required to generate 49 states?(May-2015-NEW) 01
[NLJIET]
1 Give the difference between sequential circuit and combinational circuit.(Jul-2022 03
NEW)[NLJIET]
Distinguish between Combinational Circuit & Sequential Circuit(Nov-2017- 03
NEW)[NLJIET]
Distinguish between combinational and sequential logic circuits. Give the applications of 07
flip-flops.(May-2016-NEW) [NLJIET]
Explain Design Procedure for Combinational Circuit & Difference between Combinational 04
Circuit & Sequential Circuit.(May-2012-OLD)
2 Answer the following (i)Give comparison between combinational and Sequential circuits 04
(ii)What is race-around condition in JK flip-flop? (May-2011-OLD) [NLJIET]
3 State & explain any four operating characteristics of a flip flop (Dec-2015-OLD) [NLJIET] 07
4 Draw logic diagram, graphic symbol, and Characteristic table for clocked D flip flop(Nov- 03
2017-NEW) [NLJIET]
Draw logic diagram, graphic symbol, and Characteristic table for clocked D flip flop(May- 03
2011-OLD)[NLJIET]
Show the logic diagram of clocked D Flip-flop(Dec-2009-OLD) [NLJIET] 02
5 Explain SR flip-flop using characteristic table & characteristic equation(Feb-2023-NEW) 03
[NLJIET]
Explain RS flip flop in detail. (Jan-2017-NEW) [NLJIET] 04
Explain SR flip-flop using characteristic table & characteristic equation.(Dec-2019-NEW) 03
[NLJIET]
What is a combinational circuit? Why it is required in digital circuits? Explain working and
construction of R-S flip flop in detail. (Nov-2017-OLD) [NLJIET] 07
6 Explain NAND SR Latch. (Jul-2022-NEW) [NLJIET] 03
Draw gated SR latch using NAND gates only. (May-2018-NEW) [NLJIET] 03
7 Draw logic diagram, graphical symbol and Characteristic table for clocked T flip-flop. 03
8 Draw the circuit of a J-K flip-flop.(Aug-2023-NEW) [NLJIET] 03
Explain JK Flip-Flop. (Jul-2022-NEW) [NLJIET] 07
Explain JK Flipflop. What is disadvantage of it and how it can be eliminated?(Jan-2013- 07
OLD) [NLJIET]
Explain JK flip flop with its characteristic table and excitation table.(Jun-2017-NEW) 04
[NLJIET]
With logic diagram and truth table explain the working JK Flipflop. Also obtain its 07
characteristic equation. How JK flip-flop is refinement of RS flip-flop?(Dec-2010-OLD)
[NLJIET]
9 Discuss edge triggered flip flop in detail. (Jun-2016-OLD) [NLJIET] 07
10 Explain S-R clocked flip flop. (Feb-2022-NEW) [NLJIET] 04
Discuss Clocked R-S Flip-flop with Logic diagram, Symbol, Characteristic table and 04
Characteristic equation(Jul-2022-OLD) [NLJIET]
With neat sketch explain the operation of clocked RS flip-flop(Dec-2009-OLD) [NLJIET] 05
With the help of function table and circuit diagram explain the working of clocked SR flip 04
flop.(May-2015-NEW) [NLJIET]
Discuss Clocked R-S Flip-flop with Logic diagram, Symbol, Characteristic table and 07
Characteristic equation.(Dec-2018-NEW) [NLJIET]
11 Draw the circuit diagrams and Truth table of all the Flip flops (SR, D).(Jun-2019-NEW) 04
[NLJIET]
Draw the circuit diagrams and Truth table of all the Flip flops (SR, D, T and JK).(Dec-2014- 07
NEW) [NLJIET]
Draw the Characteristic tables of following Flip-flop.(Dec-2018-NEW) [NLJIET] 03
1. R-S 2. J-K 3. T
Draw the truth tables for JK & T FF. Using these truth tables, derive & explain the excitation 07
tables of JK & T FF.(May-2018-NEW) [NLJIET]
Draw & explain T Flip Flop and D Flip Flop (Jan-2017-OLD) [NLJIET] 07
Explain the working of D Flipflop and T Flipflop using Truth Table (May-2017-OLD) 07
[NLJIET]
Draw and explain working of following flip-flops.(Mar-2010-OLD) [NLJIET] 07

[1] Clocked RS [2] JK
Draw the circuit diagrams, Truth table and excitation table of all the Flip flops (SR, D, T 07
and JK). (Feb-2022-OLD) [NLJIET]
12 Explain working of master-slave JK flip-flop with necessary logic diagram, state equation 07
and state diagram(Jun-2019-NEW) [NLJIET]
Explain working of master-slave JK flip-flop with necessary logic diagram, state equation 07
and state diagram(Nov-2017-NEW)[NLJIET]
Draw and explain Master – slave Flip flop.(Dec-2014-OLD) [NLJIET] 07
Write a note on Master-Slave Flip-Flop.(May-2014-OLD) [NLJIET] 07
With logic diagram explain the function of master-slave flip-flop.(Nov-2013-OLD) 05
[NLJIET] 07
Explain Master Slave Flip Flop through J K Flip Flop.(May-2012-OLD) [NLJIET] 07
Explain the working of the Master Slave J K flip-flop(May-17-OLD)[NLJIET] 06
Explain the working of the Master Slave J K flip-flop(Dec-2011-OLD) [NLJIET] 06
Explain working of master-slave JK flip-flop with necessary logic diagram, state equation
and state diagram(May-2011-OLD)[NLJIET] 03
Explain Master Slave JK flip-flop with truth table and circuit diagram(Jun-2017-
NEW)[NLJIET] 07
Draw & explain Master-Slave J-K Flip Flop (Jan-2017-OLD)[NLJIET] 07
Draw & explain Master-Slave J-K Flip Flop (Nov-2017-OLD)[NLJIET] 07
Explain working of master-slave JK flip-flop with necessary logic diagram, state equation
and state diagram(Jul-2022-OLD)[NLJIET]
13 What is race around condition (racing)? How to solve it? (July-2022-NEW)[NLJIET] 07
What is race around condition in JK flip flop. (Feb-2022-NEW)[NLJIET] 03
Write a brief note on race around condition and its solution. Draw & explain the logic 07
diagram of master-slave JK flip-flop.(Mar-2021-NEW) [NLJIET]
What is race around condition in JK flip flop.(Dec-2019-NEW)[NLJIET] 03
What is race around condition in JK flip flop.(Jun-2019-NEW)[NLJIET] 03
What is race around condition in JK flip flop.(Jan-2017-NEW)[NLJIET] 03
14 Do the conversion of JK flip flop to T flip flop and D flip flop to JK.(Feb-2023-NEW) 07
[NLJIET]
Implement D flip flop using JK flip flop.(Feb-2022-NEW) [NLJIET] 04
Construct D FF using SR FF. Write truth table of D FF. (Nov-2020-NEW) [NLJIET] 03
Design D FF using SR FF. Write truth table of D FF (Mar-2021-NEW) [NLJIET] 03
Design JK flip-flip using D flip-flip. (Dec-2019-NEW) [NLJIET] 07
How SR FF can be converted into JK FF? Draw & explain in brief.(Nov-2020-NEW) 04
[NLJIET]
Convert D flip flop into SR flip flop.(May-2015-NEW) [NLJIET] 07
Implement T flip flop using D flip flop. (May-2016-NEW) [NLJIET] 03
Implement D flip flop using JK flip flop.(Dec-2014-NEW) [NLJIET] 07
Convert SR flip-flop into JK flip-flop(Mar-2010-OLD) [NLJIET] 07
Convert J K Flip Flop to S R Flip flop. Show the logical diagram of clocked S R Flip flop 07
with AND and NOR gates.(Dec-2014-OLD) [NLJIET]
Implement T flip flop using JK flip flop. (Jul-2022-OLD) [NLJIET] 03
Implement D flip flop using T flip flop. (Feb-2022-OLD) [NLJIET] 04
15 Write a brief note on edge-triggered SR and JK Flip-Flops.(May-2014-OLD) [NLJIET] 07
16 Design a sequential with JK flip-flops to satisfy the following state equations: (i)A(t+1) = 07
A’B’CD+A’B’C+ACD+AC’D’ (2) B(t+1) = A’C+CD’+A’BC’ (3) C(t+1) = B (4) D(t+1)
= D’ (Nov-2013-OLD)[NLJIET]

Design a sequential with JK flip-flops to satisfy the following state equations: (i)A(t+1) = 07
A’B’CD+A’B’C+ACD+AC’D’ (2) B(t+1) = A’C+CD’+A’BC’ (3) C(t+1) = B (4) D(t+1)
= D’ (May-2012-OLD) [NLJIET]
17 Explain different methods of Triggering of flip-flop. (Aug-2023-NEW)[NLJIET] 03
Explain clock triggering mechanism. (Jul-2022-NEW)[NLJIET] 04
18 Explain D type positive edge triggered flip flop.(May-2013-OLD)[NLJIET] 07
Discuss D-type edge- triggered flip-flop in detail.(Dec-2009-OLD)[NLJIET] 07
19 For the figures 1, 2, & 3, plot the output waveforms referenced to the clock signal assuming 07
the initial contents of all FFs is Q = 0. Assume all FFs are edge triggered.(Dec-2015-NEW)
[NLJIET]
20 Explain the procedure followed to analyse a clocked sequential circuit With suitable 10
example(Dec-2011-OLD) [NLJIET]
21 Explain edge triggering and level triggering (Jan-2017-NEW) [NLJIET] 03
22 Plot the out waveform referenced to the clock signal assuming the initial contents of the 03
flip-flops is q=0. Assume all flip-flops are edge triggered. (Jun-2017-NEW) [NLJIET]
23 Draw high assertion & low assertion input SR latches. (May-2018-NEW) [NLJIET] 03
Draw & explain in brief a high assertion input SR latch. (Dec-2015-NEW) [NLJIET] 03
24 1. Fill in values for S & R to cause the Q values of the SR FF given in figure 4. 04
2. Plot the output waveform for the inputs shown in figure 5, assuming the initial contents
of the FF is Q = 0. (Dec-2015-NEW) [NLJIET]
25 Write a short note on the applications of the flip-flops.(Nov-2020-NEW) [NLJIET] 07

26 Determine the minimum state table equivalent shown in following table and draw the 07
reduced state diagram. (Dec-2018-New) [NLJIET]
27 Define following terms w.r.t State Machine. 1. State Table 2. State Diagram.(Dec-2018- 03
New) [NLJIET]
Define: state table, state equation, state diagram, input & output equations(Dec-2011-OLD) 04
[NLJIET]
Define State Table and State Diagram (Jul-2022-OLD) [NLJIET] 03
28 With suitable design example discuss the basic design principles of Asynchronous State 07
Machines design(Jul-2022-OLD) [NLJIET]
29 Compare asynchronous and synchronous state machines(Jul-2022-OLD) [NLJIET] 03
TOPIC:2 shift registers, applications of shift registers, serial to parallel
converter, parallel to serial converter, ring counter, sequence generator
1 Define the following terms: Register (Nov’13 OLD) [NLJIET] 01
2 How many flip flops are required to build a shift register to store following numbers? (May- 04
2012-OLD) [NLJIET] (01
(i)Decimal 28 (ii) Binary 6 bits (iii) Octal 17 (iv) Hexadecimals A Marks
Answer : (i) 5 (ii) 6 (iii) 6 (iv) 4 Each)
1 Draw & explain in brief the logic diagram of 4-bit bidirectional shift register.(Nov-2020- 04
NEW) [NLJIET]
With a neat sketch design 4-bit bidirectional shift register.(May-2015-NEW) [NLJIET] 07
Draw & explain in brief the logic diagram of 4-bit bidirectional shift register.(Mar-2021- 04
NEW) NLJIET]
With necessary sketch explain Bidirectional Shift Register with parallel load.(Nov-2017- 07
NEW) [NLJIET]
Write a short note on four bit Universal Shift Register.(Dec-2014-NEW) [NLJIET] 07
Explain in detail bidirectional shit register with parallel load.(Jan-2013-OLD) [NLJIET] 07
Draw and explain the block diagram of 4-bit bidirectional shit register with Parallel load. 07
(Dec-2011-OLD) [NLJIET]
With necessary sketch explain Bidirectional Shift Register with parallel load.(Nov-2017- 07
NEW) [NLJIET]
Write short note on four bit Universal Shift Register. (Feb-2022-OLD)[NLJIET] 07
2 Design a circuit for 4-bits parallel register with load with D Flip-Flops. Load input decides 07
whether to load new input or to apply no change conditions.(May-2014-OLD) [NLJIET]
3 What is the difference between serial and parallel transfer? What type of registers are used 07
in each case.(May-2013-OLD) [NLJIET]
4 Design the four bit Johnson counter and explain the operation.(Aug-2023-NEW)[NLJIET] 07
Explain Johnson Counters.(May-2012-OLD) [NLJIET] 07
Construct a Johnson counter with Ten timing signals.(Dec-2009-OLD) [NLJIET] 07
5 Define the different mode of operation of registers & explain any two in details.(May-2012- 07
OLD) [NLJIET]
6 Describe the operation of a shift register with suitable diagram.(Aug-2023- 04
NEW)[NLJIET] 07
What is the function of shift register? With the help of simple diagram explain its working.
With block diagram and timing diagram explain the serial transfer of information from
register A to register B.(Dec-2010-OLD) [NLJIET] 07
Discuss in detail shift Registers.(Nov-2017-OLD)[NLJIET]
7 What are qualitative differences between parallel loading and serial loading in shift 04
registers? (Aug-2023-NEW)[NLJIET]
Explain 4 bit serial in serial out shift register (Jun-2019-NEW)[NLJIET] 04
Explain 4 bit serial in serial out shift register (Jan-2017-NEW)[NLJIET] 07

Draw and explain 4-bit serial-in serial-out shift register using D FFs.(May-2018-NEW) 04
[NLJIET]
Explain the working of SISO shift register. (Dec-2019-NEW) [NLJIET] 04
With neat logic diagram, explain serial in parallel out shift register(Jan-2017- 07
OLD)[NLJIET] 04
Explain Serial Transfer w.r.t Shift Register with suitable example.(Dec-2018-NEW)
[NLJIET] 07
Classify Registers. Describe any one of them in details(May-2017-OLD)[NLJIET] 04
Explain 4-Bit serial in serial out shift register. (Jul-2022-OLD)[NLJIET]
8 Construct a ring counter with five timing signals. (Feb-2022-NEW)[NLJIET] 04
Design 4-bit Ring counter using D flip-flip.(Dec-2019-NEW) [NLJIET] 07
Draw and explain Ring counter. (Jun-2019-NEW) [NLJIET] 04
Draw and explain Ring counter (Jun-2017-NEW)[NLJIET] 04
Write a short note on ring counter. (Jul-2022-OLD)[NLJIET] 04
9 Explain types of shift-register and their application.(Feb-2023-NEW)[NLJIET] 04
Discuss the application of shift registers. (Jul-2022-NEW)[NLJIET] 03
List out various application of the shift register and explain any one.(Nov-2020-NEW) 03
[NLJIET]
10 List out and explain any one application of the register (Mar-2021-NEW)[NLJIET] 03
TOPIC:3 Ripple(Asynchronous) counters, synchronous counters,
counters design using flip flops, special counter IC’s, asynchronous
sequential counters, applications of counters
1 Define the following terms: Counter (Nov-2013-OLD) [NLJIET] 01
2 How many flip flops are required to count the sequence from 0 to 63?(Jan-2017-NEW) 01
[NLJIET] Answer : 6
1 Design a 3 bit synchronous counter using JK flip flop. (Aug-2023-NEW)[NLJIET] 07
2 Explain working of counter. (Jul-2022-NEW) [NLJIET] 04
3 Design a 4-bit synchronous down counter using T flip-flops.(Mar-2021-NEW) [NLJIET] 07
4 Design 3-bit synchronous up counter using T flip flop. (Jan-2017-NEW) [NLJIET] 07
Design a 3-bit synchronous up counter using K-maps and positive edge-triggered JK FFs. 07
Design a mod-12 Synchronous up counter using D-flipflop.(Dec-2014-NEW) [NLJIET] 07
Design a 3-bit synchronous up counter positive edge-triggered JK FFs.(Feb-2010-OLD) 07
[NLJIET]
5 Design a sequential circuit using JK Flip-Flops and two states Q0 and Q1 such that, 09
1. It moves to the next state for input 0. (00 to 01, 01 to 10,…, 11 to 00)
2. It moves to the previous state for input 1. (reverse from the above mentioned
steps) (May-2014-OLD) [NLJIET]
Design sequential counter as shown in the state diagram using JK flip-flops.(Mar-2010-
OLD) [NLJIET] 07
6 Differentiate synchronous counter and asynchronous counter.(Feb-2023-NEW)[NLJIET] 03

Give the comparison between synchronous and asynchronous counters.(Nov-2017-NEW) 04

[NLJIET]
Give the comparison between synchronous and asynchronous counters.(May-2016-NEW) 04
[NLJIET]
7 Explain the working of 4 bit binary ripple counter. (Feb-2022-NEW) [NLJIET] 07
Design 4-bit ripple counter using negative edge triggered JK flip flop.(Nov-2017-NEW) 07
[NLJIET]
Design 4-bit ripple counter using negative edge triggered JK flip flop.(May-2015-NEW) 07
[NLJIET]
Write a note on Binary Ripple Counter.(May-2014-OLD) [NLJIET] 07
With logic diagram explain the operation of 4 bit binary ripple counter. How up counter can 07
be converted into down counter?(Nov-2013-OLD) [NLJIET]
Explain 4 bit binary ripple counter.(May-2012-OLD) [NLJIET] 07
Explain working of 4-bit binary ripple counter(Dec-2011-OLD) [NLJIET] 07
Give classification of counters and explain asynchronous 4-bit binary ripple counter 07
With logic diagram explain the operation of 4 bit binary ripple counter.Explain the count 07
sequence.How up counter can be converted into down counter?(Dec-2010-OLD)
[NLJIET] 07
Explain 4 bit ripple counter using timing diagrams (May-2017-OLD) [NLJIET]
8 Explain 3 bit binary counter with necessary diagrams. (Jun-2016-OLD) [NLJIET] 07
9 Design a synchronous BCD counter with JK Flipflop.(May-2016-NEW)[NLJIET] 07
Design a synchronous BCD counter with JK Flipflop.(Dec-2014-OLD)[NLJIET] 07
Design a synchronous BCD counter with JK Flipflop.(May-2013-OLD)[NLJIET] 07
Design BCD synchronous Counter (May-2017-OLD) [NLJIET] 07
10 Design and explain 4-bit Ripple UP/DOWN Counter using positive edge triggered Flip 07
flop.(Dec-2014-OLD) [NLJIET]
11 Design mod-6 asynchronous counter using T flip flop. (Feb-2023-NEW) [NLJIET] 07
Design and implement a Modulo-6 Asynchronous counter using T Flip flop.(Dec-2014- 07
OLD) [NLJIET]
Design and Implement a Mod-10 asynchronous counter with T FF.(May-2014-OLD) 07
[NLJIET]
Design 4 bit asynchronous up counter. (Jul-2022-OLD) [NLJIET] 07
12 Design a counter to generate the repetitive sequence 0,4,2,1,6(Feb-2022-NEW) [NLJIET] 07
Design a counter with the following binary sequence: 0, 1, 3, 7, 6, 4 and repeat. Use T – 07
flip-flops. (Dec-2019-NEW) [NLJIET]
Design a counter to generate the repetitive sequence 0, 3, 5, 7, 4 using D FFs.(May-2018- 07
NEW) [NLJIET]
Design a counter with the following binary sequence:0, 1, 3, 7, 6, 4 and repeat. Use T 07
flipflop. (Jan-2013-OLD) [NLJIET]
Design a counter with following binary sequence: 0,1,3,7,6,4, and repeat.(Use T flip- 07
flop)(Dec-2009-OLD) [NLJIET]
Design counter with the following binary sequence:0, 4,2,1,6 and repeat. Use JK flip- 07
flops(Dec-2010-OLD) [NLJIET]
Design a counter with following binary sequence: 0,4,2,1,6 and repeat (Use JK flip- 07
flop)(Dec-2009-OLD) [NLJIET]
Design a counter to generate the repetitive sequence 0,1,2,4,3,6(Jun-2017-NEW) 07
[NLJIET]
Design a counter for following binary sequence 0-1-3-4-6-0.(Dec-2018-NEW) [NLJIET] 07
Design a counter using T FF for following binary sequence 0-1-3-4-6-0. (Jul-2022-OLD) 07
[NLJIET]

13 Explain BCD Ripple counter and draw its logic diagram and timing diagram.(Jan-2013- 07
OLD) [NLJIET]
Draw the state diagram of BCD ripple counter, develop it’s logic diagram, and explain it’s 07
operation.(Dec-2009-OLD) [NLJIET]
Design BCD Ripple Counter (May-2017-OLD) [NLJIET] 07
14 Explain 4-bit up-down binary synchronous counter.(May-2012-OLD) [NLJIET] 07
15 Design Modulo-8 counter using T flip flop. (Jan-2017-NEW) [NLJIET] 07
16 How does a counter works as frequency divider? Explain with suitable example. 04
(Jan-2017-NEW) [NLJIET]
Draw a frequency divider using JK FFs to divide input clock frequency by a factor of 8. 04
(Feb-2022-OLD) [NLJIET]
17 Design and explain BCD Counter (Jan-2017-OLD) [NLJIET] 07
18 Design a synchronous Counter that goes 0,2,3,7,0,2,3,… (May-2017-OLD) [NLJIET] 07
19 What is “Lock out” condition in counter? How to avoid it.(Dec-2018-NEW) [NLJIET] 03
What is “Lock out” condition in counter? How to avoid it. (Jul-2022-OLD) [NLJIET] 03
20 Design a 3-bit binary counter.(Dec-2018-NEW) [NLJIET] 07
21 Design a 4-bit ripple up counter using JK flip-flops.(Mar-2021-NEW) [NLJIET] 04
Design 3-bit ripple up-counter using negative edge triggered JK flip flops. Also draw the 04
waveforms. (May-2018-NEW) [NLJIET]
Design a 3-bit ripple up counter using positive edge-triggered JK FFs. (Feb-2022-OLD) 07
[NLJIET]
22 Design synchronous counter for sequence: 0->1-> 3->4->5->7-> 0 using T flip-flop.(Jun- 07
2019-NEW) [NLJIET]
23 Design a 3-bit synchronous up counter using JK flip-flops.(Nov-2020-NEW) [NLJIET] 07
24 Construct a 3-bit ripple up counter with preset and clear facility using T FFs.(Nov-2020- 04
NEW) [NLJIET]
25 Design a 4 bit binary up counter (Nov-2017-OLD) [NLJIET] 07
26 Draw a frequency divider using JK FFs to divide input clock frequency by a factor of 8. 03
27 Explain the working of 4 bit asynchronous counter (March-2010-OLD) [NLJIET] 07
MODULE 4: A/D AND D/A CONVERTERS

TOPIC:1 Digital to analog converters, weighted resistor/converter, R-2R
Ladder D/A converter, specifications for D/A converters, examples of
D/A converter ICs, sample and hold circuit, analog to digital converters:
quantization and encoding, parallel comparator A/D converter,
successive approximation A/D converter, counting A/D converter, dual
slope A/D converter, A/D converter using voltage to frequency and
voltage to time conversion, specifications of A/D converters, example of
A/D converter ICs
1 List out various characteristics of a D/A converter. Discuss any one.(Mar-2021-NEW) 03
[NLJIET]
Discuss any two characteristics of a D/A converter. (Nov-2020-NEW)[NLJIET] 04
2 How can we describe the resolution of a D/A converter? (Aug-2023-NEW)[NLJIET] 03
A 10-bit D/A converter provides an analog output which has a maximum value of 10.23 04
volts. Find the resolution of this D/A converter. (Aug-2023-NEW)[NLJIET]
A 10-bit D/A converter has a step-size of 10 mV. Determine the full-scale output voltage 04
and the percentage resolution. (Aug-2023-NEW)[NLJIET]
3 Explain the specification of D/A converter.(Dec-2019-NEW)[NLJIET] 03
4 List out various commonly used D/A converters. Draw & explain any one D/A converter. 07
(Feb-2023-NEW)[NLJIET]
Classify different types of digital to analog converters (Jul-2022-NEW)[NLJIET] 03
List out various commonly used D/A converters. Draw & explain any one D/A 07
converter.(Mar-2021-NEW)[NLJIET]
5 Explain R-2R ladder type D/A converter. (Feb-2023-NEW)[NLJIET] 03
Explain the working of R-2R ladder type D/A converter.(Aug-2023-NEW)[NLJIET] 07
What is Digital to Analog converter? Draw and Explain R-2R DAC(Feb-2022-NEW) 07
[NLJIET]
Write short note on R-2R ladder type DAC.[NLJIET] 07
With the help of neat diagram, explain the working of R 2R ladder type DAC. Draw suitable 07
waveforms.[NLJIET]
Explain R-2R ladder type digital to analog converter.[NLJIET] 07
Explain R-2R ladder type D/A converter (Dec-2019-NEW) [NLJIET] 04
6 Explain interfacing of a digital computer to the analog world.[NLJIET] 07
7 Draw the diagram of Switched capacitor type DAC and explain its operation.[NLJIET] 04
8 Describe operation of D/A converter with binary-weighted resisters(Jul-2022- 07
NEW)[NLJIET]
Draw & explain weighted-resistor D/A converter with necessary equations. (Nov-2020- 07
NEW) [NLJIET]
9 State and define any three specifications of ADC.[NLJIET] 03
10 Draw & explain Flash A/D converter with necessary decoding table. Also mention pros & 07
cons of the same. (Nov-2020-NEW) [NLJIET]
Explain the working of Flash type A/D converter.[NLJIET] 07
11 Explain in detail Dual Slope A/D converter(Feb-2022-NEW)[NLJIET] 07
Explain the working of Dual slope type A/D converter.[NLJIET] 07
12 List out various commonly used A/D converters. Draw & explain any one A/D converter. 07
(Feb-2023-NEW)[NLJIET]
Explain the types of A/D convertors.(Aug-2023-NEW)[NLJIET] 03
List out various commonly used A/D converters. Draw & explain anyone A/D converter. 07
(Mar-2021-NEW) [NLJIET]
Explain any two ADC conversion techniques.[NLJIET] 07
13 Explain dual slope analog to digital converter.[NLJIET] 07
14 Describe the successive approximation A/D conversion principle with the neat diagram, 07
explain this type of A/D converter. (Aug-2023-NEW)[NLJIET]
Explain Successive Approximation A/D converter in detail. (Feb-2022-NEW)[NLJIET] 07
With block diagram explain Successive approximation ADC.[NLJIET] 07
Explain Successive Approximation type A/D converter.(Dec-2019-NEW) [NLJIET] 07
15 Write a brief note on quantization and encoding. (Nov-2020-NEW) [NLJIET] 04
Write a brief note on quantization and encoding. (Mar-2021-NEW) [NLJIET] 04
MODULE 5: SEMICONDUCTOR MEMORIES AND

PROGRAMMABLE LOGIC DEVICES
TOPIC:1 Memory organization and operation, expanding memory size,
classification and characteristics of memories, sequential memory, read
only memory (ROM),read and write memory(RAM), content
addressable memory (CAM), charge de coupled device memory (CCD)
1 List the types of ROM.(May-2016-NEW)[NLJIET]Answer:PROM,EPROM,EEPROM 01
2 How many words a 16*8 memory can store? (May-2016-NEW) [NLJIET] Answer : 8 01
3 Define the followings. EPROM (Dec-2014-NEW) [NLJIET] 01

4 Why ROMs are called nonvolatile memory?(Jan-2017-NEW)[NLJIET]Answer:Because 01
the contents of ROM cannot be erased
5 Define the term PROM. (May-2016-NEW) [NLJIET] 01
1 Discuss in brief semiconductor memory organization and its operation.(Aug-2023- 07
NEW)[NLJIET]
Write a detailed note on semiconductor memory and PLD.(Nov-2017-OLD)[NLJIET] 07
2 Explain classification of Memories.(Dec-2019-NEW) [NLJIET] 03
3 Draw and explain the structure of a RAM cell.(Aug-2023-NEW)[NLJIET] 03
4 Explain memory unit(Mar-2010-OLD) [NLJIET] 07
Write a note on Memory. (May-2016-NEW) [NLJIET] 07
5 Differentiate between RAM & ROM. (Nov-2020-NEW) [NLJIET] 03
Compare the following in every aspect. RAM and ROM (Dec-2014-NEW) [NLJIET] 3.5
6 Explain different types of random access memories. (Jun-2016-OLD) [NLJIET] 07
7 Compare the SRAMs and DRAMs.(Aug-2023-NEW)[NLJIET] 03
Compare static RAM and dynamic RAM(Jul-2022-NEW) [NLJIET] 04
Compare SRAM with DRAM. (Nov-2020-NEW) [NLJIET] 03
8 Write a short note on Read Only Memory (ROM). (Feb-2022-NEW)[NLJIET] 04
9 List out different types of ROM. Also explain ROM. (Jul-2022-NEW) [NLJIET] 07
Explain the types of ROM.(Dec-2019-NEW) [NLJIET] 04
Write a short note on ROM & its types. (Nov-2020-NEW) [NLJIET] 07
Write short note on: Read Only Memory (ROM)(Jan-2017-NEW) [NLJIET] 07
List down the various types of ROMs and discuss and two of them.(Dec-2018-NEW) 04
[NLJIET]
Explain ROM and it’s types.(Jun-2015-OLD) [NLJIET] 07
Write short note on: Read Only Memory (ROM)(May-2011-OLD)[NLJIET] 07
Write short note on EEPROM, EPROM and PROM(Mar-2010-OLD) [NLJIET] 07
10 Draw internal organization of a 16 x 4 memory chip.(Mar-2021-NEW) [NLJIET] 03
11 Obtain 2048 x 8 memory using 256 x 8 memory chips.(Mar-2021-NEW) [NLJIET] 03
TOPIC:2 Commonly used memory chips, ROM as a PLD,
Programmable logic array, Programmable array logic, complex
Programmable logic devices (CPLDS), Field Programmable Gate Array
(FPGA)
1 Define: PLA(Mar-2010-OLD) [NLJIET] 01
1 Write a short note on FPGA(Feb-2022-NEW)[NLJIET] 04
Write a short note on FPGA. (May-2016-NEW) [NLJIET] 03
Draw & explain in brief general architecture of Xilinx FPGA. (Dec-2015-NEW) [NLJIET] 03
2 What is a programmable LOGIC Array (PLA)? Describe with a logic diagram the principle 07
of operation of a PLA. What are its advantages? (Aug-2023-NEW)[NLJIET]
Write short note on Programmable Logic Arrays.(Jun-2019-NEW) [NLJIET] 04
Explain in brief: Programmable Logic Array(Jun-2017-NEW)[NLJIET] 04
Explain PLA and it’s application.(Jun-2015-OLD) [NLJIET] 07
Write short note on Programmable Logic Arrays.(Dec-2014-NEW) [NLJIET] 07
Explain in brief: Programmable Logic Array(May-2014-OLD)[NLJIET] 07
Explain PLA in detail.(May-2013-OLD) [NLJIET] 07
Explain PLA with necessary diagrams.(Jan-2013-OLD) [NLJIET] 07
Discuss PLA in detail. (Jun-2016-OLD) [NLJIET] 07
Write short note on Programmable Logic Arrays. (Jul-2022-OLD) [NLJIET] 04
Write short note on Programmable Logic Arrays. (Feb-2022-OLD) [NLJIET] 07

3 A combinational logic circuit is defined by the functions: F1= Ʃ(0,1,2,5,7) and F2= Ʃ(1, 03
2,4, 6). Implement the circuit with a PROM. (Feb-2023-NEW)[NLJIET]
Implement the following Boolean expressions using a PROM.(Aug-2023-NEW)[NLJIET]
f1 (x2, x1, x0) = ∑ m (0, 1, 2, 5, 7) 04
f2 (x2, x1, x0) = ∑ m (1, 2, 4, 6)
Implement following functions using ROM
F1 = ∑m (1,3,4,6) and F2 = ∑m (0,1,5,7). (Feb-2022-NEW)[NLJIET] 04
Using 8x4 ROM, realize the expressions F1 = AB'C + ABC' + A'BC, F2 = A'B'C + A'BC'
+ AB'C', F3 = A'B'C' + ABC. Show the contents of all locations.(May-2018- 07
NEW)[NLJIET]
Implement following functions using ROM. (Dec-2015-NEW) [NLJIET] 07
F1 = Σ m(1, 3, 4, 6)
F2 = Σ m(2, 4, 5, 7)
F3 = Σ m(0, 1, 5, 7)
F4 = Σ m(1, 2, 3, 4)
4 A combinational logic is defined by functions: (Feb-2022-NEW)[NLJIET] 07
F1(A,B,C) = ∑m (3,5,6,7) F2(A,B,C) = ∑m (0,2,4,7)
Implement the circuit with PLA having 3 inputs, 4 product terms & 2 outputs, A 07
combinational logic circuit is defined by the functions:F1= Ʃ (0,1,2,4) and F2= Ʃ (0, 5, 6,7).
Implement the circuit with a PLA having three inputs, four product terms and two 04
outputs(Feb-2023-NEW)[NLJIET]
Implement using PLA (Aug-2023-NEW)[NLJIET] 07
f1 = ∑m(0, 3, 4, 7)
f2 = ∑m(3, 5, 6, 7)
A combinational circuit is defined by the function F1 (A, B, C,) = Σ m (4, 5, 7) 07
F2 (A, B, C,) = Σ m (3, 5, 7) Implement the circuit with a PLA having 3 inputs, 3 product
term & 2 outputs. (Dec-2019-NEW) [NLJIET]
A combinational circuit is defined by functions:(Jan-2017-NEW) [NLJIET] 07
F1(A,B,C) = ∑(3, 5, 6, 7) F2(A,B,C) = ∑(0, 2, 4, 7)
Implement the circuit with PLA having three inputs, four product term and two outputs 07
A combinational circuit is defined by functions:(May-2011-OLD)[NLJIET] 07
F1(A,B,C) = ∑(3, 5, 6, 7) F2(A,B,C) = ∑(0, 2, 4, 7)
Implement the circuit with PLA having three inputs, four product term and two outputs
5 Draw and explain in detail the block diagram of CPLD.(Mar-2021-NEW) [NLJIET] 07
Draw and explain in brief block diagram of CPLD. Also compare CPLD with FPGA. 07
(Nov-2020-NEW) [NLJIET]
6 Make comparison: (May-2018-NEW)[NLJIET] 04
i. ROM vs PLA
ii. PLA vs PAL
Compare ROM, PLA and PAL.(Nov-2017-NEW)[NLJIET] 07
Compare ROM, PLA and PAL.(May-2015-NEW)[NLJIET] 07
Compare ROM, PLA and PAL. (Jul-2022-OLD) [NLJIET] 07

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New L J Institute of Engineering and Technology Semester: III (2023)

Subject Name: Digital Fundamentals

Digital Fundamentals (3130704) 2023 Page 1

Answer the following (May-2011-OLD)[NLJIET] 07

TOPIC:2 Boolean Algebra, examples of IC gates

2 Prove following using the Boolean algebraic theorems: 03

Show that AB’C + B + BD’+ ABD’ +A’C = B+C.(Nov-2017-NEW) [NLJIET] 03

Digital Fundamentals (3130704) 2023 Page 4

Convert following Hexadecimal Number to Decimal:B28, FFF, F28(Mar-2010-OLD) 04

Digital Fundamentals (3130704) 2023 Page 7

Define following:1. Figure of merit 2.Noise margin 3.Power dissipation. (Mar-2021-NEW) 03

Digital Fundamentals (3130704) 2023 Page 9

MODULE 2: COMBINATIONAL DIGITAL CIRCUITS

Digital Fundamentals (3130704) 2023 Page 11

Simplify following Boolean function using VEM (Jun-2017-NEW) [NLJIET] 07

Implement the following Boolean functions with a 3 x 1 multiplexer F (w, x, y, z) = Σ (2, 04

Design a 4-to-16 decoder by using only 2-4 decoder circuits.(May-2014-OLD) [NLJIET] 07

Explain Full Adder in detail. (Jun-2016-OLD) [NLJIET] 07

Digital Fundamentals (3130704) 2023 Page 16

33 Explain excess -3 code & gray code (Nov-2017-New)[NLJIET] 07

MODULE 3: SEQUENTIAL CIRCUITS AND SYSTEMS

Draw and explain working of following flip-flops.(Mar-2010-OLD) [NLJIET] 07

Digital Fundamentals (3130704) 2023 Page 20

25 Write a short note on the applications of the flip-flops.(Nov-2020-NEW) [NLJIET] 07

Digital Fundamentals (3130704) 2023 Page 21

Explain 4 bit serial in serial out shift register (Jan-2017-NEW)[NLJIET] 07

6 Differentiate synchronous counter and asynchronous counter.(Feb-2023-NEW)[NLJIET] 03

Digital Fundamentals (3130704) 2023 Page 23

Give the comparison between synchronous and asynchronous counters.(Nov-2017-NEW) 04

Digital Fundamentals (3130704) 2023 Page 24

MODULE 4: A/D AND D/A CONVERTERS

MODULE 5: SEMICONDUCTOR MEMORIES AND

3 Define the followings. EPROM (Dec-2014-NEW) [NLJIET] 01

Write short note on Programmable Logic Arrays. (Feb-2022-OLD) [NLJIET] 07

Digital Fundamentals (3130704) 2023 Page 28

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