Microprocessors

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2nd Edition AP EC – 403 MP
AP
Microprocessors
For D.E.C.E II Year (4th Semester)
N. Dhananjaya * D. V Ramana
T. Muralikrishna * P. Srinivas
Price Rs: 200
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Microprocessors
Second Edition: Nov – 2018
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iii
Acknowledgement
First of all, I would like to thank God, the almighty of giving me skills to write
this book.
I am very thankful to Smt. N.DEEPA for giving me an opportunity to write
this book.
I specially grateful to my mom, Smt. T. Geetha, My dad Late. Sri. T. Subba
reddy, My Uncle Sri. C. Yerrama Reddy, Sri. K. Chandra Mouli Reddy, Sri. K.
Bhaskar Reddy, Sri. Dr. K. Kumara Swamy Reddy & My brother T. Jagadeesh
and the rest of my family, who supported and encouraged me in spite of all the time
it took me away from them.
I express my sincere gratitude to Sri. Dr. N. Sudhakar Reddy, Sri.
Dr. D. Srinivasulu Reddy, Sri. Dr. C. Chandrasekhar, Smt. V. Madhurima, Smt.
N. Suguna and Sri. P. Suresh Babu for their keen interest and encouragement in
bringing out this book.
Finally, I wish to thank Sri. N. Giri Babu and the entire team of for bringing
out this book in a short time with quality printing.
Any suggestions for the improvement of this book and inclusion of new topics
will be acknowledged and appreciated.
Author - T. Murali Krishna
.
iv
Table of Contents
Chapter Name ……. Page.No

1. Overview of 8085 ……. 1.1 – 1.41
2. Architecture of 8086 ……. 2.1 – 2.43
3. Instruction set of 8086 ……. 3.1 – 3.50
4. Programming with 8086 ……. 4.1 – 4.49
5. Introduction to Advanced microprocessors ……. 5.1 – 5.21
TIME SCHEDULE
DEDICATED
TO
My Daughter MAANYA
Author
N. Dhananjaya
1
Overview of 8085
OBJECTIVES
1.1 Draw and explain the functional block diagram of 8085

1.2 List the features of 8085 microprocessor
1.3 Explain multiplexing of Address and Data Bus
1.4 List different registers in 8085 and state their function.
1.5 Draw the pin out diagram of 8085
1.6 Explain the terms operation code, operand and illustrate these terms by
writing an instruction. Understand the hex code for the same
1.7 Define fetch cycle, execution cycle and instruction cycle
1.8 Give the syntax and function of STA, LDA, IN, OUT instructions.
1.9 Draw the timing diagrams of the above instructions, and understand
thoroughly in terms of clock cycles
1‐2 Overview of 8085
1.1 Draw and explain the functional block diagram of 8085
 The fig. 1.1 shows the functional block diagram of 8085.

 The architecture of 8085 is divided into 5 groups. These are:
1. Arithmetic and logic unit group
2. Register group
3. Interrupt control group
4. Serial I/O control group
5. Instruction register, decoder, timing and control group.
 The working of various devices of 8085 is as follows.
Maanya’s M.G.B Publications Microprocessors

Overview of 8085 1‐3
1. Arithmetic and logic unit group

 All arithmetic and logical operations are performed in the Arithmetic Logic Unit
(ALU).
 The ALU group consists of Accumulator (A). Temporary Register (TR), Flag
Register (FR) and arithmetic logic unit.
 The temporary register is not accessible to the user. Therefore, the user cannot read
the content of TR.
 Actually, this register is used to store or load the operand during arithmetic and
logical operations.
Note: Accumulator, TR and flag register are explained in section 1.6 in detail.
2. Register group
 The Intel 8085 has six general purpose registers to store 8 bit data and these
registers are identified as B, C, D, E, H and L.
 When two registers are combined, 16 bit data can be stored in a register pair. The
only possible combinations of register pairs are BC, DE and HL. These register pairs
are used to perform 16 bit operations.
 In addition to 6-GPRs, there are two 16 bit register, namely, the Stack Pointer (SP)
and Program Counter (PC).
 Address Buffer: This is an 8 bit unidirectional buffer. It is used to drive external
high order address bus A15  A 8  .
 Address/Data Buffer: This is an 8 bit bidirectional buffer. It is used to drive
multiplexed address/data bus, i.e. low order address bus (A15  A 8 ) .
Due to these buffers the address and data buses can be tri stated when they are not
in use.
3. Interrupt control group
 This block accepts the different interrupt requests from external devices and the
processor initiates some operations in response to interrupt or ignores it.
 The program that is executed in response to the interrupt is called the Interrupt
Service Routine (ISR).
 The interrupt control block has five interrupt inputs RST 5.5, RST 6.5, RST 7.5,
TRAP and INTR and one acknowledge signal INTA .
4. Serial I/O control group
 In serial communication one bit is transferred at a time over a single line.
 The 8085’s serial I/O control provides two lines, SOD and SID for serial
communication.

 The serial output data (SOD) line is used to send data serially and serial input data
(SID) line is used to receive data serially.
5. Instruction register, decoder, timing and control group
 Instruction register: When an instruction is fetched by the CPU from the memory,
it is loaded in the instruction register.
 Instruction decoder: It accepts an instruction from the instruction register decodes
it and gives the decoded instruction to control logic which in turn generates the
necessary control signals.
 Timing and control unit (TCU): The timing and control unit generates timing and
control signals for the execution of instructions. It controls data flow between the
microprocessor and peripherals (including memory).
 8-bit internal data bus: It carries instructions and data between the CPU
registers.
Fig. 1.1(a) : Block diagram of 8085 (additional fig)
1.2 List the features of 8085 microprocessor

 It is an 8-bit general purpose microprocessor.
(i.e., it can access, process or provide 8-bit data simultaneously)
 It was introduced by Intel Corporation in 1976.
 It is a 40 pin DIP IC chip manufactured using N-MOS technology.

 It operates on a single +5V power supply.
 It can operate with a 3.07MHz (3 MHz) clock frequency (crystal frequency 6.14
MHz).
 It has 16 address lines, hence its maximum addressing capacity is 216=64Kbytes
(65,536) of memory.
 It has 8 data lines.
 In 8085, the lower order addresses bus [A0 to A7] and data bus [D0 to D7] are
multiplexed to reduce number of pins.
 It supports 74 instructions with 246 op-codes.
 It provides an on-chip clock generator, hence it does not require external clock
generator, but it requires an external tuned circuit like LC, RC or crystal.
 It generates 8 bit I/O address, hence it can access 28  256 input ports and 256
output ports.
 It provides 5 hardware interrupts: TRAP, RST 5.5, RST 6.5, RST 7.5, and INTR.
 It provides one accumulator, one flag register, 6 general purpose registers and two
special purpose registers.
 It provides two serial I/O lines viz SOD and SID, hence serial peripherals can be
interfaced with 8085 directly.
 It performs the following arithmetic and logical operations: 8 bit, 16 bit binary
addition, 2 digit BCD addition, 8 bit binary subtraction logical AND, OR, EXOR,
complement and shift operations.
 8085 has capability to share its bus with external bus controller (Direct memory
access controller); for transferring large amount of data from memory to I/O and
vice versa.
Note: Drawback of 8085: The data bus is multiplexed with address bus; hence it
requires external hardware to separate data lines from address lines.
1.3 Explain multiplexing of Address and Data Bus

1. Multiplexing of Address and Data Bus
In the 8085 microprocessor, the higher order address lines i.e. A15  A8 are directly
available, but the lower order address A 7  A 0 lines are multiplexed with data lines
D7  D0 on time sharing basis, i.e. during earlier part of the bus cycle these lines are
used to carry the lower order byte of the address and during later part of the bus cycle
same lines are used to carry the 8-bit data.
The main reason for multiplexing address bus and data bus is to save the number
of pins of microprocessor.

Fig. 1.3(a)
Fig. 1.3(b)
2. De-multiplexing of Address and Data Bus
 The de-multiplexing of address/data bus (separation of address and data) is done
by using 8-bit D latch IC (74LS373) along with ALE signal. The De-multiplexing
process is illustrated in fig.1.3.

 The ALE is connected to the enable pin (G) of an external latch as shown in fig. 1.3.
At the beginning of the bus cycle, CPU places high byte of address on A8-A15 lines,
low byte of address on lines AD0 -AD7 and then sends out an active high ALE
signal to the address latch.
 When ALE goes high, the latch is transparent i.e., it's output changes
according to the input data and hence the lower order byte of the 16-bit address
is latched in 8-bit latch. Thus the output of latch provides the lower order address
A 7 A 0 .
 When ALE goes low, the latch will be disabled and the lines AD7  AD0 can be used
as data bus D 7  D 0 .
 During T1 state of every machine cycle AD7  AD0 lines carry the address part. In
this T1 state ALE signal is also high to indicate address on these lines. After T1 state
the processor will use these lines as data lines for next clock cycles onwards.
1.4 List different registers in 8085 and state their function.
The fig. 1.4(a) shows Register structure of 8085

 The various registers of INTEL 8085 are used during the execution of a program for
temporary storage of data and address.
 General purpose register (GPRs) are not used for storage of any specific type of
information. Instead, operands as well as addresses or data can be stored in them at
the time of program execution.

 Registers are not accessible to the Programmer are utilized by the ALUs and the
control section for temporary storage of instruction opcode, operand or address at
various stages of instruction execution.
1.4.1. General Purpose Registers
 The 8085 microprocessor has six 8-bit general purpose registers.
 These registers are identified as B, C, D, E, H and L. They can be combined as
register pairs: BC, DE, and HL to store 16-bit data/address, or to perform some 16-
bit operations.
 These registers are programmable, meaning that a programmer can store data in
these registers during writing his program.
Note: The no. of GPRS is limited in 8085 microprocessor due to the following
reasons:
1. In 8085, 8-bits are used for op-code. In that a few bits are spared for identifying
the registers. This puts the limit on the no. of general purpose registers.
2. The size of the integrated chip increases if the no. of GPRS are increased.
Fig. 1.4(a)
1.4.2. Special Function Registers
a) Accumulator (A)
 The accumulator is a special purpose 8-bit register and it is a part of ALU because it
often serves as one of the inputs to the ALU.
 It is extensively used in arithmetic, logical and store operations, as well as in the
input and output operations.
 Accumulator acts as the destination for results of all arithmetic and logical
operations that are performed by the ALU.

 For example, during the addition of two 1 byte integers, one of the operands must
be in accumulator and the other may be either in memory or in any one of the other
registers.
 The final result of an arithmetic and logical operation is placed in accumulator.
Note:
 Accumulator is also called as Program Status Word (PSW) whenever it is combined
with the flag register.
 Note that the size of accumulator is same as the word size of the microprocessor.
b) Flag Register (or) Status Register
 The flag register consists of five flip-flops, each flip-flop is known as flag.
 The flip-flops (Flags) are set or reset according to the conditions which arise during
an arithmetic or logical operation.
 The five status flags of Intel 8085 are accommodated, in an 8-bit register as shown
in fig. 1.4(b) called as flag register.
Fig. 1.4(b)
 The conditions of the flags are tested through software instructions.
 If the flip-flop for a particular flag is set, it indicates 1. When it is reset it indicates 0.
Carry Flag Carry flag is set if carry results out of bit D7 during arithmetic addition
or if borrow needed by bit D7 during subtraction or comparison
operations. Otherwise it is reset.
Parity Flag The parity flag is set if the result of an arithmetic or logical operation
contains even number of 1s. It is reset if the result contains odd
number of 1s.
Auxiliary In an arithmetic operation when a carry (occurs from lower nibble to
Carry upper nibble) is generated by digit D3 and passed to digit D4, the
auxiliary carry flag is set. Otherwise it is reset.
Note: This flag is used internally for BCD operations. It is not available
for programmer.

Zero Flag The zero flag is set if the result of an arithmetic or logical operation is
zero, otherwise it is reset.
Sign Flag The sign flag is set when the MSB of the result of an arithmetic or
logical operation is one. It is reset when the MSB of the result is zero.
This flag is used to represent signed numbers.
c) Program Counter
 It is a 16-bit special purpose register.
 It is used to store the address of the next instruction to be executed.
 It works as the heart of the control section in a microprocessor.
Note: Program counter acts as a memory pointer to the next instruction. How processor
increments program counter depends on the nature of the instruction, for 1 byte
instruction it increments program counter by 1, for 2 byte instruction it increments
program counter by 2, for 3 byte instruction it increments program counter by 3. Such
that program counter always points to the address of the next instruction.
d) Stack Pointer
 It is a 16-bit special purpose register.
 It holds the address of the top of the stack.
 Stack is a group of memory locations in read/write memory. It is used for saving
the contents of program counter and general purpose registers.
 The stack pointer content is automatically decrement by right amount whenever
information is stored into the stack.
 Similarly incremented by right amount if the data is retrieved from the stack.
1.4.3. Instruction Register
 The processor first fetches the op-code of the instruction from the memory and
stores this op-code in the instruction register.
 It is then sent into the instruction decoder.
 The instruction decoder decodes it according to timing and control signals.
1.4.4. Temporary Registers
 Temporary data register: It is an 8-bit register used to hold the 8-bit data
temporarily which is needed for ALU. The ALU has two inputs. One input is
supplied by accumulator and other from temporary data register.
 W and Z registers are other temporary registers.
 These registers are used to hold 8-bit data during the execution of some
instructions. These registers are not available for programmers, since 8085 uses
them internally.

Note:
 The programmer cannot access the temporary data register. However it is used for
execution of the most arithmetic and logical instructions.
 Example: ADD B is an instruction in the arithmetic group of instructions which
adds the contents of register A and register B and stores result in register A. The
addition operation is performed by ALU. The ALU take inputs from the register A
and temporary data register. The contents of register B are transferred to temporary
data register which supplies the second input to the ALU.
1.5 Draw the pin out diagram of 8085

 Microprocessor 8085 is a 40-pin IC.
 It can operates on +5V power supply and 3MHz frequency.
 The pin configuration of microprocessor 8085 is shown in fig. 1.5.
 These 40 pins are divided into six groups according to their functions. These groups
are:
Group Function Pin Details
1 Power supply & frequency signals Vcc, Vss, X1, X2, CLK OUT
2 Higher order address bus A15 - A8
3 Multiplexed address/data Bus AD7 - AD0
4 Control & status signals RD , WR , ALE, S0, S1,IO/ M ,
5 Serial I/O ports SID, SOD

6 Externally initiated signals &
acknowledge signals
a. Interrupt signals TRAP,RST7.5, RST6.5, RST5.5,
INTR, INTA ,
b. DMA signals HOLD, HLDA,
c. RESET signals
Re set IN , Reset OUT, READY
Group 1: Power supply and frequency signals

• Vcc and Vss: Pin number 40 and 20 are used as power supply pins. In which VCC
(+5V) is given to the 40th pin and ground (VSS) is connected to 20th pin.

• X1 and X2: Pin number 1 and 2 are used for crystal pins. Between these two pins
a Crystal (or tuned RC or LC network) is connected to provide the required clock
frequency to the microprocessor.
Fig. 1.5(a)

Fig. 1.5(b)
Note: The microprocessor is works at 3MHz of clock frequency. The crystal has to
generate 6MHz of clock frequency because the frequency is divided by two
internally.
d) CLK (output): Pin number 37 is used for output the clock signal. The
processor supply system clock to the other devices through this pin. The
frequency is half of the crystal frequency.

Group 2: Higher Order Address Bus (Output)
Pins 21 to 28 are used as higher order address pins. These pins have only mono
function i.e. to carry the higher order address. These are unidirectional pins. These are
designated as A8 to A15.
Note: Instead of having 24 pins for address and data lines, 8085 has only 16 pins. Out of
the 16 pins 8 pins are used to carry the higher order address and the other 8 pins are
multiplexed to carry the address as well as the data. This multiplexing is done to keep
the number of pins as minimum as possible.
Group 3: Multiplexed Address/Data Bus
Pins 12 to 19 are bi directional pins. They have dual function i.e. for data
transfer as well as to carry the lower order address. These pins are designated as AD0 to
AD7. The function of these pins will be decided by the status of the ALE signal.
Group 4: Control and Status Signal
a) Control Signals
This group of signals includes 2 control signals ( RD , WR ), and one special
signal (ALE) to perform special operations. Functions of these signals are as follows.
 RD : The pin number of RD is 32. It is an active low output control signal. If the
signal at this pin is low; the processor will read the information from memory or
input devices.
 WR : The pin number of WR is 31. It is an active low output control signal. If the
signal at this pin is low; the processor will write the information into memory or
input devices.
 ALE: It is an address latch enable signal. It goes high during first clock cycle of
every machine cycle. A high level on this pin indicates that bits on the multiplexed
bus AD7 to AD0 are lower order address bits.
Note: Falling edge of ALE may be used to latch address from lower order address
lines AD7 to AD0 .
b) Status Signals
This group of signals includes three status signals (IO/ M , S0 and S1,). These
signals are as follows.
 IO/ M : This status signal is used to differentiate between I/O and memory
operations. When it is at high, it indicates an I/O operation. When it is at low it
indicates a memory operation.
Note: The IO/ M signal is combined with RD & WR to generate I/O and memory
control signals.

 S0 & S1: These are output status signals used to give information about the
operation performed by microprocessor. The S1 and S0 lines specify four different
conditions of 8085 machine cycles. These 4 cycles are as follows:
S1 S0 Status
1 1 Opcode fetch
1 0 Read
0 1 Write
0 0 Halt
Note: When S1 and S0 is combined with IO/ M we get status of all the machine cycles
operations performed by 8085 as shown in Table.
Table : 8085 machine cycle status and control signals
Machine cycle status
IO/ M S1 S0 Status Control signal used
0 1 1 OPCODE RD  0
fetch
0 1 0 Memory read RD  0
0 0 1 Memory WR  0
write
1 1 0 I/O read RD  0
1 0 1 I/O write WR  0
1 1 1 Interrupt INTA  0
acknowledge
Z 0 0 Halt
Z X X Hold RD, WR  Z and INTA  1
Z X X Reset
Note: Z-Tristate (High impedance ) condition
X- Unspecified condition
Group 5: Serial IO Signal
 SID (input): Serial input data line. This line is used in serial data communication.
Through this pin, the serial data is received by the processor. The data on this line is
loaded into accumulator bit 7. Whenever a RIM instruction is executed.
 SOD (output): Serial output data line. This line is used in serial data
communication. Through this pin, the serial data is transmitted by the processor.
The output SOD is set or reset as specified by the SIM instruction.
Group 6: Externally initiated Signals
a. Interrupt signals TRAP,RST7.5, RST6.5,
RST5.5, INTR and INTA ,
b. DMA signals HOLD and HLDA,
c. Reset signals Re set IN , Reset OUT, and
Ready.
a) Interrupt signals:
The 8085 has 5 hardware interrupt signals that can be used to interrupt a
program execution.
Interrupt Description
INTR (Input) Interrupt Request: This is used as a general purpose interrupt.

Among interrupts it has lowest priority and non vectored
interrupt.
Show this as active Interrupt Acknowledge: This signal is sent by the
low by placing a bar microprocessor after INTR is received. This is used to
over INTA (output) Acknowledge the interrupt.
RST 7.5 (Inputs Restart Interrupts: These are vectored interrupts that transfer
RST 6.5 the program control to specific memory locations. They have
higher priorities than INTR interrupt. Among these three
RST 5.5
priority order is 7.5, 6.5 and 5.5.
TRAP (Input) This is non mask able interrupt and has highest priority.
Note:
1. The INTR and INTA signals are basically used to expand interrupt system to
more than 5.
2. The order of priorities of interrupts is as follows.
TRAP Highest priority
RST 7.5
RST 6.5
RST 5.5
INTR Lowest priority

b) DMA signals
 HOLD: It indicates that another device is requesting for the use of the address &
data bus. On receiving the HOLD request, the 8085 CPU completes the current
instruction (sets HLDA high) and relinquishes (gives) control of address & data
buses. The processor regains the buses after the removal of the HOLD signal.
 HLDA: This active high signal is used to acknowledge HOLD request.
c) RESET signals
 Reset IN : A low on this pin.
a) Resets the PC to Zero
b) Resets the interrupt enable and HLDA flip flops.
c) Tri-states the data bus, address bus and control bus (Note: only during
Reset is active)
d) Affects the contents of processor internal registers randomly.
 RESET OUT (output): This signal is used by the microprocessor to reset its
peripheral devices. It cann be used as a system RESET. The signal is synchronized
to the processor clock.
 Ready(Pin 35)
o It is used by the microprocessor to sense whether a peripheral is ready or not for
data transfer.
o A slow peripheral may be connected to the microprocessor through Ready line. If
the Ready is high the peripheral is ready to send or accept data. If it is low the
microprocessor waits till it goes high.
o The main function of this pin is to synchronize slower peripheral to the faster
microprocessor.
Additional Information
Pin diagram of 8085
8085 microprocessor was introduced by INTEL in the year 1976. It is an 8-
bit general purpose microprocessor. It has forty pins and requires +5V single
power supply. Previously it was designed with NMOS technology and present
it is designed with HMOS technology. The fig.1.5 (a) shows the pin diagram of
8085.
Pin No / Type Pin Name Function
1,2 X1, X 2 A tuned circuit like LC, RC or Crystal is connected
(Input) (Crystal or RC between These two pins to provide timing signal to
network processor.
connection)
3 Reset OUT It can be used to reset other peripherals connected in
(Output) (Peripherals the system.
reset)
4 SOD This is an output signal which enables the
(Output) (Serial Output transmission of serial data bit by bit to the external
Data) device.
5 SID This input signal is used to accept serial data bit by
(Input) (Serial Input bit from the external device.
Data)
6 TRAP This is an active high level, edge triggered, non
(Input) (Non maskable maskable, highest priority interrupt.
interrupt request)
7 RST 7.5 These are active high, edge (RST 7.5) or level (RST 6.5
(Input) (Restart interrupt and RST 5.5) triggered maskable interrupts.
7.5) These are also called vectored interrupts.
8 RST 6.5
(Input) (Restart interrupt
6.5)
9 RST 5.5
(Input) (Restart interrupt
5.5)
10 INTR INTR is an active high, level triggered general
(Input) (Interrupt purpose interrupt.
request) Among interrupts it has lowest priority and non
vectored interrupt.
11 INTA It is an output signal from microprocessor to
(Output) (Interrupt acknowledge the interrupt.
acknowledge)
12 to 19 AD0  AD7 These 8 pins are used to carry the lower order 8-bit
(Bidirectional (Multiplexed address. These are bidirectional.
tristate) Address/data
bus)
20 VSS It is ground terminal of 5volts supply
(Ground)
21 to 28 A8  A15 These pins are used to carry the higher order 8-
(Output, (Address bus) addresss bits (A15-A8) of 16- bit address. These are
tristate) unidirectional.
29,33 S0  S1 These pins are status pins. These pins indicate the
(Output) (Status signals) status of processor. They indicates which machine

cycle is in progress.
30 ALE The ALE signal is used to separate AD0  AD7 (i.e.
(Output, (Address Latch de-multiplex) to A 0  A 7 and D0  D7 . To do this
tristate) Enable)
separation a latch is connected to AD0  AD7 lines.
The latch is controlled by ALE signal.
A high level on this indicates that bits on the
multiplexed bus AD7 to AD0 are lower order address
bits.
31 WR The processor will write the information into
(Output, (Write control) memory or output devices when the signal at this pin
tristate) is low.
32 RD The signal at this pin is low; the processor will read
(Output, (Read control) the information from memory or input devices.
tristate)
34 IO / M This is the signal which separates memory and I/O
(Output, (Input-output/ devices. When IO/ M =0 the microprocessor is
tristate) memory) performing a memory related operation and when
IO/ M =1 the microprocessor is performing an I/O
device related operation.
(High=I/O, Low=Memory)
35 READY It is used by the microprocessor to sense whether a
(Input) (Wait-state peripheral is ready or not for data transfer.
request) The main function of this pin is to synchronize
slower peripheral to the faster microprocessor.
36 Re set IN A low signal at this pin Re set IN resets the
(Input) (System reset) processor.
37 CLK OUT This signal is used as a system clock for other
(Input) (Peripheral clock devices.
signal)
38 HLDA This active high signal is used to acknowledge
(Output) (Hold HOLD request.
acknowledge)
39 HOLD It indicates that another device is requesting for the
(Input) (Hold request) use of the address & data bus.
40 VCC A 5 Volts supply is connected to this pin.
(Input) (Power supply)

Fig.1.5 (a)
1.6 Explain the terms operation code, operand and illustrate

these terms by writing an instruction. Understand the hex code
for the same
 Each instruction contains two fields as shown in fig. 1.6.
 The first part of an instruction specifies the given task to be performed by the
computer is called ‘Operation Code’ or ‘Op-code’.

 The second part of the instruction is the data to be operated on, is known as
‘’operand’’.
Fig. 1.6
 The operand or data indicated in the instruction is in the forms such as:
o 8-bit or 16-bit data/address,
o Internal registers or a register and
o Memory location.
 In some cases, the operand or address/data may be absent, in the instruction.
 Example: Let us consider an instruction LDA 8100 H. In this instruction LDA is
op-code and 8100 H (16-bit address) is an operand.
Note: LDA is load the accumulator direct. The meaning of this instruction is load
the contents of a memory location whose address is 8100 H into the accumulator.
Instruction
Comment
Op-code Operand
ADI 17H The operand may be 8-bit data
LDA 8100H The operand may be 16-bit address
MOV A,B The operand may be general
purpose registers
INR M The operand may be memory
location
CMA --- In this instruction operand is not
given, it is implied.
1.7 Define fetch cycle, execution cycle and instruction cycle

1. Fetch cycle (FC)
 The process of getting an instruction from memory or I/O for execution is called
fetch operation.
 The amount of time required to fetch an instruction from the memory or I/O is
called fetch cycle.
 A typical fetch cycle is shown in the fig. 1.7(a).
Fig. 1.7(a)
 During the first clock cycle, the microprocessor unit (MPU) places the address of
the instruction on the address bus.
 During the 2nd and 3rd clock cycle the MPU receives the instruction (op-code) from
the memory.
2. Execute Cycle (EC)
 The total time required to decode the instruction fetched and execute it is known as
execute cycle.
 For simple instructions, one clock cycle is enough for decoding and execution.
 A typical execute cycle is shown in the fig. 1.7(b).
 The MPU takes one clock cycle for decoding. After Decoding, the MPU executes the
instruction. It takes two clock cycles for execution.
Fig. 1.7(b)
Note:
 Note that if an instruction contains data or operand and address which are still in
the memory, the processor has to perform one or two memory read operations to
get the desired data.
 After the execution, it may be necessary that the write operation. For this memory
write operation is performed.
 So the execution of an instruction may have one or two memory READ or WRITE
or both the cycles.
 Hence the execute cycle depends on the addressing mode and size of the
instruction.

Note: The time required to complete an execution is known as execute cycle.
3. Instruction Cycle
 The time required to complete the execution of an instruction is called an
instruction cycle.
 It is also defined as the time required to fetch, decode and execute an instruction is
known as instruction cycle.
 An instruction cycle consists of a fetch cycle and execute cycle i.e.
IC = FC + EC
 The 8085/808A instruction cycle consists of one to five machine cycles.
Fig. 1.7
Machine Cycle and T-state
1. Machine Cycle
 The time required to complete the operation of accessing either memory or I/O is
known as machine cycle.
 In the 8085, the machine cycle may consist of 3 to 6 T-states.
 In a machine cycle one basic operation such as op-code fetch, memory read,
memory write, I/O read or I/O write is performed.
 An instruction cycle consists of 1 to 5 machine cycles.
2. T-State
 The time required to complete a sub step in a machine cycle is known as T-state.
 So one cycle of the system clock is referred to as a T-state.

Instructions of 8085
An instruction is a group of binary bits (binary pattern) to perform a specific
task/work/function. The group of all instructions, called instruction set, determines
entire range of operations that are performed by the microprocessor. The 8085 has 74
important instructions. The instruction set of the 8085 can be classified based on their
size and their function.
2. Classification of Instructions Based on Size

The instruction set is classified based on the size as
a) 1-Byte instructions
b) 2-Byte instructions
c) 3-Byte instructions
a) 1-Byte Instructions
These are also called as one word instructions. A 1-byte instruction includes
both the op-code and the operand for the operation to be performed in the same byte.
That is the information regarding the operands is contained in the op-code itself. The
format of single-byte instruction is shown in the fig. 1-byte instruction occupies only
one memory location.
Op-code
1-byte
Examples for 1-byte instructions are MOV B, A (content of accumulator copied
into register B), XRA B (the content of the register B exclusive ORed with content of the
register A (accumulator).
b) 2-Byte Instructions
In a 2-byte instruction the 1st byte specifies the op-code and the 2nd byte specifies
8-bit data or 8-bit address (I/O port address).
Op-code Operand
1-byte 2-byte
This instruction occupies two memory locations. Examples for 2-byte
instructions are ADI A, 44H (the 8-bit data 44H is added with data in the register A),
MVI B, 99H (The 8-bit data 99H is transferred into the register B). All the immediate
instructions are two byte instructions. IN 23H (transfers the data present at the 8-bit
address 23H(I/O Port address) into the accumulator)
c) 3-byte Instructions
The total size of the instruction is 3-bytes. In a 3-byte instruction first byte
specifies the op-code and remaining two bytes specifies the 16-bit address. This
instruction occupies three memory locations.
Op-code Operand Operand
1-byte 2-byte 3-byte

Example for 3-byte instructions are LDA 2299H (The content of the memory
location bearing address 2299H is copied to the accumulator) JMP 2139H the program
control is transferred to the 16-bit address specified in the instruction i.e. 2139H)
2 Classifications of Instructions Based on their Function:
The instructions can be classified into five groups based on their function. They
are
a) Data Transfer Instructions
b) Arithmetic Instructions
c) Logical Instructions
d) Branching Instructions
e) Machine control Instructions
a) Data Transfer Instructions
This group of instructions are used to transfer (copy) the data from one location
(source) to another location (destination), without changing the data of the source. The
transfer of data can be taken place between general purpose registers or register to
memory location or memory location to register or between I/O devices and
accumulator. The general op-codes used for data transfer are MOV, LDAX, LDA,

LHLD, LXI, MVI, STAX, STA, IN, OUT, XCHG, PUSH and POP. No flags are affected
after execution of these instructions.
b) Arithmetic Instructions
This group of instructions is used to perform arithmetic operations such as
addition, subtraction, decrement and increment. The general op-codes used for
arithmetic instructions are ADD, ADI, SUB, SBB, DAA, DAD, DCR, INR, INX, DCX etc.
After execution of these instructions the flags are affected.
c) Logical Instructions
This group of instructions is used to perform logical operations such as ORing,
XORing, ANDing, comparison, rotation, complementing and shifting. The general op-
codes used for logical operations are ANA, ORA, XRA, CMP, CMC, RLC, RAR, RRC
etc. After execution of these instructions the flags are affected.
d) Branching Instructions
This group of instructions is used to change the sequence of flow of program
control from one memory location to another location either conditionally or
unconditionally. These instructions will modify the content of the program counter.
Most of the instructions are worked based on the status of the flags. The general op-
codes used for Branching operations are JMP, JC, JNC, JZ, JM, JPE, JPO,CALL, RET,
RSTn etc.,
e) Machine control Instructions
These instructions control the machine (processor) operations. The machine
control operations are Halt, Interrupt, No operation. The op-codes for the machine
control operations are HLT, DI, EI, SIM, RIM, NOP etc.
1.8 Give the syntax and function of STA, LDA, IN, OUT
instructions.
1.8.1. Execution of STA instruction
 STA means store accumulator directly.
 The general format of this instruction is STA addr16.
 This instruction stores the content of the accumulator in the memory location whose
address is specified in the instruction.
STA addr16 : (addr16)  (A )
 It is a 3-byte instruction.
 It requires 4 machine cycles (or) 13 T-states to execute.
 After execution of this instruction, no flags are affected.

Example 1:
Instruction STA 2050 H
Operation (2050H)  (A)
Description The content of accumulator is moved to memory location whose address
is 2050H.
Example 2:
Instruction STA C200H
Operation (C200H)  (A)

Description The content of accumulator is moved to memory location whose
address is C200H.
Example 3:
Address Mnemonics Op-code
41FF H STA 526A H 32 H
4200 H 6A H
4201 H 52 H
 Execution:
o STA means Store Accumulator -The content of the accumulator is stored in the
specified address (526A H).
o Opcode Fetch machine cycle: The opcode of the STA instruction is said to be 32 H.
It is fetched from the memory 41FF H.
o Memory Read Machine Cycle: The lower order memory address (6AH) is read
from the memory 4200H.
o Memory Read Machine Cycle: Read the higher order memory address (52H) is read
o Memory Write Machine Cycle: The combination of both the addresses are
considered and the content from accumulator is written in 526A H.
o Assume the memory address for the instruction and let the content of accumulator
is C7 H. So, C7 H from accumulator is now stored in 526A H.
1.8.2. Execution of LDA instruction
 LDA means Load the accumulator directly.
 The general format of this instruction is LDA addr16.
 The data present in the memory location, specified by a 16-bit address in the
instruction is copied to the accumulator.
LDA addr16 : (A)  (addr16)
 After execution of this instruction, no flags are affected.
 It requires 4 machine cycles (or) 13 T-states to execute.
Example 1:
Instruction LDA 205DH
Operation (A)  (205DH)
Description The content of memory location whose address is 2050H is moved to
accumulator.
Example 2:
Instruction LDA C100H
Operation (A)  (C100H)

Description The content of memory location whose address is C100H is copied to

accumulator.
Example 3:
Address Mnemonics Op-code
8000 H LDA 8500 H 3A H
8001 H 00 H
8002 H 85 H
 Execution:
o LDA means Load Accumulator. The content of the memory location whose address
is 8500 H is copied into the accumulator.
o Opcode Fetch machine cycle: The opcode of the LDA instruction is said to be 3A H.
It is fetched from the memory 8000 H.
o Memory Read Machine Cycle: The lower order memory address (00H) is read from
the memory 8001H.
o Memory Read Machine Cycle: Read the higher order memory address (85H) is read
o Memory Write Machine Cycle: The combination of both the addresses are
considered and the content from memory location 8500 H is written into
accumulator.
o Assume the memory address for the instruction and let the content of accumulator
is C7 H. So, C7 H from accumulator is now stored in 526A H.
o Let the content of memory location (8500H) is 82 H. So, 82 H from memory location
is now stored in A.
1.8.3. Execution of IN instruction
 The general format of this instruction is IN addr8.
 The data available at the port, whose address is mentioned in the instruction, is
copied to the accumulator.
IN addr8 : (A )  (8  bit port address)

 It is a data transfer instruction.
 It requires three machine cycles to execute.
 It requires 10 T-states to execute.
 After executing this instruction no flags are affected.
 Example: IN 20H
o When IN 20H instruction is executed, the microprocessor reads data from
input port bearing address 20H.
o The address of input port is given in the instruction i.e. 20H. The data is read
from input port and transferred to accumulator.
 Execution:
o The first machine cycle is a OPCODE fetch which takes OPCODE from memory.
o The next machine cycle will be operand fetch to take port address.
o This address is stored in temporary register and microprocessor starts next
machine cycle i.e. I/O read, during which data from the input port is fetched
and transferred to the accumulator.
1.8.4. Execution of OUT instruction
 The general format of the instruction is OUT addr8.
 The content of the accumulator is copied to the port, whose address is mentioned in
the instruction.
OUT addr8 : (8  bit port addres)  (A)
 It requires three machine cycles for execution.
 It requires 10 T-states for execution.
 After execution no flags are affected.
 Example: OUT 08H
o The data available in the accumulator is copied to the out port, whose address is
08H.
 Execution:
o The first machine cycle is a OPCODE fetch which takes OPCODE from memory.
o The next machine cycle will be operand fetch to take port address.
o This address is stored in temporary register and microprocessor starts next
machine cycle i.e. I/O write to transfer the content of accumulator the output
port.
Note:
(1) Contents of A 0  A 7  A8  A15 i.e. same in both IN
and OUT instruction.
(2) The differentiation between IN/OUT is made by
RD and WR .
1.9 Draw the timing diagrams of the above instructions, and

understand thoroughly in terms of clock cycles
1.9.1. Timing diagram for STA
 STA means store accumulator directly.
 It requires 4 machine cycles for execution.
 No. of T-states are 13.
Timing diagram for STA 3090H
Address Mnemonics Hex code
8550 H STA 3340 H 32 H
8551 H 40 H
8552 H 33 H
Let A = 99 H (data)
The STA 3340H instruction loads contents of A register to the memory location whose
address is 3340H. To perform this, 8085 requires 4 machine cycles.
1. OPCODE Fetch: The program counter places the address on the higher order and the
lower order address bus. This cycle will fetch OPCODE from program memory using
PC. The PC is then incremented by 1 to point to the next byte. The opcode of this
instruction is 32H.
2. Memory Read: The program counter places address on the lower order address bus
and the higher order address bus. The lower order byte of the address specified is read
using PC. The PC is then incremented by one to point to next byte.
3. Memory Read: The program counter retains the address on the lower order address
bus and the higher order address bus. The higher order byte of the address is read
using PC. The PC is then incremented by one to point to next instruction.
4. Memory Write: This machine cycle is used for writing the data from the accumulator to
addressed memory location. Address for this is given by the above 2 memory read
cycles have taken the higher and lower order address.
The fig shows the timing diagram of STA 3340H


1.9.2. Timing diagram for LDA

 LDA means Load the accumulator directly.
 It requires 4 machine cycles for execution.
 No. of T-states are 13.
Timing diagram for LDA 3330H
8550H LDA 3330 H 3A H
8551H 30 H
8552H 33 H
Let (3330H) = 45 H (data)
 The LDA 3330H loads the A register with data from memory location. The address
of memory location is 3330H.
 To perform this, 8085 requires 4 machine cycles.
1. OPCODE Fetch: The program counter places the address on the higher order and
the lower order address bus. This cycle will fetch OPCODE from program memory
using PC. The PC is then incremented by 1 to point to the next byte.

2. Memory Read: The program counter places address on the lower order address bus and the
higher order address bus. The lower order byte of the address specified is read using PC.
The PC is then incremented by one to point to next byte.
3. Memory Read: The program counter places the address on the lower order address bus and
the higher order address bus. The higher order byte of the address is read using PC. The PC
is then incremented by one to point to next instruction.
4. Memory Read: This machine cycle is used for reading the data into the accumulator from
addressed memory location. Address for this is given by the above 2 memory read cycles
have taken the higher and lower order address.
Fig. shows the timing diagram of LDA 3330 instruction.

1.9.3. Timing diagram for IN
The general format of this instruction is IN (8-bit port address)
 The data available at the port, whose address is mentioned in the instruction, is
copied to the accumulator.
 It requires three machine cycles for execution.
 It requires 10 T-states for execution.
 After executing this instruction no flags are affected.
 The function of this instruction can be understood from the following example.
Timing diagram for IN 03H
8550 H IN 05 H DB H
8551 H 05 H
Let Data = 22 H
 This instruction IN 05H will copy the contents at port whose address is 05H into the
accumulator.
1. OPCODE Fetch: The program counter places address on the lower order address
bus and the higher order address bus. This cycle is used to read OPCODE of IN
instruction i.e., DB H. The address for this machine cycle is given by PC. The PC is
then incremented by 1.
2. Memory Read: The program counter places the address on the lower order address
bus and the higher order address bus. The data byte is read from the addressed
input port. Program counter is incremented by 1.
3. I/O Read: In this I/O read machine cycle the address is given by temporary
register. It is a 8 bit address so same contents are transferred on AD0  AD 7 and
A 8  A15 and ALE is made high. The status of IO/ M line will be high, as it is a I/O
operation. All other operations are same as memory read operation.
The fig shows the timing diagram of IN 05H.

1.9.4. Timing diagram for OUT

The general format of the instruction is OUT (8-bit port address)
 It is a 2-byte instruction. It requires three machine cycles for execution. It requires 10
T-states for execution. After execution no flags are affected.
Timing diagram for OUT 20H
8550 H OUT 20 H D3 H
8550 H 20 H
Let A= 37 H (Data)
The data available in the accumulator is copied to the out port, whose address is
20 H. Assume the data available in the accumulator before execution is 37 H.
 The function of this instruction can be understood from the following example.
Example 1: Draw the Timing diagram for STA 3090H
Solution:
3054 H STA 3090 H 32 H
3055 H 90 H
3056 H 30 H
Let A = 99 H (data)

Example 2: Draw the Timing diagram for LDA 3330H

3324H LDA 3330 H 3A H
3325H 30 H
3326 H 33 H
Let (3330H) = 45 H (data)

Example 3: Draw the Timing diagram for IN 03H
2090 H IN 03 H DB H
2091 H 03 H
Let Data = 22 H
Example 4: Draw the Timing diagram for OUT 08H

4025 H OUT 08 H D3 H
4026 H 08 H
Let A= 37 H (Data)


2
Architecture of 8086
OBJECTIVES
Upon completion of the chapter the student should be able to Understand
the working of Transmission Lines
1.0 C Programming Basics.

2.1 Give the evolution of INTEL family microprocessors
2.2 Compare 8-bit and 16-bit microprocessors
2.3 Explain the concepts of Sequential processing, Parallel processing and
Pipelining
2.4 State the need of memory segmentation
2.5 State the features of 8086 microprocessor
2.6 Draw and explain the functional block diagram of 8086.
2.7 State the need of bus control logic
2.8 State the importance of segment registers
2.9 Mention the function of Instruction Pointer and its importance
2.10 Explain the Instruction Queue and its storage
2.11 List different General purpose registers and explain
2.12 State the purpose of Pointer and Index registers
2.13 Explain the working of ALU and control unit
2.14 List different flags of 8086 and mention their use
2.15 Draw and explain the pin diagram of 8086.
2.16 Describe the maximum and minimum mode operation.
2.17 Illustrate the generation of 20-bit Physical address with an example
2.18 Draw the timing diagrams of memory read and memory write cycles.
2.19 State the need of interrupts.
2.20 Explain the Interrupt response in 8086
2.21 List different types of interrupts
.
2‐2 Architecture of 8086
2.1 Give the evolution of INTEL family microprocessors

2.1.1. First Generation Microprocessors
1. The microprocessors introduced between 1971 and 1973 were the first generation
processors.
2. In 1971, Intel Corporation released the world’s first microprocessor, Intel 4004.
3. It was a 4-bit microprocessor.
4. It was designed with P-MOS technology.
5. This technology provided low cost, slow speed and low output currents and was
not compatible with TTL levels.
6. The first 8-bit microprocessor, Intel 8008 was introduced by Intel Corporation in
1972, which could perform operations on 8-bit data.
7. Some of the first generation microprocessors are: Intel 4004, Intel 4040, Intel 8008,
National IMP-4 and National-8 etc.
2.1.2. Second Generation Microprocessors
1. The second generation microprocessors appeared in 1973 and were manufactured
in NMOS Technology.
2. The NMOS technology offers faster speed and higher density than PMOS and it is
TTL compatible.
3. In 1973 the Intel Company introduced a better version and powerful 8-bit
microprocessor, the Intel 8080.
4. In 1976, the same company released the improved version of 8080, Intel 8085.
5. Some of the second generation microprocessors are: Intel 8080, Intel 8085,
Motorola M6800, and National CMP-8 etc.
2.1.3. Third Generation Microprocessors
1. After 1978, the third generation microprocessors were introduced.
2. These are 16-bit processors and designed using HMOS (High Density MOS)
Technology.
3. The HMOS is four times faster than NMOS and the density of HMOS is also
doubled.
4. In the 1978 the first 16-bit general purpose microprocessor Intel 8086 was
introduced by Intel Corporation (faster than 8085).
5. Some of the third generation microprocessors are: Intel 8086, Intel 80186, Intel
80286, Motorola 68000, Zilog Z80000 and National NS16016 etc.

Architecture of 8086 2‐3
2.1.4. Fourth Generation Microprocessors

1. The fourth generation microprocessors were introduced in the year 1980.
2. The fourth generation processors are 32-bit processors and are fabricated using
the low power version of the HMOS technology called the CHMOS.
3. Some of the fourth generation microprocessors are: Intel 80386, Intel 80486,
Motorola MC88100, and National NS 16032.
2.1.5. Fifth Generation Microprocessors
1. Pentium processors are considered as 5th generation microprocessors.
2. The Pentium is 32-bit microprocessor.
3. It has 32-bit address bus and 64-bit data bus and wide range of clock speeds from
60 MHz to 3.2 GHz.
4. It has capability to execute two instructions in one clock cycle.
5. Therefore a Pentium processor working at 1 GHz clock can execute 2000 Million
instructions per second (MIPS).
*Note: Generation of Intel Microprocessors
Generation Examples Word length
4004 4-bit
1st Generation
8008 8-bit
8080
2nd Generation 8-bit
8085
8086
3rd Generation 80186 16-bit
80286
80386
4th Generation 32-bit
80486
Pentium - I
Pentium - II
5th Generation 32-bit
Pentium - III
Pentium - IV

*Note: The table shows different types of Intel processors.
Micro Year of Word Memory
processor introduction Length Addressing Remarks
capacity
4004 1971 4-bit 1KB First microprocessor
8008 1972 8-bit 16KB First 8-bit
microprocessor
8085 1976 8-bit 64KB Popular, widely
used.
8086 1978 16-bit 1MB First 16-bit
microprocessor
8088 1980 8/16-bit 1MB Widely used in
PC/XT
80286 1982 16-bit 16MB real,4 GB Widely used in
virtual PC/AT
80386DX 1985 32-bit 4GB real, 64 TB Contains 2,75000

virtual transistors.
80386SX 1988 16/32-bit 16 MB real, 64 TB 32-bit internal

virtual architecture. 16-bit
external data bus.
80486 1989 32-bit 4GB real, 64 TB Contains floating

virtual point coprocessor
2.2 Compare 8-bit and 16-bit microprocessors

 n-bit microprocessor means how many bits a microprocessor can process at a
time.
 8-bit means that microprocessor can process only 8bit addition, subtraction etc.
 As in case 16-bit can process data of 16-bit for any kind of operation to be
performed.
 Naturally the greater the number of bits to be processed the good it is.

Sl. Parameters 8 – bit 16 – bit

No microprocessors microprocessors
1 Width of data bus. 8 - bit. 16 – bit.
2 Address bus. Up to 16 bits. Up to 24 bits.
3 Memory addressing Limited. More.
capacity.
4 Data handling Limited. More.
capacity.
5 Nature of instruction Normal. Powerful.
set.
6 Execution speed. Low. High.
7 Facilitation to write Low level languages. High level languages.
programs.
8 Cost. Low. High.
9 Memory The memory space is not The memory space is
segmentation. segmented. segmented.
10 Addressing modes. Less addressing modes. More addressing modes.
11 External hardware. It requires less external It requires more external
hardware. hardware.
12 Multi processor It does not have multi It supports multi
support. processing support. processing.
13 Co–processor It does not have It has
Interface. co–processor interface. co-processor interface.
14 Pipe lining. It does not support. It supports pipelined
architecture.
15 Arithmetic support. It only supports integer It supports integer and
arithmetic. real arithmetic.
16 Examples. 8080 & 8085. 8086 & 80286.

2.3 Explain the concepts of Sequential processing, Parallel

processing and Pipelining
2.3.1 Sequential Processing
 Definition: The process of fetching next instruction unless execution of current
instruction is not completed is known as sequential processing.
 Sequential processing is also known as serial processing.
 Basically the executions of instruction have been four parts.
o Fetching (reading the instruction from memory)
o Decoding (converting into machine level)
o Execution (getting of desired result)
o Storing (store the result in the memory)
 When CPU contains only one functional unit then it performs the above tasks
serially as shown in fig. 2.3.
Fig. 2.3
 Advantage: The processor which uses sequential processing requires less
hardware and system cost is very low.
 Disadvantages: It requires more time, so the processing speeds slow; the
processor efficiency which uses sequential processing is low.
2.3.2 Parallel Processing
 Parallel processing is also called parallel computing.
 The simultaneous use of more than one CPU (processor) to execute a program is
known as parallel processing (see fig. 2.2).
 Parallel processing used to provide simultaneous data processing tasks for
increasing computational speed of computer system.
 Ideally, parallel processing makes programs run faster.

Fig. 2.2
 Advantage: It improves cost performance ratio of the system.
 Disadvantage: The amount of hardware increases with parallel processing and
with it the cost of system increases.
2.3.3 Pipelining
 Pipelining is the advanced feature of parallel processing.
 Definition: The process of fetching the next instruction while current instruction
is under execution is called pipelining.
 Pipelining has become possible due to the use of queue.
 It is useful to speed up program execution.
 A pipeline allows multiple instructions to be processed at the same time.
 When CPU contains more than one functional units and each functional unit
performs a part of the task identically, this technique is called pipelining.
 The fetch unit fetches instruction from memory and execution unit performs
execution of instruction simultaneously as shown in fig. 2.3
Fig. 2.3
 Advantage: The computing speed is very high than the first two methods.
*Note: The pipeline method is implemented in the most advanced microprocessors like
Intel Pentium, Pentium Pro etc.
2.4 State the need of memory segmentation

 Memory segmentation is the division of computer's primary memory into
segments (parts) or sections.
 The 8086 has a 1MB memory space. This large amount of memory space cannot
utilize at a time.
 To utilize the total memory in proper way, we have to partition the memory.
 Definition: The process of portioning the large memory is called memory
segmentation and partition is referred as segment.
Fig. 2.4
 The complete 1 MB memory divided into 16 segments and each of 64 KB of size.
 Each segment is assigned a base address that identifies the starting address of the
segment.

 Only four segments can be active at a time. They are code segment, data segment,
stack segment and extra segment.
 Advantages of Memory Segmentation
o To achieve better memory organization.
o Provision of separate stack segment, the operating system will not be
corrupted.
o Easy of design of multitasking/multi-user system.
2.5 State the features of 8086 microprocessor

1. The Intel 8086 microprocessor was introduced in 1978 by Intel Corporation.
2. It was the first 16-bit microprocessor.
*Note: The word 16-bit means that its arithmetic logical unit, internal registers
and most of its instructions are designed to work with 16-bit binary words.
3. It is available as 40-pin Dual-Inline-Package (DIP).
4. It is designed by HMOS technology.
5. It consists of 29,000 transistors.
6. It has a 16-bit data bus and 20 bit address bus.
7. It can directly access 1MB (220or 10, 48, 576) memory locations.
8. Its clock frequency is 5MHz to 10MHs.
Processor Operating Clock Frequency
8086 5 MHz
8086-2 8 MHz
8086-1 10 MHz
9. It can generate 16 bit I/O address; hence it can access 216=65,536 I/O ports.
10. It has 16-bit ALU; this means 16-bit numbers are directly processed by 8086.
11. It has multiplexed address and data bus.
12. It provides fourteen 16-bit registers.
13. It supports multiprogramming.
14. It has more than 20,000 instructions.
15. The 8086 is operating in two modes namely minimum mode and maximum
mode.
16. It can operates on +5V supply.

2.6 Draw and explain the functional block diagram of 8086.

 The internal architecture of Intel 8086 is shown in the fig. 2.6.
Fig. 2.6
 This can be divided into two independent functional units. These are:
o Bus interface Unit (BIU)
o Execution Unit (EU)
 BIU communicates with the devices outside the microprocessor and fetches the
instructions from memory and stores them in instruction queue register.
 EU is responsible for executing the instructions fetched by BIU.
*Note:
1. These two functional units (BIU & EU) can work simultaneously to increase
system speed and hence the throughput.
2. Throughput is a measure of number of instructions executed per unit time.
Functional Units of 8086 Architecture:
 Basically the 8086 µp (microprocessor) consists of two functional units. These are:
1. Bus Interface Unit (BIU)
2. Execution Unit (EU).
2.6.1. Bus Interface Unit (BIU)

 It provides a full 16-bit bi-directional data bus and 20-bit address bus.
 This unit is responsible for transfer of instructions, data and addresses to the
execution unit through the system bus.
 It is also responsible for transferring the data between the processors memory and
I/O devices.
 The functional parts of BIU are:
o Instruction queue
o Segments registers
o Instruction pointer
o Address summer and
o Bus control logic
 The functions of BIU are to:
1. Fetch the instruction or data from memory.
2. Write the data to memory.
3. Write the data to the port.
4. Read data from memory.
5. Read data from the port.
6. Calculate physical address of memory.
2.6.2. Execution Unit (EU)
 The purpose of the execution unit is to execute the instructions.
 The EU works in parallel with BIU.
 The functional parts of the EU are:
o General purpose registers
o Pointer and Index registers
o Arithmetic and Logic Unit (ALU)
o Flag register
o Control Unit.
 Basically, it performs four kinds of operations. These are fetch, decode, execute,
and write operations.
o Fetch: Read instruction from the instruction queue of BIU.
o Decode: Decode the fetched instruction.
o Execution: Perform the operation specified by the instruction.
o Write (store): Store the result in the destination.

*Note:
1. All these four operations will be performed by the EU in some definite number
of clock cycles.
2. During execution, EU may test the status and control flags and update these
flags based on the results of execution.
2.7 State the need of bus control logic

2.7.1. Introduction
1. Bus: A bus is a physically a bunch of conducting wires over which electrical signals
of data are transmitted.
2. Classification of buses: Buses can be classified into three types.
a. Address bus
b. Data bus
c. Control bus
a) Address Bus: The group of conducting lines that carries address is called
address bus.
b) Data Bus: The group of conducting lines that carries data is called data bus.
c) Control Bus: The control bus is used to carry necessary control signals
between the p and memory and I/O devices.
*Note: The group of conducting lines that carries data, address and control signals in a
micro computer (micro processed based CPU) systems are called system bus.
Multiplexing is not allowed in system bus.
2.7.2 Bus Control Logic Unit
 The bus control logic unit is a sub unit of bus interface unit (BIU).
 It generates all the bus control signals such as read and writes signals for memory
and I/O devices.
 This unit generates four control signals to select the memory (or) I/O devices and
causes them to perform a read or a write operations.
 The four control signals are IOR (Input/output read signal) IOW (Input/output
write signal), MEMR (Memory read signal) and MEMW (Memory write signal).
*Note: The bus control logic is required to generate following signals.
1. Address line signals (A0 to A15).
2. Data bus signals (D0 - D15).
3. Read/Write signals ( RD / WR ).
4. Memory/IO operation signals (M/ IO ).
5. Address latch enable signal.
2.7.3 Need of Bus Control Logic

The bus control logic is needed:
o To read data from memory.
o To write data to memory.
o To read data from I/O devices.
o To write data to I/O devices.
o Fetching instruction from memory.
o Sending out address.
2.8 State the importance of segment registers

 The memory space 1M (220) byte of 8086 is segmented into 16 (16 x 64K =220)
segments. The maximum size of each segment is 64K bytes.
 However at any given time the 8086 only works with four 64KB segments within
1MB memory.
 The four segments are:
1. DS  Data Segment
2. CS  Code Segment
3. SS  Stack Segment
4. ES  Extra Segment
 Each segment is associated with 16 bit segment register.
 The four 16 bit segment register are:
o Data Segment (DS) register
o Code Segment (CS) register
o Stack Segment (SS) register
o Extra Segment (ES) register
 These segment registers are to hold the upper 16 bits of starting addresses of four
memory segments.
 Hence these registers serve as base registers.
 The starting address is also known as base address or segment base.
*Note: A 64KB segment can be located anywhere within the 1M byte address space.
2.8.1 Importance of Segment Registers
Segment Register Function
1. Code Segment Register This defines the memory location where the program code
(instructions) is stored.

2. Data Segment Register This defines where data from the program will be stored.
3. Stock Segment This defines where the stack is stored.
Register
4. Extra Segment Register This segment registers which is not dedicated for any
definite purpose. It is extensively used in string
instructions.
*Note: Stack is a portion of memory set aside to store address and data, whenever the
processor performs the branch operations.
2.9 Mention the function of Instruction Pointer and its

importance
 Instruction pointer is a programmable 16 bit register.
 It is analogous to program counter (PC) in the 8085 microprocessor.
 It holds the address of the next instruction to be fetched.
 Its role is to point to the next instruction to be executed in the CPU.
 The instruction pointer will be modified when jump or call instructions are used.
2.10 Explain the Instruction Queue and its storage

 BIU fetches the instructions from memory and stores them in instruction queue
register.
 Definition: A group of high speed registers in which pre-fetched instructions are
stored is known as instruction queue.
 The length of instruction queue of 8086 µp is 6 bytes.
 The instruction queue works on first in first out (FIFO) basis.
 Importance:
o To speed up the execution of programs, by pre-fetching six instructions in
advance from memory.
o In pipelining this instruction queue is place a vital role.
2.11 List different General purpose registers and explain

 The group of flip-flops that are used for storing of data is called register.
 The 8086 microprocessor has four 16-bit general purpose registers (GPRs). These
are: AX, BX, CX, and DX.
 Each 16-bit general purpose register can be split into two 8-bit registers.

 If the letters L and H specify the lower and higher bytes of a particular register,
then ‘AH’ is higher byte of an ‘AX’ register and ‘AL’ is lower byte of an ‘AX’
register.
 The letter ‘X’ is used to specify the complete 16-bit register.
Register Name of the Special function

Register
AX 16-bit The register AX is always involved in multiplication and
Accumulator division as the default operand.
Stores the 16-bit result of certain arithmetic and logic
operation.
AL 8-bit Stores the 8-bit result of certain arithmetic and logic
accumulator operations.
BX Base Register Used to hold the base value in base addressing mode to
access memory data.
CX Count Register This register can be used to hold a count value during
string and loop instructions.
DX Data Register Used to hold data for multiplication and division
operations.
This is the only GPR that can be used as an I/O
addresses pointers in the IN and OUT instructions.
2.12 State the purpose of Pointer and Index registers

 All segment registers are 16-bit. But it is necessary to put 20–bit address (physical
address) on the address bus.
 To get 20-bit physical address one (or) more pointer (or) index registers are
associated with each segment register.
 These registers can also be called as special purpose registers.

Fig. 2.12
2.12.1. Pointer Registers
The 8086 processor has two pointer registers. These are:
1. Stack Pointer (SP)
2. Base Pointer (BP
1. Stack Pointer (SP)
 It is a 16-bit register.
 Stack pointer (SP) is used with stack segment (SS) to access the stack.
 To generate 20-bit physical address the contents of the SS register are shifted four
bits left (multiply by 10H) and the contents of SP are added to the shifted result.
 If the contents of SP are 9F20H and SS are 4000H then the physical address is
calculated as follows.
 After shifting four bits left, SS = 40000H.
Now SS = 40000H
+ SP = 9F20H
PhysicalAddress = 49F20 H
2. Base Pointer (BP)

 Primarily used to access data on the stack. In this case, the 20–bit physical stack
address is calculated from BP and SS.
 It can also be used to access data in other segments.
*Note: To generate 20-bit physical address the contents of the SS register are shifted
four bits left (multiply by 10H) and the contents of BP are added to the shifted result.
2.12.2. Index Register
The 8086 microprocessor has two index registers. These are:
a) Source Index register (SI)
b) Destination Index register (DI)

1. Source Index (SI) Register
 Source index (SI) can be used to hold the offset of a data word in the data segment
(DS).
 In this case, the 20–bit physical data address is calculated from SI and DS.
2. Destination Index (DI) Register
 The ES register points to the extra segment in which data is stored.
 String instructions always use ES and DI to determine 20 – bit physical address for
the destination.
*Note: The index registers SI, DI are used as general purpose registers, as well as for
offset storage in case of indexed, based and relative based indexed addressing modes.
2.13 Explain the working of ALU and control unit

2.13.1. ALU (Arithmetic Logic Unit)
 It is an important unit of execution unit (EU).
 The Arithmetic Logic Unit is a digital circuit that performs arithmetical and logical
operations.
 It performs 8-bit (or) 16 bit mathematical operations such as addition, subtraction,
multiplication, division, increment and decrement etc.
 It performs logical operations like logical AND, OR, XOR, NOT operations.
 The size of the ALU defined the size of the microprocessor.
2.13.2. Control Unit
 The control unit is the actual brain of the processor.
 It generates signals which are required for all the operations to be performed by
the CPU and required for the control of input / output and other devices
connected to CPU.
2.14 List different flags of 8086 and mention their use

 A flag is a flip flop it can store either 0 or 1.
 The flag register of 8086 µp is 16-bit register.
 The 16-bit flag register of 8086 processor stores information about the “status of
CPU” after execution of the instruction of operation and “status of processor”.
 The flag register contains 9 active flags as shown in the fig. 2.14
 The flag register of 8086 µp contains 2 parts:

1. CPU status flags or Conditional flags (6): These are used to indicate some
condition produced by instruction.
2. Control flags (3): These are used to control certain operations of the processor.
*Note: The flag register is modified or real directly through special instructions known
as processor control instructions such as CLD, STI, CLC, STD etc.
Flag Register of 8086 µp
Conditional Flags Control Flags
1. Carry Flag (CF) 1. Trap Flag (TF)
2. Parity Flag (PF) 2. Interrupt Flag (IF)
3. Auxiliary Flag (AF) 3. Direction Flag (DF)
4. Zero Flag (ZF)
5. Sign Flag (SF)
6. Overflow Flag (OF)
Fig. 2.14
2.14.1. Conditional Flags
These flags are set according to some results of arithmetic operation.
1. Carry Flag (CF)
 In case of addition this flag is set if there is a carry out of the MSB.
 The carry flag also serves as a borrow flag for subtraction. In case of subtraction
it is set when borrow is needed.
*Note: It can be set by executing instruction STC (set carry flag) and can be cleared by
executing CLC (clear carry flag) instruction.
2. Parity Flag (PF)
 It is set to 1 (PF=1) if result of operation contains an even number of 1’s otherwise
parity flag is zero.

3. Auxiliary Carry (AC)
 This flag is set, if there is an overflow out of bit 3 (D3 bit to D4 bit) i.e. carry from
lower nibble to higher nibble.
 This flag is used for BCD operations and it is not available for programmer.
4. Zero Flag (ZF)
 The zero flag set (ZF=1) if the result of operation in ALU is zero and reset (ZF=0)
if the result is non zero.
 The ZF is also set if a certain register content becomes zero following an
increment/decrement operation of that register.
5. Sign Flag (SF)
 After the execution of arithmetic or logical operations if the MSB of result is 1 then
the sign bit is flag (SF=1).
 SF=1 indicates the result is negative; otherwise it is positive.
6. Overflow Flag Register (OF)
 This flag is set if result is out of range.
 For addition, this flag is set when there is a carry into MSB and no carry out of
MSB or vice versa.
 For subtraction, it is set when MSB needs borrow and there is no borrow from
MSB or vice versa.
2.14.2. Control Flags
These flags are set in order to achieve some specific purposes.
1. Trap Flag (TF)
 It is used for single step control.
 It allows user to execute one instruction of a program at a time for debugging.
 When trap flag is set, program can be run in single step mode.
*Note: One way to debug a program is to run the program one instruction at a time
and see the contents of used registers and memory variables after execution of every
instruction. This process is called’ single stepping’ through a program. Trap flag is
used for single stepping through a program.
2. Interrupt Flag (IF)
 It is an interrupt enable/disable flag.
 If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt
is disabled.
*Note: It can be set by executing instruction STI and can be cleared by executing CLI
instruction.

3. Direction Flag (DF)
 It is used with string instructions.
 If DF=0, the string is processed from its beginning with the first element having
the lowest address.
 If DF=1, the string is processed from its highest address towards the low address.
*Note: It can be set by executing instruction STD and can be cleared by executing CLD
instruction.
Example:
 Give the contents of the flag register after execution of following addition.
0110 0101 1101 0001
0010 0011 0101 1001
1000 1001 0010 1010
a) SF (Signal Flag) = 1
b) ZF (Zero Flag) = 0
c) PF (Parity Flag) = 1
d) CF (Carry Flag) = 0
e) AF (Auxiliary Carry Flag)= 0
f) OF (Over flow Flag) = 1
2.15 Draw and explain the pin diagram of 8086.

 The 8086 has 40 pins arranged in dual in line package.
 Based on “8086 operating modes we can divide or classify the 40 pins into 3
groups.
o The pins are operated in maximum mode.
o The pins are operated in minimum mode.
o The pins are common for both modes.
*Note:
1. The signal assigned to pins 24 to 31 will be different for minimum and maximum
mode operation.
2. The signals assigned to all other pins are common for minimum and maximum
mode of operation.

Fig. 2.15
2.15.1. Pins are Common for both Modes
The signals common for minimum and maximum mode are listed in table.
Table 2.1: COMMON SIGNALS
Name Description / Function Type
AD15 – AD0 Address/Data Bidirectional, Tristate
A19/S6 to A16/S3 Address/Status Output, Tristate
BHE /S7 Bus High Enable /Status Output, Tristate
MN/ MX Minimum/Maximum mode control Input
RD Read control Output, Tristate
TEST Wait on test control Input

READY Wait state control Input
RESET System reset Input
NMI Non-maskable Input
interrupt request
INTR Interrupt request Input
CLK System clock Input
VCC +5 V Power supply input
GND Ground Power supply ground
2.15.2. Pins for Minimum Mode Operation of 8086

The minimum mode signals of 8086 are listed in table.
Table 2.2: MINIMUM MODE SIGNALS (MN/MX = VCC(logic high))
Name Description / Function Type
HOLD Hold request Input
HLDA Hold acknowledge Output
WR Write control Output, Tristate
M/ IO Memory/IO control Output, Tristate
DT/ R Data transmit/Receive Output, Tristate
DEN Data enable Output, Tristate

ALE Address latch enable Output
INTA Interrupt acknowledge Output
Fig. 2.15

2.15.3. Pins for Maximum Mode Operation of 8086

The maximum mode signals of 8086 are listed in table.
Table 2.3: MAXIMUM MODE SIGNALS (MN/MX=Ground(Logic low))
Name Description/Function Type
RQ / GT1 , RQ / GT0 Request/Grant bus access control Bidirectional
LOCK Bus priority lock control Output, Tristate
S2 , S1 , S0 Bus cycle status Output, Tristate
QS1, QS0 Instruction queue status Output
Fig. 2.15
2.15.4. Pin Description of 8086 p
Pin number Symbol Description
1 & 20 GND Used as the grounding purpose.
2-16 & 39 AD15 –AD0 Address Data bus: These are the time
multiplexed memory.
17 NMI Non Maskable Interrupt:
 NMI is the non-maskable interrupt input.
 It is positive edge triggered interrupt (A
transition from low to high initiate the
interrupt).
 It is type 2 interrupt.
 It is vectored interrupt.
 NMI has higher priority than INTR.
18 INTR Interrupt Request:
 INTR is the maskable interrupt input.
 It is a level triggered interrupt. (INTR must
be held high until it is recognized to generate
an interrupt signal).
 It is non-vectored interrupt.
 It can be enabled or disabled.
 It can be enable by STI instruction and
disabled by using the instruction CLI.
19 CLK Clock input:
 The clock input provides the basic timing for
the processor and the bus control.
 The 8086 does not have on-chip clock
generation circuit.
 Hence 8284 clock generator chip is used to
generate the required clock.
 The CLK output of 8284 is connected to the
8086 CLK pin.
Note :
1. A clock signal is asymmetrical square wave
with the 33%duty cycle.
2. The 8284 also provides the RESET and
READY signals to 8086.
3. The range of frequency for different 8086
versions is from 5MHz to 10MHz.
21 RESET  Reset terminates the processor activity.
 When the processor is reset, CS contains
FFFFH and IP contains 0000H.
 Therefore the physical address (PA) is
FFFF0H.
 Now the processor will start fetching
instruction from 20-bit physical address
FFFF0H.
*Note: After reset, DS, SS, ES and flags are
cleared and queue is emptied.
22 READY  It is used by the microprocessor to identify
whether a peripheral is ready to transfer data
or not.
 A slow peripheral may be connected to the
microprocessor through this pin.
 If this pin is high the peripheral is ready.
23 TEST  TEST is an input signal for microprocessor.
 This signal is used for testing of
microprocessor.
 When this pin goes low the microprocessor
continues execution else, processor remains
in idle state.
 This pin is used for synchronizing the 8086
with external hardware such as a
coprocessor.
24 INTA Interrupt Acknowledge:
 This is related to the non-vectored interrupt
INTR.
 When this pin goes low, the processor
accepted the interrupt request by the
peripheral.
25 ALE Address Latch Enable: It is used to de-
multiplex the address and data lines using
external latches.
24 & 25 QS1 & QS0 Queue Status: The processor provides
information about the status of the code pre-
fetch queue on these lines.
QS1 QS0 Operation
0 0 No operation.

0 1 1st byte of op code fetched
from queue.
1 0 Queue is empty.
1 1 Subsequent byte from the
queue.
26 DEN Data Enable:
When this pin goes low the processor activates
the external date bus buffer.
It is used to enable the trans-receivers to separate
the data from the multiplexed address/data
signal.
27 DT/ R Data Transmit/ Receive:
 It is used to identify, whether the processor
receiving the data or transferring the data.
 When this pin goes high microprocessor
transfers the data.
 When this pin goes low the microprocessor
receives the data.
28 M/ IO Memory / Input Output:
 It is used to distinguish memory I/O
operation.
 For memory operation M/ IO = 1.
 For I/O operation M/ IO = 0.
26, 27 and 28 S0 , S1 and S2 These are the status lines which reflect the type
of operation.
S2 S1 S0 Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 0 0 Instruction fetch
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Inactive

29 WR  It controls the write operation.

 When this pin goes low the data on the bus is
written into the selected memory or I/O
location.
LOCK  It is an output signal activated by the LOCK

prefix instruction.
 The LOCK pin remains low until the
completion of the instruction prefixed by
LOCK.
 A low on this pin prevent other processor
from gaining control of the system bus.
*Note: It LOCK = 0, then all interrupts are
masked and no HOLD request is granted.
30 & 31 HLDA ,HOLD HOLD (31) :
 The process of an I/O port accessing memory
directly without passing data through the
microprocessor is called direct memory
access or DMA.
 The DMA controller activates the HOLD
input of 8086, whenever DMA data transfer is
requested by an I/O port.
*Note: It is usually used by DMA controller to get
the control of bus.
Hold Acknowledgement (30):
 It is an acknowledge signal by the processor
to the DMA control.
 When this pin goes high, the DMA controller
takes control over the system buses and
generates the necessary control signals and
memory address.
 So that the peripheral can perform the DMA
data transfer.
RQ / GT1 &  These are used by local bus masters, in

maximum mode, to get the control of bus.
RQ / GT0
 When a local bus master needs a control over
system bus, it sends a negative pulse through
these pins.
 At the end of current bus cycle, the
microprocessor drive its pins to high
impedance state and sends acknowledge
single to the device which request the bus
control through these pins.
 After receiving the acknowledge signal, the
local master bus takes the control over the
system bus.
 After completion of its operation, the local
master bus sends a signal to the processor
which indicates the end of control.
 Immediately the processor takes the control
over the system bus.
32 RD Read:
 It controls read operation.
 When it goes low, the microprocessor is
reading date from selected memory or I/O
device.
33 MN/ MX  The logic level at this pin decides whether the
processor is to operate in either minimum or
maximum mode.
 If MN/ MX =VCC, then the processor
operates in minimum mode.
 If MN/ MX = GND, then the processor
operates in maximum mode.
34 BHE / S7 Bus High Enable /Status:
 This pin is used to indicate the transfer of
data over the higher order (D15-D8) data bus.
 It goes low for the data transfer over D8 – D15.
35,36,37 & 38 A19/ S6 Address/Status signals:
A18/ S5  These are multiplexed address and stats lines.
A17/ S4  A16–A19 is higher order address bus.
A16/ S3  S3 and S4 are segment identifier signals.
S4 S3 Indications
0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access
1 1 Data segment access
 S5 indicates the status of the interrupt enable
flag.
 S6 is always zero and no significance is
attached to it.
40 VCC +5V power supply for the operation of the
internal circuit.
2.16 Describe the maximum and minimum mode operation.

 There are two available modes of operation for the 8086 microprocessor. These
are:
o Minimum mode
o Maximum mode
2.16.1. Minimum Mode Operation of 8086 µp system
 This is a uni-processor mode, in which only single 8086 microprocessor is used.
 Definition: The arrangement of microprocessor based system in which we are
using only one microprocessor is called as minimum mode.
 This is used in simple systems.
 In a minimum mode system, the microprocessor 8086 is operates in minimum
mode by connecting its MN/ MX pin to logic 1.
 In this mode, all control signals for memory and I/O are generated by the
microprocessor chip itself.
 In minimum mode system, of 8086 we have a single microprocessor and the
remaining components are latches, trans-receivers, clock generator, memory
device and I/O devices.
 The latches are generally buffered output D-type flip-flops, like 74LS373.
 These latches are used for separating the valid address from the multiplexed
address/data signals and are controlled by the ALE signal generated by 8086 µp.

Fig. 2.16
 Trans-receivers are the bidirectional buffers they are also called as data amplifiers;
these are used to separate the valid data from the multiplexed address/data bus.
 Trans-receivers are controlled by the DEN DEN & DT / R .
 Memory devices are used for the Monitor storage, Program storage.
 Usually EPROMS are used for monitor storage and RAMs are used for program
storage.
 I/O devices are used for communication with the processor as well as some
special purpose peripherals.
 The clock generator 8284 is used to generate the clock, reset, and ready signals for
the processor.
 8086 µp has 20 address lines and 16 data lines so 8086 CPU requires three octal
address latches and two octal data buffers.
2.16.2. Maximum Mode Operation of 8086 µp system
 This is a Multi-processor mode in which a co-processor is used along with an
8086.
 Definition: The arrangement of microprocessor based system in which we are
using multi microprocessors is called as maximum mode.

 In a maximum mode system, the microprocessor 8086 is operates in maximum
mode by connecting the MN/ MX pin to ground.
 Control signals for memory and I/O are generated by an external bus controller
(8288).
 The bus controller (8288) is drive by the microprocessor with three status signals
S0 , S1, S3.
 In maximum mode system, there may be more than one microprocessor and one
bus controller (8288) and remaining components are clock generator, three octal
D-type latches, two octal D-type bi-directional buffers, memory devices and I/O
devices.
Fig. 2.16
 The bus controller chip has input lines S 2 , S1 , S 0 and CLK which are driven by the
CPU.
 The basic function of the bus controller chip 8288 is to derive control signals like
ALE, DEN, DT / R , MRDC, MWTC, IORC, & IOWC .
 IORC, IOWC are I/O read command and I/O write commands signals
respectively.
 The MRDC, MWTC are memory read command and memory write commands
signals respectively.
2.16.3. Differences between Minimum Mode & Maximum Mode
Sl.No Minimum mode Maximum mode
1. The arrangement of The arrangement of microprocessor based
microprocessor based system in system in which we are using multi
which we are using only one microprocessors is called as maximum
microprocessor is called as mode.
minimum mode.
2. MN/ MX pin is connected to logic MN/ MX pin is connected to ground.
1.
3. In this mode, all control signals Control signals for memory and I/O are
for memory and I/O are generated by an external BUS Controller
generated by the microprocessor (8288).
chip itself.
4. In this all the instructions of 8086 In this all the instructions of 8086 can be
can be utilized except the utilized including the instruction LOCK .
instruction LOCK .
5. This mode is not used when This mode can be used for multiplexed
multiplexed operations are to be operations.
performed.
6. The pins from 24 to 31 in this The pins from 24 to 31 in this mode are:
mode are: INTA , ALE, DEN , QS1 , QS 2 , S0 , S1 , S 2 , LOCK , RQ / GT1 and
DT/ R , M/ IO , WR , HLDA and RQ / GT0
HOLD
2.17 Illustrate the generation of 20-bit Physical address with an

example
2.17.1. Need for Calculation of Physical Address
 The 20 – bit address is called physical address.
 The physical address is also called as absolute address.
 Physical address identifies each byte location in the 1 MB memory space.
 The physical addresses range from 00000 H to FFFFFH as shown in fig. 2.17
Fig. 2.17
 The internal registers of 8086processor are 16-bit (4 hex digit) wide, whereas the 1-
MByte main memory locations require 20 bit (5 hex digit) wide physical address
(PA).
 So before performing any operation related to memory the 20-bit physical address
is generated.
2.17.2 Generation of Physical Address
Fig. 2.17

 The physical address is divided into two 16-bit parts, called segment addresses
and offset, before storing it into CPU registers.
 The 16-bit content of one of the four segment registers (CS, DS, ES, SS) is known as
the segment address and content of an offset register (residing in IP, BP, SP, BX,
SI or DI) is known as offset address.
 The 20-bit physical address is generated by shifting the contents of segment
register four bit positions left (multiply by 10H) and adding the offset value.
 Fig. 2.17 shows pictorially the actual process of generating a 20-bit physical
address.
*Note: The below table gives the default 16-bit segment register and the source register
of the offset for the instructions.
Segment Address Offset Instruction kind
CS IP Instruction address
(code segment)
SS SP or BP Stack Address
(Stack Segment)
DS BX, DI, SI, Data address
8-bit number or 16-bit (Data Segment)
number
ES DI for string instructions String destination
address (Data Segment)
*Note: The generation of 20-bit physical address is illustrated in the following
examples.
Example 1: Calculate the physical address of 548B H: 1242 H.
Ans:
Given data: 548B H: 1242 H
Let CS = 548B H and IP = 1242 H
Step 1: Multiply the contents of CS by 10 H.
= 548B H  10H = 548B0 H
Step 2: Add the result with the contents of IP.
CS  548B0
IP  +1242
55A F2
55AF2 H is physical address (or) absolute address.
Example 2: Find the physical address of the first and last locations as a segment. The
segment base is 2000H.
Ans:
1) To physical address of the first location:
Let CS = 2000 H and IP = 0000 H (first location)
CS: IP  2000 H: 0000 H.
Physical address of the first location is,
= (2000 H  10 H) + 0000 H= 20000H
2) To physical address of the last location:
Let CS = 2000 H and IP = FFFF H (last location)
CS: IP  2000 H: FFFF H.
Physical address of the last location is,
= (2000 H  10 H) +FFFF H = 2FFFF H.
Example 3: If the segment registers CS, DS and SS have values 1000H, 2000H and
3000H respectively. What will be the 20-bit start and end addresses of the code, data
and stack segments?
Ans:
Let CS = 1000 H, DS = 2000 H and SS = 3000 H
1. Code Segment:
20-bit start address = (CS  10 H) + 0000 H = 10000 H
20-bit end address = (CS  10 H) + FFFF H = 1FFFF H
2. Data Segment:
20-bit start address = (DS  10 H) + 0000 H =20000 H
20-bit end address = (DS  10 H) + FFFF H =2FFFF H
3. Stack Segment:
20-bit start address = (SS  10 H) + 0000 H = 30000 H
20-bit end address = (SS  10 H) + FFFF H = 3FFFF H
Example 4: Calculate the offset value required to point to absolute address 05AC4 H if
the corresponding contents of the segment register are 0514 H.
Ans:
Given data: Physical address
(or) 05AC4 H
Absolute address
CS = 0514 H
IP (or) segment =?

We have,
Physical Address (PA) = (CS  10 H) + offset
Offset = PA – (CS  10 H)
 Offset = 05AC4 H – (0514 H  10 H)
= 05AC4 H – 05140 H
 Offset = 0984 H.
Example 5: If an absolute address of the type 6A3D9 H is given, express it in the form
of CS : IP
Ans:
Let us assume that CS contains 6000 H. Then,
Offset address = PA – (CS  10 H)= 6A3D9 H – (6000 H X 10 H)n= A3D9 H
Hence, CS : IP = 6000: A3D9 H
2.18 Draw the timing diagrams of memory read and memory

write cycles.
1. Minimum Mode Bus Cycles
Fig: Timing diagram for 8086 minimum mode memory read.

 The timing diagram for 8086 minimum mode memory read operation is shown in
fig.
 During T1 or the 1st clock pulse, the read bus cycle starts and valid address is
latched.
 During T2, the read control signal are issued and data enable signal is asserted.
Note that during this state READY signal is also checked to insert wait status, if
needed. During, T3, the data from the memory is read by sampling the data bus at
the end of T3. During T4, all bus signals are deactivated in preparation for the next
clock cycle.
 The timing diagram for 8086 minimum mode memory write operation is shown in
fig. i.e., This is the same as read cycle Timing Diagram except that the DT/R- line
goes high indicating it is a data transmission operation for the processor to
memroy/peripheral.
 Again DEN line goes low to validate data and WR line goes low, indicating a write
operation.
 Note that the control signal logic levels and timing diagram are similar to that of
read operation, except for data transmit or receive mode, read and write signals.
The response of the ready signal is not shown here, as it behaves in the same way as
data read process.
Fig: The timing diagram for 8086 minimum mode memory write

2. Maximum Mode Bus Cycles of 8086 System
 The timing diagram for 8086 maximum mode memory read operation is shown in
fig. In maximum mode, status codes need to be active to generate control signals
from bus controller. Here MRDC signal is used instead of RD as in case of
minimum mode S0, S1 and S2 are active and are used to generate control signal
through the bus controller.
 The timing diagram for 8086 maximum mode memory write operation is shown in
fig.
 The control signal logic levels and timing diagram are similar to that of read
operation, except for data transmit and receive, memory read and write signals.
 Here the T-states correspond to the time during which DEN is low. WRITE control
goes low, DT/R- is high and data output is available from the processor on the data
bus.
Fig. Maximum mode: memory read bus cycle of 8086 system

Fig. Maximum mode: memory writes bus cycle of 8086 system
2.19 State the need of interrupts.

 In general, the process of interrupting the normal program execution to carry out
a specific task/work is referred to as interrupt.
 The processor can be interrupted in the following ways.
a) By an external signal generated by a peripheral.
b) By an internal signal generated by a special instruction in the program.
c) By an internal signal generated due to an exceptional condition which occurs
while executing an instruction. (For example, in 8086 processor, divide by zero
is an exceptional condition which initiates type-0 interrupt and such an
interrupt is also called exception).
 Whenever external device needs some service from the microprocessor it place a
request in the form of interrupt.
 When a microprocessor receives an interrupts signal it stops executing current
normal program, save the status (or content) of various registers (IP, CS and flag
register in case of 8086) in stack and then the processor executes a

subroutine/procedure that is executed in response to an interrupt is also called
Interrupt Service Subroutine (ISR).
 At the end of ISR, the stored statuses of registers in stack are restored to respective
register, and the processor resumes the normal program execution from the point
(instruction) where it was interrupted.
2.20 Explain the Interrupt response in 8086

 At the end of each instruction cycle, the 8086 checks to see if any interrupts have
been requested.
 If any interrupt has been requested the 8086 responds to the interrupt and the
processor performs the following operations depicted in fig. 2.20.
Fig. 2.20
 When an interrupt occur the following actions takes place.
Step 1: Decrements the stack pointer by 2 and saves the flags onto the stack.
(SP)  (SP) – 2 (SP)  Flags
Step 2: Disables the INTR interrupt by clearing the interrupt flag (IF) in the flag
register.
(IF)  0
Step 3: Clears the trap flag (TF) in the flag register to stop the generation of the
single step interrupt.
(TF)  0

Step 4: Decrements the stack pointer by 2 and saves the contents of code
segment (CS) register onto the stack.
(SP)  (SP) – 2 (SP)  (CS)
Step 5: Decrements the stack pointer by 2 again and saves the contents of the
instruction Pointer (IP) onto the stack.
(SP)  (SP) – 2 (SP)  (IP)
Step 6: Loads the code segment (CS) with the segment address of the interrupt
service routine [ISR].
(CS)  Segment address of ISR
Step 7: Loads instruction pointer (IP) with the offset address of the interrupt
service routine (ISR) in the code segment of ISR.
(IP)  Offset of ISR
2.21 List different types of interrupts

For 8086 the interrupts are classified into three types.
 Hardware Interrupts
 Software Interrupts
 Predefined Interrupts
2.21.1. Hardware Interrupts
 The interrupts initiated by applying appropriate signals to INTR and NMI pins of
8086 are called hardware interrupts.
 The hardware interrupts of 8086 are NMI and INTR.
 The NMI is a non maskable interrupt, where as INTR is a maskable interrupt.
 The NMI is edge triggered on a low to high transition.
 The rising edge of NMI is serviced at the end of the current instruction.
*Note: The hardware interrupts initiated through INTR are maskable by clearing the
interrupt flag, (IF), i.e., the hardware interrupts are masked/disabled when IF=0 and
they are unmasked/enabled when IF =1. The interrupts initiated through INTR has
lower priority than software interrupts.
2.21.2. Software Interrupts
 These are generated by inserting “INT” instruction in a program.
 The 8086 has 256 types of software interrupts denoted by the instruction INT n
where, n is the type and number ranging from 00H to FFH.

2.21.3. Predefined Interrupts
 These are also called as dedicated interrupts.
 The Intel 8086 has ‘5’ predefined interrupts. These are:
1. Type 0 interrupt (Divide by zero interrupt)
2. Type 1 interrupt (Single step interrupt)
3. Type 2 interrupt (Non-maskable interrupt)
4. Type 3 interrupt (Break point interrupt)
5. Type 4 interrupt (Over flow interrupt)
1) Type 0 Interrupt
 Type 0 interrupt is divide by zero interrupt.
 This interrupt is a non-maskable and is automatically interrupted whenever a
division by zero is attempted.
2) Type 1 Interrupt
 Type 1 interrupt is single step interrupt.
 Single step control is used for debugging Assembly Language Program (ALP).
 In single step control, the processor executes one instruction and then stops.
 There after the contents of registers and memory locations can be examined to see
the result.
 If the result is correct, the user gives a command to execute the next instruction.
 In 8086, the Trap Flag (TF) is set to ‘1’ to implement single-step control.
*Note: This interrupt is also non-maskable interrupt.
3) Type 2 Interrupt
 Type 2 is the Non-Maskable Interrupt (NMI).
 It is used for some emergency conditions.
 For example, it is used to save program and data, when power supply fails.
 An external circuit is used to detect the power failure and send an interrupt signal
to 8086 through NMI pin.
 If AC power fails, the DC voltage supplied to computer may remain for 50ms due
to capacitors provided in the filter circuits.
 This time is sufficient to save program and data in some RAM having battery
back-up supply.
 The program along with data is restored, when power returns and can be
executed again from the point, where it was interrupted.
4) Type 3 Interrupt
 Type 3 interrupt is a break point interrupt.
 The type 3 interrupt is produced by execution of the INT 3 instruction.
 A break point is inserted in a program for debugging ALP.
 The system executes all the instructions up to the break point and then stops
execution.
 Depending on system the register contents may be displayed on the CRT (or) in a
simple system the control is returned to the user.
5) Type 4 Interrupt
 Type 4 interrupt is an overflow interrupt (INTO).
 The 8086 overflow flag (OF) is set to 1, if the signed result of an arithmetic
operation on two signed numbers is too large to represent in the destination
register or memory location.
 To implement type 4 interrupt ‘INTO’ instruction is inserted in the program
immediately after the arithmetic instruction.
 If OF is not set, the INTO instruction simply performs no operation (NOP).
 If OF is to set (1), the INTO instruction performs type 4 interrupt.
2.21.4. Priorities of 8086 Interrupts
 When two (or) more interrupts occur simultaneously, interrupts are taken up one
by one. For this purpose, priority is assigned to interrupts.
 The interrupts of the highest priority is serviced first and then the interrupt of
next higher priority is taken.
 The priorities of interrupts of 8086 are given below.
Interrupt Priority
Divide error, INT n, INTO Highest
NMI
INTR
Single step Lowest

3
Instruction set of 8086 and programming
OBJECTIVES
3.1 Draw the generalized Instruction format of 8086

3.2 Illustrate the generation of code with few examples
3.3 Explain Addressing modes of 8086 with examples
3.4 Classify the Instruction set of 8086
3.5 Understand the data transfer instructions of 8086.
3.6 Understand the Arithmetic instructions of 8086.
3.7 Understand the Logic instructions of 8086.
3.8 Understand the processor control instructions of 8086.
3.9 Understand the instructions affecting flags of 8086.
3.10 Understand the control transfer (branching) instructions of 8086.
3.11 Understand the String manipulation instructions of 8086.
3‐2 Instruction set of 8086 and programming
3.1 Draw the generalized Instruction format of 8086

 There are six general formats of instructions in 8086 instruction set.
 The length of an instruction may vary from one byte to six bytes.
3.1.1. One byte Instruction
 This format is only one byte long and may have the implied data or register
operands.
 The least significant 3-bits of the op-code are used for specifying the register
operand, if any. Otherwise, all the 8-bits form an op-code and the operands are
implied.
3.1.2. Register to Register
 This format is 2 bytes long.
 The first byte of the code specifies the op-code and width of the operand specified
by W bit.
 The second byte of the code shows the register operands and R/M field, as shown
below.
 The register represented by the REG field is one of the operands.

 The R/M field specifies another register or memory location, i.e. the other
operand.
3.1.3. Register to/from Memory with no Displacement
 The format is also 2 bytes long and similar to the register to register format except
for the MOD field as shown.
 The MOD field shows the mode of addressing.

 The MOD, R/M, REG and the W fields are decided in
3.1.4. Register to/from Memory with Displacement
 This type of instruction format contains one or two additional bytes for
displacement along with 2-byte i.e. the format of the register to/from memory
with no displacement.
 The format is as shown below.

Instruction set of 8086 and programming 3‐3
3.1.5. Immediate Operand to Register

 In this format, the first byte as well as the 3-bits from the second byte which are
used for REG field in case of register to register format is used for op-code.
 It also contains one or two bytes of immediate data.
 The complete instruction format is as shown below.
3.1.6. Immediate Operand to Memory with 16-bit Displacement

 This type of instruction format requires 6 bytes for coding.
 The first 2 bytes contain the information regarding OP-CODE, MOD, and
R/M fields.
 The remaining 4 bytes contain 2 bytes of displacement and 2 bytes of data as
shown below.
3.2 Illustrate the generation of code with few examples

The following examples illustrates the generation of codes.
Example 1: Generate the machine code for the assembly language instruction MOV
AX, BX (Let the op-code of MOV is 100010).
Solution:
MOV AX, BX Move the contents of BX register into AX
register
 It may be noted that the above instruction is specified in register addressing
mode.
 We can specify either of AX (or) BX using the REG field.

Case-I: Here, we have to specify AX using REG field.
 First byte for the above instruction is of the form:
Op-code D W
100010 1 1
 Second byte for the above instruction is of the form:
MOD REG R/M
11 000 011
Op-code : 100010
D=1 : AX as destination register.
W=1 : To indicate 16-bit (word) operation.
(AX & BX are 16-bit registers)
MODE = 11 : Register addressing mode.
REG = 000 : Destination register address (i.e. AX)
R/M = 011 : Source register address (i.e. BX)
 The complete 2-byte machine code for the assembly language instruction MOV
AX, BX is shown in fig. 3.2.(a)
Fig. 3.2(a)
 Therefore the machine code is, 8BC3H.
Case-II: Here, we have to specify BX using REG field.
Op-code D W
100010 0 1

MOD REG R/M
11 000 011
Op-code : 100010
D=0 : BX as source register.
W=1 : To indicate 16-bit (word) operation.
(AX & BX are 16-bit registers)
MODE = 11 : Register addressing mode.
REG = 011 : Source register address (i.e. BX)
R/M = 000 : Destination register address (i.e. AX)
 The complete 2-byte machine code for the assembly language instruction MOV
AX, BX is shown in fig. 3.2.(b).
Fig. 3.2(b)
 Therefore the machine code is, 89D8H.
Example 2: Generate code for an instruction MOV CL, [SI]. [Consider the op-code
for MOV is 100010].
Solution:
MOV CL, The contents of a memory location whose 16-bit effective address (offset)
[SI] is stored in SI are transferred to the CL.
 It may be noted that the above instruction is specified in register indirect
addressing mode.
 We can specify either of CL (or) [SI] using the REG field.
 Here, we have to specify CL using REG field.
Op-code D W

100010 1 0
MOD REG R/M

00 001 100
Op-code : 100010
D=1 : CL as destination register.
W=0 : To indicate 8-bit (byte) operation.
(CL is 8-bit register)
MODE = 00 : Register indirect addressing mode.
REG = 001 : Destination operand register address
(i.e. CL)
R/M = 100 : Source operand register address (i.e.
[SI] )
 The complete 2-byte code for an instruction MOV CL, [SI] is shown in fig. 3.2.(c)
Fig. 3.2(c)
 Therefore the machine code is, 8A0CH.
Example 3: Generate code for the instruction
MOV 7C89H [BP], DX.
Solution:
MOV 7C89H The contents of DX are moved to a memory location whose 16-bit
[BP], DX effective address is obtained by adding the contents in BP and the 16-bit
displacement C6A2H.

 It may be noted that the above instruction is specified in based addressing with
16-bit displacement ((BP) + D16).
 Here, we have to specify DX using REG field.
Op-code D W
100010 0 1
MOD REG R/M
10 010 110
 Third and fourth bytes for the above instruction is of the form:
3rd Byte 4th Byte
Displacement Displacement
(Higher) (Lower)
7C 89
*Note: If the instruction contains 16-bit displacement, this may be placed in byte 3 and
byte 4.
Op-code : 100010
D=0 : DX as source register.
W=1 : To indicate 16-bit (byte) operation.
(DX is 16-bit register)
MODE = 10 : Based addressing with 16-bit
displacement.
REG = 101 : Source operand register address (i.e.
DX)
R/M = 110 : Destination operand register address
(i.e. [SI] )
16-bit : 7C89H
displacement
 The complete 2-byte code for an instruction MOV 7C89H [BP], DX is shown in fig.
3.2.(d)

Fig. 3.2(d)
3.3 Explain Addressing modes of 8086 with examples

 An instruction consists of an op-code and an operand. The operand may reside in
the accumulator, a general purpose register or in a memory location.
 Definition: The way in which an operand is specified (or referred to) in an
instruction is called addressing mode.
 The 8086 has 12 basic addressing modes and can be classified into 5 groups. These
are:
Group I: Addressing modes for register and immediate data
1. Register addressing mode
2. Immediate addressing mode
Group II: Addressing modes for data in memory
3. Direct addressing mode
4. Register indirect addressing mode
5. Based addressing mode
6. Indexed addressing mode
7. Based index addressing mode
8. String addressing mode
Group III: Addressing modes for I/O ports
9. Direct I/O port addressing mode
10. Indirect I/O port addressing mode
Group IV: Relative addressing mode
11. Relative addressing mode
Group V: Implied addressing mode
12. Implied addressing mode
1. Register Addressing Mode
 In this addressing mode the data on which the instruction operates is stored in
either an 8-bit or a 16-bit general purpose register.
 All registers except IP can be used in this mode.
Examples:
MOV CX, AX Copies the contents of AX register into CX register.
ADD BX, AX This instruction adds the contents of AX to BX and stores the sum
in the BX.
2. Immediate Addressing Mode
 In this addressing mode the data (8-bit or 16-bit) on which the instruction operates
is specified within the instruction itself.
 The immediate data can only be the source operand.
Examples:
MOV DL, 08H The 8-bit data 08H given in the instruction is moved to DL
register
ADD AX, 0A284 H The 16-bit data 0A284H is added to the contents of AX register.
*Note:
1. When the immediate data starts with a hexadecimal digit (A to F) the data must
began with 0 as in example 2 above. This is to distinguish the data from alphabets.
2. The immediate data must be specified in the instruction without any square
brackets [ ] (or) parentheses ( ).
3. Direct Addressing Mode
 It is similar to ‘Immediate Addressing Mode’.
 In immediate addressing mode, data follows the instruction op-code, while in this
case an effective address follows the instruction op-code.
 In the direct addressing mode signed 8-bit or unsigned 16-bit displacement will be
specified in the instruction. The displacement is the effective address as shown in
fig. 3.3(a)
Fig. 3.3(a)
*Note:
1. In case of 8-bit displacement the effective address is obtained by sign extending
the 8-bit displacement to 16-bit.
2. Usually the contents of DS or SS registers are used to calculate the 20-bit physical
address.

3. In direct addressing mode the effective address specified in the instruction must
be placed within the square brackets [ ].
Examples:
MOV AX, Here, data resides in a memory location in the data segment (DS), whose
[5000H] effective address may be computed using 5000H as the offset address
and content of DS register as segment address.
4. Register Indirect Addressing Mode

 In this addressing mode the effective address is stored in either base register (or)
index register (see fig. 3.3(b) ).
 The base register can be only BX and the index register can be source index (SI) or
destination index (DI) register.
*Note:
1. The register name is specified within the square brackets [ ] to indicate indirect
addressing mode.
2. The content of DS is used for segment Base Address (BA) calculation.
3. The base address is obtained by multiplying the content of segment register by
1016.
Fig. 3.3(b)
Examples:
MOV The contents of a memory location who’s 16-bit EA provided in the register
CX, [SI] SI is transferred to the register CX.
EA = (SI), BA  DS   1610 , MA  BA  EA
CX   MA  [MA = Memory Address] (or)
CL   MA  and CH   MA  1
ADD The contents of a memory location who’s 16-bit EA provided in the base
AX, [BX] register BX is added to the contents of the register AX. Result is placed in
AX.

5. Based Addressing Mode
 In this addressing mode the 16-bit effective address is obtained by adding the
contents of BX or BP and the displacement (signed 8-bit or unsigned 16-bit
displacement) provided in the instruction itself as shown in fig. 3.3.(c)
*Note: In case of 8-bit displacement, it is sign extended to 16-bit before adding to base
value.
Fig. 3.3(c)
*Note:
1. When BX is used to hold base value for EA then we use DS.
2. When BP is used to hold base value for EA then we use SS.
Examples:
MOV AX, The effective address is calculated by sign extending the 8-bit
[BX + 08H] displacement given in the instruction to 16-bit and adding to the content
of BX register.
The content of memory location is moved to AL register and the content
of next memory location is moved to AH register.
Sign Extend
0008H     08H
EA  BX   0008H
BA  DS   16 10 ; MA  BA  EA
AX  MA  (or)
AL   MA  and AH   MA  1
MOV AX, The contents of a memory location who’s 16-bit EA is obtained by
1234H [BX] adding the contents of BX and the 16-bit displacement 1234H is
transferred into AX.
*Note: An 8-bit displacement, can be extended to 16-bit by making all of the bits in the
higher order byte equal the most significant bit in the lower order byte. This is known as
sign extension.

6. Indexed Addressing Mode
 It is similar to that of based addressing mode.
 In this addressing mode the 16-bit effective address is obtained by adding the
contents of index registers SI or DI and the displacement (signed 8-bit or unsigned
16-bit displacement) provided in the instruction itself as shown in fig. 3.3.(d)
*Note: In case of 8-bit displacement it is sign extended to 16-bit before adding to
index value.
Fig. 3.3(d)
Examples:
MOV CX, This instruction will copy a byte from a memory location whose
[SI+0A2H] address is calculated by adding the displacement to the content of
source index register (SI) in to the CX register.
Sign Extend
FFA2H     A2H
EA  SI   FFA2H
BA  DS   16 10 ; MA  BA  EA
CX   MA  (or)
CL   MA  and CH   MA  1
MOV CX, The contents of a memory location who’s 16-bit EA is obtained by
9848H [SI] adding the contents of SI and the 16-bit displacement 9848H is
transferred into CX.
7. Based index Addressing Mode
 This mode is the combination of both based addressing mode and indexed
addressing mode.
 In this addressing mode the effective address is given by sum of base value, index
value and an 8-bit or 16-bit displacement specified in the instruction as shown in
fig. 3.3 (e)
 The base value is stored in BX or BP register.
 The index value is stored in SI or DI register.

*Note: In case of 8-bit displacement, it is sign extended to 16-bit before adding to
base value.
Fig. 3.3(e)
Examples:
MOV DX, [BX This instruction copies the content of a memory location whose
+ SI + 0AH] effective address is [BX + SI + 0AH] in to DX register.
Sign Extend
000AH     0AH
EA  BX   SI   000AH
BA  DS   16 10 ; MA  BA  EA
DX   MA  (or)

DL   MA  and DH   MA  1
8. String Addressing Mode
 In string addressing mode:
o The effective address of source data is stored in SI register.
o The effective address of destination data is stored in DI register.
Fig. 3.3(f)
 The segment register used for calculating base address for source data is DS and
can be overridden.
 The segment register used for calculating base address for destination is ES and
cannot be overridden.

9. Direct I/O Port Addressing Mode
 This addressing mode is used to access data from standard I/O ports.
 In the direct port addressing mode, an 8-bit port address is directly specified in
the instruction.
 This allows fixed access to ports numbered 00H-FFH (0-255).
 During the execution of a program, the port address cannot be changed hence the
name fixed I/O port addressing mode.
Examples:
Read Operation
IN AL,20H This instruction transfers data byte from the 8-bit port address 20H
to register AL.
IN AX,75H This instruction moves the content of input port whose address is
75H to AL and the content of input port with address 76H to AH.
Write Operation
OUT 20H,AL This instruction transfer’s data byte from AL to the 8-bit port address
20H.
OUT 75H,AX This instruction moves the content of AL to output port whose
address is 75H and the content of AH to output port with address
76H.
10. Indirect I/O Port Addressing Mode
 In this case port address will not be provided explicitly in the instruction.
 In 8086, the 16-bit port address is stored in DX register allowing 64K 8-bit ports
(or) 32K 16-bit ports.
 During the execution of a program the port address can be changed hence the
name variable I/O port addressing.
Examples:
Read Operation
IN AL, DX Let DX = 5000H. The instruction transfers the 8-bit content from 16-
bit port address 5000H contained in DX register to AL.
IN AX, DX Let DX = 5000H. The instruction moves the 8-bit content of input
port 5000H and 5001H into AL and AH respectively.
Write Operation
OUT DX, AL Let DX = 7000H. The instruction transfers the 8-bit content of AL to
16-bit port address 7000H contained in DX.
OUT DX, AX Let DX = 7000H. The instruction moves the 8-bit content of AL and
AH to output port 7000H and 7001H respectively.
11. Relative Addressing Mode
 In this addressing mode the effective address of a program instruction is specified
relative to instruction pointer (IP) by an 8-bit signed displacement.
Example:
JZ 0AH Jump if zero flag is set to one (ZF = 1).
Sign Extend
000AH     0AH
If ZF = 1, then IP   IP   000AH ; EA  IP   000AH
BA  CS   16 10 ; MA  BA  EA
12. Implied Addressing Mode

 In this mode, the instruction assumes that data is in a pre-defined register.
 The register on which implicit addressing instruction operates, vary from one
instruction to another instruction.
 For example in the instructions CMC, STD or CLC etc, the data is in the flag
register.
 Such instructions are called as zero address instructions.
Examples:
CMC This instruction complements the carry flag.
STD It sets the direction flag to 1.
CLC This instruction resets the carry flag to zero.
3.4 Classify the Instruction set of 8086

 An instruction is a binary pattern designed inside a microprocessor to perform a
specific function.
 The entire group of instructions that a microprocessor can execute is called
Instruction Set.
 8086 has more than 20,000 instructions.
 The 8086 instructions are categorized into the following 6 types.
1. Data Transfer Instructions of 8086
 These instructions are used to transfer data from a source operand to a destination
operand.
 The source operand in most of the cases remains unchanged.

 The data transfer group includes instructions for moving data between registers,
register and memory, register and stack memory, and accumulator and I/O
device.
2. Arithmetic Instructions of 8086
 The arithmetic group includes instructions for addition and subtraction of binary,
BCD and ASCII data, and instructions for multiplication and division of signed
and unsigned binary data.
3. Logical Instructions of 8086
 The logical group includes instructions for performing logical operations like
AND, OR Exclusive OR, complement, Shift, Rotate etc.
4. Processor Control Instructions of 8086
 The processor control group includes instructions to set/clear the flags, to delay
and halt the processor execution.
5. Control Transfer (Branching) Instructions of 8086
 The control transfer group includes instructions to call a procedure /subroutine in
the main program. It also includes instructions to jump from one part of a
program to another part either conditionally (after checking flags) or
unconditionally (without checking flags).
6. String Manipulation Instructions of 8086
 The string manipulation group includes instructions for moving string data
between two memory locations and comparing string data word by word or byte
by byte.
3.5 Understand the data transfer instructions of 8086.

The instruction set of 8086 microprocessor includes a variety of instructions to
transfer data/address into registers, memory locations and I/O ports. The various
mnemonics used for data transfer instructions are MOV, XCHG, PUSH, POP, IN, OUT,
etc., and they perform any one of the following operations.
 Copy the content of a register to another register.
 Copy the content of a register to memory or vice-versa.
 Load the immediate operand to memory/register.
 Copy the content of a register/memory to segment register (excluding CS
register) or vice versa.
 Exchange the content of two registers or register and memory.
 Copy the content of accumulator to port or vice-versa.
 Load effective address in segment registers.

 The data transfer instructions generally involve two operands: source operand
and destination operand.
 The source and destination operand should be of same size, either both the
operand size should be byte or word. This means that only 8-bit data can be
moved to 8-bit register/ memory and only 16-bit data can be moved to 16-bit
register/memory.
 Moving the content of 8-bit register to 16-bit register/memory or vice-verse is
illegal.
 The source can be a register or a memory location or an immediate data.
 The destination can be a register or a memory location.
 In double operand instructions the source and destination cannot refer to
memory locations in the same instruction. Therefore, copying the content of one
memory location to another memory location in a single instruction is not
possible (except PUSH instruction).
 The data transfer instructions (except POPF and SAHF instructions) do not affect
the flags of 8086.
 The data transfer instructions of 8086 are classified into four groups as shown in
below table.
Group - 1 Group - 2 Group - 3 Group - 4
General purpose byte or Special address Flag transfer Simple input and output
word transfer transfer instructions port transfer
instructions instructions instructions
1. MOV 1. LEA 1. LAHF 1. IN
2. PUSH 2. LDS 2. SAHF 2. OUT
3. POP 3. LES 3. PUSHF
4. XCHG 4. POPF
5. XLAT
Group 1: General Purpose Byte or Word Transfer Instructions

Syntax/Operation Explanation
MOV dest, src  The MOV instruction copies a word or a byte of data
(dest)  (src) from source (src) to a destination (dest).
Examples:  The destination can be a register or a memory
o MOV CX, AX location.
o MOV BX,592FH  The source can be a register, a memory location, or
o MOV CL,[357AH] an immediate number.

 The source and destination in an instruction can’t
both be memory locations.
 MOV instruction does not affect any flags.
PUSH src  Push register or memory to stack.
(SP)  (SP) - 2  The push instruction decrements stack pointer by
SS:[SP]  (src) two and copies a word from source to the location in
Example: the stack where the stack pointer points.
o PUSH AX  The source word can be general purpose register, a
segment register or a memory location.
; Decrement SP by 2, copy
AX to stack.
POP dest  Push register or memory.
(dest)  SS:[SP]  The POP instruction copies a word from a stack
(SP)  (SP)+2 location pointed by the stack pointer to the
Example: destination.
o POP AX  The destination can be a general purpose register, a
segment register, or a memory location.
; Copy a word from a top
of a stack to AX and  After a word is copied to the specified destination,
increment SP by 2. the stack pointer is automatically incremented by 2.
XCHG dest, src  The XCHG instruction exchanges the contents of a
(dest)  (src) register with the contents of another register (or) the
Example: contents of a register with the contents of memory
location.
o XCHG BX, CX
; Exchange word in BX with  The instruction cannot exchange the contents of two
word in CX. memory locations.
o XCHG AL, CL *Note: The segment registers can’t be used in this
instruction.
XLAT  This instruction transfers 8-bit data from a memory

(AL)  DS:[BX + (AL)] location to AL register. The effective address of
Example: memory location is given by the sum of the contents
of BX and AL registers.
o MOV AL, code
MOV BX, 2400H  The instruction is useful in code translation.
XLAT

Group 2: Special Address Transfer Instructions

LEA reg16, src  Load Effective Address.
(reg16)  (EA)  Source operand produces effective address (EA).
Example:  Load “effective address” of source (src) operand
o LEA CX, TOTAL into specified 16–bit register.
;Load CX with offset of  The source operand must be a memory variable
TOTAL in DS. and the destination must be a 16-bit general
o LEA AX,[BX] [DI] purpose register.
;Load AX with EA = [BX] +
[DI]
LDS reg16, mem16  Load register and DS register.
(reg16)  (mem16)  This instruction copies a word from two memory
DS  (mem16) + 2 locations into the register specified in the
Example: instruction.
o LDS CX, [3900H]  It then copies a word from the next two memory
; Copy contents of memory locations into DS register.
at displacement of 3900H
and 3901H to CX. Then copy
contents of memory at
displacement of 3902H and
3903H to DS.
LES reg16, mem16  Load register and ES register.
(reg16)  (mem16)  This instruction copies a word from two memory
ES  (mem16) + 2 locations into the register specified in the
Example: instruction.
o LES AX, [3483H]  It then copies a word from the next two memory
locations into ES register.
Group 3: Flag Transfer Instructions

LAHF  Load AH with Flags
(AH)  Lower byte  This instruction copies the contents of lower byte of 8086 flag
of flags register to AH register.

SAHF  Store AH in Flag register
Lower byte of flags  The contents of the AH register are copied into the lower byte
 (AH) of the 8086 flag register.
PUSHF  PUSH Flag register on the stack
(SP)  (SP) - 2  This instruction decrements the stack pointer by 2 and copies
SS:[SP]  CPU Flags the word in the flag register to the memory location(s)
pointed by the stack pointer.
POPF  POP word from top of stack to Flag register
CPU Flags  SS:[SP]  This instruction copies a word from the two memory locations
(SP)  (SP) + 2 at the top of stack to the flag register and increments stack
pointer by 2.
Group 4: Simple Input and Output Port Transfer Instructions

IN ACC, port ( or  Input byte or word from port
DX)  The IN instruction will copy data from a port to the
Byte : (AL)  [port] accumulator.
Word: (AL)  [port],  AL or AX registers acts as accumulator.
(AH)   If an 8-bit port is read, the data will go to AL and if a 16-bit
[port+1] port is read the data will go to AX.
*Note: The IN instruction can be executed in two different
addressing modes.
a) In direct addressing mode 8-bit address of the port is
directly specified in the instruction.
b) In indirect addressing mode the 16-bit address of the port is
specified through DX register.
OUT port (or DX),  Output byte or word to port
ACC  The OUT instruction copies a byte or word from AL or from
Byte : [port]  (AL) AX to the specified port.
Word: [port]  (AL), *Note: The OUT instruction can be executed in two different
[port+1]  addressing modes.
(AH) a) In direct addressing mode 8-bit address of the port is
directly specified in the instruction.
b) In indirect addressing mode the 16-bit address of the port is
specified through DX register.

The data transfer instructions of 8086 are listed in below table, with a brief
description about each instruction.
Group -1: General purpose byte or word transfer instructions
1. MOV Copying data (byte/word) from the specified source to
destination.
2. PUSH Pushing the data (word) from the specified register on to top of
stack.
3. POP Fetching the data (word) from top of the stack to the specified
location.
4. XCHG Exchange of data (byte or word) between source and destination
operands.
5. XLAT The content (8-bit) of memory is transferred to AL. The effective
address of memory is given by sum of BX and AL.
Group - 2: Special address transfer instructions
1. LEA Load effective address into the specified register.
2. LDS Load the specified register and DS register from the consecutive
word locations of memory.
3. LES Load the specified register and ES register from the consecutive
word locations of memory.
Group - 3: Flag transfer instructions
1. LAHF Load AH register with the low byte of the flag register.
2. SAHF Store (copy) the AH register to low byte of the flag register.
3. PUSHF Pushing the flag register on to top of the stack.
4. POPF Fetching the data from top of the stack to the flag register.
Group - 4: Simple input and output port transfer instruction
1. IN Copying a data (byte or word) from the specified port to
accumulator (AL or AX)
2. OUT Copying a data (byte or word) from the accumulator (AL or AX)
to the specified port.

3.6 Understand the Arithmetic instructions of 8086.

 The arithmetic group includes instructions for performing the following
operations.
o Addition or Subtraction of binary, BCD or ASCII.
o Multiplication or division of signed or unsigned binary.
o Increment, decrement or comparison of binary data.
 The mnemonics used for arithmetic instructions are ADD, ADC, SUB, INC, DEC,
MUL, DIV, CMP, etc.
 The arithmetic instructions generally involve two operands: source operand and
destination operand.
 The source can be a register, a memory location or an immediate data.
 The destination can be a register or memory.
 The result of arithmetic operation is stored in destination register or memory
except in case of comparison (In comparison the result is used to modify the flags
and then the result is discarded).
 In double operand arithmetic instructions, the source and destination cannot refer
to memory locations in the same instruction. Therefore performing arithmetic
operation directly on two memory data is not possible.
 In double operand arithmetic instructions except division, the source and
destination operand should be of same size, either both the operand size should be
byte or word.
 In all arithmetic instructions employing immediate addressing mode, if the
immediate operand/data is 8-bit and the size of register/memory is 16-bit then
the immediate operand in sign extended to 16-bit.
 The arithmetic operation is performed between the sign extended data and the
content of register/ memory.
 The arithmetic instructions alter the flags of 8086.
 The processor uses the result of arithmetic operation to alter the flags. The flags
reflect the status of result (for example, the result is zero or not; result has carry or
not, etc.).
 The arithmetic instructions of 8086 are classified into 5 groups as shown in below
table.

Group-1 Group-2 Group-3 Group- 4 Group- 5
Addition instructions Subtraction instructions Multiplication Division Sign
instructions instructions extension
Instructions
1. ADD 1. SUB 1. MUL 1. DIV 1. CBW

2. ADC 2. SBB 2. IMUL 2. IDIV 2. CWD
3. INC 3. DEC 3. AAM 3. AAD
4. AAA 4. NEG
5. DAA 5. CMP
6. AAS
7. DAS
Group 1: Addition Instructions

ADD dest, src  This instruction adds the contents of the source to
(dest)  (src) + (dest) the destination and places the result in the
Examples: destination.
o ADD BX, AX  The source can be a register, a memory location or
o ADD BX, [SI] an immediate number.
o ADD AL, 25H  The destination can be a register or a memory
location.
 Both the source and destination cannot refer to
memory locations in the same instruction.
ADC dest, src  It adds the two operands with the carry flag.
(dest)  (src)+(dest)+(CF)  Rest all the details are the same as that of ADD
instruction.
INC dest  The INC instruction adds 1 to the specified
(dest)  (dest) + 1 destination.
Examples:  The destination may be a register or memory
o INC BX location.
o INC CL
AAA  ASCII Adjust after Addition.
It works according to the  This instruction can be used to convert the
following Algorithm: contents of AL register to unpacked BCD form.
If low nibble of (AL) > 9 or (AF)  This instruction is executed after addition of two
= 1 then:
o (AL) = (AL) + 6 ASCII/unpacked BCD numbers.
o (AH) = (AH) + 1 *Note: The data entered from the terminal is
o (AF) = 1 usually in ASCII format. In ASCII 0-9 are
represented by codes 30-39. This instruction allows
o (CF) = 1
you to add the ASCII codes instead of first
else converting them to decimal digit using masking of
o (AF) = 0 upper nibble. AAA instruction is then used to
o (CF) = 0 ensure that the result is the correct unpacked BCD.
In both cases:
Clear the high nibble of AL.
Example:
ADD AL,BL
AL=00110101, ASCII 05
BL=00111001, ASCII 09
After addition
AL = 0110 1110, that is, 6EH
incorrect
(temporary result)
AAA
AL = 00000100.
Unpacked BCD for 04
Carry = 1, indicates the result is
14
DAA  Decimal Adjust Accumulator.
Instruction works as follows:  It adjusts the sum in AL register to a valid packed
o If the value of the low order BCD format.
four bits (D3-D0) in the AL is  This instruction is used after adding two packed
greater than 9 or if AF is set, BCD numbers.
the instruction adds 6 (06) to *Note: This instruction operates only on AL
the low order four bits. register. So we have to see that the result is in AL
o If the value of the high order register after the addition of two packed BCD
four bits (D7-D4) in the AL is numbers.
greater than 9 or if carry flag
is set, the instruction adds 6
(60) to the higher order four
bits.

Example:
AL = 0101 1001 (59-BCD) BL =
0011 0101 (35-BCD)
ADD AL, BL
AL = 10001101 or 8EH (incorrect
BCD)
DAA
AL = 1001 0100 (94 BCD Correct).
Group 2: Subtraction Instructions

SUB dest, src  These instructions subtract the number in the source
(dest)  (dest) – (src) from the number in the destination and put the
Examples: result in the destination.
o SBB DX, BX  The source can be a register, a memory location or an
o SBB BX, [SI] immediate number.
o SUB AL, 30H  The destination can be a register or a memory
location.
 Both the source and destination cannot refer to
memory locations in the same instruction.
DEC dest  The DEC instruction subtracts 1 from the specified
dest  (dest) – 1 destination and stores the result in the destination.
Example:  The destination may be a register or memory
o DEC AL location.
NEG dest  Negate: change sign of destination operand.

dest  (0 - dest)  This instruction replaces the number in a destination
Example: with the 2’s complement of that number.
 NEG AL  The destination can be a register or a memory
Replace number in AL with location.
its 2’s complement.
CMP dest, src  This instruction compares a byte or word from the
Example: specified source with a byte or word from the
 CMP BL, 01H specified destination.
Compare immediate  The source may be an immediate number, a register,

number 01H with byte in or a memory location.
BL.  The destination may be a register or a memory
 CMP CX, BX location.
Compare word in BX with  However the source and destination both can’t be
word in CX. memory location.
 The comparison is done by subtracting the source
byte or word from the destination byte or word. But
the result is not stored in the destination.
 Source and destination remains unchanged, only
flags are updated.
AAS  ASCII Adjust after Subtraction.

Algorithm:  Function of this instruction is same as that of AAA
If low nibble of (AL) > 9 or instruction except that it is used after subtraction of
(AF) = 1 then: two ASCII/unpacked BCD numbers.
o (AL) = (AL) - 6  This instruction can be used to convert the contents
o (AH) = (AH) - 1 of AL register to unpacked BCD form.
o (AF) = 1
o (CF) = 1
else
o (AF) = 0
o (CF) = 0
In both cases:
Clear the high nibble of AL.
Example:
AL = 0011 0101 ASCII 5
BL = 0011 1001 ASCII 9
SUB AL,BL
Result:
AL= 1111 1100 = - 4 in 2’s
complement, CF = 1
AAS
AL = 0000 0100 = 04(BCD)
CF = 1 borrow needed.

DAS  Decimal Adjust after Subtraction.
Instruction works as follows:  This instruction is used after subtracting two packed
o If the value of the low order BCD numbers to make sure the result is correct
four bits (D3-D0) in the AL packed BCD.
is greater than 9 or if AF is  It adjusts the contents in AL register to a valid
set; the instruction packed BCD format.
subtracts 6 (06) from the *Note: DAS only works on the AL register.
low order four bits.
o If the value of the higher
order four bits(D7-D4) in the
AL is greater than 9 or if
carry flag is set, the
instruction subtracts 6 (60)
from the high order four
bits.
Example:
AL=86 BCD
BH=57 BCD
SUB AL,BH
AL=2F H, CF =0
DAS
Results in AL = 29 (BCD)
Group 3: Multiplication Instructions

MUL src  It is an unsigned multiplication instruction.
Byte: AX  (AL  src8)  This instruction multiplies an unsigned byte
Word:DX:AX  (AX  src16) from source and unsigned byte in AL register
*Note: (or) unsigned word from source and unsigned
word in AX register.
If you want to multiply a byte
with a word, then first convert  The source can be a register or a memory
byte to a word operand. location.
 When the byte is multiplied by the contents of
Example:
AL, the result is stored in AX.
MOV AX,0005H
 The most significant byte is stored in AH and
MOV CX,0002H least significant byte is stored in AL.
MUL CX  When a word is multiplied by the contents of
Result: AX, the most significant word of result is stored
DX=0000H in DX and least significant word of result is
stored in AX.
and AX=000AH
IMUL src  Integer Multiply.
AL = 11100100 = -2810  It is a signed multiplication instruction.
BL = 00001110 = 1410  Rest all the details are the same as that of MUL
IMUL BL instruction.
Result:
AX = F98C16 = - 165210
MSB = 1 because negative result.
AAM  ASCII Adjust after Multiplication.
Algorithm:  After the two unpacked BCD digits are
AH = AL / 1010 multiplied, the AAM instruction is used to
AL = remainder adjust the product to two unpacked BCD digits
in AX.
Example:
AL=0000 0101 unpacked BCD 05
BH=0000 1001 unpacked BCD 09
MUL BH
(AX) = (AL)  (BH)
= 002DH =004510
AAM
AX=00000100 00000101 BCD 45 :
Correct result
Group 4: Division Instructions

DIV src  It is an unsigned division instruction.
Byte: AX / Byte  For DIV instruction source may be a register or memory
Result: location.
AL = 8-bit Quotient  It divides word by byte or double word by word.
AH = 8-bit Remainder  When dividing a word by a byte, the word must be in
Word: (DX AX) / word AX register. After the division AL will contain an 8-bit
quotient and AH will contain an 8-bit remainder.
Result:
AX = 16-bit Quotient  When a double word is divided by a word, the most

DX = 16-bit Remainder significant word of the double word must be in DX and
Example: the least significant word must be in AX. After the
AX = 00CB H = 20310 division AX will contain a 16-bit quotient and DX will
contain a 16-bit remainder.
BH = 04 H = 0410
DIV BH
Result:
AL=Quotient=32H = 5010
AH=Remainder=03H=0310
IDIV src  Integer division.

 It is a signed division instruction.
 Rest all the details are the same as that of DIV
instruction.
AAD  ASCII Adjust before Division.
Algorithm:  AAD converts two unpacked BCD digits in AH and AL
(AL )=((AH)  10) + (AL) to the equivalent binary number in AL.
(AH) = 0  This adjustment must be made before dividing the two
Example: unpacked BCD digits in AX by an unpacked BCD byte.
AX = 0607 unpacked BCD  After the division AL will contain the unpacked BCD
number 67 quotient and AH will contain the unpacked BCD
remainder.
CH = 09 unpacked BCD
AAD
AX= 0043H = 006710
DIV CH
(Divide AX by unpacked
BCD in CH)
Result:
AL = 07 unpacked BCD
AH = 04 unpacked BCD

Group 5: Sign Extension Instructions

1. CBW
2. CWD
CBW  Convert Byte to Word.
If(AL)<80H  This instruction converts byte in AL to word in AX.
then (AH)  0  The conversion is done by extending the sign bit of AL
else (AH)  FFH throughout AH.
CWD  Convert Word to Double Word.
If (AX) < 8000H  This instruction converts word in AX to double word in DX:
then (DX)  0 AX.
else (DX)   The conversion is done by extending the sign bit of AX
FFFFH throughout DX.
The arithmetic instructions of 8086 are listed in below table, with a brief
Group -1: Addition instructions
1. ADD Add two operands (byte to byte or a word to word) specified in the
instruction.
2. ADC Add two operands specified in the instruction along with the carry
(CY).
3. INC It increments the byte or word by one. The operand can be a
4. AAA It adjusts AL so that it contains a correct unpacked BCD digit.
5. DAA It adjusts the sum in AL register to a valid packed BCD digit.

Group -2: Subtraction instructions
1. SUB Subtraction of source operand from the destination operand and
store the result in the destination operand.
2. SBB Subtraction of source operand and carry (CY) from the destination
operand and store the result in the destination operand.

3. DEC It decrements the byte or word by one. The operand can be a
4. NEG It creates 2’s complement of a given number. That means it changes
the sign of a number.
5. CMP Compare data specified in the instruction.
6. AAS ASCII adjustment after subtraction.
7. DAS Adjust to a valid BCD after subtraction.
Group -3: Multiplication instructions
1. MUL It is an unsigned multiplication instruction. It multiplies two bytes
to produce a word or two words to produce a double word.
2. IMUL It is a signed multiplication instruction.
3. AAM ASCII adjustment after multiplication.
Group - 4: Division instructions
1. DIV It is an unsigned division instruction. It divides word by byte or
double word by word.
2. IDIV It is an signed division instruction.
3. AAD It converts unpacked BCD digits in the AH and AL register into a
single binary number by setting (AL) = ((AH)  1010) + (AL) and
clearing AH to 0.
Group - 5: Sign extension Instructions
1. CBW This instruction converts byte in AL to word in AX. The conversion
is done by extending the sign bit of AL throughout AH.
2. CWD This instruction converts word in AX to double word in DX : AX.
The conversion is done by extending the sign bit of AX throughout
DX.
3.7 Understand the Logic instructions of 8086.

 The logical group includes instructions for performing AND, OR, Exclusive-OR,
complement, shift and rotate operations on binary data.
 The mnemonics used for logical instructions are AND, OR, XOR, TEST, SHR, SHL,
RCR, RCL etc.
 The logical instructions except shift and rotate involve two operands: source
operand and destination operand.
 The source operand can be register, memory location or immediate data.
 The destination can be a register or memory.
 The result of logical operation is stored in destination register or memory except in
case of TEST (In TEST operation the result is used to modify the flag and then the
result is discarded).
 In double operand logical instructions the source and destination cannot refer to
memory locations in the same instruction. Therefore performing logical operation
directly on two memory data is not possible.
 In double operand logical instructions, the source and destination operand should
be of same size, either both the operand size should be byte or word.
 The logical instructions alter the flags of 8086.
 The processor uses the result of logical operation to alter the flag. The flag reflect
the status of the result (for example, the result is zero or not).
 The logical instructions of 8086 are classified into 3 groups as shown in below
table.
Group-1 Group-2 Group-3
Bit manipulation Shift instructions Rotate instructions
instructions
1. NOT 1. SHL / SAL 1. ROL
2. AND 2. SHR 2. ROR
3. OR 3. SAR 3. RCL
4. XOR 4. RCR
5. TEST
Group 1: Bit Manipulation Instructions

NOT dest  It complements each bit to produce 1’s complement
Example: of the specified operand.
BX = 0011 1010 0001 0000  The destination operand can be a register or
NOT BX memory location.
BX = 1100 0101 1110 1111
AND dest, src  This instruction logically ANDs each bit of the
Example: source byte or word with the corresponding bit in
AL =1001 0011= 93H the destination and stores result in the destination.
BL =0111 0101= 75H  The source may be an immediate number, a register

AND BL, AL or a memory location.
BL =0001 0001= 11H  The destination may be a register or a memory
location.
 The source and destination both cannot be memory
locations in the same instruction.
OR dest, src  This instruction logically ORs each bit of the source
Example: byte or word with the corresponding bit in the
AL =1001 0011= 93H destination and stores result in the destination.
BL =0111 0101= 75H  Rest all the details are the same as that of AND
OR BL, AL instruction.
BL =1111 0111= F7H
XOR dest, src  This instruction logically XORs each bit of the source
Example: byte or word with the corresponding bit in the
AL =1001 0011= 93H destination and stores result in the destination.
BL =0111 0101= 75H  Rest all the details are the same as that of AND
XOR BL, AL instruction.
BL =1110 0110= E6H
TEST dest, src  This instruction ANDs the content of a source byte
Example: or word with the contents of the specified
AL = 0101 0001 destination word and updates the flags.
TEST AL, 80H.  But neither operand is changed.
This instruction would test if
the MSB bit of the AL register
is zero or one. After the TEST
operation ZF will be set to 1 if
the MSB of AL is zero.
Group 2: Shift Instructions

SHL dest, count  Shift Logical Left.
SAL dest, count  Shift Arithmetic Left.
The operation performed by  SHL and SAL are two mnemonics for the same
this instruction is shown in instruction.
below.
 The destination byte or word is shifted left by the
Ex number of bits specified in count.
CFMSB LSB 0
am  Zeros are shifted into the LSB.
ples:  The MSB is shifted into the carry flag (CF).
 SAL CX, 1  The destination can be a register or a memory
Shift word in CX 1 bit location.
position left, 0 in LSB.  Bits shifted into CF previously will be lost.
 MOV CL, 05H *Note:
Load desired number of 1. The number of shifts is indicated by count. But if
shifts in CL. the number of shifts required is one, you can place
SAL AX, CL 1 in the count position.
Shift word in AX left 5 times 2. If the number of shifts is greater than 1 then shift
0s in 5 least-significant bits. count must be loaded in CL register and CL must
be placed in the count position of the instruction.
SHR dest, count  Shift Logical Right.

The operation performed by  The destination byte or word is shifted right by the
this instruction is shown in number of bits specified in count.
below.  Zeros are shifted into the MSB.
0MSB LSBCF  The LSB is shifted into the carry flag (CF).
 Rest all the details are the same as that of SHL/SAL
instructions.
SAR dest, count  Shift Arithmetic Right.

The operation performed by  The destination byte or word is shifted right by the
this instruction is shown in number of bits specified in count with preserving
below. sign bit.
MSB LSB CF  As a bit is shifted out of the MSB position, a copy of
the old MSB is put in the MSB position. The LSB
will be shifted into CF.
instructions.
Group 3: Rotate Instructions

ROL dest, count  Rotate Left.
The operation performed by  The destination byte or word is rotated left by the
below.  MSB is placed as a new LSB and a new CF.

CF  MSB LSB instructions.
ROR dest, count  Rotate Right.

The operation performed by  The destination byte or word is rotated right by the
below.  LSB is placed as a new MSB and a new CF.
CF MSB LSB
instructions.
RCL dest, count  Rotate through Carry Left.

The operation performed by  The destination byte or word is rotated left through
this instruction is shown in carry by the number of bits specified in count.
below.  MSB is placed as a new carry and previous carry is
CF  MSB LSB placed as a new LSB.
instructions.
RCR dest, count  Rotate through Carry Right.
The operation performed by  The destination byte or word is rotated right
this instruction is shown in through carry by the number of bits specified in
below. count.
CF  MSB LSB  LSB is placed as a new carry and previous carry is
placed as a new MSB.
instructions.
The logical instructions of 8086 are listed in below table, with a brief description
about each instruction.
Group – 1: Bit Manipulation Instructions
1. NOT Invert each bit of a byte/word.
2. AND AND each bit in byte/word with corresponding bit of other
byte/word.
3. OR OR each bit in a byte/word with corresponding bit of other

byte/word.
4. XOR Exclusive OR each bit in a byte/word with corresponding bit of other
byte word.
5. TEST AND operands to update flags, but do not change operands.
Group – 2: Shift Instructions
1. SHL/SAL Shift bits of word/byte left, put 0’s in LSB (s).
2. SHR Shift bits of word/byte right, put 0’s in MSB (s).
3. SAR Shift bits of word or byte right; copy old MSB into new MSB.
Group – 3: Rotate Instructions

1. ROL Rotate bits of byte/word left, MSB to LSB and to CF.
2. ROR Rotate bits of byte/word right, LSB to MSB and to CF.
3. RCL Rotate bits of byte/word left, MSB to CF and CF to LSB.
4. RCR Rotate bits of byte/word right, LSB to CF and CF to MSB.
3.8 Understand the processor control instructions of 8086.

 The processor control group includes instructions to set or clear carry flag,
direction flag and interrupt flag.
 It also includes HLT, NOP, LOCK and ESC instructions which control the
processor operation.
 The processor control instructions of 8086 are classified into 2 groups as shown in
below table.
Group -1 Group - 2
Flag Manipulation Machine Control
Instructions Instructions
1. STC 1. HLT
2. CLC 2. WAIT
3. CMC 3. ESC
4. STD 4. LOCK
5. CLD 5. NOP
6. STI
7. CLI

Group 1: Flag Manipulation Instructions

STC  This instruction sets the carry flag.
(CF)  1  STC does not affect any other flag.
CLC  This instruction resets the carry flag to zero.
(CF)  0  CLC does not affect any other flag.
CMC  This instruction complements the carry flag.
(CF)  ( CF )  CMC does not affect any other flag.
STD  It sets the direction flag to 1.
(DF)  1  So that SI or DI can be decremented automatically after execution
of string instructions.
CLD  It clears the direction flag to 0.
(DF)  0  So that SI and / or DI can be incremented automatically after
execution of string instructions.
STI  This instruction sets the interrupt flag to 1.
(IF)  1  This enables INTR interrupt of the 8086.
CLI  This instruction resets the interrupt flag to 0.
(IF)  0  Due to this 8086 will not be respond to the interrupt signal on its
INTR input.
Group 2: Machine Control Instructions

HLT  The HLT instruction will cause the 8086 to stop fetching and
executing instructions.
WAIT  When this instruction executes, the 8086 enter the idle condition
where it is doing no processing.
ESC  ESC instruction when executed, free the bus for an external
master like a co-processor or peripheral devices.
LOCK  The LOCK prefix may appear with another instruction.
 When it is executed, the bus access is not allowed for another
master till the lock prefixed instruction is executed completely.
 This instruction is used in case of programming for
multiprocessor systems.
NOP  At the time of execution of NOP instruction, no operation is
performed except fetch and decode. It takes three clock cycles to
execute the instruction.
The processor control instructions of 8086 are listed in below table, with a brief
Group -1: Flag Manipulation Instructions
1. STC Set carry flag, CF=1.
2. CLC Clear carry flag, CF=0.
3. CMC Complement the state of carry flag.
4. STD Set direction flag, DF=1.
5. CLD Clear direction flag, DF=0.
6. STI Set interrupt flag, IF=1.
7. CLI Clear interrupt flag, IF=0.
Group -2: Machine Control Instructions
1. HLT It will cause the 8086 to stop fetching and executing instructions.
2. WAIT Wait until signal on test pin is low.
3. LOCK An instruction prefix, prevents another processor from taking the bus
while the adjacent instruction executes.
4. ESC Escape to external co-processor i.e. 8087 or 8089.
5. NOP No operation.
3.9 Understand the instructions affecting flags of 8086.

 The 8086 microprocessor has 9 flags.
 In this, six flags are altered by arithmetic and logical instructions, and three flags
are used to control the processor operation.
 The flags which are altered by arithmetic and logical instructions are carry flag,
auxiliary carry flag, parity flag, zero flag, sign flag and overflow flag.
 The flags which are used to control the processor operation are trace flag (or single
step trap), interrupt flag and direction flag.
 The status of various flags after execution of arithmetic and logical instructions are
listed in table.
 The 8086 processor has instructions to directly set or clear the interrupt flag,
direction flag and carry flag.
 While servicing an interrupt the 8086 processor, save the status of flags in stack
and the status of the flags are restored at the end of service procedure by executing
IRET instruction.
 The 8086 also has instruction to directly save the flags in stack (PUSHF) and to
restore the saved flags (POPF).
Instructions Flags
O D I T S Z A P C
AAA U - - - U U + U +
AAD U - - - + + U + U
AAM U - - - + + U + U
AAS U - - - U U + U +
ADC + - - - + + + + +
ADD + - - - + + + + 0
AND 0 - - - + + U + 0
CLC - - - - - - - - 0
CLD - 0 - - - - - - -
CLI - - 0 - - - - - -
CMC - - - - - - - - +
CMP + - - - + + + + +
CMPS + - - - + + + + +
DAA U - - + + + + +
DAS U - - - + + + + +
DEC + - - - + + + + -
DIV U - - - U U U U U
IDIV U - - - U U U U U
IMUL + - - - U U U U +

INC + - - - + + + + -
INT - - 0 0 - - - - -
INTO - - 0 0 - - - - -
IRET R R R R R R R R R
MUL + - - - U U U U +
NEG + - - - + + + + +
OR 0 - - - + + U + O
POPF R R R R R R R R R
RCL + - - - - - - - +
RCR + - - - - - - - +
ROL + - - - - - - - +
ROR + - - - - - - - +
SAHF - - - - R R R R R
SAL/SHL + - - - + + U + +
SAR + - - - + + U + +
SBB + - - - + + + + +
SCAS + - - - + + + + +
SHR + - - - + + U + +
STC - - - - - - - - I
STD - 1 - - - - - - -
STI - - 1 - - - - - -
SUB + - - - + + + + +
TEST 0 - - - + + U + 0
XOR 0 - - - + + U + 0
*Note:
1. “+”... Flag is altered and defined (i.e., set or cleared according to the result).
2. “U”…. Flag is undefined (i.e., altered but not defined.).
3. “-“…. Flag is not altered / affected.
4. “R”...The flag is restored from previous saved value.

5. “1”… Set to 1.
6. “0”… Cleared to 0.
3.10 Understand the control transfer (branching) instructions of
8086.
 The control transfer group consists of call, jump, loop and software interrupt
instructions.
 Normally a program is executed sequentially (i.e., the program instructions are
executed one after the other), when a branch instruction encountered program
execution control is transferred to the specified destination or target instruction.
 The transfer of program execution control is done either by changing the content of
IP or by changing the content of IP and CS.
 When the content of IP alone is modified, the program control branches to new
memory location in the same segment.
 When the content of IP and CS are modified, the program control branches to new
memory location in another memory segment.
 The control transfer instructions do not affect the flags of 8086.
 The jump and loop instructions can be classified into conditional and unconditional
instructions.
 In conditional instructions, the status of one or more flags is checked and control
transfer takes place only if the specified condition is satisfied.
 The control transfer (Branching) instructions of 8086 are classified into 4 groups as
shown in below table.
Group - 1 Group - 2 Group - 3 Group - 4

Unconditional Conditional transfer Iteration control Interrupt
transfer instructions instructions instructions
instructions
1. CALL 1. JA/JNBE 1. LOOP 1. INT
2. RET 2. JAE/JNB 2. LOOPE / LOOPZ 2. INTO
3. JMP 3. JB/JNAE/JC 3. LOOPNE/ 3. IRET
4. JBE/JNA LOOPNZ
5. JE/JZ
6. JG/JNLE
7. JGE/JNL
8. JL/JNGE

9. JLE/JNG
10. JNC
11. JNE/JNZ
12. JNO
13. JNP/JPO
14. JNS
15. JO
16. JP/JPE
17. JS
18. JCXZ
Group 1: Unconditional Transfer Instructions

a) Call and Return Instructions
 The CALL instructions transfer control to a subprogram or subroutine or a
procedure after saving return address in the stack memory.
 There are two types of call instruction: Intra-segment or near call and Intra-
segment or far call.
 A near call refers to calling a procedure stored in the same code segment memory
in which main program (or calling program) resides.
 A far call refers to calling a procedure stored in different code segment memory
than that of main program.
 While executing near call, the content of IP alone is pushed to stack.
 While executing far call the content of CS and IP are pushed to stack.
 Every procedure or subroutine end with RET instruction.
 The execution of RET instruction at the end of subroutine or procedure; will pop
the content of top of stack to IP in case of near call or to IP and CS in case of far
call. Thus the program control returns back to main program.
b) Unconditional Jump Instructions
 The unconditional jump instructions do not check any flag condition.
 When the unconditional jump instruction is executed the program control is
transferred to new memory location either in same segment or in another segment.
 In near jump instruction the program control is transferred to new memory
location in the same segment by modifying the content of instruction pointer (IP).
 In far jump instruction the program control is transferred to new memory location
in another segment by modifying the content of instruction pointer (IP) and code
segment (CS) register.
CALL  The CALL instruction is used to transfer execution to a
subroutine subprogram or procedure.
RET  The RET instruction will return execution from a procedure to

the next instruction after the CALL instruction in the calling
program.
JMP  Unconditional Jump.
 This instruction unconditionally transfers the control of
execution to the specified address using 8-bit or 16-bit
displacement or CS: IP.
Group2: Conditional Transfer Instructions

These instructions will cause a jump to a label given in the instruction if the
desired condition(s) occurs in the program before the execution of the instruction. If the
jump is not taken, execution simply goes on to the next instruction.
Instruction Description Condition for jump
code
1. JA/JNBE Jump if above/jump if not below or equal CF = 0 and
ZF = 0
2. JAE/JNB Jump if above or equal/jump if not below CF = 0 and
ZF =1
3. JB/JNAE/JC Jump if below/jump if not above or equal CF = 1 and
ZF = 0
4. JBE/JNA Jump if below or equal/jump if not above CF = 1 and
ZF = 1
5. JE/JZ Jump if equal/jump if zero flag ZF = 1
6. JG/JNLE Jump if greater/jump if not less than or equal ZF = 0 and
CF = 0
7. JGE/JNL Jump if greater or equal/jump if not less than SF = 0
8. JL/JNGE Jump if less/jump if not greater than or equal SF  0
9. JLE/JNG Jump if less than/jump if not greater than ZF = 1 and

SF  0
10. JNC Jump if no carry CF = 0
11. JNE/JNZ Jump if not equal/jump if not zero ZF = 0
12. JNO Jump if no overflow OF = 0
13. JNP/JPO Jump if not parity/jump if parity odd PF = 0
14. JNS Jump if not sign or jump if positive SF = 0
15. JO Jump if overflow flag = 1 OF = 1
16. JP/JPE Jump if parity/jump if parity even PF = 1
17. JS Jump if sign flag = 1 or jump if negative SF = 1
18. JCXZ Jump if CX is zero CX = 0
Group 3: Iteration control instructions

LOOP Repeat execution of the group of instructions until the content of CX
Loop if (CX) ≠ 0 is zero. After each execution CX is decremented by one.
(CX) ← (CX) – 1
LOOPE/LOOPZ Repeat execution of the group of instructions, if the content of CX is
Loop if (CX) ≠ 0 and not zero and the ZF=1. After each execution CX is decremented by
ZF=1 one.
(CX) ← (CX) – 1
LOOPNE/LOOPNZ Repeat execution of the group of instructions, if the content of CX is
Loop if (CX) ≠ 0 and not zero and the ZF=0. After each execution CX is decremented by
ZF=0 one.
(CX) ← (CX) – 1
Group 4: Interrupt Instructions

INT Type  Interrupt Type N.
 This instruction causes the 8086 to call a far procedure.
 The term type in the instruction refers to a number between 0-
255 which identifies the interrupt.
 The address of the procedure is taken from the memory whose

address is four times the type number.
*Note: For the execution of this instruction, the IF must be
enabled.
INTO  Interrupt on Overflow.
 This command is executed, when the overflow flag is set.
 The new contents of IP and CS are taken from the address 0000:
0010.
 This is equivalent to Type 4 interrupt instruction.
IRET  Return from ISR.
 At the end of each ISR, when IRET is executed the values of IP,
CS and flags are retrieved from the stack to continue the
execution of the main program.
The control transfer instructions of 8086 are listed in below table, with a brief
Group 1: Unconditional transfer instructions
1. CALL Call a procedure and save return address on stack
2. RET It returns the control from procedure to calling program.
3. JMP Jump unconditionally from one place to another.
Group 2: Iteration control instructions
1. LOOP Loop through a sequence of instructions until CX=0
2. LOOPE/LOOPZ Loop through a sequence of instructions while ZF=1, and
CX≠0
3. LOOPNE/LOOPNZ Loop through a sequence of instructions while ZF=0 and
CX≠0
Group 3: Interrupt Instructions
1. INT Interrupt program execution, call service procedure
2. INTO Interrupt program execution if, OF=1
3. IRET Return from interrupt service processor to main program.

3.11 Understand the String manipulation instructions of 8086.

 A sting is a sequence of bytes or words.
 The 8086 instruction set includes instructions for string movement, comparison,
scan, load and store.
 It also consists of REP instruction prefix which is used to repeat execution of string
instructions.
 The string instructions end with “S” or “SB” or “SW”. Here, “S” represents string,
“S” represents string byte and “SW” represents string word.
 All string instructions have implied source and destination operand. (i.e., the
operands are not specified as a part of the instruction).
 The string instructions MOVS and CMPS assume that the source operand is in
data segment memory, and the destination is in extra segment memory.
 The string instruction STOS and SCANS assumes that the source operand is in
accumulator, and destination is in extra segment memory.
 The string instruction LODS assumes that the source operand is in data segment
memory and destination is accumulator.
 For string operations, the offset or effective address of the source operand is stored
in SI register and that of destination operand is stored in DI register.
 On execution of a string instruction depending on direction flag [DF], SI and DI
registers are automatically updated to point to the next byte/word of the source
and destination.
 If DF=0, then SI and DI are incremented by one for byte and incremented by two
for word.
 If DF = 1, then SI and DI are decremented by one for byte and decremented by two
for word.
String Instructions
1. REP/ REPE / REPZ / REPNE / REPNZ
2. MOVS / MOVSB / MOVSW
3. CMPS / CMPSB / CMPSW
4. SCAS / SCASB / SCASW
5. LODS / LODSB / LODSW
6. STOS / STOSB / STOSW
REP  Repeat.
 This is an instruction prefix written before one of the
Examples: string instructions.
REP MOVSB STR1, STR2  It will cause CX register to be decremented and the
 It copies byte by byte string instruction to be repeated until CX = 0.
contents.  REPE, REPZ, REPNE and REPNZ are the other
 REP repeats the operation mnemonics for the same prefix. They stand for repeat if
MOVSB until CX becomes equal, repeat if zero, repeat if not equal and repeat if
zero. non-zero respectively.
MOVS (Move String)
MOVSB  Move String Byte.
MAS = (DS) x 1610 + (SI)  One byte of a string data stored in data segment is copied
MAd = (ES) x 1610 + (DI) into extra segment, and SI and DI are automatically
(MAd ← (MAS) incremented / decremented by 1 depending on direction flag
(DF).
If DF = 0, then
(DI) ← (DI) + 1 ; (SI) ← (SI)
+1
If DF = 1, then
(DI) ← (DI) – 1 ; (SI) ← (SI) –
1
MOVSW  Move String Word.

MA = (DS) x 1610 + (SI)  One word of a string data stored in data segment is copied
MAE = (ES) x 1610 + (DI) into extra segment, and SI and DI are automatically
(MAE ; MAE + 1)←(MA ; MA+1) incremented / decremented by 2 depending on direction flag
If DF=0,then (DF).
(DI)←(DI) + 2; (SI)← (SI)+2
If DF=1,then
(DI)←(DI) – 2; (SI)← (SI)–2
CMPS (Compare String)

CMPSB/CMPSW  Compare String Byte / Compare String Word.
MA = (DS) x 1610 + (SI)  One byte/word of a string data in extra segment is subtracted
MAE = (ES) x 1610 + (DI) from one byte/word of a string data in the data segment and
Modify flags ← (MA) – the result is used to modify flags.
(MAE)  The content of DI and SI are automatically incremented
If (MA) > (MAE) then /decremented depending on direction flag (DF).
CF =0 ; ZF = 0 ; SF = 0  For byte operation the content of DI and SI are incremented/
decremented by 1.
If (MA) < (MAE) then
 For word operation, the content of DI and SI are incremented
CF =1 ; ZF = 0 ; SF = 1 / decremented by 2.
If (MA) = (MAE) then
CF =0 ; ZF = 1 ; SF = 0
For byte operation :
If DF = 0, then
(DI) ← (DI) + 1 ; (SI) ← (SI)
+1
If DF = 1, then
(DI) ← (DI) – 1 ; (SI) ← (SI) –
1
For word operation :
If DF = 0, then
(DI) ← (DI) + 2 ; (SI) ← (SI)
+2
If DF = 1, then
(DI) ← (DI) – 2 ; (SI) ← (SI) –
2
SCAS (Scan String)

SCASB  Scan String Byte.
MAE = (ES) x 1610 + (DI)  One byte of string data in extra segment is subtracted from
Modify flags ← (AL) – (MAE) the content of AL and the result is used to modify flags.
If (AL) > (MAE) then  The content of DI and SI are automatically incremented /
CF = 0 ; ZF = 0 ; SF = 0 decremented by 1 depending on direction flag (DF).
If (AL) < (MAE) then
CF = 1 ; ZF = 0 ; SF = 1
If (AL) = (MAE) then
CF = 0 ; ZF = 1 ; SF = 0
If DF = 0 then, (DI) ← (DI) +
1
If DF = 1 then, (DI) ← (DI) - 1
SCASW  Scan String Word.
MAE = (ES) x 1610 + (DI)  One word of string data in extra segment is subtracted from
Modify flags ← the content of AX and the result is used to modify flags.
(AX) – (MAE ; MAE +1)  The content of DI and SI are automatically incremented /
If (AX) > (MAE ; MAE +1) decremented by 2 depending on direction flag (DF).

then CF = 0 ; ZF = 0 ; SF = 0
If (AX) < (MAE ; MAE +1)
then CF = 1 ; ZF = 0 ; SF = 1
If (AX) = (MAE ; MAE +1)
then CF = 0 ; ZF = 1 ; SF = 0
If DF = 0 then, (DI) ← (DI) +
2
If DF = 1 then, (DI) ← (DI) –
2
LODS (Load string)
LODSB  Load string Byte.
MA = (DS) x 1610 + (SI)  One byte of a string data stored in data segment is copied
(AL) ← (MA) into the AL register and SI is automatically incremented /
If DF = 0 then, (SI) ← (SI) + 1 decremented by 1, depending on direction flags (DF).
If DF = 1 then, (SI) ← (SI) – 1
LODSW  Load string Word.
MA = (DS) x 1610 + (SI)  One word of a string data stored in data segment is copied
(AX) ← (MA ; MA +1) into the accumulator. SI is automatically incremented /
If DF = 0 then, (SI) ← (SI) + 2 decremented by 2, depending on direction flags (DF).
If DF = 1 then, (SI) ← (SI) – 2
STOS (Store String)
STOSB  Store String Byte.
MAE = (ES) x 1610 + (DI)  The content of AL register is stored as one byte of string data
(MAE) ← (AL) in the extra segment. DI is automatically incremented /
If DF = 0 then, (DI) ← (DI) + decremented by 1 depending on direction flag (DF).
1
1
STOSW  Store String Word.

MAE = (ES) x 1610 + (DI)  The content of AX register is stored as one word of string
(MAE ; MAE + 1) ← (AX) data in the extra segment. DI is automatically incremented /
If DF = 0 then, (DI) ← (DI) + decremented by 2 depending on direction flag (DF).
2
2

The string instructions of 8086 are listed in table 3.13, with a brief description
about each instruction.
REP An instruction prefix repeat following instruction until
CX=0.
MOVS/MOVSB/MOVSW Move byte/word from one string to another.
CMPS/CMPSB/CMPSW Compare two string byte /word.
SCAS/SCASB/SCASW Scan string, compare a string byte with a byte in AL or a
string word with a word in AX.
LODS/LODSB/LODSW Load string byte/word into AL/AX.
STOS/STOSB/STOSW Store byte/word from AL/AX into string.

4
Programming with 8086
OBJECTIVES
Upon completion of the chapter the student should be able to Understand the working of
Transmission Lines
4.1 Describe assembler directives

4.2 Describe the use of various assembly language development tools like Editor,
Assembler, Linker, Locator and Debugger.
4.3 Explain about assembly language Programming
4.4 Describe the procedure for executing assembly language program with an assembler
4.5 Write simple assembly language programs using data transfer instructions
i) To transfer data between registers
ii) To transfer data between register and memory location
iii) To transfer data from one memory location to another memory
location
4.6 Write simple assembly language programs using arithmetic instructions
i) To perform addition/ subtraction/ multiplication/ division of two 8/ 16
bit numbers.
ii) To perform 1‘s complement subtraction
iii) To perform addition of series of ‗n‘ numbers
4.7 Write simple assembly language programs using logical instructions
i) To perform AND/ OR/ XOR operations on two 8/ 16 bit numbers
ii) To perform conversion from binary to gray on 4 bit data
4.8 Write simple assembly language programs using string manipulation instructions
i) To find the length of the given string
ii) To reverse the given string
4.9 Explain conditional and loop statements.
4.10 Write simple assembly language programs using conditional and loop statements.
i) To find the biggest/ smallest of the given series of numbers
ii) To arrange the given series of numbers in ascending /descending
order
4.11 State the need of Subroutine
4.12 Explain CALL, RETURN instructions
4.13 Explain Subroutine programming in 8086.
4.14 Give simple program using subroutine and parameters passing
i) To find the factorial of the given number
4‐2 Programming with 8086
4.1. Describe assembler directives

 Directives are the instructions, to assembler, Linker and loader.
 Directives are also called as Pseudo-instructions.
 Definition of Assembler directive: The Pseudo instruction which gives the
direction to the assembler is called as assembler directive.
 The assembler directives are used to specify start and end of a program, attach
value to variables, allocate storage locations to input/output data, to define start
and end of segments, procedures, micros etc.
*Note: No machine codes are generated for assembler directives.
 Some of the assembler directives that can be used for 8086 assembly language
program development are listed in table.
a) Types of Assembler Directives:
Assembler Functions
Directive
1. DB Define byte. Used to define byte type variable.
2. DW Define word. Used to define 16-bit variable.
3. DD Define Double word. Used to define 32-bit variable.
4. DQ Define Quad word. Used to define 64-bit variable.
5. DT Define Ten bytes. Used to define ten bytes of a variable.
6. ASSUME Indicates the name of each segment to the assembler.
7. SEGMENT Defines the start of a memory segment.
8. ENDS End of segment. Indicates the end of a memory segment.
9. ORG Origin. Used to assign the starting address for a program
module of data segment.
10. EVEN Informs the assembler to align the data array starting from even
address.
11. END Indicates the end of the program.
12. PROC Procedure. Defines the beginning of a procedure.
13. ENDP End of procedure. Indicates the end of a procedure.
14. EQU Equate. Used to equate numeric value or constant to a variable.
15. MACRO Defines the name, parameters, and start of a macro.

Programming with 8086 4‐3
16. ENDM End of macro. Indicates the end of a macro sequence.

17. COMMENT Indicates a comment
18. EXITM Terminates macro expantions
19. EXTRN Indicates externall defined symbole
20. LABEL creates a new label with specified type and current location
counter
21. LOCAL declares local variable in macro definition
22. .MODEL specifies mode for assembling the program.
23. PTR assigns a specific type to a variable or to a label
24. PUBLIC identifies symbols to be visible outside module
25. TITLE defines the program listing title
4.1.1. Data Definition & Storage Allocation Directives
 These assembler directives are used to define the program variables and allocate a
specified amount of memory to them.
 The data definition & storage allocation directives are: DB, DW, DD, DQ and DT.
1. DB Define Byte
 The directive DB is used to define a byte type variable.
 It reserves specific amount of memory to variables and store the values specified
in the statement as initial values in the allotted memory locations.
 The range of values that can be stored in a byte is 0 to 255 for unsigned numbers
and -128 to 127 for signed numbers.
 General Form:
Name of variable DB Initialization Value(s)
 Examples:
1. Total DB 0:
The above statement informs the assembler to reserve one byte of memory for a
variable named TOTAL and initialize with value zero during execution of the
program.
2. Table DB 83, 100, 200, 55, 255
The above statement reserves 5 bytes of consecutive memory locations for the
variable TABLE and initializes them to 83, 100, 200, 55 and 255.

2. DW: Define Word
 The directive DW is used to define a word type (2 bytes) variable.
 It can be used to define single or multiple word variables.
 The range of values that can be stored in a word is 0 to 65535 for unsigned
numbers and -32768 to +32767 for signed numbers.
 General form:
Name of variable DW Initialization Value(s)
 Examples:
1. Total DW 0:
The above statement informs the assembler to reserve two bytes of memory for a
variable named TOTAL and initialize with the value zero during execution of the
program.
2. Table DW 83, 100, 200, 55, 9255
The above statement reserves 10 bytes of consecutive memory locations for the
variable TABLE and initializes them to 83, 100, 200, 55 and 9255.
3. DD: Define Double Word
 The directive DD is used to define a double word type (4 bytes) variable.
 It can be used to define single or multiple double variables.
 The range of values that can be stored in a double word is 0 to 232 - 1 for
unsigned integer numbers and -232-1 to 232-1-1 for signed integer numbers.
 The DD type variables are useful in the math coprocessor instructions where
large numbers are used in computation.
 General form:
Name of variable DD Initialization Value(s)
 Examples:
1. Total DD 0:
The above statement informs the assembler to reserve four bytes of memory for a
program.
2. TWONUM DD “84”
The above statement informs the assembler to reserve four bytes of consecutive
memory locations for a variable named TWONUM and the first byte in initialized
with the ASCII equivalent of ‘4’, the second byte is initialize with the ASCII
equivalent of ‘8’, other bytes will be initialize to zero. The variable contains the value

00 00 38 34 H.
4. DQ: Define Quad word
 The directive DQ is used to define a quad word (8 bytes) type variable. It can be
used to define single or multiple quad word variables.
 The range of values that can be stored in a quad word is 0 to 264-1 for unsigned
integer numbers and -264-1 to +264-1 - 1 for signed integer numbers.
 The DQ type variables are useful in match coprocessor instructions where large
numbers are used in computation.
 General form:
Name of variable DQ Initialization Value(s)
 Examples:
1. Total DQ 0:
The above statement informs the assembler to reserve eight bytes of memory for a
program.
2. TWONUM DQ “84”
The above statement informs the assembler to reserve eight bytes of consecutive
memory locations for a variable named TWONUM; the first byte is initialized with
the ASCII equivalent of ‘4’ and the second byte is initialized with the ASCII
equivalent of ‘8’. The variable contains the value 00 00 00 00 00 00 38 34 H.
5. DT: Define Ten bytes
 The directive DT is used to defines ten bytes type variable.
 It can be used to define single or multiple 10-byte variables.
 The range of value that can be stored in ten bytes is 0 to 280-1 for unsigned
integer numbers and -280-1 to +280-1-1 for signed integer numbers.
 The DT type variables are useful in math coprocessor instructions where large
numbers are used in computation.
 General Form:
Name of variable DT Initialization Value(s)
 Examples:
1. Total DT 0
The above statement informs the assembler to reserve ten bytes of memory for a
program.

2. TWONUM DT “84”
The above statement informs the assembler to reserve ten bytes of consecutive
memory locations for a variable named TWONUM; the first byte is initialized with
the ASCII equivalent of ‘4’ and the second byte is initialized with the ASCII
equivalent of ‘8’. The variable contains the value 00 00 00 00 00 00 00 00 38 34 H.
4.1.2. Program Organization Directives
The 8086 programs are organized as a collection of logical segments. The
directives used to organize the program segments are ASSUME, SEGMENT and ENDS
etc.
1. ASSUME
 The ASSUME directive is used to tell the assembler that the name of the logical
segment should be used for a specified segment.
 The 8086 works directly with only 4 physical segments: a code segment, a data
segment, a stack segment, and an extra segment.
 Its general form is,
ASSUME Segment_Register: Segment_Nmae
Examples:
ASUME CS: This tells the assembler that the logical segment named CODE contains
CODE the instruction statements for the program and should be treated as a
code segment.
ASUME DS: This tells the assembler that for any instruction which refers to a data in
DATA the data segment, data will found in the logical segment DATA.
2. SEGMENT
 The directive SEGMENT is used to indicate the beginning of a code/data/stack
segment.
Segment_name SEGMENT
Example:
CODE SEGMENT It starts the logic segment containing code.
3. ENDS:
 The directive ENDS is used to indicate the end of a code/data/stack segment.
Segment_name ENDS

Example:
CODE SEGMENT It starts the logic segment containing code.
. . . Program code
. . .
CODE ENDS End of segment named as CODE.
*Note: The directives SEGMENT and ENDS must enclose the program or data defining
statements.
4.1.3. Alignment Directives
 These directives are used to control the location counter used by the assembler
during machine code generation.
 They include: ORG and EVEN.
1. ORG
 The directive ORG (origin) is used to assign the starting address (effective
address) for a program/data segment.
ORG Numirical_value
ORG 1000 H This directive informs the assembler that the statements
following ORG 1000H should be stored in memory starting
with effective address 1000H.
2. EVEN
 The directive EVEN will inform the assembler to store the program/data
segment starting from even address.
 The 8086 requires one bus cycle to access a word at even address and two bus
cycles to access a word at odd address.
 The even alignment with EVEN directive help in accessing a series of
consecutive memory words quickly.
4.1.4. Programs End Directives
 This directive is used to inform the assembler, the physical end of a program.
 It is performed using the directive END.
END:
 END directive is placed after the last statement of a program to tell the assembler
that this is the end of the program module.
 The assembler will ignore any statement after an END directive.

4.1.5. Value-Returning Attribute Directives
 These directives make the programmer’s task easier by providing flexibility,
increasing readability, and cause the assembler to substitute some numeric
constant depending on the data item.
 They include: LENGTH, SIZE, OFFSET, SEG and TYPE.
4.1.6. Procedure Definition Directives
 The procedure definition directives are used to define subroutines.
 It offers modular programming constructs like PROC and ENDP.
4.1.7. Macro Definition Directives
 The macro definition directives are used to define macro constants macro
functions.
 The directives EQU, MACRO, and ENDM are used in the definition of a macro.
4.2 Describe the use of various assembly language development

tools like Editor, Assembler, Linker, Locator and Debugger.
 Most of the program development tools are programs (software), which run on
PC in order to write, assemble, debug, modify and test the assembly language
programs.
 The assembly language program development tools are included with in
assemblers such as Turbo Assembler (TASM) and Microsoft Assembler (MASM)
etc.
 The assembly language program development tools are:
1. Editor
2. Assembler
3. Linker
4. Locater
5. Debugger
4.2.1. Editor (Text Editor)
 The editor is software tool which, when run on a PC, allow the user to
type/enter and modify the assembler language program.
 The editor provides a set of commands for insertion, deletion, modification of
letters, characters, statements, etc.
 The main function of an editor is to help the user to construct the assembly
language program in the right format.
 The program created using editor is known as source program and usually it is
saved with file extension.ASM.

 For example, if a program for addition is developed using editor then it can be
saved as “ADDITION.ASM”. Some examples of editors are NE (Norton Editor),
EDIT (DOS Editor), etc.,
4.2.2. Assembler
 An assembler is software is used to translate the assembly language program
(source file) to the machine language program (object file).
 The input for the assembler is source program which is saved with file extension
*.ASM as shown in fig. 3.12.
 Assembler produces the output as object code (*.OBJ) and reports program errors
during translation.
 Examples: Turbo Assembler (TASM) and Microsoft Assembler (MASM) etc.
Fig. 4.2
4.2.3. Linker
 A Linker is a software tool which is used to combine object files of program
modules and library functions into a single executable file.
 Thus a linking program which basically converts an *.OBJ file(s) to a single *.EXE
file(s) as shown in fig. 3.12.
 Examples: LINK (Microsoft’s linker), TLINK (Borland’s Turbo linker) etc.
4.2.4. Locater
 A Locator is a program, used to assign the specific address of where the segments
of object code are to be loaded into the memory.
4.2.5. Debugger
 The debugger is also a software tool that allows the execution of program.
 The process of locating and correcting the errors in a program using a debugger is
known as debugging.
 The program execution in single step mode or break point mode.
 In single step mode debugger stops the program execution after each instruction.
 User can check the result after execution of each instruction and proceed to the
execution of next instruction.
 In break point mode the debugger allows the user to set a break point at any
point in the program.
 The debugger allows the execution of program up to the break point and then
stop.
 User can check the results at this point and proceed to execution of rest of the
program if results are as per his lines.
 The debugger also allows the user to look at the contents of different registers
and memory locations.
4.3 Explain about assembly language Programming

 Assembly language is a low level programming language.
 Definition: A program written in mnemonics is known as assembly language
program.
 Mnemonic is a group of alphabets which suggest operation to be performed by
the instruction.
 For example, the mnemonic for addition is ADD, the mnemonic for subtraction is
SUB and the mnemonic for the instruction to copy data from one location to
another is MOV.
 The program written in this language can be converted in to machine code for
execution and it is performed by the translator known as assembler.
 Assembly language is case insensitive; therefore programs can be coded either in
upper case, lower case or combination of upper/lowercase characters.
 Advantage: The writing of programs in assembly language is much easier as
compared to the writing of a program in machine language.
 Disadvantage: It is not portable i.e. the programs written for one
microcomputer cannot be used for any other because each computer has its own
assembly language.
 Assembly language statements are usually written in a standard form that has 4
fields as shown below table.
Table: Assembly Language statement format.
Label Instruction Comments
Mnemonic (or) Operand
Op-code

1. Label:
 The first field is label field.
 A label is a symbol or group of symbols used to represent an address in a jump
(or) call (or) any kind of branch operation instruction.
 Labels are usually followed by a colon (:).
2. Mnemonics
 The second field is mnemonic field.
 Instruction mnemonics are also called op-codes.
 Assembly language uses 2, 3, or 4- letter mnemonics to represent each instruction
type.
3. Operand
 The third field is operand field.
 The operand field of the statement contains the data, the memory address. The
port address, or the name of the register on which the instruction is to be
performed.
4. Comments
 The final field in an assembly language statement is comment field, which starts
with a semicolon.
 A comment field describes function of an instruction.
 Comments do not become the part of the machine language program, but they are
very important.
4.4 Describe the procedure for executing assembly language

program with an assembler
Before assembling or linking a program, the assembler programs must be in the
current directory or DOS path. The assembler programs are TASM.EXE, MAXM.EXE,
LINK.EXE and TD.EXE.
1. Assembling
 Create a source file ADD.ASM for the addition program using an editor and
save to disk. To edit this file, we should type a command C>TASM>EDIT
ADD.ASM, at the prompt and press enter.
 Assemble the ADD.ASM by running assembler on it. To run assembler type
C>TASM>TASM ADD.ASM and press enter. The source files are converted in
object files or machine cods if there no error.

2. Linking
 To link the object file(s), the linker (LINK.EXE) reads the object file(s), link them,
and creates an executable file.
 Type C>TASM>LINK ADD.OBJ at the prompt and press enter for linking.
3. Executing
 Once the program is assembled and linked, it may be run by typing
C<TASM>ADD on the prompt. But the program does not generate any output,
so we will probably have to run the program using a debugger.
 Type C>TASM>TD ADD.EXE and press enter to run and execute program.
 Add locations using add watch option of option menu.
 Execute the program corresponding to “reft” location using run menu.
 Result can be seen in AX, other registers and reserved locations.
4.5 Write simple assembly language programs using data

transfer instructions
i) To transfer data between registers
Example: Transfer 8 bit data of BH into CL.
Solution:
MOV CL, BH
Example: Transfer 16 bit number of AX into BP.

Solution.
MOV BP, AX
ii) To transfer data between register’s and memory location

Example: Explain MOV AX,[1575 H] instruction.
Solution:
Let us take contents of DS = 1573 H. so the physical address can be calculated as
follows:

So with this instruction, 16 bit data location whose physical address is 16CA5 H is
transferred to register AX as shown below:
iii) To transfer data from one memory location to another memory

Location
The 8 data bytes are stored from memory location4.000H to 4 007H. write
8086 ALP to transfer the block of data to new location 5000H to 5007H.
MOV SI, 4000H Set source index
MOV DI, 5000H Set destination index
MOV CX,08H Set count
UP: MOV AL, [SI] Move from source
MOV [DI], AL Move into destination
INC SI Increment SI
INC DI Increment DI
DEC CX Decrement count
JNZ UP Perform until count is zero
HLT

4.6 Write simple assembly language programs using arithmetic

instructions
i) To perform addition/ subtraction/ multiplication/ division of two 8/
16 bit numbers.
Program 1: 8-BIT ADDITION
Mnemonic Operand Comments
MOV AX, 0000 Initialize data segment to 0000H
MOV DS,AX
MOV AL,[4000] Load 8- bit number in AL
ADD AL,[4001] Add content of AL & memory
MOV [4002],AX Store the result
INT 03H
Example 1:
Output Input
CARRY SUM 8 BIT DATA-2 8 BIT DATA-1
4003H 4002H 4001H 4000H
00H 35H 12H 23H

Example 2:
Output Input
CARRY SUM 8 BIT DATA-2 8 BIT DATA-1
4003H 4002H 4001H 4000H
01H 1FH 23H 0ECH
Program 2: 8-BIT Subtraction

MOV AX, 000 Initialize data segment to

MOV DS,AX 0000H
MOV AL,[4000] Load 8- bit number in AL

SUB AL,[4001] Subtract the content of
memory from AL
INT 03H
Example 1:
Output Input
BORROW DIFFERENCE 8 BIT DATA-2 8 BIT DATA-1
4003H 4002H 4001H 4000H
00H 22H 12H 34H
Example 2:
Output Input
BORROW DIFFERENCE 8 BIT DATA-2 8 BIT DATA-1
4003H 4002H 4001H 4000H
01H 67H ABH 12H

Program 3: 8-BIT MULTIPLICATION
MOV AX, 0000
MOV DS, AX
MOV AL, [4000]
MOV BL, [4001]
MUL BL
MOV [4002], AX
INT 03H
Input and Output
Output Input
Upper byte of result Lower byte of result Multiplicand Multiplier
4003H 4002H 4001H 4000H
03 A8 34H 12H
Program 4: 8-BIT DIVISION

MOV AX, 0000
MOV DS, AX
MOV AX, [4000]
MOV BL, [4002]
DIV BL
MOV [4003], AX
INT 3
Input and Output
Output Input
Remainder Quotient Divisor Dividend
4003H 4002H 4001H 4000H
01 02 03 07

Program 5: 16-BIT Addition without carry

MOV AX, 0000 Initialize data segment to 0000H

MOV DS,AX
MOV AL,[4000] Load 16- bit number in AX
ADD AL,[4002] Add content of AX & memory
INT 03H
Input:
16 bit data-2 16 bit data-1
4003H 4002H 4001H 4000H
43H 44H 12H 34H
Output:
SUM
4005H 4004H
55H 78H
Program 6: 16-BIT ADDITION with carry
Method- I
Flow Chart:
Fig. 3.13

Program:
Label Instructions Comments
MOV AX, 2017H Load the first data in AX

register.
MOV BX, 0F123H Load the second data in BX
register.
MOV CL, 00H Clear the CL register for carry.
ADD AX, BX Add the two data; sum will be

in AX.
MOV [4004H], AX Store the sum in memory

locations .
JNC DOWN Check the status of carry flag.
INC CL If carry flag is set, increment
CL by one.
DOWN: MOV [4006H], CL Store the carry in memory
location.
HLT Stop execution of the program.
Method- II
Program:
MOV SI, 4000H Set SI register as pointer for data.
MOV AX, [SI] Get the first data in AX register.
MOV BX, [SI + 2] Get the second data in BX

register.
MOV CL, 00H Clear the CL register for carry.
ADD AX, BX Add the two data, sum will be in

AX register.
MOV [SI + 4], AX Store the sum in memory location

(4004H).
JNC DOWN Check the status of carry flag.
INC CL If carry flag is set, increment CL

by one.
DOWN: MOV [SI + 6], CL Stores carry in memory location
(4006H).
Sample Data & Result:
Example 1:
Data Result
First 16-bit Number: 2017H Sum =113AH
Second 16-bit Number: F123H Carry=01H
OR
Input:
16 bit data-2 16 bit data-1
4003H 4002H 4001H 4000H
F1H 23H 20H 17H
Output:
CARRY SUM
4006H 4005H 4004H
01H 11H 3AH
Program 7: 16-BIT SUBTRACTION

Write an assembly language program to subtract two numbers of 16-bit data.
Store the magnitude of the result in memory. In one of the memory location store
00H to indicate positive result or store 01H to indicate negative result.

Flow Chart:
Fig. 3.14
Program:
MOV SI, 1100 H Load the address of data in SI

register.
MOV AX, [SI] Get the minuend in AX
register.
MOV BX, [SI+2] Get the subtrahend in BX
register.
MOV CL,00 H Clear the CL register to
account for sign.
SUB AX,BX Get the difference in AX
register.
JNC STORE Check the status of carry flag.
INC CL If carry flag is set, increment
CL by one.
NOT AX Take 2’s complement of
ADD AX, 0001H difference.

STORE: MOV [SI+4], AX Store difference in memory

location (1104 H).
MOV [SI+6], CL Store sign bit in memory
location (1106 H).
Example 1:
Data Result
Minuend = 840CH Difference = 2EBEH
Subtrahend = B2CAH Sign Bit = 01H
Program 8: 16-Bit MULTIPLICATION

Write an assembly language program to multiply two numbers of 16-bit data.
Flow Chart:
Fig.

Program:
MOV SI, 1100H Set SI as pointer for data.
MOV AX, [SI] Get the 1st data in AX register.
MOV BX, [SI+2] Get the 2nd data in BX register.
MUL BX Multiply AX and BX. The

product will be in AX and DX
registers.
MOV [SI+4], AX Save the lower 16 bits of
product in memory.
MOV [SI+6], DX Save the upper 16 bits of
product in memory.

Example 1:
Data Result
Data 1= EF1AH Output Data : BFC2 8A20H
Data 2= CD50H
BFC2H 1106 (RESULT DX)

8A20H 1104 (RESULT AX)
CD50H 1102 (INPUT BX)
EF1AH 1100 (INPUT AX)

Program 9: 16-Bit DIVISION

Write an assembly language program to divide 32-bit data by 16-bit data.
Flow Chart:
Fig. 3.17
Program:
MOV AX, [SI] Get the lower 16-bit of dividend

in AX register.
MOV DX, [SI+2] Get the upper 16-bit of dividend
in DX register.
MOV BX, [SI+4] Get the divisor in BX register.
DIV BX Divide the content of AX and

DX with content of BX.
The quotient will be in AX
register.
The remainder will be in DX
register.
MOV [SI+6], AX Save the quotient in memory.
MOV [SI+8], DX Save the remainder in memory.

Example 1:
Data Result
Dividend = 71C2580AH
Quotient = 75EEH
(32-bit data)
Divisor = F6F2H Remainder = 290EH
(16-bit data)
Program 10: 1‘s complement subtraction

MOV BX, 92H
MOV AX, 41H
NOT AX
ADD AX,BX
JC Down1
NOT AX
JMP down2
Down1: INC CX
ADD AX, CX
Down 2: MOV [4004H], AX
INT 3
Data Result
Minuend = 92H Difference = 51H
Subtrahend = 41H Sign Bit = 00H

Program 11: To perform addition of series of n‘numbers

MOV SI, 8000
MOV CX, [SI]
MOV AX, 0000
MOV BX, AX
LABEL1: INC BX
CMP BX, CX
JNZ LABEL 1
MOV DI, 8010
MOV [DI], AX
INT 03
Input:
8000: CX: 05
Output:
8010: AX: 0FH (5h+4h+3h+2h+1h)
4.7 Write simple assembly language programs using logical

instructions
i) To perform AND/ OR/ XOR operations on two 8/ 16 bit
numbers
Program 1: 8 bit logical AND operation
MOV AX, 0000H
MOV DS, AX
AND AX,
MOV AL, [4000]
MOV BL, [4001]
AND AL, BL
MOV [4002], AL
INT 03

Program 2: 8 bit logical OR operation

MOV AX, 0000H
MOV DS, AX
AND AX,
MOV AL, [4000]
MOV BL, [4001]
OR AL, BL
MOV [4002], AL
INT 03
Program 3: 8 bit logical EXOR operation

MOV AX, 0000H
MOV DS, AX
AND AX,
MOV AL, [4000]
MOV BL, [4001]
XOR AL, BL
MOV [4002], AL
INT 03
Program 4: 16 bit logical AND operation

MOV AX, 0000H
MOV DS, AX
AND AX,
MOV AX, [4000]
MOV BX, [4002]
AND AX, BX
MOV [4004], AX
INT 03

Program 5: 16 bit logical OR operation

MOV AX, 0000H
MOV DS, AX
AND AX,
MOV AX, [4000]
MOV BX, [4002]
OR AX, BX
MOV [4004], AX
INT 03
Program 6: 16 bit logical XOR operation
MOV AX, 0000H

MOV DS, AX
AND AX,
MOV AX, [4000]
MOV BX, [4002]
XOR AX, BX
MOV [4004], AX
INT 03
Program 7: Binary to gray on 4 bit data

DATA SEGMENT
OPR DB 09H ; 09H - 1001
RES DB ?
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START:
MOV AX,DATA
MOV DS,AX
MOV AX,0000H
MOV AL,OPR
MOV BL,AL
RCR AL,1
XOR AL,BL
MOV RES,BL
INT 3
CODE ENDS
END START
Result:
Binary value 1001
Gray value 1101
4.8 Write simple assembly language programs using string

manipulation instructions
Program 1: To find the length of the given string
DATA SEGMENT
Str DB “INDIA$”
DATA ENDS
ASSUME CS: CODE, DS: DATA
CODE SEGMENT
START: MOV AX, DATA
MOV DS, AX
MOV AX, 0000H
MOV CX, 0000H
MOV SI, OFFSET Str
X: MOV AL, [SI]
CMP AL, ‘$’
JE Y
INC SI
INC CX
JMP X
Y: INT 3H
CODE ENDS
END START

Result:
Initial Count: 00H
Length of the string CX: 05H
Program 2: To reverse the given string
ASSUME CS: CODE
CODE SEGMENT
ORG 2000H
START: MOV SI, 4000H
MOV DI, 5000H
MOV CL, 05H
ADD DI, 04H
REPEAT: LODSB
MOV [DI], AL
DEC DI
LOOP REPEAT
INT 3H
CODE ENDS
END START
4.9 Explain conditional and loop statements.

 Conditional structures are used to make a conditional loop.
 These help the assembler to form the conditional loops in assembly language
programs.
 Basically, we have four types of conditional structures. These are:
1) IF-THEN
2) IF-THEN-ELSE
3) MULTIPLE IF –THEN-ELSE
4) REPEAT-UNTIL
4.9.1. IF-THEN
 The IF-THEN structure has the following format:
IF condition THEN
action
action
 This structure says that, IF the stated conditional is found to be true, the series of
actions following THEN will be executed.
 Otherwise, execution will skip over the actions after the THEN and proceed with
the next main line instruction.
 Example:
IF carry THEN
Increment register AH
 The simple IF-THEN is implemented with a conditional jump instruction.
 This structure can be understood by the following assembly language program.
A program using IF-THEN
A program to add two 8-bit values with carry
MOV AH, 00H Clear register AH.
MOV BL, 99H
MOV BH, 99H
ADD BH, BL BH=BH+BL.
MOV AL, BH Store LSB in AL.
JNC END Jump if CF=0.
INC AH Store carry in AH.
END: INT 3 End of program.
Result: 99H+99H=0132H
AH=01H AL=32H
4.9.2. IF-THEN-ELSE
 This type of statement is used to indicate a choice between two alternative courses
of actions.
 The IF-THEN-ELSE structure has the following format:

IF condition THEN
action
action
ELSE
action
action
 This is different situation from the simple IF-THEN, because here either one series
of actions or another series of actions is done before the program goes on with the
next main line instruction.
 This structure can be understood by the following assembly language algorithm
and flow chart.
 Algorithm:
Read Temperature
IF Temperature 300 THEN
Light Green Lamp
ELSE
Light Yellow Lamp
Read pH Sensor
 Flow Chart:
Fig.
A program using IF-THEN-ELSE
A program to determine the largest of two 16-bit values store
the largest value in register AX.
MOV BX, 9901H
MOV CX, 9902 H
CMP BX, CX Compare BX and CX.
JA COPY_B Jump if BX is above CX.
COPY _C: MOV AX, CX Store CX in AX.
JMP END Jump to label END.
COPY_B: MOV AX, BX Store BX in AX.
Result: AX=CX=9902H
*Note:
IF B>C THEN
A=B
ELSE
A=C
4.9.3. MULTIPLE IF-THEN-ELSE

 In different programming applications we have to choose one of several
alternative actions based on the some variable read in or on a command code
entered by user.
 To choose one alternative from several we use MULTIPLE IF-THEN-ELSE
structure.
 This structure is also called as nest IF-THEN-ELSE structure.
 MULTIPLE IF-THEN-ELSE structure has the following format:

IF condition1 THEN
action1
ELSE IF condition2 THEN
action2
ELSE
action3
 This structure can be understood by the following assembly language algorithm

and flow chart.
 Algorithm:
Read Temperature
IF Temperature <300 THEN
Light Yellow Lamp
ELSE IF Temperature <400 THEN
Light Green Lamp
ELSE Light Red Lamp
Read pH Sensor
 Flow Chart:
Fig. 3.24
A program using Multiple IF-THEN-ELSE structure
A program to read a key press from keyboard display it on a ASCII display.
IN AL, 80H Read from keyboard.
MOV BL, AL Copy data to register BL.
CHK_3: CMP BL, 03H Compare BL with 3.
JNE CHK_2 Jump if BL not equal 3.
MOV AL, 33H Store ASCII code for ‘3’ in AL.
JMP DISP Display AL on ASCII display.
CHK_2: CMP BL, 02H Compare BL with 2.
JNE SET_1 Jump if BL not equals 2.
MOV AL, 32H Store ASCII code for 2 in AL.
JMP DISP Display AL on ASCII display.
STEP_1: MOV AL, 31H Store ASCII code for 1 in AL.
DISP: OUT 81H, AL Display AL on ASCII display.
*Note:
IF B=3 THEN
A = 33H
ELSE IF B=2 THEN
A = 32H
ELSE
A = 31H
4.9.4. REPEAT-UNTIL
 Repeat-Until structure has the following format:
REPEAT
action
action
UNTIL some condition is present

 An important point about REPEAT-UNTIL structure is that the action or series of
actions is done once before the condition is checked.
 Example:
REPEAT
Keep Heater ON
UNTIL Temp<1000
 The following assembly language program illustrates the use of REPEAT-UNTIL

type statement.
A program using REPEAT-UNTIL STRUCTURE
A program to determine a SUM of first TEN natural numbers.
MOV CL, 0AH Setup loop counter.
MOV AL, 00H Set initial sum to 0.
MOV BL, 01H First number in BL.
BACK: ADD AL, BL
INC BL
DEC BL
JNZ BACK
4.10 Write simple assembly language programs using

conditional and loop statements.
i) To find the biggest/ smallest of the given series of
numbers
Program 1: FINDING GREATEST NUMBER
Write an assembly language program to find the biggest number in an 8-bit array.
Flow Chart:

Fig. 4.10
Program:
MOV SI, 1100H Set SI register as pointer for

array.
MOV DI, 1200H Set DI register as pointer for
result.
MOV CL,[SI] Set CL as count for elements in
the array.
INC SI Increment the address pointer.
MOV AL, [SI] Set first data as largest.

DEC CL Decrement the count.
AGAIN: INC SI Make SI to point to next data in

array.
MOV BL, [SI] Get the next data in BL register.

CMP AL, BL Compare the current largest
data in AL with BL.
JNC AHEAD If carry is not set then AL is
greater than BL, hence proceed
to AHEAD.
MOV AL, BL If carry is set then make BL as
current largest.
AHEAD: DEC CL Decrement the count.
JNZ AGAIN If count is not zero repeat

search.
MOV [DI], AL Store the largest data in
memory.

Example 1:
Data Result
count = 05
Output data: FEH
Data1= 4EH
Data2= 30H
Data3= 98H
Data4= ACH
Data5= FEH
ii) To arrange the given series of numbers in ascending

/descending order
Program 1: : SORTING AN ARRAY IN ASCENDING ORDER
Write an assembly language program to sort an array of 8-bit data in ascending

order.
Flow Chart:
Fig. 4.10
Program:
MOV SI, 1100H Set SI register as pointer for

array.
MOV CL, [SI] Set CL as count for N-1
repetitions.
DEC CL
REPEAT: MOV SI, 1100H Initialize pointer.

MOV CH, [SI] Set CH as count for N-1

comparisons.
DEC CH
INC SI Increment the pointer.
REPCOM: MOV AL, [SI] Get an element of array in

AL register.
INC SI
CMP AL, [SI] Compare with next element
of array in memory.
JC AHEAD If AL is lesser than memory,
then go to AHEAD.
XCHG AL [SI] If AL is less than memory
then exchange the content of
XCHG AL, [SI-1] memory pointed by SI and
the previous memory
location.
AHEAD: DEC CH Decrement the count for
comparisons.
JNZ REPCOM Repeat comparison until CH
count is zero.
DEC CL Decrement the count for
repetitions.
JNZ REPEAT Repeat N-1 comparisons
until CL count is zero.
HLT Stop execution of the
program.

Data Result
Input data: Output data:
07H(COUNT) 11H
AAH 22H

77H 44H
FFH 77H
22H AAH
11H BBH
44H FFH
BBH
4.11 State the need of Subroutine

 In different programming languages a subroutine may be called a procedure or a
subprogram.
 When a group of instructions are to be used several times to perform a same
function in a program, then we can write them as a separate subprogram called
subroutine or procedure.
 Definition: a group of instructions stored as a separate program in memory and it
is called from the main program whenever required is known as procedure.
 The concept of subroutine or procedure is mainly used to avoid repetition of
smaller programs (group of instructions).
 The procedures are written and assembled as separate program modules and
stored in memory.
 When procedure is called in the main program, the program control is transferred
to procedure and after executing the procedure the program control is transferred
back to main program.
 In 8086 processor, the instruction CALL is used to call a procedure in the main
program and the instruction RET is used to return the control to main program.
 This is illustrated in fig. 4.11.
 To define a procedure we are using PROC and ENDP assembler directives.
 The directive PROC indicates the beginning of the procedure and the directive
ENDP indicates the end of the procedure to the assembler.
 The directives PROC and ENDP must enclose the procedure code which defines
the subroutine.
 Note that the procedures must be defined within the code segment only.
 The following is the general form that shows the declaration of both the main
procedure and sub-procedure (subroutine).

Fig. 4.11
Main PROC
.
.
.
Main ENDP
SUB PROC
.
.
.
Sub ENDP
 Advantages:
o Procedures occupy less memory space.
o It saves the programmer’s time.
 Disadvantages:
o In procedures the program flow is interrupted.
o Takes more time to execute.
o The overhead time is required to call the procedure and return to the
calling program.
o Procedure needs the stack.
4.12 Explain CALL, RETURN instructions

 The group of instructions which are reusable in the program is called procedure.
 The concept of procedure is mainly used to avoid repetition of smaller programs.
 The 8086 microprocessor supports CALL and RET instructions for procedure call.
4.12.2.1 Procedure CALL
 The CALL instruction is used to transfer program control to a subroutine (or)
procedure.
 The CALL instruction performs two operations when it executes.
o First stores the address of instruction after CALL instruction on the stack.
o The second operation of CALL is to change contents of the instruction pointer
(IP) and some cases the contents of code segment (CS) register to contain
starting address of the procedure.
 There are two basic types of CALLs. These are:
 Near CALL
 Far CALL
Near CALL:
 If the call is to procedure in same code segment as the CALL instruction it is near
CALL.
 Near CALL is also called Intra segment (within a segment) CALL.
 When procedure is called by near CALL instruction the processor will push the
contents of IP on to stack.
 Then IP is loaded with the effective address of the procedure.
 Thus the program control is transferred to the starting address of the procedure
stored in the same code segment and so processor start executing of procedure
instructions.
 The address of a near call is two bytes long.
Far CALL
 If the call is to procedure in another code segment it is far CALL.
 Far CALL is also called as Inter segment (outside a segment) CALL.
 When procedure is called by far CALL instruction the processor will push the
contents of both CS and IP on to stack.
 Then the subroutine segment address is moved to CS and its offset is moved to IP.
 Thus the program control is transferred to the starting address of the called
procedure and so the processor starts executing the procedure instructions.
 The address of a far call is four bytes long.
4.12.2 Procedure RETURN
 The RET instruction is placed at the end of procedure to transfer program control
from the procedure back to the main program.
 RET instruction can be categorized into two types. These are:
 Near RET
 Far RET
Near RET:
 If procedure is defined as near, the execution of the RET replaces the IP with a
word from the top of the stack and increments SP.
 The word that is popped from the stack is the offset address of the instruction
following the CALL.
 Thus the program control is returned back to the main program.
Far RET:
 If a procedure is defined as far, the execution of RET instruction POPs two words
from the stack and places them into the registers IP and CS.
 Thus the program control is returned back to the main program.
4.12.3 Parameter Passing
 Procedures require input data or constants for their execution.
 The data or constants may be passed to procedure by main program.
 There are four ways to pass parameters to and from procedure:
o Using registers
o Using general memory
o Using pointers
o Using stack
*Note:
1. The Parameters that are used to transfer data to a procedure are known as
‘input parameters’.
2. The parameters used to transfer result from the procedure are known as
‘output parameters’.
3. The parameters used to transfer data in both directions are called input-output
parameters.

4.13 Explain Subroutine programming in 8086.

4.14 Give simple program using subroutine and parameters passing
4.14.1. Passing Parameters using Registers
In passing parameters using registers the data to be passed is stored in registers &
these registers are accessed in the procedure to process the data.
Example 1:
CODE SEGMENT Assembler directive.
Main Program
MOV AL, DATA Data to be passed is
loaded in the AL register.
CALL Pro_Name Call procedure Pro_Name.
CODE ENDS Assembler directive.
Pro_Name PROC NEAR
MOV INPUT, AL Procedure access the data
Procedure
from AL register.
RET Return back to main
program.
Pro_Name ENDP Assembler directive.
program.
Example 2:. Write an ALP for addition of two 16-bit numbers using parameters
passing through registers.
MOV AX, Data1 Load the first 16-bit data in AX register.

Main Program
MOV BX, data2 Load the second16-bit data in BX register.
CALL ADD Call procedure ADD.
MOV SUM, AX Store the sum in memory locations (Ex:

1104H & 1104H).

ADD PROC NEAR Procedure for addition.
Procedure for
ADD AX, BX Add the two data; sum will be in AX.
addition
RET Return back to main program.
ADD ENDP Assembler directive.
4.14.2. Passing Parameters using Memory
passing through registers.
MOV [1000], data2 Load the second16-bit data in memory
Main Program
locations 1000H and 1001H.

1104H & 1104H).
ADD AX, [1000] Add the contents of AX and memory Procedure for
location; sum will be in AX. addition

4.14.3. Passing Parameters using Pointer
passing through pointers.
Progra
Main

MOV BX, 1000H Memory pointer.
MOV [BX], Data2 Load the second 16-bit data in memory
location 1000H.
1104H & 1104H).
Procedure for
ADD AX, [BX] Add the contents of AX and memory
addition
location pointed by BX; sum will be in AX.

i) To find the factorial of the given number

Program 10: FACTORIAL OF 8-BIT DATA
Write an assembly language program to determine the factorial of 8-bit data.
Flow Chart:

Fig. 4.14
Program:
MOV AL, [SI] Get the data in AL.
MOV AH, 00H Initialize upper word of the

result as zero.
CMP AX, 0001H Check whether data is 01.
JNG STORE If data is 01, then store 01 as

factorial.
MOV CX, AX Set CX as count for number
of multiplications.
DEC CX Decrement the count.
MOV BX, AX Set the data as multiplier.
REPEAT: DEC BX Decrement the multiplier.

MUL BX Get the product1 (P1) in AX
and DX register.
PUSH AX Save lower word of product1
in stack.
PUSH DX Save upper word of product1
in stack.
MOV AX, BP
MUL BX Get the product2 (P2) in AX

and DX register.
POP DX Get the upper word of
product1 in DX register.
ADD AX, DX Get sum of lower word of P1
and Upper word of P2 in AX.
MOV BP, AX Set the sum as second word
of the result.
POP AX Set lower word of P1 as first
word of result.
LOOP REPEAT Repeat multiplication until
count is zero.
STORE: MOV [SI+1], AX Store the lower word of the
result in memory.

MOV [SI+3], BP Store the upper word of the

result in memory.
program.
Example 1:
Data Result
Input Data : 0BH Output data: 02611500H

5
Advanced microprocessors
OBJECTIVES
5.1 Give the features of 80286 microprocessor

5.2 Describe the architecture of 80286.
5.3 Explain operating modes of 80286
5.4 Describe memory management of 80286.
5.5 State the features of 80386
5.7 Explain the operating modes of 80386
5.8 Explain memory organization in 80386
5.9 Describe pipe lining.
5.10 Describe instruction level parallelism.
5.11 Compare RISC and CISC.
5.13 Describe the architecture of 80486
5.14 State the features of Pentium microprocessor
5.15 Compare 80286,386,486 and Pentium processors
5‐2 Advanced Microprocessors
5.1 Give the features of 80286 microprocessor

1. The Intel 80286 is a high performance 16-bit microprocessor and introduced in the
year 1982.
2. It is an advanced version of Intel 8086 microprocessor with memory management
and protection.
3. Because of memory management and protection capabilities, 80286 can be used
for multiuser and multitasking systems.
4. It has 24 address lines and 16 data lines. The address and data lines are completely
separate. They are not multiplexed (speeds up processing and simplifies
hardware).
5. It has 16MB (224) of physical memory.
6. It has 1GB (230) of virtual memory (by using memory management unit).
7. The operating frequency is 12 MHZ.
8. The 80286 is 6 times faster than 8086.
9. It is designed with CHMOS technology.
10. It is available in three IC packages:
 68 pin PLCC (Plastic Leaded Chip Carrier)
 68 pin LCC (Lead Less Chip Carrier)
 68 pin PGA (Pin Grid Array)
11. It is highly pipelined.
12. It contains four functional units. These are: Bus Unit (BU), Instruction Unit (IU),
Execution Unit (EU) and Address Unit (AU).
13. 80286 operating in two modes: Real Address Mode (RAM) and Protected Virtual
Address Mode (PVAM).
14. The 80286 was the first family member designed specifically for use as CPU in a
multiuser microcomputer.
15. The 80286 flag register contains 15 flags.
16. It contains of 8 general purpose registers (AX, BX, CX, DX, SI, DI, BP and SP) and
4 segments (CS, DS, ES and SS).

 Fig. 5.2 represents the functional block diagram of 80286.
 80286 microprocessor has four processing units:
1. Bus Unit(BU)
2. Instruction Unit(IU)
3. Execution Unit(EU)
Advanced Microprocessors 5‐3
4. Address Unit(AU)
*Note: All the four units work in parallel within the CPU.
Fig. 5.2
1. Bus Unit (BU)
1. The bus unit provides a 16-bit data bus, a 24-bit address bus and the signals
needed to control bus operations.
2. It performs bus operations such as memory and I/O read / write operations.

3. It has 6-bit pre-fetch queue, which pre-fetches the instructions up to six bytes and
places them in queue for the instruction unit.
4. This unit also supervises the data flow between processor (80286) and coprocessor
(match processor 80257) and vice-versa.
2. Instruction Unit (IU)
1. The instruction unit fully decodes up to three pre-fetched instructions and holds
them in a 3-byte instruction queue.
2. Thus the speed of 80286 is faster than 8086.
3. Execution Unit (EU)
1. The execution unit reads the decoded instructions from instruction queue
sequentially and executes them sequentially with the help of ALU and set of
registers available in it.
4. Address Unit (AU)
1. The function of this unit is to compute physical address to access the memory.
2. The computation of the physical address is depends upon the mode of operation
of the microprocessor.
3. In real address mode, the 80286 addresses 1MB (220) of physical memory. Hence in
this mode only A0 – A19 lines are used and A20 – A23 lines are ignored.
4. In protected virtual address mode, the 80286 addresses 16MB (224) physical
memory. Hence in this mode all the 24 address lines (A0 – A23) are used.
*Note: In PVAM, the AU operates as Memory Management Unit (MMU).
5.3 Explain operating modes of 80286

The 80286 operates in two modes:
1. Real Address Mode (RAM)
2. Protected Virtual Address Mode (PVAM)
1. Real Address Mode (RAM)
1. The 80286 microprocessor is operated in the Real Address Mode when the 80286 is
reset.
2. The 80286 microprocessor will remain in this mode, unless it is switched to
protected mode by the software.
3. In this mode it can access up to 1 MB of physical memory.
4. This mode is referred to as real address mode because the physical memory
address is generated simply by adding an offset (IP, BX, BP, SI, DI and SP) to a
segment base ((CS, DS, ES and SS) as in case of 8086.
5. The Real Address Mode is also called as physical memory address mode.

6. The working of 80286 in Real Address Mode is similar to that of 8086 in maximum
mode.
7. In this mode the 80286 will directly execute the 8086 machine code programs with
only minor modification.
8. The execution will be faster due to extensive pipelining and the improved
hardware in 80286.
9. In the Real Address Mode, the interrupt vector table of 80286 is organized in the
first 1K byte of memory starting from address 00000 H to 003FF H.
10. In this mode the addresses form FFFF0 H to FFFFF H are reserved for system
initialization.
11. In this mode after reset, the program execution starts from FFFF0 H.
12. This mode is usually used to initialize peripherals devices, load the main part of
the operating system from disk into memory and load some registers.
2. Protected Virtual Address Mode (PVAM)
1. The 80286 microprocessor enters into the protected virtual address mode from the
real address mode by setting the PE (Protection Enable) bit of Machine Status
Word (MSW).
2. The main features of Protected Virtual Address Mode are:
o Memory management,
o Virtual addressing,
o Memory protection mechanism,
o Task switching and interrupt processing.
3. In this mode, 80286 access 16MB of (From 000000 H to FFFFFF H) physical
memory and 1GB of virtual memory.
*Note: In this mode, memory larger than 1 MB can be accessed.
4. In this mode the physical address (24 bit) is generated by adding 24-bit segment
base address to 16-bit offset address
5. The segment base address is provided by the descriptors
6. The descriptor is a block of contiguous eight memory locations containing
information of a segment, like segment base address, segment limit, segment
type, privilege level, segment availability in physical memory.
5.3.1. Differences between Real Address Mode & Protected Virtual
Address Mode
Real Addressing Mode (RAM) Protected Virtual Address Mode (PVAM)
1. Upon reset, the 80286 operates 1. By setting PE bit of MSW, the 80286 entering
in real (physical) address mode. into PVAM.

2. In real address mode the 80286 2. In PVAM, the 80286 supports the concept of
acts as a fast 8086. virtual memory and memory management.
3. In this mode 80286 access only 3. In this mode 80286 access 16MB of physical
1MB of physical memory. memory and 1GB of virtual memory.
4. In this mode 20-bit physical 4. In this mode 24 bit physical address is
address is generated in the same generated by adding 24-bit base address of
way as that in 8086. the selected descriptor and the 16-bit offset.
5. In this mode all the memory 5. In this mode 80286 works with all of its
management and protection memory management and protection
mechanism are disabled. capabilities.
5.4 Describe memory management of 80286.

The memory management unit (MMU) of 80286 has two functions:
1. Converts the logical address into physical address.
2. It avoids the interference between users and operating systems. This feature
is called protection.
*Note:
1. The address used in programs is known as Logical Address.
2. The address required by the memory hardware is known as physical
address.
5.4.1. Conversion of Logical Address into Physical Address
 When the 80286 is switched to protected virtual mode. The virtual memory comes
in use.
 In 80286, the physical memory is 16MB and the virtual memory is 1GB.
 The each location of the virtual memory is represented by a 32-bit virtual address
(logical address).
 When a part of the program to be executed is transferred from secondary memory
to the physical memory, the Memory Management Unit computes the physical
address (translates the 32-bit virtual address to 24-bit physical address) where it
will be placed in the physical memory.
 The 32-bit virtual address or logical address consists two components, one is 16-
bit segment selector (upper) and second one is 16-bit offset (lower) as shown in
fig. 5.4.
o The 16-bit selector is used to fetch a descriptor from a descriptor table. The
descriptor provides segment base address, the privilege level of the
segment and some control bits.

o Out of 16-bits of a selector, 14 bits are address bits and 2 privilege-level bits.
Using 14 bits we can select any one of 16,384 (214) descriptors in the descriptor
table.
 Now the segment base address is added to 16-bit offset address to generate
the 24-bit physical address.
 The physical address generation in PAVM is shown in fig. 5.4
Fig. 5.4
*Note:
1. In 80286,
 The number of descriptors = 16KB
 The maximum size of the segment = 64 KB
 The virtual memory space = 16KB  64KB = 1GB.
Virtual Memory = No. of descriptors  Maximum size of the segment
2. The descriptor is a block of contiguous 8 memory locations (8  8 = 64bits). It
containing:
 Information of segment (segment base address, segment size and type).
 Descriptor type (Global Descriptor Table (GTD) & Local Descriptor Table
(LTD).
 Privilege level bits.
3. Since descriptor can define size of segment, the size of segment in 80286 is not
uniform as in 8086.
4. The size of the segment is from 1 KB to 64 KB.


1. The Intel 80386 is the logical extension of 8086 & 80286.
2. It is the first 32-bit microprocessor introduced by Intel Corporation in 1985.
3. 80386 is available in 132 PGA (Pin Grid Array) package.
4. It is designed with CHMOS III technology
5. It has 32-bit data bus.
6. It has 32-bit non-multiplexed address bus.
7. It has 4GB (232) of physical memory.
8. It supports 64TB (246) of virtual memory.
9. The operating clock frequencies of 80386 are 12.5 MHZ, 20 MHZ or 33 MHZ.
10. It contains six functional units (bus interface unit, execution unit, segment unit,
paging unit, instruction decode unit, code pre-fetch unit).
11. It has 16 - byte pre-fetch queue.
12. It has 4GB maximum segment size.
13. It has integrated memory management unit.
14. It has pipelined architecture i.e. it can perform instruction fetching, decoding,
execution and memory management function in parallel.
15. The major features of the 80386 are: multitasking, memory management and
software protection.
16. The 80386 can works in three modes:
Real address mode, Protected virtual address mode and virtual 8086 mode.
17. It has 8-general purpose 32-bit registers.
18. It contains 2,75,000 transistors on a single chip.
19. It requires single +5V D.C power supply for the operation.
20. It supports 8, 16, 32-bit data types.
21. It contains 129 basic instructions.
22. Intel 80386 microprocessor is commercially available in two versions (80386 SX &
80386DX). 80386 DX version is more powerful than the 80836SX version.
80386DX 80386SX
1. The first member in 80386 1. Low cost version of the 80386.
families.
2. 32-bit address bus. 2. 24-bit address bus.
3. 32-bit data bus. 3. 16-bit data bus.
4. Packaged in 132 pin ceramic 4. 100 pin flat package.
pin grid array (PGA).
5. 4GB of physical memory. 5. 16 MB of physical memory.


 The internal architecture of 80386 is divided into 6 functional units as shown in
fig. 4.3.
 These are:
2. Code Pre Fetch Unit (CPFU)
3. Instruction Decode Unit (IDU)
4. Execution Unit (EU)
5. Segment Unit (SU)
6. Paging Unit (PU)
Fig. 5.6
1. The bus interface unit generates signals for memory and I/O interface.
2. This unit provides a 32-bit data bus, 32-bit address bus and the signals needed to
control transfers over the bus.
3. The physical address of memory and I/O are output through bus interface unit.
2. Code Pre Fetch Unit (CPFU)
1. The function of this unit is that fetching of instructions from memory when bus
interface unit is free.
2. The code pre fetch unit consist a 16-byte pre fetch queue, in which fetched
instructions are stored.
*Note: A 16-byte pre fetch queue holds the pre fetched instruction bytes until the
decoder needs them.
3. Instruction Decode Unite (IDU)
1. The instruction decode unit takes instruction bytes from 16-byte pre fetch queue
and decodes them.
2. The decoded instructions are then stored in instruction queue in instruction
decode unit.
3. The instruction queue in decoded unit holds the three decoded instructions.
*Note: The queues in code pre-fetch and instruction decode units are FIFO (First In
First Out) queues.
4. Execution Unit
1. The execution unit read the decoded instructions from decode unit and processes
them.
2. The execution unit of 80386 consists the following sub units:
a) Control unit b) Data unit c) Protection test unit
3. The control unit consists of a ROM, which stores the micro codes and this unit
generates required control signals.
4. The data unit includes an ALU, a 64 bit barrel shifter and eight general purpose
registers.
The data unit performs the operations requested by the control unit.
The barrel shifter is used for fast shift, rotate, multiply and divide operations.
5. The protection test unit checks for segmentation violation under the control of the
microcode.
5. Segmentation Unit
1. The segmentation unit translates logical addresses into linear addresses at the
request of the execution unit.
2. The segmentation unit compares the effective address for the length limit
specified in the segment descriptor.
3. The segment unit adds the segment base and the effective address to generate
linear address.
4. Before calculation of linear address it also checks for access rights. The violation of
access rights causes a protection exception to be generated.
6. Paging Unit
1. When the 80386 paging mechanism is enabled, the paging unit translates linear
addresses generated by the segmentation unit or the code pre-fetch unit into
physical addresses.

2. If paging unit is not enabled, the physical address is the same as the linear
address, and no translation is necessary.
3. The paging unit gives physical address to the Bus Interface Unit to perform
memory and I/O accesses.
Fig. 5.6
5.7 Explain the operating modes of 80386

The 80386 microprocessor can be operated in three modes. These are:
1. Real Address Mode (Real mode)
2. Protected Virtual Address Mode (Protected Mode)
3. Virtual 8086 Mode (V86 Mode)
1. Real Mode
1. Real address mode or simply real mode is the simplest and most basic operating
mode that the 80386 supports.
2. Whenever the 80386 is reset or powered up it begins operating in real mode.
3. In the real mode 80386 works as fast 8086 with 32-bit registers and data types.
4. In this mode the processor 80386 can access 1 MB of physical memory with 20-bit
physical address just like as 8086.
5. Paging unit is disabled in real mode, and hence the real addresses are the same as
the physical addresses.
6. To form a physical memory address, appropriate segment registers contents (16-
bits) are shifted left by four positions and then added to the 16-bit offset address.
2. Protected Mode
1. The 80386 processor can switched to protected mode from real mode by setting
the PE (Protection Enable) bit.
2. In this mode the processor 80386 can run all the programs of 80286 and 8086
under the control of memory management and protection abilities of 80386.
3. In this mode the processor 80386 can access 4GB (232) of physical memory and
64TB (246) (Terra Bytes) of virtual memory per task.

3. V86 Mode
1. In this mode 80386 can go back and forth repeatedly between V86 mode and
protected mode at a fast speed.
2. The processor 80386 can switched to V86 mode from protected mode by setting
VM (Virtual mode) bit of flag register.
3. The VM bit may be reset to zero to pull back the 80386 into protected mode.
4. When entering into V86 mode the 80386 can execute an 8086 program. The
processor can then leave V86 mode and enter protected mode to execute an 80386
program.
5. In this mode the processor access 1MB of physical memory that may be anywhere
in 4GB address space of protected mode.
6. In this mode the paging mechanism and protection capabilities are available.
*Note:
1. Once 80386 enter the protected mode from real mode, it cannot return back to the
real mode without reset operation.
2. Paging unit may not be necessarily enabled in the virtual mode, but may be
needed to run the 8086 programs which require more than 1MB of memory for
memory management functions.
3. Protected mode vastly increases the linear address space to 4GB and allows the
running of virtual memory programs of size 64TB. It also provides sophisticated
memory management and protection mechanism.
5.8 Explain memory organization in 80386

1. The physical memory system of the 80386 is 4 GB in size.
2. Fig. 5.8 shows the organization of the 80386 physical memory systems.
3. The memory of 80386 is divided into four 8-bit wide memory banks, each
containing up to 1 GB of memory.
4. This 32-bit wide (4  8 = 32) memory organization allows bytes, words, or
double words of memory data to be accessed directly.
Fig. 5.8

5. The 80386 microprocessor transfers up to 32-bit data in a single memory or
machine cycle, whereas the early 8088 microprocessor requires four machine
cycles to accomplish the same transfer and the 8086 and 80286 require two
machine cycles.
6. The address generated to select any memory location in 80386 microprocessor is
the range from 00000000h to FFFFFFFFh.
7. In the 80386, the memory banks are accessed via four bank enable signals
BE3  BE0 .
8. The lower two address lines A1 and A0 are internally decoded to generate these
four bank enable signals BE3  BE0 .
9. A single byte to be accessed when one bank enable signal is activated by the
microprocessor.
10. A word to be accessed when two bank enable signals are activated by the
microprocessor.
11. A double word (32 bits) data to be accessed when all the four bank signals are
activated by the microprocessor.
12. In most cases, a word (16 bits) is addressed in bank 0 and, 1, or in bank 2 and 3.
13. Memory location 00000000h is in bank 0, location 00000001h is in bank 1,
location 00000002 is in bank 2, and location 00000003h is in bank 3.
5.9 Describe pipe lining.

1. Definition: Pipelining is the process of fetching the next instruction before the
current instruction is executed.
2. It is useful to speed up program execution.
3. A pipeline allows multiple instructions to be processed at the same time.
4. Example: Compare the three-instruction sequences as shown in figures. 5.9 & 5.9
Non-pipelined: On a non-pipelined machine, 9 clock cycles are needed for the
individual fetch (F), decode (D), and execute (E) cycles (see fig 5.9).
Pipelined: On a pipelined machine, where fetch, decode and execute operations
are performed in parallel.
Only five cycles are needed to execute the same three instructions (see fig 5.9).
The first instruction requires three cycles to complete. Additional instructions then
completes at a rate of one per cycles.
Fig. 5.9 Non-pipelined

Fig. 5.9 Pipelined
5.10 Describe instruction level parallelism.

1. We know that more than one clock cycles are involved in the instruction cycle.
2. These clock cycles are required to perform various steps in the instruction
execution.
3. These steps belong to various processing stages in the instruction cycle. These are:
 S1 – Fetch (F): Read instruction from the memory.
 S2 – Decode (D): Decode the op-code and fetch source operand (s) if necessary.
 S3 – Execute (E): Perform the operation specified by the instruction.
 S4 – Store (S): Store the result in the destination.
4. Usually, instruction is executed by performing above mentioned stages one after
the other.
5. When these stages for several instructions are performed simultaneously to
reduce overall processing time, the processing is called instruction pipelining.
6. Now consider the timing diagram for the 4 stage instruction pipeline as shown in
fig. 5.10.
Fig. 5.10
 As shown in fig. 5.10 instruction processing is divided into 4 stages hence the
name it is known as 4 stage instruction pipeline.
 The 4 stages are: fetch (F), decode (D), execute (E) and write (W). A separate
hardware unit is provided to perform each of these steps.

 The fig. 5.10shows 4 stages of execution of four subsequent instructions i.e. i, (i +
1), (i + 2) and (i + 3).
Clock cycle Operation
1st Clock Cycle (0 - 1)  ith instruction is fetched
2nd Clock Cycle (1 - 2)  ith instruction is decoded
 (i +1) instruction is fetched
3rd Clock Cycle (2 - 3)  ith instruction is executed
 (i +1) instruction is decoded
4th Clock Cycle (3 - 4)  ith instruction result is written
 (i +1) instruction is executed
 (i +2) instruction is decoded
 It may be noted that this process continued until the last instruction (i +3)
completed.
5.11 Compare RISC and CISC.

CISC RISC
1. Large number of instructions. 1. Small number of instructions.
2. CPU complexity is high. 2. CPU complexity is less.
3. Instructions are executed by micro 3. Instructions are executed by
program. hardware.
4. An instruction takes multiple clock 4. An instruction takes one or two clock
cycles. cycles.
5. Slower. 5. Faster.
6. Variable instruction lengths. 6. Uniform instructions lengths.
7. High cost. 7. Low cost.
8. Less number of general purpose 8. More number of general purpose
registers i.e. 8-10 registers. registers i.e. 32-35 registers.
9. Many addressing modes. 9. Few addressing modes.
10. Not pipelined. 10. Highly pipelined.
11. In addition to load and store 11. Only load/store instructions are used
instructions, memory access is possible to access memory.
with other instructions also.
12. Program size is small. 12. Program size is large.
13. Used mostly in PCs and in 13. Used mostly in workstations.
conventional main frames.
14. Clock speed is slow. 14. Clock speed is high.
15. These are not reliable. 15. High reliable.

 Basically this is an upgraded advanced version of 80386 and it was released in the year
1989.
 The important additional features of the 486 processor in comparison with the 386 processor
are as follows.
o Built in math coprocessor. In the 386 system, a math coprocessor is an external
device.
o 8K byte of code and data cache memory on the chip.
o Highly pipelined execution unit.
1. The 80486 is the first processor with an on-chip floating point unit.
2. The Intel 80486 is a 32-bit processor with high performance than 80386.
3. The architecture of 80486 = [Architecture of 80386 + Math coprocessor (80387) +
8 k byte cache memory] on a single chip.
4. It works 3 times faster than the combined operation of 80386 and 80387.
5. The five stage instruction pipeline allows the 80486 processor to execute many
instructions in one clock period.
6. It has a 32-bit data bus.
7. It has a 32-bit address bus.
8. It has 4GB physical memory and 64TB virtual memory.
9. It has 8K byte code and data cache, which speeds up the execution of
instructions.
10. 80486 is available in 168-pin PGA (Pin Grid Array) package.
11. It is fabricated using CHMOS-IV technology.
12. 80486 is a CISC processor.
13. It is currently available with 25MHZ, 33MHZ, 50MHZ, 66 MHZ and 100MHZ
clock.
14. It contains more than 1.2 million transistors.

5.13 Describe the architecture of 80486
Fig. 5.13
 The internal block diagram of Intel 80486 is shown in fig. 5.13.
 The major functional parts of Intel 80486 are:
1. Bus interface unit
2. Data processing unit

3. Memory management unit
4. Five stage instruction pipeline
5. 8KB cache memory unit
6. Floating point unit
1. The bus interface unit generates necessary signals for memory and I/O interface.
2. This unit also checks the parity during read operation, if there is any error it will
generates error signal.
2. Data Processing Unit (DPU)
1. The data processing unit consists of ALU, Barrel shifter and arrays of registers.
2. The data processing unit performs the operations requested by the control unit.
3. The barrel shifter is used for fast shift, rotate, multiply and divide operations.
3. Memory Management Unit (MMU)
1. The memory management unit consists of segmentation unit and paging unit.
2. This unit is also called as address unit, because this generates physical address to
access the memory.
4. Five Stage Instruction Pipeline (FSIP)
1. The 80486 processor has five stage instruction pipeline execution, which includes
a) Pre-fetch b) first decode c) second decode d) execute and e) write
back
2. Due to five stage pipeline, the 80486 processor can execute two instructions
simultaneously if execution of one instruction does not depend on the other
instruction.
5. 8KB Cache Memory Unit (CMU)
1. The 8KB cache memory can be used to store both code and data.
2. The cache memory contains static RAMs which are very fast as compared to the
dynamic RAMs.
6. Floating Point Unit (FPU)
1. The floating point unit performance the floating point operations.
2. Floating point operations could not be pipelined with any other floating point
operations.
5.14 State the features of Pentium microprocessor

1. A salient feature of Pentium is its superscalar, super pipelined architecture.
2. The superscalar architecture of the Pentium contains three independent
processing units:
 Floating point processor
 Two integer processing units labeled U and V by intel. This enhances the
speed of integer arithmetic of Pentium to charge extent.
3. It requires a power supply of +5V and 3.3A of current.
4. It can address up to 4GB of physical memory.
5. It has numeric coprocessor (or) math processor which is operates about five times
faster than the 80486 math processor.
6. The operating clock frequency varies from 60 to 100 HZ.
7. The Pentium contains 8K byte instruction cache and an 8K byte data cache.
8. The Pentium processor is packaged in a huge 237-Pin PGA (Pin Grid Array).
5.15 Compare 80286,386,486 and Pentium processors
Fig. 5.15
The internal block diagram of Intel Pentium microprocessor is shown in fig.5.15
The functional parts of Pentium are:
1. Core execution unit
2. Integer pipe line unit
3. Floating point pipe line unit

1. Core Execution Unit (CEU)
1. This unit contains code cache, data cache and branch predictions.
2. Pentium uses a separate 8 KB code cache and 8KB data cache as the super scalar
design.
3. Branch prediction demands more bandwidth than a unified cache.
4. The parallel execution of data memory reference requires simultaneous access for
loading & storing.
2. Integer Pipe Line Unit (IPLU)
1. It has 5 stages pre-fetch, instruction decode, address generation, execution & write
back stages.
 Pre-fetch: In the pre-fetch stage of the pipeline, the CPU fetches the instruction
from the instruction cache, which stores the instruction to be executed.
 Instruction decode: In this stage, the CPU decodes the instruction & generates
a control word.
 Address Generation: In this stage, the control word from the previous stage is
again decoded for final execution & CPU generates addresses for data memory
references.
 Execution: In the execution stage, the CPU executes the data operands.
 Write back: In this final stage, the CPU updates the registers contents (or) the
states in the flag register depending on the execution result.
3. Floating Point Unit (FPU)
1. There are three internal units add, divide and multiply. Therefore three types of
floating point operations can operate simultaneously within i.e. FPU can do
simultaneous addition, division and multiplication.
2. The FPU has an 8-stage pipeline.
3. In this processor, the first 3stages are identical to integer pipeline i.e. pre-fetch,
instruction decode and address generation. The next stages are operand fetch, first
execute, second execute, register write and error reporting stages.
*Note: The FPU of Pentium is up to ten times faster than the FPU of 80486 processor for
common operations including add, multiply and divide.
S.No. Parameter 80286 80386 80486 Pentium
1. Year of 1982 1985 1989 1993
introduction
2. No. of bits 16-bit 32-bit 32-bit 32-bit
process
3. Type of package 68 pin lead less 132 PGA 168 PGA 237 PGA
package
4. Process CHMOS CHMOS CHMOS BIMOS
Technology
5. Clock Rates 10 – 16 MHZ 12 - 40 16- 100 60- 100
MHZ MHZ MHZ
6. No. of address 24 bits 32 bits 32 bits 32 bits
lines
7. No. of data lines 16-bits 32-bits 32-bits 64-bits
8. Physical memory 16 MB 4 GB 4 GB 4 GB
9. Virtual memory 1 GB 64 TB 64 TB 64 TB
10. No. of caches Nil Nil One Two
11. Instruction No Yes Yes Yes
pipelining

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Chapter Name ……. Page.No

2. Architecture of 8086 ……. 2.1 – 2.43

3. Instruction set of 8086 ……. 3.1 – 3.50

4. Programming with 8086 ……. 4.1 – 4.49

5. Introduction to Advanced microprocessors ……. 5.1 – 5.21

1.1 Draw and explain the functional block diagram of 8085

1.1 Draw and explain the functional block diagram of 8085

 The fig. 1.1 shows the functional block diagram of 8085.

Maanya’s M.G.B Publications Microprocessors

1. Arithmetic and logic unit group

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Fig. 1.1(a) : Block diagram of 8085 (additional fig)

1.2 List the features of 8085 microprocessor

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1.3 Explain multiplexing of Address and Data Bus

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1.4 List different registers in 8085 and state their function.

The fig. 1.4(a) shows Register structure of 8085

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1.5 Draw the pin out diagram of 8085

2 Higher order address bus A15 - A8

3 Multiplexed address/data Bus AD7 - AD0

4 Control & status signals RD , WR , ALE, S0, S1,IO/ M ,

5 Serial I/O ports SID, SOD

Group 1: Power supply and frequency signals

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INTR (Input) Interrupt Request: This is used as a general purpose interrupt.

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1.6 Explain the terms operation code, operand and illustrate

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1.7 Define fetch cycle, execution cycle and instruction cycle

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2. Classification of Instructions Based on Size

1-byte 2-byte 3-byte

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Operation (C200H)  (A)

Operation (A)  (C100H)

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Description The content of memory location whose address is C100H is copied to

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1.9 Draw the timing diagrams of the above instructions, and

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