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Co Po Pso
Co Po Pso
Co Po Pso
Bloom’s
CO’s Statement Knowledge
Level (KL)
KEC072.1 Express the concept of VLSI design and CMOS circuits and delay study. L2
KEC072.5 Interpret faults in digital circuits, Fault Models and various Testing L3
Methodologies.
CO Mapping with PO & PSO
KEC 072.1 3 2 2 1 2 1
KEC 072.2 2 2 3 1 1 1 1 2 1
KEC 072.3 3 2 1 1 1 1 2 2 1
KEC 072.4 2 1 1 1 1 2 1 1
KEC 072.5 1 1 1 1 1 1 1 1
Average 2.20 1.60 1.60 1.00 1.00 1.00 1.40 1.60 1.00
3: Highly Correlated
2: Moderately Correlated
1: Weakly Correlated
Blank : No Correlation