1-Design an array multiplier showing its all stages to perform multiplication of two 4-bits

binary numbers
Let us consider two unsigned 4-bit numbers multiplication in which the multiplicand, A is
equal to A3A2 A1A0 and the multiplier B is equal to B3B2B1B0. The partial products are
produced depending on each multiplier bit multiplied by the multiplicand.
Each partial product consists of four product terms and these are shifted to the left relative to
the previous partial product as shown in figure. All these partial products are added to
produce the 8 bit product.

The logic circuit for the 4× 4 binary multiplications can be implemented by using three
binary full adders along with AND gates. Above production draw using AND gates.
2-Draw a flowchart for performing floating point addition and subtraction operations.
3-Comparison between Restoring and Non-Restoring Division algorithm.

4- Write a procedure to add two IEEE single precision floating point numbers. Each number
is represented by a 32- element Boolean array.
In IEEE754 first bit is sign which is 1 for both hence both are negative. next eight bits are for
exponent i.e. 0b01111101 for a and 0b10000101 which correspond to 125 and 133 in
decimal. These exponents have a offset of 127 so actual exponents are 125-127=-2 and 133-
127=6
• Rest bits are mantissa and the actual floating point number is 1.mantissa x
2^exponent where 1.mantissa is in binary. So our numbers
are 1.00101010100101110110001 x 2^-2 and 1.01000101100001011100001 x
2^6

For adding we make the exponent same (the larger one, i.e. 6), hence we
have 1.00101010100101110110001 x 2^-2 + 1.01000101100001011100001 x 2^6 =
0.0000000100101010100101110110001 x 2^6 + 1.01000101100001011100001 x 2^6 = ...

5-Hardware implementation of Booths algorithm.

Booth’s algorithm
1. Multiplier and multiplicand are placed in the Q and M register respectively.
2. Result for this will be stored in the AC and Q registers.
3. Initially, AC and Q-1 register will be 0.
4. Multiplication of a number is done in a cycle.
5. A 1-bit register Q-1 is placed right of the least significant bit Q0 of the register Q.
6. In each of the cycle, Q0 and Q-1 bits will be checked.
i. If Q0 and Q-1 are 11 or 00 then the bits of AC, Q and Q-1 are shifted to the right by 1
bit.
ii. If the value is shown 01 then multiplicand is added to AC. After addition, AC, Q0, Q-
1 register are shifted to the right by 1 bit.
iii. If the value is shown 10 then multiplicand is subtracted from AC. After subtraction
AC, Q0, Q-1 register is shifted to the right by 1 bit.