Logic and Digital Systems

Haroon Chughtai
Logic and
Digital Systems
1. Boolean Logic, Gates & Devices
2. Assembly & Computers
Haroon Chughtai Logic and Digital Systems 17/04/2013
Contents
1.1 Digital Vs. Analogue ............................................................................................................... 7
Advantages of Digital Systems ............................................................................................................ 7
Disadvantages of Digital Systems ....................................................................................................... 7
Basic Logic Principles........................................................................................................................... 7
1.2 Logic Devices .......................................................................................................................... 8
Relays .................................................................................................................................................. 8
Thermionic Valves ............................................................................................................................... 8
Transistors ........................................................................................................................................... 8
Use as Switches ............................................................................................................................... 8
CMOS FET ........................................................................................................................................ 8
1.3 Boolean Logic and Logic Gates ................................................................................................ 9
Boolean Values.................................................................................................................................... 9
Logic Gates .......................................................................................................................................... 9
Truth Tables .................................................................................................................................... 9
Boolean Operators and Gates ............................................................................................................. 9
OR Gate ........................................................................................................................................... 9
AND Gate......................................................................................................................................... 9
NOT Gate ......................................................................................................................................... 9
XOR Gate ....................................................................................................................................... 10
NAND, NOR and XNOR .................................................................................................................. 10
Multi-Input Gates .............................................................................................................................. 11
Boolean Relationships and Forms..................................................................................................... 11
De Morgan’s Theorem .................................................................................................................. 11
Laws of Boolean Algebra ............................................................................................................... 11
Rules of Boolean Algebra .............................................................................................................. 11
Sum of Products (SOP) Form ......................................................................................................... 12
Simplification and Minimisation ....................................................................................................... 13
Minimisation by Boolean Algebra ................................................................................................. 13
Minimisation by Karnaugh Maps .................................................................................................. 13
1.4 Binary Arithmetic ................................................................................................................. 15
Binary Number System ..................................................................................................................... 15
Integer and Fractional Parts .......................................................................................................... 15
Conversion: Decimal to Binary ...................................................................................................... 15
2
Some Terminology ........................................................................................................................ 15

Binary Addition ................................................................................................................................. 15
Half Adder ..................................................................................................................................... 16
Full Adder ...................................................................................................................................... 16
Multi-bit Full Adder ....................................................................................................................... 16
Binary Subtraction and Signed Numbers .......................................................................................... 17
Representing Negative Binary Numbers: 2’s Complement .......................................................... 17
Signed Addition ............................................................................................................................. 17
Inverting Signed Binary Numbers ................................................................................................. 17
Binary Subtraction......................................................................................................................... 18
Sign Extension ............................................................................................................................... 18
Subtraction Machine ..................................................................................................................... 18
Summary of Unsigned and Signed Operation of an Adder Circuit ................................................... 18
1.5 Sequential Logic ................................................................................................................... 19
Basic Bistable Circuit ......................................................................................................................... 19
SET-RESET Latches............................................................................................................................. 19
NAND S-R Latch ............................................................................................................................. 19
NOR S-R Latch ............................................................................................................................... 20
Application: Switch Denouncing ................................................................................................... 20
Transparent Latch (Gated D Latch) ................................................................................................... 20
D Flip-Flop ......................................................................................................................................... 21
Divide-by-2 Circuit......................................................................................................................... 21
Ripple Counters ................................................................................................................................. 21
Ripple Down-Counter.................................................................................................................... 21
Ripple Up-Counter ........................................................................................................................ 21
Delays and Glitches in Ripple Counters ........................................................................................ 22
Decade Ripple Counter ................................................................................................................. 22
The J-K Flip-Flop ................................................................................................................................ 23
Versatility of the J-K Flip-Flop ....................................................................................................... 23
Synchronous Counter........................................................................................................................ 23
Summary: Synchronous and Asynchronous Sequential Logic ...................................................... 24
Data Registers ................................................................................................................................... 24
Shift Registers ............................................................................................................................... 24
Binary Multiplication ..................................................................................................................... 25
3
Monostable Flip-Flop ........................................................................................................................ 25

1.6 Multiplexers ......................................................................................................................... 26
MUXs for Logic .............................................................................................................................. 26
Demultiplexers (DMUX) ................................................................................................................ 26
MUX/DMUX Pairs .......................................................................................................................... 27
1.7 Memory Devices and Programmable Logic Devices ............................................................... 28
Read Only Memory (ROM)................................................................................................................ 28
ROM Cell ....................................................................................................................................... 28
Implementing Logic with PROM ................................................................................................... 29
Programmable Logic Devices ............................................................................................................ 29
PALs ............................................................................................................................................... 29
EPLDs ............................................................................................................................................. 29
Summary of Programmable Logic Devices ....................................................................................... 30
Timing Hazards in PLDs ..................................................................................................................... 30
Avoiding Timing Hazards ............................................................................................................... 30
RAM Devices ..................................................................................................................................... 30
Types of RAM Devices ................................................................................................................... 30
Flash Memory ................................................................................................................................... 31
Memory Devices Summary ............................................................................................................... 31
7 Segment Displays ........................................................................................................................... 32
1.8 Application: Heart Rate Metre .............................................................................................. 33
The Challenge.................................................................................................................................... 33
Circuit Design .................................................................................................................................... 33
Timing Diagram ................................................................................................................................. 34
System Accuracy ............................................................................................................................... 34
1.9 Other Notations for Binary Numbers..................................................................................... 35
Hexadecimal Notation ...................................................................................................................... 35
Octal Notation ................................................................................................................................... 35
ASCII .................................................................................................................................................. 35
2.1 Introduction to Microprocessors ........................................................................................... 36
Definition of a Computer .................................................................................................................. 36
Structure of a Computer ................................................................................................................... 36
Overview of Operation.................................................................................................................. 36
Microprocessor/CPU Structure ......................................................................................................... 36
4
Arithmetic Logic Unit .................................................................................................................... 37

Register Array................................................................................................................................ 37
Control Unit................................................................................................................................... 37
Internal Bus ................................................................................................................................... 37
Basic Microprocessor Operation....................................................................................................... 38
Example Operation ....................................................................................................................... 38
Opcodes and Operands................................................................................................................. 38
Program Actions............................................................................................................................ 39
Programming .................................................................................................................................... 39
Machine Code ............................................................................................................................... 39
Assembly Code .............................................................................................................................. 40
Programming Pathways ................................................................................................................ 41
Advantages of Assembly ............................................................................................................... 41
2.2 Assembly Programming ........................................................................................................ 42
Addressing Modes............................................................................................................................. 42
Register Addressing....................................................................................................................... 42
Immediate Addressing, # .............................................................................................................. 42
Extended Addressing .................................................................................................................... 42
6809 Instructions .............................................................................................................................. 42
Data Transfer ................................................................................................................................ 42
Arithmetic and Logical .................................................................................................................. 43
Stack .............................................................................................................................................. 43
Jumps and Branches ..................................................................................................................... 44
Counting Loop Example .................................................................................................................... 44
Subroutines ....................................................................................................................................... 45
How JSR and RTS Work ................................................................................................................. 45
Considerations .............................................................................................................................. 46
2.3 Data I/O ............................................................................................................................... 47
The Peripheral Interface Adaptor (PIA) ............................................................................................ 47
Example ......................................................................................................................................... 47
Getting the Input Value................................................................................................................. 47
Problem with Polling ..................................................................................................................... 48
Interrupt-Driven I/O .......................................................................................................................... 48
Interrupt Mechanism .................................................................................................................... 48
5
Interrupt Service Subroutine ........................................................................................................ 48

Interrupt Vectors........................................................................................................................... 49
Direct Memory Access (DMA) ........................................................................................................... 49
Serial I/O ........................................................................................................................................... 50
RS-232 Serial Transfer ................................................................................................................... 50
USB ................................................................................................................................................ 50
2.4 Digital-Analogue Interconversion and Pentium 386 ............................................................... 51
Digital to Analogue............................................................................................................................ 51
Analogue to Digital............................................................................................................................ 51
Digital Ramp ADC .......................................................................................................................... 51
Quantisation Error ............................................................................................................................ 52
Pentium 386 ...................................................................................................................................... 52
2.5 The Operating System .......................................................................................................... 53
Overview ........................................................................................................................................... 53
Structure ........................................................................................................................................... 53
Processes........................................................................................................................................... 53
Fate of Processes .......................................................................................................................... 54
OS Multitasking ................................................................................................................................. 54
OS File Organisation .......................................................................................................................... 54
Disk File Structures........................................................................................................................ 54
6
1.1 Digital Vs. Analogue

 Analogue signals represent physical events or information as a continuously
variable voltage
o This is known as a signal
 Digital signals represent information as a sequence of distinct voltage levels
o Binary systems do this with two states: HIGH and LOW
o Information is represented by the order and duration of the voltage
levels
o Logic circuits deal with signals that vary abruptly between two defined
levels
Advantages of Digital Systems

 Known level of accuracy throughout the system
 Reliable, because more immune to
o electrical interference
o temperature and humidity
o component ageing
 Can introduce “intelligence” and improve communication with the user
 Can change the design easily (eg. to add new functions)
Disadvantages of Digital Systems

 Circuits are more complex/have more wires
 Increased cost of manufacture
o Complexity built into standard modules
o Falling cost of chips
Basic Logic Principles

 There are three basic logical operations: OR, AND & NOT

7
1.2 Logic Devices
Relays
 Electromagnetic device
 Allows current through a coil to
close one or more independent set
of switch contacts
 Can be NO or NC
 Bulky, slow (100 us) and unreliable
 Power hungry
Thermionic Valves
 Faster (10 us)
 Large and hot
 Unreliable
Transistors
 Fast (10 ns)
 Very small (microns), allowing integrated chips
 Very reliable
Use as Switches
 Transistors are 3-terminal
devices
 An input voltage applied to the
control terminal causes a
conducting path between the
other 2 terminals to be closed
(ON) or opened (OFF)
CMOS FET
 Current flows between two contact electrodes, the source and the drain, via a
pathway known as a channel.
o Above the channel is a further electrode, the gate.
 Field applied across an insulating layer between the gate and the substrate can
be made to control the resistivity of the channel.
o So the source-drain current may be passed or blocked at will
o The device acts as a switch.
 Different types of CMOS transistors exist.
o N-channel FETs operate via flow of electrons
 Output is HIGH when input is HIGH (and vice-versa)
o P-channel FETs operate using
holes
 Output is HIGH when
input is LOW (and vice-
versa)
8
1.3 Boolean Logic and Logic Gates

Boolean Values
 In Boolean logic there are only two possible values
o 1 or TRUE to represent HIGH or ON
o 0 or FALSE to represent LOW or OFF
Logic Gates
 Logic gates are electronic circuits constructed from transistors
o One or more input wires
o One output wire
 The voltage on the output depends on the input
o How it depends is based by the logical function performed by the internal
circuitry
 To analyse a circuit we presume every input is either HIGH or LOW
Truth Tables
 A circuit’s behaviour can be described concisely by tabulating the output
values for every possible combination of input values
o Examples below
Boolean Operators and Gates

OR Gate
 Q is HIGH if input A OR input B is HIGH (or both)
o i.e. Q = 1 if A = 1
OR B = 1 (or
both)
 So OUT= A OR B
represented by the shorthand
o Note that is the Boolean operator AND, not plus
 The 1 symbol inside means that 1 or more inputs must be 1 to make Q take the
value 1
AND Gate
 OUT = 1 only if A = 1
AND B = 1 at the same
time
o In Boolean
algebra:
NOT Gate
 Here, when A is HIGH
the lower transistor
“switch” closes, causing
the output to go LOW, being effectively connected to 0 volts.
o i.e. when A is HIGH, OUT is LOW
 When A is LOW, the output is at voltage as the upper transistor closes.
o When A is LOW, OUT is HIGH.
 So OUT is the opposite (inverse) of A
 In Boolean algebra: ̅
9
XOR Gate
 Takes 2 inputs, and
generates an output which is
1 if either A or B is 1 but
not both.
o This is called the exclusive-OR (XOR) function.

NAND, NOR and XNOR
 AND, OR and XOR with output inversions
 NAND and NOR gates are versatile as they can be used to implement all other
Boolean operations:
o They are functionally complete
NAND gate Inverter
 Connecting the two inputs of a NAND creates a NOT gate
o This can be used to create other NAND only gates
NAND gate OR
 This arrangement demonstrates
how AND functions can be
converted to OR functions
o By inverting the inputs and
putting them through a
NAND gate we get OR
functionality
o This is known as De
Morgan’s Theorem (see
below)
Using NANDs
10
Multi-Input Gates
 The number of potential inputs depends on the gate:
o OR and AND gates (and NOR and NAND) can have any number of inputs
o XOR and XNOR gates can have only two inputs
o The NOT gate (inverter) has only one input
 For the multi-input gates, the Truth Table is constructed using a separate
column for each input.
o Each additional input doubles the number of possible combinations
of 1 or 0 states – each combination occupies one row of the table
o Therefore for N inputs, there will be rows
Boolean Relationships and Forms

De Morgan’s Theorem
 De Morgan’s Theorem states that:
o ̅ ̅ ̅̅̅̅̅̅̅̅
 To change from the OR form to the AND form you break the bar and change
operations
o Invert the variables, change the operator and invert the group
Laws of Boolean Algebra
 Commutative Law
o Order of the variables makes no difference
o
o
 Associative Law
o Grouping of variables makes no difference
o ( ) ( )
o ( ) ( )
 Distributive Law
o The operator outside the bracket operates on all variables inside the
bracket
o ( )
o ( ) ( )( )
Rules of Boolean Algebra
1.
o Variable ORed with 0 is always the variable
2.
o Variable ORed with 1 is always 1
3.
o Variable ANDed with 0 is always 0
4.
o Variable ANDed with 1 is always the variable
5.
o Variable ORed with itself is always the variable
6. ̅
o Variable ORed with its complement is always 1
7.
o Variable ANDed with itself is always the variable
11
8. ̅
o Variable ANDed with its complement is always 0
9. ̿
o Double complement of a variable is always the variable
10.
o Can be proved by applying the distributive law, rule 2 and rule 4
 ( )
11. ̅
o ̅ ( ) ̅ ( ) ̅ ̅ ̅
( ̅ )( ) ( )
Sum of Products (SOP) Form
 When two or more product terms are
summed by Boolean addition (OR) the
resulting expression is a sum-of-products
(SOP)
o E.g.,
̅ ̅ ̅ ̅
o Can be directly translated into gates
but may not be the most efficient
design
 E.g. ( )
 First requires 3 gates but second requires 2
Canonical Form: Standard SOP Form
 A standard (or canonical) SOP expression is one in which all the variables in
the domain appear in each product term in the expression
o E.g.: (̅ ) ( ̅ ) ( )
o Generally: ( ) ̅ ̅ ̅ ̅
 In canonical SOP each product term is known as a minterm
 Not efficient, but sometimes useful in analysis and design
o E.g. truth table construction and Karnaugh map simplification method
Converting SOP to Canonical SOP
 An SOP expression can be forced into
canonical form by ANDing the incomplete
terms with terms of the form ̅ where X
is the missing variable
Converting Canonical SOP to Truth Table Format
 A SOP is equal to 1 if any of the product
terms is equal to 1
o So the output is 1 when any minterm is
represented in the table
 Where each variable
̅
 can be written as the sum of row numbers
having TRUE minterms ∑( )
12
Simplification and Minimisation

 To minimise the cost of implementation we must minimise the number of
operations needed (gates).
 Reducing the number of gates also increases the speed of operation.
Minimisation by Boolean Algebra
 Make use of relationships and theorems to simplify Boolean expressions:
o Perform algebraic manipulation resulting in reduced complexity
 3 things to try:
o Grouping
 For example by the absorption rule
o Multiplication by redundant variables such as ( ̅)
 This does not change the
logic but may enable
minimisation by grouping
o De Morgan’s theorem
 Expressions containing several inversions stacked one upon the
other may often by simplified by applying DeMorgan's
Theorem.
 DeMorgan's Theorem
"unwraps" the
multiple inversion
 Aim to reduce the
number of different
operators present
Minimisation by Karnaugh Maps
 Karnaugh maps are a graphical method of minimisation
o Grid of squares
o Each square represents one minterm
o Only one variable changes between adjacent
squares
 Minterms ordered according to Gray code
o Squares on edges are considered adjacent to
squares on opposite edges
Filling out a Karnaugh Map
 Write the Boolean expression in SOP form
 For each product term, write a 1 in all the
squares which are included in the expression, and
write 0 everywhere else
Simplifying the SOP
 Minimisation is done by spotting patterns of 1's and 0's
o Simple theorems are then used to simplify the Boolean description of the
patterns
 If there are pairs of adjacent 1's
o Remember that adjacent squares differ by only one variable
o Hence the combination of 2 adjacent squares has the form ( ̅)
 This can be simplified (from before) to just P
13
 Here the adjacent squares differ only in A so

can be combined to just BC
o Indicated by ringing adjacent squares
Grouping the 1s
1. A group must contain 1, 2, 4, 8 or 16 cells
2. Each cell in a group must be adjacent to one or more cells in that group
 But not all cells in the group have to be adjacent to each other
3. Always include the largest possible
number of 1s in a group in accordance
with rule 1
4. Each 1 on the map must be included in
at least one group
 The 1s already in a group can be
included in another group as
long as the overlapping groups 𝐴𝐵 𝐶̅ 𝐷 ̅
𝐵𝐷 𝐴𝐵𝐶
include non-common 1s
Don’t Care Conditions
 In certain cases some of the minterms may never occur or it may not matter
what happens if they do
 In such cases we fill in the Karnaugh
map with an X meaning don't care
 When minimising, an X is like a "joker"
 X can be 0 or 1 - whatever helps
best with the minimisation
Determining the Minimum SOP expression
1. Each group of cells containing 1s creates one product term composed of all
the variables that occur in only one form
 Variables that occur both uncomplemented and complemented
within the group are eliminated
2. When all the minimum product terms are derived from the map they are
summed to form the minimum SOP expression
14
1.4 Binary Arithmetic

 Binary logic circuits are not only useful for making controllers.
o The binary system can also represent numbers of any magnitude.
 Logic circuits can therefore be realised which will perform arithmetical
operations on these binary numbers.
o The principle behind almost all digital calculators and computers.
Binary Number System

 Uses just 2 symbols: 0 and 1
o Example: 10011 in binary is:
 In each position we have a BInary digiT (BIT)

o The right hand digit is the Least Significant Bit (LSB)
o The highest number that we can represent with N digits is 2N-1
Integer and Fractional Parts
 Binary numbers can contain fractional
parts as well as integer parts
 This 8-bit number is in Q3 format
o Meaning: it has 3 bits after the
binary point
 Beware of quantisation error
Conversion: Decimal to Binary

 Simply do repeated division by 2
o The remainders are the
BITs starting from the LSB
Some Terminology
 Some terms commonly used in computing are:
o FLAG: a binary number having only one bit
o NIBBLE: a binary number having 4 bits
o BYTE: a binary number having 8 bits
o WORD: a number having 16 or more bits
Binary Addition
 Looking at each column in turn, we see that the rules are:
o 0 + 1 = 1, carry out = 0
o 1 + 0 = 1, carry out = 0
o 1 + 1 = 0, carry out = 1
o (and 0 + 0 = 0 , carry out = 0)
 We can write these rules as a truth table:
o Clearly and
15
Half Adder
 This can be used to construct a half-adder
 The half adder will generate the Sum and Carry-out for one column of an
addition sum.
 However, it does not allow for a possible Carry-in from a previous column.
o To do this, we must use TWO half-adders: one to form the sum of A
and B, then another to add any carry-in to this intermediate sum.
 If EITHER of the two additions generates a carry-out, we must indicate that
fact by setting the final Carry-out to 1.
o The total circuit is called a Full Adder.
Full Adder
Multi-bit Full Adder

 The Full Adder performs the
complete add-with-carry
operation for one column (bit) of
a binary sum.
 Therefore to add two numbers of N
bits each, a row of N full adders
would be required.
o The result would need
(N+1) bits in general in case
of overflow
 This is catered for by
the C_OUT being the MSB
 For example, to add two numbers A and B, each up to 15,
o each number has 4 bits, so we'd need 4 full-adders:
16
Binary Subtraction and Signed Numbers

 We could work out a different truth table and logic circuit to do binary
subtraction
o More sensible to use our existing array of full-adders to do a modified
form of binary addition:
o i.e. 43 SUB 28 = 43 ADD (-28)
 So we need a method of representing negative numbers.
Representing Negative Binary Numbers: 2’s Complement
 2’s complement is a common method to represent negative numbers:
o Uses half the possibilities for positive numbers and half for negative
numbers
o To achieve this, let the MSB have a
NEGATIVE weighting
 Construction of 2's Complement Numbers
o 4-bit examples:
 Note that:
o Signed numbers are positive if the MSB is 0
o Signed numbers are negative if the MSB is 1
o MSB is often called the "Sign Bit"
 Positive signed numbers have same bit pattern as positive
unsigned numbers
o Same ideas apply to any number of bits.
 e.g. for 8 bit numbers, the MSB has a weighting of -128
Signed Addition
 The same hardware can be used for 2's complement
signed numbers as for unsigned numbers
o Main advantage of 2's complement form
 Consider 4 bit numbers:
o Adder circuitry will "think" the negative
numbers are 16 greater than they actually
are
 But if we take only the 4 LSBs of the result (i.e.
IGNORE the carry-out of the MSB) then the answer will be correct providing
it is within the range: -8 to +7.
 To add two N-bit signed numbers without the risk of overflow (which will
give wrong answers), we need to:
o Sign extend to N+1 bits
o Use an N+1 bit adder
Inverting Signed Binary Numbers
 Inverting all the bits of a 2's complement number X gives:
o -X-1 since adding it back onto X gives -1
 Hence to multiply a signed number by -1 (ie. negate it):
o First invert all the bits
o Then add 1
 Exception:
o Doesn’t work for the maximum negative number
o e.g. doesn't work for -128 in a 8-bit system
17
Binary Subtraction
 ( )
o Now
o So -
o And
 Therefore ( )
o
o Note that the carry out of the MSB has been discarded so the binary
word is the same length as the inputs
Sign Extension
Sometimes we need to extend a number to have more bits:
 In Decimal:
o Converting 12 into a 4 digit number gives 0012
o We add 0's to the left-hand side
 In Unsigned binary:
o Converting 0011 into an 8 bit number gives 00000011
o We add 0's to the left-hand side
 In Signed binary we must duplicate the sign bit (MSB):
o Converting 0011 into 8 bits gives 00000011 (duplicate the 0 MSB)
o Converting 1011 into 8 bits gives 11111011 (duplicate the 1 MSB)
o Called "Sign Extension”
Subtraction Machine
 We found that A SUB B = (A ADD B ) ADD 1
o This is very easy to implement on our array of full-adders
 We just have to pass all of the B-input bits through inverters,
 Then we must set Carry-in to
a 1 on the least significant
full-adder (remember that for
addition it was set to 0)
 A practical arithmetic processor has a
single control input that switches the B-
inverters in or out as required.
o One way to do this is to use XOR
gates as controllable inverters:
 If B' = U XOR B, then B’ = B
when U is LOW, and B' = B
when U is HIGH
Summary of Unsigned and Signed Operation of an Adder Circuit
18
1.5 Sequential Logic

 The gate circuits considered so far are known as Combinational Logic circuits
o This is because their outputs are formed from some combination of
their present inputs
o Combinational circuits do not have any memory.
 Another class of circuits are called Sequential circuits
o Their outputs depend upon the past history of their inputs
o Sequential circuits therefore exhibit memory properties.
Basic Bistable Circuit

 The simplest way of making a circuit have memory
is to use positive feedback from output to input:
 Here the input signal is inverted twice and fed
back to the output.
o This makes the circuit have two stable
states:
 X high and Y low, or X low and Y high.
SET-RESET Latches
NAND S-R Latch
 If we put NANDs instead of the inverters, we can
use the two spare inputs to force the bistable
circuit into either of its two stable states:
1. Initially both ̅ and ̅ are high.
 X and Y are unknown.
2. A low-going pulse on S will INPUTS OUTPUTS Comments
̅ ̅ ̅
force X high, by the NAND
0 0 1 1 Invalid
action. 0 1 1 0 SET
 This is defined as 1 0 0 1 RESET
SETTING the latch. 1 1 NC NC No change:
3. This high X is fed back to the latch remains in previous condition
input of the other NAND gate (unknown initially)
 Since R is normally high, that will cause Y to go low.
4. This low at Y is fed back to the first NAND gate, reinforcing the high at X
regardless of what now happens at the S input.
 Thus once the latch is SET, any more pulses at the S input will have no
further effect.
5. Once it is set, the only way to change the state of the latch is to assert a low-
going pulse at the R input
 This will force Y high, and hence X low, thereby CLEARING the latch.
 Once the latch is cleared, subsequent pulses at the R input will have no
further effect.
6. If both S and R are taken low at the same time, both X and Y outputs will go
high,
 Because both NANDs will each have one low input.
 However, this is an unstable state and will revert.
7. In the stable states, Y is normally the inverse of X
 The two outputs are therefore called and ̅
19
Active-Low Inputs
 Because ̅ and ̅ produce their effect when they
are taken from high to low, they are called
active-low inputs.
o To show this, they have half-arrowheads
on the logic symbol.
NOR S-R Latch
 An S-R Latch can also be made using NOR gates.
 In this case the inputs will set or clear the latch
when they are taken from a low to a high state
o So they are active-high inputs.
 They are shown without the half-arrowheads on the
logic symbol.
o Also their names do not have bars above them
Application: Switch Denouncing
 A common application for S-R latches is in cleaning up multiple pulses which
are often obtained from a mechanical switch or push button
o This is because the spring contacts bounce rapidly several times when the
switch is pressed.
 The SR latch gives an output which changes firmly from one state to the
other and stays in the new state until a different pushbutton is pressed.
o This makes the operation of a control panel much more reliable.
Transparent Latch (Gated D Latch)

 Often necessary for a circuit to store the current value
of a particular signal for use at some future time.
o Two circuits which can do this are the
Transparent (/Gated D) Latch and the D Flip-
flop.
 For the Transparent Latch: INPUTS OUTPUTS Comments
o EN is the ENABLE input ̅
o When EN=1, Q=DATA 0 1 0 1 RESET
o When EN=0, Q=Q0 1 1 1 0 SET
 DATA has no effect X 0 ̅ No change from previous output
20
D Flip-Flop
 Similar to the Transparent Latch but the control input is
called CLOCK instead of ENABLE.
o The CLOCK input is edge-triggered
 Q takes on the sampled value of the D
(DATA) input
at the instant INPUTS OUTPUTS Comments
̅
when the X 0 ̅ No change from previous output
CLOCK X 1 ̅ No change from previous output
changes from 0 0 1 RESET
low to high. 1 1 0 SET
o At all other times Q
remains unchanged.
 The D input is ignored most of the time, and is only sampled for a brief
instant at each CLOCK rising edge.
o The edge sensitivity of the CLOCK input is indicated by the > inside the
logic symbol, and the up arrow in the truth table
Divide-by-2 Circuit
 The D input is connected to the INVERTED Q output
 At each rising edge of CLOCK, whatever is on D is
stored and becomes the new value of Q
o Since D is always the inverse of Q, the flip-flop
will therefore change state at each CLOCK
rising edge
 So Q alternates at a frequency which is half that of the CLOCK input.
Ripple Counters
Ripple Down-Counter
 Connecting three divide-by-2 circuits
in a chain will therefore divide an input
frequency by 8
 E.g. if CLOCK has a frequency of 8 kHz
o Q0 will change at 4 kHz
o Q1 will change at 2 kHz
o Q2 will change at 1 kHz.
 This gives a modulus 8 countdown from
7 to 0 and then repeats
Ripple Up-Counter
 If we want to make the counter count up
instead of down,
o We need to connect the CLOCK
input of each stage to the
INVERTED Q output of the
preceding stage
21
Delays and Glitches in Ripple Counters

 When a ripple counter counts from, e.g. 3
to 4, the following events occur in
sequence:
1. CLOCK goes from 0 to 1
2. Q0 goes from 1 to 0
 For each flip-flop, there is a propagation delay of typically 30 nanoseconds
between the change at its C input and the change at its Q output
o Thus Q2 will change some 90 ns after the original CLOCK rising edge
o The changeovers in the flip-flops propagate or "ripple" along the chain
from Q0 to Q2
o The total delay before the count state is valid therefore depends on
the length of the chain.
 While the rippling is in progress, the Q outputs may pass through unwanted
rapid changes or
"glitches" before
reaching their final
state, e.g.:
 Glitches can cause
major problems in
some circuit applications
o But due to their simplicity, ripple counters are often used for counting,
or for frequency division by a power of 2
Decade Ripple Counter
 Counting from 0 through 9 is useful
o The modulus is 10, hence we have a "decade" counter
 To do this, we could build a counter with 4
flip-flops
o This gives a possible count up to 15
o Arranged so that when it has
reached 9 the next clock pulse will
reset it to zero
o An AND gate detects the state where
Q3 and Q1 are both 1 (representing
a count of 8+2 = "10") and feeds the
output of this gate to a special
CLEAR (CLR) input on all the flip-flops
 Resets count to zero
 However this method is rather prone to spurious resetting, caused by glitches
on the Q outputs during rippling
o Instead a synchronous counter is preferred (see later on)
22
The J-K Flip-Flop

 The J-K Master-Slave Flip-flop is a device which avoids the uncertainty of the
S-R latch
INPUTS OUTPUTS Comments
̅
0 0 ̅ No change from previous output
0 1 RESET
1 0 1 0 SET
1 1 ̅ Toggle
 Operation after next clock pulse

o If J and K are different, Q takes on the value of J
o If J and K are both 0, Q remains unchanged;
o If J and K are both 1, Q changes to its inverse (it "toggles")
 Information from J and K is read on the RISING edge of the clock, and is
translated at the Q outputs into action on the FALLING edge of the clock.
 Additional S and R inputs are sometimes included to permit asynchronous set
and reset of the outputs respectively.
 These signals override the J and K inputs, without waiting for the
clock to change.
Versatility of the J-K Flip-Flop
 The J-K flip-flop is a versatile building block in sequential circuits
 For instance, it can be used:
o As a D flip-flop, by connecting J to K via an inverter
o As a divide-by-2 element by joining both J and K to a logic 1 level.
 Or, if we join J and K inputs together and call the
common input T, the J-K device will act as a "toggle"
flip-flop:
o For the T flip-flop, on the next clock cycle:
 If T = 0 then Q remains unchanged
 If T = 1 then Q changes to its inverse
Synchronous Counter
 Using T flip-flops, we can make a more
reliable type of counter, the Synchronous
Counter.
o In this, all the flip-flops change
simultaneously (if required) at the
end of the clock pulse
o Does not suffer from the delays
and glitches inherent in Ripple Counters
 For a synchronous counter, each flip-flop is "told" whether to
change or not on the next clock cycle
o This information is obtained from the current state of the
other flip-flops:
o (If all LSB outputs are HIGH then toggle)
 We can arrange for a synchronous counter to be reset at any given
count state, so it can have any desired modulus
23
Summary: Synchronous and Asynchronous Sequential Logic

 Synchronous
o The timing of all state transitions is controlled by a common clock
o Changes in all variables occur simultaneously
 Asynchronous
o State transitions occur independently of any clock and normally
dependent on the timing of transitions in the input variables
o Changes in more than one output do not necessarily occur
simultaneously
 Clock
o A clock signal is a square wave of fixed frequency
o Often, transitions will occur on one of the edges of clock pulses
 i.e. the rising edge or the falling edge
Data Registers
 A circuit which can temporarily store
all the bits of a binary number
o Easily made from a row of JK
flip-flops used as D flip-flops
 One flip-flop per bit of the number to
be stored
 Shared clock, so when the clock pulse arrives the
values of all the D input bits are read in and
stored simultaneously
o A typical personal computer will have
several 16-bit and 32-bit data registers in its
arithmetic unit
 The diagram above shows a 3-bit register
o Logic symbol:
Shift Registers
 Flip-flops are arranged in a
chain
o Each Q output forms
the input to the next
stage:
 Each clock cycle causes the data pattern to shift
one place down the chain.
o New bit values can be fed in at the Data
input
o Bits are lost from the final output (here Q2)
 If DATA is set to 0 then each clock pulse will cause
the binary number to double until bits are lost.
24
Binary Multiplication
 Example: Let A = 3 (multiplicand), B = 5 (multiplier)
o Then C = A x B = 3 x 5 in decimal
 In binary we can write:
o A 00011x
o B 00101=
 So C = 1 x (1 x 3) ie. 1 x (1 x A)
+ 0 x (2 x 3) + 0 x (2 x A)
+ 1 x (4 x 3) + 1 x (4 x A)
 So we can do the
multiplication by
repeatedly doubling A, and
then adding the new value
to the result,
o But only IF the
corresponding bit of
B is a 1
o A is doubled by
shifting its bits to the
left.
 The process works correctly for negative numbers, providing the rules for 2's
complement are obeyed.
o Consistent word length must be used
o And the sign bit is always the MSB.
Machine Multiplication
 Binary multiplication can be done efficiently in a machine, using a sequence of
shift, test and add operations
 The logic circuits are included in the arithmetic unit of all microprocessors and
personal computers
o The shifts are done by shift registers (NB. must have adequate length!)
o The bit tests can be done using AND gates;
o The additions are done using full-adders
Monostable Flip-Flop
 Has only one stable state, Q = 0
o A clock pulse at its input, M,
flips it into its unstable
state, Q = 1, and then after a
known time interval it
reverts ("flops") back into the stable state Q = 0 again
 Used to generate pulses or time delays of known duration
 This is determined by connecting capacitors and resistors of the
appropriate value into a charging circuit which controls the following actions:
o While Q = 1, current flows from Vcc through R into C
o Voltage across C rises: ( )
o When it reaches some threshold value, Q gets reset to 0
o Upper limit on R, but not C
25
1.6 Multiplexers
 Multiplexers aka MUX
o Digital electronic devices
with several data inputs and
one data output
 One input is selected
by the "select inputs"
 Binary data on the
selected input is fed to
the output
 The label means that the four possible

combinations of A and B could be thought
to represent four separate gating inputs
G0, G1, G2 and G3.
o The data inputs are labelled to show which one is "let through" to by
a 1 on each of these conceptual G inputs.
MUXs for Logic
 Sometimes, combinational logic can be implemented more efficiently using
MUXs rather than gates
o Set the inputs associated with true minterms to 1
o Set other inputs to 0
 E.g. ̅ ̅ ̅
o In this situation "1" is
output if the input
variables (A,B,C) select
D3, D4 or D7.
o This will correspond to
lines 3, 4 and 7 of the
truth table above.
o Remember that lines of
the truth table are
numbered starting at 0 (not 1)
Demultiplexers (DMUX)
 Demultiplexers are digital electronic devices with
several data outputs and one data input
o One output is selected by the "select inputs"
o Binary data on the input is fed to the selected
output
26
MUX/DMUX Pairs
 A MUX/DMUX pair is
commonly used in
communication and
logic systems where
some complex piece of
processing circuitry
must be time-shared
between several signal
paths to economise the
design:
27
1.7 Memory Devices and Programmable Logic Devices

 Bistable flip-flop is one type of memory device
o This, and data registers made from flip-flops, are mainly suitable for
temporary storage of bits or numbers.
o Not very economical for long-term storage, or for holding large arrays
of values in a computer
 Use either Read-Only Memory (ROM) devices or Random-Access Memory
(RAM).
o Contain a large compact array of very simple memory elements.
Read Only Memory (ROM)

 A ROM cell can store 1 bit of information
o Data can be read but not altered (written)
 ROM is non-volatile
o Data is retained even when the power supply to the chip is removed
o Data can be read after turning the power on again
 Applications of ROM
o Permanent storage of programs for microprocessors
o Look-up tables of data
o Implementing combinational logic
ROM Cell
 A voltage is stored to represent a 0 or 1 as
required
o Many such cells are arranged in an array of
rows and columns
 If the “row-line” is addressed, the switch closes
and the stored voltage appears on the “column-line”
o The switch is implemented with a (MOS) transistor
 Storage mechanism for 1 or 0 depends on design of the ROM cell
Mask Programmed ROM
 The mask programmed ROM is programmed at the time of
manufacture
 Switch transistor is made to have a low threshold voltage to
program a 0 and a high threshold to program a 1
o A "low threshold voltage" means the channel of the
transistor will conduct when the row-line goes to
logic 1
Typical ROM Device

 6 address inputs - half for row select, half
for column select
 Row select energises all the switch
transistors in one row
 Column select uses a multiplexer to select
just one column
 Outputs are normally high (1) but "pulled
down" to 0 if a cell is programmed to 0
28
Field Programmable ROM (PROM)

 Programmable using a PC-based system
o A semiconductor fuse is blown to program a cell to
1 (disconnects the column-line from logic '0')
Erasable-Programmable ROM (EPROM)
 Programmable using a PC-based system
 The gate capacitance of a MOS transistor is charged
(electrically) to store a 0 or discharged (by UV light) to
store a 1
 First the entire EPROM is erased to 1's with UV light for 15
minutes, then individual cells are electrically programmed
to 0's
Implementing Logic with PROM
 2n x 1-bit PROM devices have n inputs and 1
output
 So they can be used to implement logic directly
o E.g. OUT = X.Y+Z
 Program the first 8 addresses according to the
OUT column
o Connect X to A2, Y to A1 and Z to A0 of the
PROM
o Usually "cheaper" than using gates for complex logic involving many
variables, or where the K-map won't simplify
Programmable Logic Devices

 Several different "architectures" available
o E.g. PALs and EPLDs are examples of PLDs
 PAL: Programmable Array Logic
 EPLD: Erasable Programmable Logic Device
 Implements SOP expressions in canonical form
o Made from a Programmable AND section and a Fixed OR section
o Typically can implement 8 product terms
PALs
 PALs are programmed like PROMs, using fuses
o One-time programmable
o Blow fuses to break unwanted connections
o Readout is fast
PAL Architecture
 Before fuses blown, every input of every AND is
connected to every and ̅
EPLDs
 EPLDs are (re-)programmed like EPROMs
o Erasable using UV light (typically 15 minutes' exposure needed)
o Programmed one bit at a time, but only a short time needed per bit
o Readout is slower than PALs
29
Summary of Programmable Logic Devices

ROMs
o Implement arbitrary logic functions
o Efficient for large combinational logic circuits
EPLDs
o Implement canonical SOP Boolean expressions
 Advantages:
o Reduction in chip count
o Easy upgrade by just reprogramming
 Disadvantages:
o Programming equipment required
o Non-standard parts to stock and document
Timing Hazards in PLDs

 Gates inside PLDs have finite
propagation delay
o This can cause glitches
in logic waveforms
 Consider an inverter
o Propagation delay of
~10nS
Avoiding Timing Hazards
 Using a Karnaugh map, look for groups of minterms which do NOT overlap
o These are potential hazards
 Avoid the hazard by introducing additional groups so that no non-
overlapping groups remain
o Groups here are ̅
 These do not overlap
 Therefore potential hazard
o Introduce the additional term to
avoid the hazard
RAM Devices
 ROM, PROM and EPROM and PLDs are used to hold bit patterns or numbers
which are essentially constant
o In addition to the various types of ROM, computers need to store and
manipulate large arrays of numbers which can be altered at will.
 For this purpose we use read/write memory devices in a Random-Access
Memory (RAM)
o RAM is similar to ROM in the way the arrays are organised and the row
and column addressing works
Types of RAM Devices
 Two main types of RAM device:
o Static RAM (SRAM): Each bit cell is a small flip-flop made of 2 or 4
transistors
o Dynamic RAM (DRAM): Each bit cell uses a capacitor to store charge,
plus a buffer amplifier to maintain it:
30
 In both SRAM and DRAM, the data is maintained only while the power remains
on (ie data is "volatile" )
 Static RAM is simple to operate, but more space consuming
 Dynamic RAM can
achieve very high
density but the charge
on each tiny capacitor
quickly leaks away
o So DRAM
requires extra
circuitry to refresh the charge in each capacitor
o The process of reading out data also alters the charge
o Hence the need for a buffer amplifier and switching, via transistors
Flash Memory
 Compromise between EPROM and RAM to obtain
"non-volatile RAM"
o Charges are stored on an extra, isolated
"floating gate" of a MOSFET so they do not
leak away so rapidly
 Can use as RAM while power is on
 Behaves as EPROM when power is off
 Useful, was expensive but increasingly cheaper
now
Memory Devices Summary
31
7 Segment Displays
 LCD (liquid crystal display) or LED (light-
emitting diode) devices can display digits made
of up to 7 segments or lines
 The decimal character set '0' - '9' needs 4 bits
o So decode 4 bits into 7 control signals
using a BIN/7SEG decoder
 A specialised kind of
demultiplexer
 The 7 segment decoder is just about the largest
circuit that would be economic to implement
using gates
o Other implementation methods include
ROM, PLD, etc…
32
1.8 Application: Heart Rate Metre
The Challenge
 Given a trigger pulse corresponding to each heartbeat, generate the
instantaneous HR in beats per minute.
o You will need a clock input signal at e.g. 100Hz to give you a reference
(you can assume it is available);
o You will need a circuit, together with the reference signal, to work out
the time interval between two consecutive heart beats;
o You will need a circuit to convert the time interval to an instant heart
rate and store it for display.
 A standard way to measure time intervals:
o Feed a REF clock signal (of constant, known frequency, here 100 Hz)
into a counter
o Allow it to count up from zero for the length of the unknown interval
 Then the final count value will be
 Hence the sequence of operations for the HR meter is:
1. Reset the counter to zero.
2. At first trigger pulse, begin counting the REF clock transitions
3. At next trigger pulse:
a. Stop counting the REF clock
b. Save the final value of the counter, (INTV), in a data register.
c. Reset the counter to zero, and allow it to start counting
immediately.
4. Convert the stored value of INTV to an instantaneous rate, IHR
a. We could use a ROM or EPROM as a reciprocal look-up table
5. Display the value of IHR
6. Repeat from step 3
Circuit Design
 The proposed design is:
33
Timing Diagram
System Accuracy
 A typical medical instrumentation design requirement:
o "Given a trigger pulse corresponding to each heartbeat, display the
instantaneous heart rate (HR) in beats per minute
o This must be accurate to within 3 beats/min over the range 50-125
beats/min".
 To display the instantaneous , we will need to measure the time interval
between successive trigger pulses and then find the reciprocal ( ).
o Working range of heart rates,
o Working range of intervals,
o To preserve an accuracy of 3 bpm over the whole range, we consider
the worst case
 Where the , ie.
 When interval t= 0.48 sec, we have to distinguish between a rate of 125 and 122
bpm
o ie. between an interval of 0.480 and one of 0.491 seconds
o We can do this if we measure each interval with a resolution of 0.01
seconds,
 i.e. to the nearest hundredth of a second.
 At the other end of the working range, where the HR = 50, we will be able to
distinguish between an interval of 1.20 and 1.21 seconds, (HR = 49.6 bpm)
o So we will easily satisfy the accuracy specification.
 Because the REF clock input is 100Hz, the counter will contain 48 at the end of
an interval of 0.48 sec, and 120 at the end of an interval of 1.2 sec, etc.
o By sending this value to the address lines of the EPROM, we can simply
look up the corresponding heart
rate value as a binary number
from 125 down to 50
o We must program these values
into the EPROM at the correct
locations 
34
1.9 Other Notations for Binary Numbers

 Important to remember that inside a computer, all numbers are in binary.
o Decimal, hexadecimal (hex), octal and other notations are just convenient
ways for humans to handle large binary numbers outside the computer.
Hexadecimal Notation
 Hexadecimal is more compact notation
o Long binary numbers are tedious and error-prone to write out
o Based on groups of 4 bits (giving 16 possible patterns for each group)
 Divide binary into groups of 4 bits, starting with the LSB and working to the left:
o group as
 For each group of 4 bits write the hexadecimal value
Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F
digit
 So
o Also written as
Octal Notation
 Octal Notation (not used much nowadays):
o Takes the bits in groups of 3 (each group has 8 possible patterns)
o The corresponding octal digits are 0 1 2 3 4 5 6 7 
 E.g. if (as before), 
o Group as: 
o So in octal,
ASCII
 When word processing we type alphabetic and numeric characters into the
computer and arrange them.
o Inside the computer the characters are treated simply as binary numbers.
o These are indistinguishable from the binary numbers used to perform
calculations
 To represent alphabetic / numeric characters in binary, there is a standardised
code: ASCII
o American Standard Code for Information Interchange
 In ASCII, every printable character is assigned a unique 8-bit binary
number (a byte) whose value is as shown in the ASCII table.
o E.g. the character 's' has value 0 1 1 1 0 0 1 1 = 115 or 73H
10
o Whereas the character 'S' is 0 1 0 1 0 0 1 1 = 83 or 53H

10
35
2.1 Introduction to Microprocessors

Definition of a Computer
 A computer is machine that can perform a sequence of arithmetic and logical
operations by following a program of instructions stored within the machine
o Unlike a calculator it can change the sequence of instructions
depending on the input data or the output
o A computer can make decisions which alter the course of its own
program
Structure of a Computer
 All computers consist of basic functional
blocks that include a central processing
unit (CPU), memory and input/output
ports
o These are connected together by
three internal buses: the data bus,
the address bus and the control
bus
Overview of Operation
 Instructions and data are stored in memory in specific locations determined by
the program
o Each location has a unique address
o Instructions obtained by the CPU placing an address on the address bus
o Instructions transferred via data bus as they are requested
o CPU executes the instructions sequentially
 The instructions modify data stored in memory or obtained
through input devices
o Processed data may be stored back in memory or sent to an output device
via the data bus
o Signals on the control bus are generated by the CPU to coordinate all
these operations
Microprocessor/CPU Structure
 The microprocessor is a digital IC that can be programmed
to perform various operations on data
o It is the CPU of a computer
o Can do arithmetic and logic operations, move data and
make decisions based on certain instructions
 Consists of several units each designed for a specific job
o The specific units, their design and organisation is
called the architecture
o The architecture determines the instruction set and
process for executing those instructions
 Four basic units to all microprocessors are the arithmetic
logic unit (ALU), the instruction decoder/register, the
register array and the control unit as well as buses
36
Arithmetic Logic Unit

 The ALU is the key processing unit of the microprocessor
o A set of gates and flip-flops arranged as full-adders, shift registers and
bit-testers
 Directed by control unit to perform
o Arithmetic operations (addition, subtraction, multiplication and division)
o Logic operations (NOT, AND, OR and XOR)
 Data for ALU are obtained from the register array
 Precise signal path is determined by a set of control inputs which are set by
the contents of the instruction register
Register Array
 Collection of registers that are contained within the microprocessor
o During program execution, data and memory addresses are
temporarily stored here
o ALU can rapidly access these making the program run more efficiently
 Some are general purpose whilst others have specific uses
o Details of the most important three are given
Program Counter
 The PC contains a binary number representing the location in memory where the
next instruction is to be fetched from
Accumulator
 ACC stores the result of the latest arithmetic/logical operation from the ALU.
 Its contents can also be used as input to the ALU.
Instruction Register
 The IR contains a binary number which tells the ALU what operations to
perform.
 This is done by using the individual bits of the IR to set the inputs of various
gates in the ALU high or
low
o E.g. add/subtract.
Control Unit
 The control unit is in charge
of the processing of
instructions once they are
decoded
 Provides the timing and
control signals for getting
data into and out of the
microprocessor and for
synchronising execution.
Internal Bus
 The three main registers and the ALU communicate with each other by means of
a BUS which is simply a set of conducting paths which are time-shared.
o Only one register at a time can transmit data on to the bus, while the
others all have to 'listen' even if they need take no action.
37
Basic Microprocessor Operation

 A typical CPU or MPU cannot perform even apparently simple instructions (such
as S = Q + R) directly.
o These must be broken down into very simple basic operations in
which one, or at most two, binary numbers are fetched from memory,
manipulated in the ALU, and saved in the memory again.
o The basic operations are: fetch from memory : add : complement : test
: shift : save in memory
 For most of the time, the instructions and the data are all stored in the main
RAM memory.
o They are fetched into the processor, one at a time, as needed, and do
not usually stay there for very long.
o Contents of the RAM can be read without being altered, or else new
contents can be placed there by the CPU, as appropriate.
Example Operation
 To perform S = Q + R we have to instruct
the CPU to do the following sequence:
o Instr 1: Fetch the value of Q into the
accumulator from its specified RAM
memory location
o Instr 2: Add the value of R from its
specified RAM location to the
contents of the accumulator
o Instr 3: Store the result in another
RAM location we reserved for S.
Opcodes and Operands
 Each instruction held in memory consists
of two parts:
o An OPCODE which specifies what operation to perform
o OPERAND which specifies where the relevant data can found or put
 So for this example:
o The opcode for "fetch a value into the accumulator from a RAM location"
might be 03H
 The address of the operand Q in memory is A7H
 So the whole of Instr 1 would be 03A7H
o Similarly, the opcode for "Add a value in RAM to the contents of the
accumulator" might be 05H
 The address of the operand R in memory is A8H
 So the whole of Instr2 would be 05A8H
o Suppose the opcode for "Store the contents of the accumulator in a RAM
location" is 13H
 The address we reserved for S is 51H
 So the whole of Instr3 would be 1351H
38
Program Actions
 To run the program, we set the
Program Counter register to 43H
so that the first instruction will be
fetched.
 It will automatically be
incremented after each instruction.
So:
 We did not place an instruction in location 46H so the action of the processor
when it reaches this location will be unpredictable.
o We must therefore place a STOP instruction in location 46H.
 The opcode for STOP might be FFH, and no operand is needed.
 So the instruction would be FF00H.
 Having done that, when we set the Program Counter to 43H to start the program,
this time it will run correctly and stop with the final value 0035H stored in
location 51H, which is the one we reserved for S.
o The original values of Q and R will remain unchanged.
Programming
Machine Code
 This sequence of instructions we built up in the RAM memory is called a
machine code program
o It is just a series of binary numbers, indistinguishable from data
 Numbers which are instructions have a very specific meaning to the
processor
o The bits of the opcode act as inputs to the control gates in the
processor.
 There are many types of processor, by different manufacturers, all wired up in
different ways,
o So the opcodes of the machine code instructions are specific to a given
family of processors.
 Machine code allows the programmer to have complete control of every binary
number inside the machine at any instant.
o But Machine code programming is difficult, slow and error-prone:
 A typical processor has 60-200 different opcodes
 A program could contain 1000 to 100,000 instructions
o For everyday use, we have a much more convenient method of producing
the machine code program;
 This is called Assembly Code (or Assembly Language)
programming
39
Assembly Code
 Assembly code is set of mnemonics to represent the opcodes
o Plus some rules for specifying the operands
 The assembler is a pre-written machine code program that translates your
own assembly code into machine code, and checks for errors.
o Supplied by the manufacturer
o Specific to a microprocessor architecture
 Example: S = Q + R had to be implemented as:
Pseudocode Assembly
1. Instr 1: Fetch the value of Q into 1. LDA Q ("Load the accumulator
the accumulator from its with the value Q")
specified RAM memory 2. ADD R ("Add the value R to the
location; accumulator")
2. Instr 2: Add the value of R from 3. STA S ("Store the accumulator
its specified RAM location to the contents in S")
contents of the accumulator; 4. HLT
3. Instr 3: Store the result in
another RAM location we
reserved for S;
4. Halt.
o Notice that these instructions have the same general form as the binary
machine code instructions, ie. Opcode | Operand.
Equate Directives
 The equate directive EQU can be used to assign constants
 We can specify these by placing Equate Directives (EQU) at the start of our
program:
o Q EQU A7H
o R EQU A8H
o S EQU 51H
 Now whenever the assembler sees the symbol Q as an operand, it can put A7
hexadecimal into the operand part of the machine code instruction.
o Similarly for R and S
Origin Directive
 The assembler needs to be told
that we want our first machine
code instruction to be at a
specific memory location 43H
(recall the memory map)
 We do this by placing an Origin
Directive (ORG) before the first
instruction:
40
Loading an Running
 The assembler will translate the program into the machine code instructions, as
a binary image of the desired memory map
o In small systems, the Assembler will automatically load the machine code
instructions into memory for you
 Pre-set the data values for Q and R
 Then set PC to the desired start address (here 43H) to run the
program immediately.
 The result Q+R will be placed in S.
o In larger systems the Assembler will store the machine code program on
disk, for you to load and run it when required.
Programming Pathways
 There are various ways
of producing the
machine code program
o Machine code is
the only form the
processor can
directly act on
 Programs written in
high-level languages
are even easier to
write, read and
understand than
assembly language
programs.
Advantages of Assembly
 Assembly offers benefits to speed, efficiency and program size
o These are important when programming a MPU as a component, or in a
single-board computer
 These have only very small on-board memory, and often a slower
clock rate
 High-level languages tend to produce large machine code programs even for
simple applications.
o This is because application program gets translated into binary object
code, which is then linked with other object code modules from a library,
to form the final executable binary program.
o S = Q+R could generate a program needing 5000 to 10,000 memory
locations.
o These large programs inevitably take longer to run than the equivalent
Assembly Code program.
41
2.2 Assembly Programming

 There are many different microprocessors and the assembly language is
architecture specific so one must be selected
 We will consider the Motorola 6809
o AccA and AccB are both 8 bit registers but can be used as one 16 bit
register
o Condition code registers have a bit that has information on the previous
operation performed by the ALU
 Act as flags that indicate overflow, zero value, -ve, etc…
Addressing Modes
 So far, we have represented operands by the memory address of the data which
is to be operated on (e.g. A7H for Q)
o Most processors offer several different ways of specifying operands.
o These are called the addressing modes.
Register Addressing
 The relevant register is specified using a letter.
 Example: CLR A (clear the A accumulator to zeros), INC B (increment the B
accumulator by 1).
o Often written as, e.g., CLRA
Immediate Addressing, #
 The actual value of the operand, not its address, is supplied as part of the
instruction.
 Example: ADDA #7EH means add the value 7EH to the 8-bit A Accumulator.
o [Compare this with: ADDA 7EH which means: add the contents of location
7EH to Accumulator A].
o Immediate mode is used for operations involving constants.
Extended Addressing
 The full two-byte address of the data is supplied as the operand part of the
instruction.
 Usually we simply specify the data by a label (Example: LDA Q) and let the
assembler decide which addressing mode to use.
6809 Instructions
 Operation codes are divided into four categories:
o Data Transfer
o Arithmetic/Logical
o Stack Operations
o Jumps and Branching
Data Transfer
 All data transfers are done via the registers.
 These instructions may affect the N,Z, and V flags in the Condition Codes (CC)
Register.
o Store register in memory: STA, STB…
o Load memory into register: LDA, LDB…
42
Arithmetic and Logical

 Can operate either on registers, or directly on memory locations.
o May affect the N,V,C,Z and H flags in the CC Register:
 Add 8-bit operand to accumulator: ADDA, ADDB
 Subtract 8-bit operand from accumulator: SUBA, SUBB
 Logical (Boolean) AND 8-bit operand with accumulator: ANDA, ANDB
 Logical OR 8-bit operand with accumulator: ORA, ORB
 Increment accumulator or memory location: INCA, INCB, INC
 Decrement accumulator or memory location: DECA, DECB, DEC
 Arithmetic left-shift accum. or memory loc: ASLA, ASLB, ASL
 Arithmetic right-shift accum. or memory loc: ASRA, ASRB, ASR
 Rotate accum or memory location one place to right or left, via carry: RORA,
RORB, ROR, and ROLA,ROLB, ROL
o Preferred to shift in some cases as no bits lost
 Complement accum or memory location: COMA, COMB, COM

 Test accum or memory for negative or zero: TSTA, TSTB, TST
 Add 16-bit operand to Accumulator D: ADDD
 Multiply A by B, put result in D: MUL
o ( Note: destroys A and B )
Stack
 A stack is an area of memory used as a structure for the temporary storage
and quick retrieval of register contents.
o Operates on a Last-In, First-Out (LIFO) basis
 Like a push-down stack of plates in a canteen.
o Data items are retrieved in reverse order to the order in which they
were added to the stack.
 In a microprocessor system, this is implemented using a static area of memory,
plus a pointer register (System or User) which indicates where the most
recent addition was made
o i.e. It points to the
"top" of the stack.
o In practice,
implemented upside
down, as a memory
"stalactite" rather
than a "stalagmite".
 In the 6809 there are two separate stacks
o These are controlled by the System Stack Pointer, S and the User Stack
Pointer, U.
 Data is added to the stack using a Push instruction (PSHS or PSHU), stating
what registers are to be saved:
o Example: PSHU A,B,X saves accumulators A,B and index reg X
43
 The most recent entry can be retrieved from the stack using a Pull
instruction (PULS or PULU):
o Example: PULU A,B,X retrieves the registers from the above Push
 The programmer has to keep track of what is currently at the top of the stack.
o But the Stack Pointer register automatically decrements itself by the
correct amount during PUSH operations and increments itself correctly
during PULL operations.
Jumps and Branches
 Jump and branch instructions alter the value in the PC to change the program
flow.
Unconditional Jumps
 Simple Jump : JMP label
o The assembler will decide which addressing mode to use
 Relative Branch: BRA signed 8-bit offset value
o The operand indicates the amount by which the PC is to be altered.
o Example: BRA –8H causes a backward jump to instruction 8 locations
earlier in the program.
o We can also use labels, and allow the assembler to calculate the offset
value for the branch instruction.
Conditional Branches
 A relative branch occurs if the stated condition of the flag bits in the CC register
is fulfilled.
o This forms the decision making process in computer programs - the real
basis of the power and flexibility of computers.
 Generally used following arithmetic, logical or comparison instructions.
Examples:
o BEQ branch if equal (Z=1) or if a result was zero
o BNE branch if not equal (Z=0)
o BMI branch if minus (N=1) ie. if result was negative
o BPL branch if plus (N=0) ie. if result was positive or zero
o BCS branch if Carry flag is set (C=1)
o BVS branch if Overflow occurred (V=1)
Counting Loop Example

 Consider the program below:
 Note: this is not the simplest form.
 The reason for using two labels, LP1 and LP2 here is that the range of the BEQ
instruction is limited to +/-
127 locations, but the range
of the JMP instruction is
unlimited.
 Coding it as above would
allow the length of the
working-loop to exceed 127
locations.
44
Subroutines
 A subroutine is a section of code which can be used or 'called' several times by
different parts of the main program
o Normally requires some input data (via registers or memory locations)
o Leaves its results in registers or memory locations
 We might want to multiply Accumulator A by ten at various points in a main
program.
o We could write out the sequence every time (in-line coding).
o However, this is wasteful
of memory.
o More economical to
code the operation as a
small subroutine, and
give it a suitable name
 Eg. AX10, and a
Return instruction:
 The AX10 subroutine can now be called from anywhere in
the main program
o Using a special JSR (Jump-To-Subroutine)
instruction:
 Each time we jump to the subroutine, we have diverted
away from the main flow of the program to the place where
AX10 is residing in memory.
o The RTS instruction at the end of the subroutine
provides the means of finding our way back to the
point where we left the main program
How JSR and RTS Work
 When the JSR AX10 is encountered, (eg. at Instr 46) the CPU
does a PUSH to store the contents of the PC on the
System Stack.
o This is the value currently pointing to the next
instruction, ie. Instr 47
 It then sets the PC to point to the address of the
instruction labelled AX10
o I.e. the start of the subroutine, and lets the
subroutine run.
o Called "passing control to the subroutine"
 At the end of the subroutine, the RTS instruction causes the CPU to PULL the
topmost value off the System Stack and back into the PC
o This will be the value pointing to the next instruction, ie. Instr 47
o This restores the state that the PC was in just after the call to AX10.
 The CPU will therefore get its next instruction from the address of Instr 47.
o So control has passed back correctly to the point where we diverted
from the main program
 Essentially upon calling a subroutine, the next PC value is stored in the
stack until RTS is called upon which normal flow resumes
45
Considerations
 In general, the advantages outweigh the disadvantages, so subroutines are
widely used in professional coding
Advantages
 Facilitates making changes
 Reduces the risk of errors (less code to write)
 Saves memory space
 Simplifies the program layout and documentation
Disadvantages
 Slower to execute than in-line coding, due to the "overhead" associated with
the stack operations
 More difficult to find intermittent errors if they occur inside a subroutine
46
2.3 Data I/O

 Computers can
communicate with
the interfacing
hardware by
treating it as a
piece of memory
The Peripheral Interface Adaptor (PIA)

 Transfer of binary data in and out of the computer is done using a Peripheral
Interface Adaptor (PIA) - a single IC.
 The PIA has several input/output (I/O) channels or ports
o Each with a Data Register and a Control Register
 The PIA shares in the traffic on the computer main signal bus
o Remember only a single device can output to a bus at one time but all can
read at once
 It is memory-mapped
o Ie. each PIA register seems to the CPU like a pseudo-location in RAM
memory
o We can choose the Base Address of the PIA (e.g. 8C10H) by setting
switches or jumper wires
 The CPU uses Load and Store instructions to access the data in the PIA
registers
o Other types of processor, including the Pentium, use a different scheme
(port-mapping), together with special I/O instruction codes.]
Example
Getting the Input Value

 The program must wait till the specific bit of the Port A Control Register goes
high, (indicating that CA1 has gone high) to signal that a new data value from
the experiment is ready at Port A.
o Then we can collect it, into Accumulator B for example.
o Squaring the input value: we can copy the input from Acc B to Acc A then
use the MULtiply instruction to form the 16-bit product.
47
Problem with Polling

 The GETINP subroutine waits for new data by
continually testing a flag bit (the MSB) in the
Port A Control Register.
o This is called 'polling' the port.
 Polled input technique works well, and is
often used in simple systems.
o However, it is inefficient because the
processor is spending most of its time in GETINP, waiting for data to
become available.
o It cannot do any other useful work in the meantime.
Interrupt-Driven I/O
 Ideally, the processor should be able to do some other, background task and deal
with Port A input data as it becomes available.
o Such a facility is provided by a different type of subroutine call, known as
an interrupt.
 When an interrupt is received, the program:
o Diverts away from the mainstream,
o Jumps to a designated subroutine called an Interrupt Service
Subroutine (ISR) to deal with the cause of the interrupt
o Then returns to the main program where it left off.
Interrupt Mechanism
 Interrupts are implemented using
extra hardware.
o When the PIA has new data
ready, it asserts logic 1 on a
special Interrupt Request
(IRQ) line that goes directly into the processor.
 When logic 1 is detected on the IRQ input line, the processor knows that it has to:
1. Complete the current instruction;
2. Save the Program Counter on the System Stack;
3. Save the other registers on the System Stack;
4. Find out the start address of the Interrupt Service Routine;
5. Load this address into the Program Counter.
Interrupt Service Subroutine
 Step 5 above passes control to the Interrupt Service Subroutine,
o This may be a portion of code rather like GETINP
o (ie. it deals with the cause of the interrupt)
 The ISR looks like a normal subroutine except that instead of ending with an RTS
instruction it ends with a Return from Interrupt (RTI) instruction.
o This RTI tells the processor to reverse the stacking operations done in
Steps 2 and 3 above, so that all the registers get restored to the state they
were in just before the interrupt.
o The main program then resumes from where it left off.
48
Interrupt Vectors
 The main difference between an Interrupt Service Routine and a normal
subroutine is that the processor gets the start address of the subroutine, not
from the operand of a JSR instruction but from a pointer location which is at a
fixed address in memory.
o Such a pointer to an ISR is called an interrupt vector.
 Most processors have multiple IRQ input lines; each has its own associated
vector, and is assigned a priority level and a distinct name.
o The vectors are usually grouped together at the very
top of memory.
o Their addresses are pre-determined by hard-wiring
in the processor.
o Each vector occupies two bytes, since it has to hold a
16-bit address, e.g. in the Motorola 6809:
o Reset has the highest priority, then NMI (non-maskable interrupt), then
SWI (Software interrupt), etc.
Direct Memory Access (DMA)
 Normal interrupt-driven input/output is powerful and flexible
o Allows a number of I/O devices to operate each at its own preferred
speed.
 But there is a limitation as all data is being passed through the CPU
accumulators;
o Only one or two bytes at a time can be transferred per machine cycle,
inefficient for transferring large blocks of data as fast as possible to/from
memory.
 Direct Memory Access (DMA) solves this by allowing an I/O device to take
control of the bus for a short period.
o A burst of data can be transferred at maximum speed.
o The CPU is taken off the bus during DMA activity.
o Transfer rates of 50-90 million bytes/second can be achieved during
the burst.
 The main CPU activity is not slowed down very much if bursts are kept short.
o The DMA controller generates an interrupt to tell the CPU when a
transfer has finished.
o More advanced DMA controllers insert their activity during parts of the
machine cycle when the bus is idle.
 Then no perceptible slowing of the CPU or program speed.
49
Serial I/O
 All of the I/O devices described so far perform parallel data transfer
o All the bits of a binary value are transferred simultaneously.
 Parallel I/O devices require as many interface circuits and transmission paths as
there are bits in the data.
o This can become expensive (multi-way cables, connectors, etc).
 An alternative is to use a serial protocol, where the bits are sent in sequence
rather than simultaneously.
o Less peripheral data lines to the outside world are required.
o Thus only one data path is needed.
 The transfer did take longer in old designs (RS232), but the speed has improved
immensely with new technologies such as Universal Serial Bus(USB)
RS-232 Serial Transfer
 An previous widely used protocol is called RS-232
o The data are 8-bit values, plus bits for START, STOP and PARITY , so
each character involves 11 bits
o Error check, e.g. Parity = the sum of all data bits, ignoring carry-out
 Data are read out in sequence, LSB first, to the Transmit line and hence to the
peripheral device (e.g. printer)
 In RS-232, a bit value of 1 is indicated by -12 volts on the data line, and a 0 is
indicated by +12 volts.
 The time duration T of each bit is pre-set, so that both the ACIA and the
peripheral device can work out when each bit ends and the next bit starts.
o Expressed as 1/T,
 The number of bits per second, also called the Baud Rate.
o Typically 9600,19200, 28K, 56K
 Example:
o Transmitting the
character 'A' = 41H =
0100 0001, using even
parity ( ):
USB
 USB stands for Universal
Serial Bus
o Byte-wise serial
protocol, with error checking
o Much more complex than RS-232
o Much faster than RS-232
 USB 2.0 = 480 Mbits/sec, cf. RS-232’s maximum of 112.5 kbits/sec
 Each USB device can identify itself to the host computer and obey complex
commands
o Plug-and-play capability requires great complexity inside the USB device
o So, special integrated circuits are made to implement this
50
2.4 Digital-Analogue Interconversion and Pentium 386

Digital to Analogue
 A Digital-to-Analogue Converter (DAC)
produces an output voltage which is
proportional to the binary value being
presented at its input:
 Two main types

o Binary-weighted current sources
o R-2R ladder network
 DACs are readily available with 8, 10, 12 or
14 bit resolution.
o More bits = more expensive
Analogue to Digital
 The natural world operates
mainly on an analogue basis.
o For obtaining digital input
to computers, we must
repeatedly sample the
analogue information and convert each sample value to a numerical
(digital) representation.
 We do this using an Analogue-to-Digital Converter (ADC)
 If the analogue signal is changing very fast, a short sampling time and frequent
repetition is necessary.
 Three main methods:
o Digital-ramp ADC: simple, but slow
o Video flash ADC: very fast, but expensive
o Successive approximation ADC(not detailed here): compromise
Digital Ramp ADC
 Operation
o The output of a binary counter is
connected to the input of a DAC
o The analog output of the DAC is
compared with the analog input
signal
o The comparator's output tell the
counter when to stop counting.
o The final binary count is
proportional to the voltage value
that was taken by the register SRG
 Disadvantage
o Conversion time depends on the
actual value of the sample voltage,
and on the bit resolution (step size)
- relatively slow.
51
Quantisation Error
 There will always be a difference between the actual (analogue) quantity and the
digital value assigned to it
o This is termed quantisation error
o Can be reduced by increasing the number of bits.
 E.g. Binary represent 10.48 and 10.52 from analogue values
o 10.50 cannot be represented
Pentium 386
 From the programmer's point of view
the Pentium family has the same
register set as the old 80386.
o Allows old programs to be
used with the new machines
 Some registers are reserved for special
purposes
 Memory access is done via
combinations of Segment Registers, to
generate 20-bit or 32-bit addresses
 There are more than 300 different
Opcodes
o However, the format of the assembly code instructions is similar to those
of the Motorola 6809, ie. Opcode|Operand
 The 386 and Pentium processors are able to run two or more tasks
concurrently
o Management of the stack is complicated, since the state of each task
must be saved and reclaimed many times.
 The stack pointer and the base pointer are used together to
achieve this.
o To manage such a complex processor, plus all the other I/O resources,
interrupts, etc., clearly requires a lot of sophisticated programming
 Not sensible to try to write every program from scratch in assembly code
o Instead, we use a set of commercial software which manages all the
hardware, and gives programmers convenient access to services
o This software is called the Operating System (OS).
52
2.5 The Operating System
Overview
 The best known Personal Computer OS is Windows.
o It was developed from a much simpler system called MS-DOS
("Microsoft's Disk Operating System") created for the first PCs
 On other types of computers and workstations, an OS called UNIX is now the
industry standard.
o A version of UNIX is available for Personal Computers too (LINUX )
 Tasks performed by the Operating System:
o Giving the user access to hardware functions
o Facilitating input and output of data
o Organising data and programs in filing systems
o Detecting and recovering from errors
o Sharing resources, programs and data between several users
o Organising communications between computers (networking)
o Accounting and billing for resource usage
Structure
 The user accesses only via the OS shell
o In older OS, the shell prompts the user
for commands which are typed in from
the keys
o Modern OS use a point-and-click shell
interface
Processes
 When the shell has determined what the user
wants, it creates a PROCESS,
o This represents this latest
application
o Remains in existence until the
application is ended.
 The shell is constantly creating, managing
and destroying discrete processes.
 The kernel provides CPU, memory and I/O services to these processes as they
ask for them.
 The user's program does NOT usually deal directly with the hardware, but is
turned into a process, which sends all its service requests via the program
interface in the kernel.
o Advantage: user programs can be easily adapted ("ported") to run on new
hardware systems, provided that the software Program Interface is made
to appear the same.
o Hence a big saving in cost, since hardware keeps evolving
53
Fate of Processes
 After a process is created, it is placed in a queue.
 Each process is in one of three states:
o Running: it has the use of the CPU
o Ready: it could use a CPU if one were
available
o Blocked: it is waiting for some event to
happen (e.g. an I/O transfer to finish)
before it can continue
OS Multitasking
 The method of states and queues allows the OS to maintain a number of
processes (i.e. programs) running concurrently
o This is known as multitasking.
 Many separate processes are created by the shell
o Each is allocated a priority level and a separate area of memory for its
code and data, so that they cannot interfere with one another except by
special permission
o Each process is given attention in turn by the OS kernel
 Additionally, the kernel must respond to other, "housekeeping" interrupts
such as the time-of-day clock or mouse movements
OS File Organisation
 The OS manages disk files and organises them into a
hierarchical tree system for ease of access
o For each logical storage device (e.g. the C: drive), there
is a Root directory and a number of branches bearing
directories and subdirectories ("folders")
 This file structure is implemented using logical links, rather
than by physically positioning the data on the disk
o The links are addresses placed in a lookup table
o Each data file on the disk itself is usually distributed
arbitrarily over the disk, to allow efficient use and re-
use of the available space
Disk File Structures
 Some viruses work by destroying or
scrambling the information in the File
Allocation Table
o This makes all files inaccessible
o However, the actual file data in the
clusters is not destroyed
o Do the disk can be repaired if the
FAT can be re-built
 Most systems keep a backup copy of the
FAT in a different place
o Some viruses find and destroy the
backup copy too
 In UNIX, LINUX and later versions of
Windows, the FAT system is replaced by a more secure scheme ("inodes")
54

Logic and Digital Systems

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Logic and Digital Systems

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Haroon Chughtai

Some Terminology ........................................................................................................................ 15

Monostable Flip-Flop ........................................................................................................................ 25

Arithmetic Logic Unit .................................................................................................................... 37

Interrupt Service Subroutine ........................................................................................................ 48

1.1 Digital Vs. Analogue

Advantages of Digital Systems

Disadvantages of Digital Systems

Basic Logic Principles

1.2 Logic Devices

1.3 Boolean Logic and Logic Gates

Boolean Operators and Gates

Boolean Relationships and Forms

Simplification and Minimisation

 Here the adjacent squares differ only in A so

1.4 Binary Arithmetic

Binary Number System

 In each position we have a BInary digiT (BIT)

Conversion: Decimal to Binary

Multi-bit Full Adder

Binary Subtraction and Signed Numbers

Summary of Unsigned and Signed Operation of an Adder Circuit

1.5 Sequential Logic

Basic Bistable Circuit

Transparent Latch (Gated D Latch)

Delays and Glitches in Ripple Counters

The J-K Flip-Flop

 Operation after next clock pulse

Summary: Synchronous and Asynchronous Sequential Logic

 The label means that the four possible

1.7 Memory Devices and Programmable Logic Devices

Read Only Memory (ROM)

Typical ROM Device

Field Programmable ROM (PROM)

Programmable Logic Devices

Summary of Programmable Logic Devices

Timing Hazards in PLDs

Memory Devices Summary

1.8 Application: Heart Rate Metre

1.9 Other Notations for Binary Numbers

o Whereas the character 'S' is 0 1 0 1 0 0 1 1 = 83 or 53H

2.1 Introduction to Microprocessors

Arithmetic Logic Unit

Basic Microprocessor Operation

2.2 Assembly Programming

Arithmetic and Logical

 Arithmetic right-shift accum. or memory loc: ASRA, ASRB, ASR

 Complement accum or memory location: COMA, COMB, COM

Counting Loop Example

2.3 Data I/O

The Peripheral Interface Adaptor (PIA)

Getting the Input Value

Problem with Polling

2.4 Digital-Analogue Interconversion and Pentium 386

 Two main types

2.5 The Operating System

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