Mega65 Developer Guide

MEGA65 TEAM
Dr. Paul Gardner-Stephen Detlef Hastik

(highlander) (deft)
Founder Co-founder
Software and virtual hardware architect General manager
Spokesman and lead scientist Marketing and sales
Martin Streit Oliver Graf

(seriously) (lydon)
Video and photo production Release management
Tax and organization VHDL and platform enhancements
Social media Antti Lukats
(antti-brain)
Dan Sanderson
Host hardware design and production
(dddaaannn)
Media and documentation Dieter Penner
MEGA65.ROM (doubleflash)
Host hardware support
Dr. Edilbert Kirk
(Bit Shifter) Mirko H.
MEGA65.ROM (sy2002)
Manual and tools Additional platforms and consulting
Gábor Lénárt Gürçe Işıkyıldız

(LGB) (gurce)
Emulator Tools and enhancements
Daniel England
Farai Aschwanden (Mew Pokémon)
(Tayger) Additional code and tools
Filehost and tools
Financial advisory Hernán Di Pietro
(indiocolifa)
Falk Rehwagen Additional emulation and tools
(bluewaysw) Roman Standzikowski
GEOS (FeralChild)
Open ROMs
Robert Steffens
(kibo) Anton Schneider-Michallek
Network technology (adtbm)
Core bug hunting Presentation and support
Reporting Errors and Omissions
This book is being continuously refined and improved upon by the MEGA65 community.
The version of this edition is:
commit d f 0 9 a 5 1 5 1 6 7 5 2 5 c c 5 b 2 e e a 2 9 c d 1 7 b a 1 c d 3 d e 5 6 3 9
date : Fri Feb 16 1 7 : 3 9 : 3 9 2024 -0800
We want this book to be the best that it possibly can. So if you see any errors, find
anything that is missing, or would like more information, please report them using the
MEGA65 User’s Guide issue tracker:
https://github.com/mega65/mega65-user-guide/issues
You can also check there to see if anyone else has reported a similar problem, while
you wait for this book to be updated.
Finally, you can always download the latest versions of our suite of books from these
locations:
• https://mega65.org/mega65-book
• https://mega65.org/user-guide
• https://mega65.org/developer-guide
• https://mega65.org/basic65-ref
• https://mega65.org/chipset-ref
• https://mega65.org/docs
3
Developing for the MEGA65
Published by
the MEGA Museum of Electronic Games & Art e.V., Germany.
WORK IN PROGRESS
Copyright ©2019 – 2024 by Paul Gardner-Stephen, the MEGA Museum of Electronic
Games & Art e.V., and contributors.
This reference guide is made available under the GNU Free Documentation License
v1.3, or later, if desired. This means that you are free to modify, reproduce and re-
distribute this reference guide, subject to certain conditions. The full text of the GNU
Free Documentation License v1.3 can be found at https://www.gnu.org/licenses/
fdl-1.3.en.html.
Implicit in this copyright license, is the permission to duplicate and/or redistribute this
document in whole or in part for use in education environments. We want to support
the education of future generations, so if you have any worries or concerns, please
contact us.
February 17, 2024
ii
Contents
1 Introduction xi
Welcome to the MEGA65! . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Other Books in this series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
Come Join Us! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
I INTRODUCTION 1
2 Welcome, and thank you! 3
3 Other Resources 7
II CROSS-PLATFORM DEVELOPMENT TOOLS 11
4 Emulators 13
Using The Xmega65 Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . 15
The keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Apple MacOS start problems . . . . . . . . . . . . . . . . . . . . . . . 16
Updating settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Using the Live ISO image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Creating a Bootable USB stick or DVD . . . . . . . . . . . . . . . . . . 17
iii
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Other Features of the Live ISO . . . . . . . . . . . . . . . . . . . . . . . 19
5 Data Transfer and Debugging Tools 21

m65 command line tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Screenshots using m65 tool . . . . . . . . . . . . . . . . . . . . . . . . 23
Load and run a program on the MEGA65 . . . . . . . . . . . . . . . . . 24
Reconfigure the FPGA to run a different bitstream . . . . . . . . . . . . 24
Remote keyboard entry . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Unit testing and logging support . . . . . . . . . . . . . . . . . . . . . . 25
Using unit tests with C . . . . . . . . . . . . . . . . . . . . . . . 25
Using unit tests with BASIC 65 . . . . . . . . . . . . . . . . . . 26
BASIC 65 example . . . . . . . . . . . . . . . . . . . . . . . . . 27
M65Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
mega65_ftp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TFTP Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Converting a BASIC text file listing into a PRG file . . . . . . . . . . . . . . . 30
6 Assemblers 33
7 C and C-Like Compilers 37

MEGA65 libc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8 MEGA65 Standard C Library 41

Structure and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
conio.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
conionit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
setscreenaddr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
getscreenaddr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
setcolramoffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
iv
getcolramoffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
setcharsetaddr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
getcharsetaddr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
clrscr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
getscreensize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
setscreensize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
set16bitcharmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
sethotregs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
setextendedattrib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
togglecase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
togglecase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
togglecase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
bordercolor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
bgcolor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
textcolor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
revers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
highlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
blink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
underline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
altpal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
clearattr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
cellcolor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
setpalbank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
setpalbanka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
getpalbank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
getpalbanka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
setmapedpal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
getmapedpal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
v
setpalentry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
fillrect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
hline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
vline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
gohome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
gotoxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
gotox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
gotoy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
moveup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
movedown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
moveleft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
moveright . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
wherex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
wherey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
pcputc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
pcputsxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
cputcxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
pcputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
cputc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
cputnc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
cputhex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
cputdec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
cputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
cputsxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
cputcxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
cputncxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
cprintf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
vi
pcprintf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
cgetc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
kbhit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
getkeymodstate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
flushkeybuf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
cinput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
VIC_BASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9 BASIC Tokenisers 63
III NATIVE DEVELOPMENT TOOLS 67
10 C65 Memory Monitor 69
11 MEGA65 Matrix Mode 71
12 Turbo Assembler 73
13 Dealing with C65 and C64-mode 75
IV MEGA65 Operating System 79
14 Developing System Programmes 81

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Flash Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Format/FDISK Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Keyboard Test Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MEGA65 Configuration Utility . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Freeze Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Freeze Menu Helper Programmes . . . . . . . . . . . . . . . . . . . . . . . . 87
Hypervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
vii
OpenROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
15 MEGA65 Hyppo Services 89

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
General Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Drive/Storage Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Disk Image Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Task and Process Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
System Partition Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Freezer Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
V MULTI-MEDIA AND DATA CONVERSION 151
VI GEOS Development 153
VII HARDWARE 155
16 Using Nexys4 boards as a MEGA65 157

Building your own MEGA65 Compatible Computer . . . . . . . . . . . . . . 161
Working Nexys4 Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
The Nexys4 board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
The Nexys4DDR board . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
The Nexys A7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Power, Jumpers, Switches and Buttons . . . . . . . . . . . . . . . . . . . . . 164
Micro-USB Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
External Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Other Jumpers and Switches . . . . . . . . . . . . . . . . . . . . . . . . 166
Connections and Peripherals . . . . . . . . . . . . . . . . . . . . . . . 167
Communicating with your PC . . . . . . . . . . . . . . . . . . . . . . . 167
viii
Onboard buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Some key mappings with a USB keyboard . . . . . . . . . . . . . . . . 170
Preparing microSDHC card . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Preparation Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Loading the bitstream from QSPI . . . . . . . . . . . . . . . . . . . . . . . . 173
Preparation Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Widget Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
PMOD-to-Joystick Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Useful Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
VIII APPENDICES 179
A Flashing the FPGAs and CPLDs in the MEGA65 181

Suggested PC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Installing Vivado . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Installing the FTDI drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Linux drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Windows drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Flashing the main FPGA using Vivado . . . . . . . . . . . . . . . . . . . . . . 207
Flashing the CPLD in the MEGA65’s Keyboard with Lattice Diamond . . . . . 220
Flashing the MAX10 FPGA on the MEGA65’s Mainboard with INTEL QUARTUS 227
B Trouble shooting 233

Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
No Digital Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . 235
MEGA65 R4, R5, R6 . . . . . . . . . . . . . . . . . . . . . . . . 235
No lights when powering on . . . . . . . . . . . . . . . . . . . . . . . . 235
ix
Vivado . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
RAM requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
mega65_ftp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Missing Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
C Schematics 239
MEGA65 R3 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
MEGA65 R2 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Nexys Widget Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . 289
D Supporters & Donors 293

Organisations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Contributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Supporters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
INDEX 307
x
CHAPTER 1
Introduction
• Welcome to the MEGA65!
• Other Books in this series
• Come Join Us!
xii
WELCOME TO THE MEGA65!
Congratulations on your purchase of one of the most long-awaited computers in the
history of computing! The MEGA65 is community designed, and based on the never-
released Commodore® 651 computer; a computer designed in 1989 and intended
for public release in 1990. Decades have passed, and we have endeavoured to invoke
memories of an earlier time when computers were simple and friendly. They were not
only simple to operate and understand, but friendly and approachable for new users.
These 1980s computers inspired many of their owners to pursue the exciting and re-
warding technology careers they have today. Just imagine the exhilaration these early
computing pioneers experienced, as they learned they could use their new computer
to solve problems, write a letter, prepare taxes, invent new things, discover how the
universe works, and perhaps even play an exciting game or two! We want to re-awaken
that same level of excitement (which alas, is no longer found in modern computing),
so we have created the MEGA65.
The MEGA65 team believes that owning a computer is like owning a home. You don’t
just use a home; you change things, big and small, to make it your own custom living
space. After a while, when you settle in, you may decide to renovate or expand your
home to make it more comfortable, or provide more utility. Think of the MEGA65 as
your very own “computing home”.
This guide will teach you how to do more than just hang pictures on a wall; it will show
you how to build your dream home. While you read this user’s guide, you will learn
how to operate the MEGA65, write programs, add additional software, and extend
hardware capabilities. What won’t be immediately obvious is that along the journey,
you will also learn about the history of computing as you explore the many facets of
BASIC version 65 and operating system commands.
Computer graphics and music make computing more fun, and we designed the
MEGA65 to be fun! In this user’s guide, you will learn how to write programs using
the MEGA65’s built-in graphics and sound capabilities. But you don’t need to be a
programmer to have fun with the MEGA65. Because the MEGA65 includes a com-
plete Commodore® 64™2 , it can also run thousands of existing games, utilities, and
business software packages, as well as new programs being written today by Com-
modore computer enthusiasts. Excitement for the MEGA65 will grow as we all witness
the programming marvels our MEGA65 community create, as they (and you!) discover
and master the powerful capabilities of this modern Commodore computer recre-
ation. Together, we can build a new “homebrew” community, teeming with software
1 Commodore is a trademark of C= Holdings
2 Commodore 64 is a trademark of C= Holdings
xiii
and projects that push the MEGA65’s capabilities far beyond what anyone thought
would be possible.
We welcome you on this journey! Thank you for becoming a part of the MEGA65
community of users, programmers, and enthusiasts!
OTHER BOOKS IN THIS SERIES

This book is one of several within the MEGA65 documentation suite. The series in-
cludes:
• The MEGA65 User’s Guide
Provides an introduction to the MEGA65, and a condensed BASIC 65 command
reference
• The MEGA65 BASIC 65 Reference
Comprehensive documentation of all BASIC 65 commands, functions and oper-
ators
• The MEGA65 Chipset Reference
Detailed documentation about the MEGA65 and C65’s custom chips
• The MEGA65 Developer’s Guide
Information for developers who wish to write programs for the MEGA65
• The MEGA65 Complete Compendium
(Also known as The MEGA65 Book)
All volumes in a single huge PDF for easy searching. 1200 pages and growing!
COME JOIN US!

Get involved, learn more about your MEGA65, and join us online at:
• https://mega65.org/chat
• https://mega65.org/forum
xiv
PART I
INTRODUCTION
2
CHAPTER 2
Welcome, and thank you!
4
I would like to begin by thanking you for your interest in the MEGA65, and in developing
software to run on it. The success of the MEGA65 as a fun retro-computing platform
depends on there being enough interesting software for people to run on it. This
requires the generous work of developers like yourself. So, again, thank you!
But developing for the MEGA65 is not merely a case of giving to the benefit of others.
We have tried hard to create a machine that is as fun to program as the Commodore
64, but with some of the barriers and frustrations worn down somewhat. That is, it is
our intention that people develop on the MEGA65 because it is fun, and then enjoy
the process. That is, the journey should very much be the destination.
Now, in saying that, the MEGA65 is quite new, and we have been flat out creating the
machine. This means that some development tools are not as ready or as simple or
integrated as we would like. Improving the tools is also an area where we hope that
many of you will enjoy contributing, so that developing for the MEGA65 can become
accessible to as many people as possible.
If you encounter barriers to your journey of developing for the MEGA65, please do let
us know, and consider creating solutions that can be shared with others. This will help
everyone to enjoy being an active part of the MEGA65 ecosystem.
Finally, my apologies to anyone who has developed tools or utilities for the MEGA65
that have escaped my memory as I have written this document. If this is the case,
please drop me an email, and I’ll update this document to include them.
5
6
CHAPTER 3
Other Resources
8
This book focusses on the process of developing for the MEGA65. To avoid it be-
ing a thousand pages long, it doesn’t describe the inner workings of the MEGA65,
except where you need to know about them, so that you can engage in the develop-
ment process. For example, if you wish to know about the capabilities of the various
custom chips in the MEGA65, and which registers do which things, please refer to the
MEGA65 Book online at https://github.com/mega65/mega65-user-guide, or con-
sider purchasing one or more of the reference volumes for the MEGA65, from which
the MEGA65 Book is formed. For example, the MEGA65 Chipset Reference Guide or
the MEGA65 Assembly Language Reference Guide.
We also hope that you, the developer community, will contribute to those books, or
write your own material that can help others in their journies with developing for the
MEGA65.
9
10
PART II
CROSS-PLATFORM
DEVELOPMENT TOOLS
12
CHAPTER 4
Emulators
• Using The Xmega65 Emulator
• Using the Live ISO image
14
At the time of writing, there is only one emulator for the MEGA65, xmega65; LGB’s
Xemu emulator suite. The LGB developers work hard to keep up with the development
of the MEGA65; however, some MEGA65 emulation may not be accurate but should
be sufficient for software development on the MEGA65.
During development, frequently test software on real hardware, such as a MEGA65 or
FPGA board capable of running a MEGA65 core.
Download the MEGA65 emulator source code from https://github.com/
lgblgblgb/xemu.
Download pre-compiled versions from https://github.lgb.hu/xemu/. Installers are
available for macOS, Windows and Linux.
A live ISO image containing the emulator, documentation, and other tools
is available from Forum64.de at https://www.forum64.de/index.php?thread/
104698-xemu-live-system-iso-file/&postID=1549927#post1549936. Should
you choose to use it you may find instructions on page 17.
USING THE XMEGA65 EMULATOR

The keyboard
The MEGA65 keyboard layout is based on the Commodore 65, which is unlike a mod-
ern PC keyboard. In most cases, the Xmega65 emulator recognizes PC keys as their
Shift
equivalent MEGA65 keys, such as letters, numbers, and common modifiers like .
Xmega65 assumes an American/U.S. layout.
Some keys are only present on the MEGA65 keyboard and have no PC equivalents.
Insert Home Page Page
Xmega65 uses the PC keys , Delete , , End , Up , and Down to represent
+ , £ , CLR
HOME ,
RUN
STOP ,
HELP
, and
RESTORE
, respectively.
15
RUN RESTORE
On most PC keyboards, this places STOP and next to each other, to make that
key combination easy to enter.
This diagram shows the PETSCII glyphs as they appear on a MEGA65 keyboard, with
the ` glyph on the left and the Shift
glyph on the right. Note that on a PC keyboard,
the key for ` is to the right of the Shift
.
Enter
Xemu lets you have two joysticks (one at a time) on the numeric keypad. over
there is used to toggle ports 1, 2 and to off when pressed repeatedly.
Please be aware the emulator by default catches F9 F10 F11 as shortcuts

of its own functions. If you want to use these keys with the emulated MEGA65, you
must configure the keyboard mapping. The files are found in the folder for Xemu’s
settings as explained on page 17. This is done by copying keymap-default.cfg
into keymap.cfg and then removing the following lines:
XEMU-EXIT F9
XEMU-FULLSCREEN F11
and changing:
F9 Unknown
F11 Unknown
into:
F9 F9
F11 F11
With these keys remapped, the full-screen and exit functions are still available from
the menu. Right-click (or control-click) anywhere in the window to access it.
Apple MacOS start problems

If a message macOS cannot verify that this app is free from malware
pops up use the following procedure when you open the app for the first time:
• Open Finder on your Mac.
• Control-click (or right-click) on the Xmega65 app icon.
• In the context menu, select Open.
16
• The message appears again, but this time there is an Open button. Click Open.
You only need to perform this procedure the first time you run the app. From now
on, you can open the app normally.
Updating settings
You may wish to edit the Xemu settings file to change the keyboard mapping or make
a backup of the SD card image file. To access these files from within Xemu, open the
menu, select Debug / Advanced then Browse system folder. Edit the keymap-
default.cfg and mega65-default.cfg files with a text editor. For specific in-
structions on how to change keymap-default.cfg please refer to page 15.
The Xemu system folder location varies by operating system:

• Windows (may be copied into the address bar of the file explorer):
%appdata%\xemu-lgb\mega65
• Linux: ~/.xemu-lgb/
• Macintosh: ~/Library/Application\ Support/xemu-lgb/mega65/
USING THE LIVE ISO IMAGE

The Live ISO image is the product of a volunteer community; not the MEGA65 team.
We include it for your convenience.
Creating a Bootable USB stick or DVD

There are many ways to create a live ISO image. The method you choose depends
on your operating system and whether you wish to install to a USB drive or burn it to
17
a DVD. Burning to a DVD is straightforward, assuming you own a computer that has a
DVD writer. If you wish to create a faster bootable USB drive, try one of the methods
below:
If you are using Windows, consider a tool like http://www.isotousb.com/.
On Linux, you can use the instructions at https://fossbytes.com/
create-bootable-usb-media-from-iso-ubuntu/.
For Apple Macs, consider these instructions at https://ubuntu.com/tutorials/
create-a-usb-stick-on-macos#1-overview.
Similar instructions are available for other popular computers, such as Ami-
gas (https://forum.hyperion-entertainment.com/viewtopic.php?t=3857), or
Sun UltraSPARC workstations (https://forums.servethehome.com/index.php?
threads/how-to-create-a-bootable-solaris-11-usb.1998/).
Finally, the popular, easy-to-use, and free cross-platform belanaEtcher is available at
https://www.balena.io/etcher/.
Getting Started
To avoid potential copyright issues, the bootable ISO image does not include propri-
etary ROMs for the MEGA65; such as legacy C65 ROMs. It does include an open-
source replacement ROM from our OpenROMs project. This ROM will boot into a
BASIC 2 environment that you can use to load and execute many C64 programs as
shown in the image below:
If you wish to use a C65 ROM that includes BASIC 10, download the appropriate ROM
file and place it on another USB stick named MEGA65.ROM. On start-up, the MEGA65
will ask if a ROM has been downloaded; as shown in the image below:
18
If the Live ISO cannot find a ROM, it will prompt you to download a ROM; as shown
below:
Other Features of the Live ISO

As the previous screen-shots show, the Live ISO provides various and convenient desk-
top shortcuts. On the left-hand side, there are shortcuts for launching the MEGA65
emulator and the C65 emulator so you can test that programs will run on both plat-
forms. As previously mentioned, both emulators are a work in progress and may not
be 100% compatiable.
Another link provides access to the MEGA65 Book. This all-in-one volume, of apporix-
mately 800 pages, contains the official MEGA65 documentation. The majority of this
developer’s guide is also present in the MEGA65 Book.
19
This ISO also includes documentation for the C65 Notepad; a program for the C65
and MEGA65 written by Snoopy (the developer of the Live ISO image). A “read me”
file contains further information about the Live ISO.
Finally, on the right-hand side, there are links to download a C65 ROM and to update
the MEGA65 Book to the latest version. This will ensure you don’t need to create a
new bootable image each time a frequent update is made to the MEGA65 Book.
To access all contents of the Live ISO image, use the file explorer.
20
CHAPTER 5
Data Transfer and Debugging
Tools
• m65 command line tool
• M65Connect
• mega65_ftp
• TFTP Server
• Converting a BASIC text file listing into
a PRG file
22
The key to effective cross-platform development is having quick and easy means to
deploy and test software on the MEGA65. This is especially true while the MEGA65
emulator continues to be developed. In fact, even once the MEGA65 emulator is com-
plete, it is unlikely that it will be able to offer full compatibility at full speed, because
the MEGA65 is much more demanding to emulate than the C64.
There are a variety of tools that can be used for data transfer and debugging.
These typically function using either the MEGA65’s serial monitor interface, or via the
MEGA65’s fast ethernet adapter. The serial monitor interface is available via the UART
lines on the JB1 header.
If you do not have access to the serial monitor interface, there are tools being devel-
oped for the fast ethernet port that provide some, but not all, of the capabilities of the
serial monitor interface. These will be documented as they become available. The re-
mainder of this chapter focusses on methods that access the serial monitor interface.
You can either connect a 3.3V UART adapter to the appropriate lines, or more con-
veniently, connect a TE-0790-03 JTAG debug module onto this connector. This gives
you a USB connection that can be used for injecting software, remote debugging and
memory inspection, as well as activating or flashing bitstreams. With this connection,
there are the following tools:
M65 COMMAND LINE TOOL

The https://github.com/mega65/mega65-tools repository contains a number of
tools, utilities and example programs. These tools are mainly for Linux but can be used
on Windows with Cygwin. One of those is the m65 command line tool. This is rather a
swiss-army knife collection of utilities in one. Common useful functions include:
Screenshots using m65 tool

To take a screenshot of the MEGA65 use:
m65 -S
This will create a file called mega65-screeen-000000.png, or if that file already

exists, the first non-used number will be used in place of 000000.
Note that this screenshot function works by having m65 emulate the function of the
VIC-IV. Thus while it produces excellent looking digital screenshots, it may not exactly
match the real display of the MEGA65. At the time of writing it does not render sprites
or bitplanes, only text and bitmap-based video modes.
23
Load and run a program on the MEGA65
To load and run a program on the MEGA65, you can use a command like:
m65 -F -4 -r foo . prg
The -F option tells m65 to reset the MEGA65 before loading the program.
The -4 option tells m65 to switch the MEGA65 to C64-mode before loading the pro-
gram. If this is left off, then it will attempt to load the program in C65-mode.
The -r option tells m65 to run the program immediately after loading.
Note that this command works using the normal BASIC LOAD command, and is thus
limited to loading programs into the lower 64KB of RAM
Reconfigure the FPGA to run a different bitstream

To try out a different MEGA65 bitstream, a command like the following can be used:
m65 -b b i t s t r e a m . bit
This will cause the named bitstream to be sent to the FPGA. As the FPGA will be re-
configured by this action, and program currently running will not merely be stopped,
but also main memory will be cleared. For models of the MEGA65 that are fitted with
8MB or 16MB of expansion memory, those expansion memories are implemented in
external chips, and so the contents of them will not be erased.
For non-MEGA65 bitstreams (such as zxunomega65 and gbc4mega65), use the ’-q’
argument instead:
m65 -q b i t s t r e a m . bit
Remote keyboard entry

The MEGA65’s keyboard interface logic supports the injection of synthetic key events
using the registers $D615 – $D617. The m65 utility uses this to allow remote typing
on the MEGA65 in a way that is transparent to software. There are three ways to use
this:
m65 -t s o m e t e x t
This form types the supplied text, in this case sometext, but does not simulate pressing
RETURN RETURN
. If you wish to simulate the pressing of , use -T instead of -t, e.g.:
24
m65 -T list
This would cause the LIST command to be typed and executed.

Finally, it is possible to begin general remote keyboard control via:
m65 -t -
In this mode, any key pressed on the keyboard of the computer where m65 is running
will be relayed to the MEGA65. Note that not all special keys are supported, and
that there is some latency, so using key repeat can cause unexpected results. But for
general remote control, it is a very helpful facility.
Unit testing and logging support

The m65 tool includes support to facilitate remote unit testing directly on MEGA65
hardware. When unit testing mode is active, m65 waits for the MEGA65 to send cer-
tain byte sequences over the serial interface which signal the current state (started,
passed, failed) of a given test. Additionally, it is possible to send log messages from
the MEGA65 to the host computer.
Unit testing mode is entered by calling m65 with the -u flag. To run a remote BASIC
program in C65-mode and simultaneously put m65 into unit testing mode, the following
command can be used:
m65 - Fur attic - ram . prg -w tests . log
The -F and -r options tell m65 to reset the MEGA65 before loading the program
”attic-ram.prg” and then automatically run it. The -u option then tells m65 go into unit
testing mode instead of exiting after launching the program. The optional -w option
makes m65 append the test results to the file ”test.log” (creating the file if it doesn’t
exist).
Please note that m65 automatically exits from unit testing mode if no test state signals
were received for over 10 seconds.
Support is provided for sending unit test signals to the host computer from C and BASIC
65 programs:
Using unit tests with C

The MEGA65 libc contains support for unit testing via functions defined in tests.h
and tests.c.
To signal the start of a test, include tests.h and use
25
unit_test_setup("testName",issueNumber);
where ”testName” is a human-readable name of the test (e.g. ”VIC-II”) and issueNum-
ber a reference to the corresponding bug issue (for example, the issue number from
github).
After starting a test, it’s possible to signal passed tests with the unit_test_ok() function:
unit_test_ok();
A failed test is signalled with unit_test_fail():
unit_test_fail("fail message");
Each time the unit_test_ok() or unit_test_fail() functions are called, the sub issue of the
test (reported on the host computer) is incremented. This makes it easier to combine
and identify multiple tests in one file.
You can send arbitrary log messages via unit_test_log():
unit_test_log("hello world from mega65!");
...and finally, when all is done, the end of unit testing is signalled by the use of
unit_test_done();
Using unit tests with BASIC 65

b65support.bin is a machine language module providing support for unit testing
from BASIC 65, available in the bin65 folder of the mega65-tools repository. This
module works by redirecting the USR vector to perform the functions needed to com-
municate with the testing host.
In an automated test scenario, you may want to inject the b65support.bin binary
into MEGA65 RAM by using m65:
m65 -@ mega65 - tools / bin65 / b 6 5 s u p p o r t . b i n @ 1 5 f e
Of course it’s also possible to load b65support.bin directly from the MEGA65 by
mounting the M65UTILS.D81 image from the freezer and issuing
BLOAD " B 6 5 S U P P O R T . BIN "
After loading, b65support.bin is initialised with
SYS $1600
Once initialised, the following functions are provided by b65support.bin:
26
A = USR ( < issueNum >)
prepares a new test with number <issueNum> and resets subissue number to 0
A = USR ("= < testName >")
sets test name and sends test start signal; for example: A=USR("=VIC-III") sets
the test name to ’VIC-III’ and signals the host computer that the test has started.
A = USR ("/ < logMessage >)
sends a log message to the host computer
A = USR (" P ")
sends the ’passed’ signal to the host computer and increases the sub issue number
A = USR (" F ")
sends the ’test failed’ signal to the host computer and increases the sub issue number
A = USR (" D ")
sends the ’test done’ signal to the host computer

All calls return the current sub issue number or ?ILLEGAL QUANTITY ERROR in case
of calling an invalid command.
BASIC 65 example
The following is a complete BASIC 65 example showing how to use m65’s unit testing
features:
27
100 rem attic ram cache test
110 poke $bfffff2 , $e0 : rem enable attic ram cache
120 sys $1600 : rem init test module
130 a = usr (379) : rem set issue number
140 a = usr ("= attic - ram - cache ") : rem set test name
150 ba nk1 28 : poke0 ,65 : rem just to be sure
160 b0 = $ 8 0 0 0 0 0 0 : b1 = $ 8 0 0 0 1 0 0 : rem attic ram areas to be tested
170 for r =0 to $ff
180 poke b0 +r ,0 : rem fill area 1 with 0
190 poke b1 +r , $ff : rem fill area 2 with $ff
200 next r
210 for t =1 to 10 : rem 10 tries
220 poke b0 ,32 : rem write to b0
230 for x =0 to $ff : t1 = b1 + x
240 a = peek ( b0 ) : rem read from b0
250 b = peek ( t1 ): b = peek ( t1 ) : rem read twice from t1
260 ifb < >255 thenf = t : t =11: x =256 : rem this shouldn ' t happen
270 next x
280 next t
290 if f =0 then begin
300 print " no faults d e t e c t e d after "; t ;" tries ."
310 a = usr (" p ") : rem signal ' test passed ' to host
320 bend : else begin
330 a = usr (" f ") : rem signal ' test failed ' to host
340 print " hyper ram fault d e t e c t e d after "; f ;" tries ."
350 print " peek ( $ "; hex$ ( t1 );") [ t1 ] is "; b ;" but should be 255"
360 bend
370 a = usr (" d ") : rem test done
M65CONNECT
This is a cross-platform graphical tool available for Windows, Linux and MacOSX, which
allows access to most of the functions of the m65 command-line tool, without needing
to use a command line, or being able to compile the tool for your preferred operating
system.
The repository for M65Connect is: https://github.com/MEGA65/m65connect
The latest binary version is available from https://files.mega65.org.
28
With the MEGA65 or Nexys FPGA switched off, connect a USB cable from your com-
puter to the MEGA65 or Nexys FPGA board. Run the M65Connect executable and
follow the prompts to connect. The program will help you identify which USB Serial
Port to communicate over.
With this tool you can easily transfer PRG programs and a variety of other files.
M65Connect can handle the transfer, switching to C64-mode, and execution of pro-
grams.
MEGA65_FTP
The mega65_ftp utility from the https://github.com/mega65/mega65-tools
repository is a little misleadingly named: While it is a File Transfer Program, it does
not use the File Transfer Protocol (FTP). Rather, it uses the serial monitor interface to
take remote control of a MEGA65, and directly access its SD card to enable copying
of files between the MEGA65 and the host computer.
Note that it does not perfectly restore the MEGA65’s state on exit, and thus should
only be used when the MEGA65 is at the READY prompt, so that any running software
doesn’t go haywire. In particular, you should avoid using it when a sensitive program
is running, such as the Freeze Menu, MEGA65 Configuration Utility, or the MEGA65
Format/FDISK utility. (This problem could be solved with a little effort, if someone has
the time and interest to fix it).
When run, it provides an FTP-like interface that supports the get, put, rename and
dir commands. Note that when putting a file, you should make sure that it is given
a name that is all capitals and has o DOS-compatible 8.3 character file name. This
is due to limitations in both mega65_ftp and the MEGA65’s Hypervisor’s VFAT32 file
system code. Again, these problems could be fixed with a modest amount of effort
on the part of a motivated member of the community.
Finally, the mega65_ftp program is very slow to push new files to the MEGA65, typ-
ically yielding speeds of around 5KB/sec. This is partly because the serial monitor
interface is capable of transferring data at only 40KB/sec (when set to 4,000,000
bits per second), and partly because the remote control process results in a lot of
round-trips where helper routines are executed on the MEGA65 to read, write and
verify sectors on the SD card. It would be quite feasible to improve this to reach close
to 40KB/sec, and potentially faster using either some combination of data compres-
sion, de-duplication of identical sectors (especially when uploading disk images) and
other techniques. Again, this would be a very welcome contribution that someone in
the community could contribute to everyone’s benefit.
29
TFTP SERVER
Work on a true TFTP server for the MEGA65 that supports fast TFTP transfers over
the 100mbit ethernet has begun, and can be used to very quickly read files from the
MEGA65. Speeds of close to 1MB/sec are possible, depending on SD card perfor-
mance. Rather than using DHCP, this utility will respond to any IP address that ends in
.65. It always uses the MAC address 40:40:40:40:40:40. True DHCP support as well
as using the MEGA65’s configured ethernet MAC address may be added in the future.
More importantly, support for writing files to the SD card is not yet complete, and
is blocked by the need for the implementation of the necessary functions in the
MEGA65’s Hypervisor for creating and growing files. A particular challenge is en-
abling the creation of files with contiguous clusters as is required for D81 disk images:
If a D81 file is fragmented, then it cannot be mounted, because the mounting mech-
anism requires a pointer to the contiguous block of the SD card containing the disk
image. In the interim, mega65_ftp can be used as a substitute.
CONVERTING A BASIC TEXT FILE

LISTING INTO A PRG FILE
If you have a untokenised BASIC program in plain text format sourced from somewhere
like an internet post, and you wish to try it on the MEGA65 without typing it in, it is
possible to convert it to a PRG.
C64List is a Windows-based command-line tool that will allow you to make the con-
version. Once you have a .PRG file, you can use a tool like M65Connect to upload it
to the MEGA65 or Nexys FPGA.
C64List is available for download from http://www.commodoreserver.com/
Downloads.asp
Ensure you have a program listing saved to a file on your local computer (for example,
program.txt) encoded as ANSI or UTF8.
Use C64List to convert the file to a PRG file using:
C64List program.txt -prg
Now you can upload your newly converted program to the MEGA65 with M65Connect
or one of the other tools described previously.
30
It is worth noting that this method will not be 100% effective on listings with special
PETSCII characters. Programs with PETSCII will require some editing on the MEGA65
itself before saving to disk.
31
32
CHAPTER 6
Assemblers
34
The table below shows an overview of assemblers known to work with MEGA65. For
general use we recommend ACME as it has good support for the 45GS02 instruction
set; is open source; and finally written in C. The latter means that it may be ported to
run natively on the MEGA65 in the future.
Name 45GS02 Source Reference

ACME yes C https://sourceforge.net/projects/acme-crossass
KickAss yes Java gitlab.com/jespergravgaard/kickassembler65ce02
LLVM-MOS yes C++ https://llvm-mos.org/wiki/Welcome
Ophis yes Python https://github.com/michaelcmartin/Ophis
BSA yes C https://github.com/Edilbert/BSA
CA65 no1 C https://github.com/mega65/cc65
The BSA assembler is currently used to build the MEGA65.ROM. Most of this source
code is written in the syntax of the ancient BSO assembler (Boston Systems Office),
which was used in the years 1989 - 1991 by software developers, working on the C65.
The BSA Assembler has a compatibility mode, which makes it possible to assemble
these old source codes with minor or none modifications. The BSA Assembler has
currently only a description of commands embedded in the C-source of the assembler.
The LLVM-MOS project comes with a GNU compatible macro assembler and disas-
sembler that supports all mnemonics of the 45GS02. It can be used as a stand-alone
tool with the command llvm-mc.
1 Our fork of CA65 (part of CC65) correctly detects the MEGA65’s CPU, but has no explicit support for
the processor’s features
35
36
CHAPTER 7
C and C-Like Compilers
• MEGA65 libc
38
Short answer: CC65 and KickC both work on the MEGA65.
Both CC65 and KickC are known to work on the MEGA65. However, both by default
have only a C64 memory model, and use only 6502 opcodes. It would be super for
someone to create a C65 memory configuration for CC65, and should not be too
hard to do.
CC65 supports overlays, which could be powerfully used with the MEGA65’s extra
memory to allow programs larger than 64KB. However, this would require writing a
suitable loader for such programs, which also does not yet exist.
Similarly, modifying the code generator of CC65 to use 45GS02 features would
not be particularly difficult to do, and would help to overcome the otherwise horri-
bly slow and bloated code that CC65 produces. Also adding first-class support for
the 45GS02 CPU features in CA65 (or perhaps even better, making CC65 produce
ACME compatible assembly output) would be of tremendous advantage, and not par-
ticularly hard to do. These would all be great tasks to tackle while you wait for your
MEGA65 DevKit to arrive!
An example template for a C program that can be compiled using CC65 and exe-
cuted on the MEGA65 can be found in the repository https://github.com/MEGA65/
hello-world. This repository will even download and compile CC65, if you don’t al-
ready have it installed on your system. This repository should work on Linux and Mac,
and on Windows under the Windows Subsystem for Linux (WSL).
The LLVM-MOS project (https://llvm-mos.org) has a MEGA65 target that has been
tested with C99, C++11, and Rust. The LLVM MOS compiler has support for 45GS02
instructions (-mcpu=mos45gs02) and comes with an assembler and disassembler. Pre-
compiled binaries of the SDK are available for Linux, Windows, and macOS.
MEGA65 LIBC
A C library is being developed for the MEGA65, and which already includes a num-
ber of useful features. This library is available from http://github.com/mega65/
mega65-libc. The procedures, functions and definitions it provides are documented
in a separate chapter.
The MEGA65 libc is currently available only for LLVM and CC65, although we would
welcome someone maintaining a KickC port of it.
39
40
CHAPTER 8
MEGA65 Standard C Library
• Structure and Usage
• conio.h
42
A C library is being developed for the MEGA65, and which already includes a num-
ber of useful features. This library is available from http://github.com/mega65/
mega65-libc. The procedures, functions and definitions it provides are documented
in a separate chapter.
STRUCTURE AND USAGE

The MEGA65 libc is purposely provided in source-form only, and with groups of func-
tions in separate files, and with separate header files for including. The idea is that you
include only the header files that you require, and add only the source files required
to the list of source files of the program you are compiling. This avoids the risk of the
compiler including functions in your compiled program that are never used, and thus
wasting precious memory space.
Note that some library source files are written in C, and thus are present as files with
a .c extension, while others are written in assembly language either for efficiency or
out of necessity, and have a .s extension.
Typical usage is to either have the mega65-libc source code checked out in an adja-
cent directory, or within the source directory of your own project. In the latter case,
this can be done using the git submodule facility.
The following sections document each of the header files and the corresponding func-
tions that they provide.
CONIO.H
conionit
Description: Initialises the library internal state
Syntax: void conioinit(void)
Notes: This must be called before using any conio library function.
setscreenaddr
Description: Sets the screen RAM start address
Syntax: void setscreenaddr(long addr);
43
Parameters: addr: The address to set as start of screen RAM
Notes: No bounds check is performed on the selected address
getscreenaddr
Description: Returns the screen RAM start address
Syntax: long getscreenaddr(void);
Return Value: The current screen RAM address start address.
setcolramoffset
Description: Sets the color RAM start offset value
Syntax: void setcolramoffset(long offset);
Parameters: addr: The offset from the beginning of the color RAM address
($FF80000)
Notes: No bounds check is performed on the resulting address. Do not exceed
the available Color RAM size
getcolramoffset
Description: Returns the color RAM start offset value
Return Value: The current color RAM start offset value.
setcharsetaddr
Description: Sets the character set start address
Syntax: void setcharsetaddr(long addr);
Parameters: addr: The address to set as start of character set

Notes: No bounds check is performed on the selected address
44
getcharsetaddr
Description: Returns the current character set start address
Return Value: The current character set start address.
clrscr
Description: Clear the text screen.
Syntax: void clrscr(void)
Notes: Color RAM will be cleared with current text color
getscreensize
Description: Returns the dimensions of the text screen
Syntax: void getscreensize(unsigned char* width, unsigned
char* height)
Parameters: width: Pointer to location where width will be returned

height: Pointer to location where height will be returned
setscreensize
Description: Sets the dimensions of the text screen
Syntax: void setscreensize(unsigned char width, unsigned char
height)
Parameters: width: The width in columns (40 or 80)

height: The height in rows (25 or 50)
Notes: Currently only 40/80 and 25/50 are accepted. Other values are
ignored.
45
set16bitcharmode
Description: Sets or clear the 16-bit character mode
Syntax: void set16bitcharmode(unsigned char f)
Parameters: f: Set true to set the 16-bit character mode

Notes: This will trigger a video parameter reset if HOTREG is ENABLED. See
sethotregs function.
sethotregs
Description: Sets or clear the hot-register behavior of the VIC-IV chip.
Syntax: void set16bitcharmode(unsigned char f)
Parameters: f: Set true to enable the hotreg behavior

Notes: When this mode is ENABLED a video mode reset will be triggered when
touching $D011, $D016, $D018, $D031 or the VIC-II bank bits of
$DD00.
setextendedattrib
Description: Sets or clear the VIC-III extended attributes mode to support blink,
underline, bold and highlight.
Syntax: void setextendedattrib(unsigned char f)
Parameters: f: Set true to set the extended attributes mode
togglecase
Description: Set lower case character set
Syntax: void setlowercase(void)
togglecase
Description: Set upper case character set
46
Syntax: void setuppercase(void)
togglecase
Description: Toggle the current character set case
Syntax: void togglecase(void)
bordercolor
Description: Sets the current border color
Syntax: void bordercolor(unsigned char c)
Parameters: c: The color to set
bgcolor
Description: Sets the current screen (background) color
Syntax: void bgcolor(unsigned char c)
textcolor
Description: Sets the current text color
Syntax: void textcolor(unsigned char c)

Notes: This function preserves attributes in the upper 4-bits if extended at-
tributes are enabled. See setextendedattrib.
revers
Description: Enable the reverse attribute
Syntax: void revers(unsigned char c)
Parameters: enable: 0 to disable, 1 to enable
47
Notes: Extended attributes mode must be active. See setextendedattrib.
highlight
Description: Enable the highlight attribute
Syntax: void highlight(unsigned char c)

blink
Description: Enable the blink attribute
Syntax: void blink(unsigned char c)

underline
Description: Enable the underline attribute
Syntax: void underline(unsigned char c)

altpal
Description: Enable the alternate-palette attribute
Syntax: void altpal(unsigned char c)

48
clearattr
Description: Clear all text attributes
Syntax: void clearattr())
cellcolor
Description: Sets the color of a character cell
Syntax: void cellcolor(unsigned char x, unsigned char y, un-
signed char c)
Parameters: x: The cell X-coordinate

y: The cell Y-coordinate
c: The color to set
Notes: No screen bounds checks are performed; out of screen behavior is
undefined
setpalbank
Description: Set current text/bitmap palette bank (BTPALSEL).
Syntax: void setpalbank(unsigned char bank)
Parameters: bank: The palette bank to set. Valid values are 0, 1, 2 or 3.

Notes: Use setpalbanka to set alternate text/bitmap palette
setpalbanka
Description: Set alternate text/bitmap palette bank.
Syntax: void setpalbanka(unsigned char bank)
Parameters: bank: The palette bank to set. Valid values are 0, 1, 2 or 3.

Notes: Use setpalbank to set main text/bitmap palette
49
getpalbank
Description: Get selected text/bitmap palette bank.
Syntax: unsigned char getpalbank(void)
Notes: Use getpalbanka to get alternate text/bitmap selected palette

Return Value: The current selected main text/bitmap palette bank.
getpalbanka
Description: Get selected alternate text/bitmap palette bank.
Syntax: unsigned char getpalbanka(void)
Notes: Use getpalbank to get main text/bitmap selected palette

Return Value: The current selected alternate text/bitmap palette bank.
setmapedpal
Description: Set maped-in palette bank at $D100-$D3FF.
Syntax: void setmapedpal(unsigned char bank)
Parameters: bank: The palette bank to map-in. Valid values are 0, 1, 2 or 3.
getmapedpal
Description: Get maped-in palette bank at $D100-$D3FF.
Syntax: unsigned char getmapedpal(void)
setpalentry
Description: Set color entry for the maped-in palette
Syntax: void setpalentry(unsigned char c, unsigned char r,
unsigned char g, unsigned char b)
Parameters: c: The palette entry index (0-255)
50
r: The red component value
g: The green component value
b: The blue component value
Notes: Use setmapedmal to bank-in the palette to modify
fillrect
Description: Fill a rectangular area with character and color value
Syntax: void fillrect(const RECT *rc, unsigned char ch, un-
signed char col)
Parameters: rc: A RECT structure specifying the box coordinates

ch: A char code to fill the rectangle
col: The color to fill
undefined
box
Description: Draws a box with graphic characters
Syntax: void box(const RECT *rc, unsigned char color, unsigned
char style, unsigned char clear, unsigned char shadow)
Parameters: rc: A RECT structure specifying the box coordinates

color: The color to use for the graphic characters
style: The style for the box borders. Can be set to
BOX_STYLE_NONE, BOX_STYLE_ROUNDED, BOX_STYLE_INNER,
BOX_STYLE_OUTER, BOX_STYLE_MID
clear: Set to 1 to clear the box interior with the selected color
shadow: Set to 1 to draw a drop shadow
undefined
51
hline
Description: Draws an horizontal line.
Syntax: void hline(unsigned char x, unsigned char y, unsigned
char len, unsigned char style)
Parameters: x: The line start X-coordinate

y: The line start Y-coordinate
len: The line length
style: The style for the line. See HLINE_ constants for available styles.
undefined
vline
Description: Draws a vertical line.
Syntax: void vline(unsigned char x, unsigned char y, unsigned
char len, unsigned char style)
Parameters: x: The line start X-coordinate

y: The line start Y-coordinate
len: The line length
style: The style for the line. See VLINE_ constants for available styles.
undefined
gohome
Description: Set the current position at home (0,0 coordinate)
Syntax: void gohome(void)
gotoxy
Description: Set the current position at X,Y coordinates
52
Syntax: void gotoxy(unsigned char x, unsigned char y)
Parameters: x: The new X-coordinate

y: The new Y-coordinate
undefined
gotox
Description: Set the current position X-coordinate
Syntax: void gotox(unsigned char x)
Parameters: x: The new X-coordinate

undefined
gotoy
Description: Set the current position Y-coordinate
Syntax: void gotoy(unsigned char y)
Parameters: y: The new Y-coordinate
undefined
moveup
Description: Move current position up
Syntax: void moveup(unsigned char count)
Parameters: count: The number of positions to move

undefined
53
movedown
Description: Move current position down
Syntax: void movedown(unsigned char count)

undefined
moveleft
Description: Move current position left
Syntax: void moveleft(unsigned char count)

undefined
moveright
Description: Move current position right
Syntax: void moveright(unsigned char count)
undefined
wherex
Description: Return the current position X coordinate
Syntax: unsigned char wherex(void)
Return Value: The current position X coordinate
54
wherey
Description: Return the current position Y coordinate
Syntax: unsigned char wherey(void)
Return Value: The current position Y coordinate
pcputc
Description: Output a single petscii character to screen at current position
Syntax: void cputc(unsigned char c)
Parameters: c: The petscii character to output
pcputsxy
Description: Output a petscii string at X,Y coordinates
Syntax: void pcputsxy (unsigned char x, unsigned char y, const
unsigned char* s)
Parameters: x: The X coordinate where string will be printed

y: The Y coordinate where string will be printed
s: The petscii string to print
Notes: No pointer check is performed. If s is null or invalid, behavior is unde-
fined
cputcxy
Description: Output a single petscii character at X,Y coordinates
Syntax: void pcputcxy (unsigned char x, unsigned char y, un-
signed char c)
Parameters: x: The X coordinate where character will be printed

y: The Y coordinate where character will be printed
c: The petscii character to print
55
pcputs
Description: Output a petscii string at current position
Syntax: void pcputs(const unsigned char* s)
Parameters: s: The string to print

Notes: No pointer check is performed. If s is null or invalid, behavior is unde-
fined
cputc
Description: Output a single screen code character to screen at current position
Syntax: void cputc(unsigned char c)
Parameters: c: The screen code of the character to output
cputnc
Description: Output N copies of a character at current position
Syntax: void cputnc(unsigned char count, unsigned char c)
Parameters: c: The screen code of the characters to output

count: The count of characters to print
cputhex
Description: Output an hex-formatted number at current position
Syntax: void cputhex(long n, unsigned char prec)
Parameters: n: The number to write

prec: The precision of the hex number, in digits. Leading zeros will be
printed accordingly
Notes: The $ symbol will be automatically added at beginning of string
56
cputdec
Description: Output a decimal number at current position
Syntax: void cputdec(long n, unsigned char padding, unsigned
char leadingZ)
Parameters: n: The number to write

padding: The padding space to add before number
leadingZ: The leading zeros to print
cputs
Description: Output screen codes at current position
Syntax: void cputs(const unsigned char* s)
Parameters: s: Am array of screen codes to print
Notes: This function works with screen codes only. To output ordinary ASCI-
I/PETSCII strings, use the ”pcputs” macro. No pointer check is per-
formed. If s is null or invalid, behavior is undefined.
cputsxy
Description: Output multiple screen codes at X,Y coordinates
Syntax: void cputsxy (unsigned char x, unsigned char y, const
unsigned char* s)
Parameters: x: The X coordinate where string will be printed

y: The Y coordinate where string will be printed
s: An array of screen codes to print
Notes: This function works with screen codes only. To output ordinary ASCI-
I/PETSCII strings, use the ”pcputsxy” macro. No pointer check is per-
formed. If s is null or invalid, behavior is undefined.
cputcxy
Description: Output a single character at X,Y coordinates
57
Syntax: void cputcxy (unsigned char x, unsigned char y, un-
signed char c)

c: The screen code of the character to print
cputncxy
Description: Output N copies of a single character at X,Y coordinates
Syntax: void cputncxy (unsigned char x, unsigned char y, un-
signed char count, unsigned char c)

count: The number of characters to output
c: The screen code of the characters to print
cprintf
Description: Prints formatted output.
Escape strings can be used to modify attributes, move cursor, etc sim-
ilar to PRINT in CBM BASIC.
Syntax: unsigned char cprintf (const unsigned char* format,
...)
Parameters: format: The string to output. The available escape codes are:
Cursor positioning
\t Go to next tab position (multiple of 8s)
\r Carriage Return
\n New line
{clr} Clear screen {home} Move cursor to home (top-left)
{d} Move cursor down {u} Move cursor up
{r} Move cursor right {l} Move cursor left
58
Attributes
{rvson} Reverse attribute ON {rvsoff} Reverse attribute OFF
{blon} Blink attribute ON {bloff} Blink attribute OFF
{ulon} Underline attribute ON {uloff} Underline attribute OFF
Colors (default palette)
{blk} {wht} {red} {cyan}
{pur} {grn} {blu} {yel}
{ora} {brn} {pink} {gray1}
{gray2} {lblu} {lgrn} {gray3}
Notes: This function works with screen codes only! To output ordinary ASCI-
I/PETSCII strings, use the ”pcprintf” macro. Currently no argument
replacement is done with the variable arguments.
pcprintf
Description: Prints formatted petscii string output.
Syntax: see cprintf
cgetc
Description: Waits until a character is in the keyboard buffer and returns it
Syntax: unsigned char cgetc (void);
Return Value: The last character in the keyboard buffer

Notes: Returned values are ASCII character codes
kbhit
Description: Returns the character in the keyboard buffer
Syntax: unsigned char kbhit (void);
Return Value: The character code in the keyboard buffer, 0 otherwise.

Notes: Returned values are ASCII character codes
59
getkeymodstate
Description: Return the key modifiers state.
Syntax: unsigned char getkeymodstate(void)
Return Value: A byte with the key modifier state bits, where bits:
Bit Meaning Constant
0 Right SHIFT State KEYMOD_RSHIFT
1 Left SHIFT state KEYMOD_LSHIFT
2 CTRL state KEYMOD_CTRL
3 MEGA state KEYMOD_MEGA
4 ALT state KEYMOD_ALT
5 NOSCRL state KEYMOD_NOSCRL
6 CAPSLOCK state KEYMOD_CAPSLOCK
7 Reserved -
flushkeybuf
Description: Flush the keyboard buffer
Syntax: void flushkeybuf(void)
cinput
Description: Get input from keyboard, printing incoming characters at current po-
sition.
Syntax: unsigned char cinput(char* buffer, unsigned char bu-
flen, unsigned char flags)
Parameters: buffer: Target character buffer preallocated by caller
buflen: Target buffer length in characters, including the null charac-
ter terminator
flags: Flags for input: (default is accept all printable characters)
CINPUT_ACCEPT_NUMERIC
Accepts numeric characters.
CINPUT_ACCEPT_LETTER
Accepts letters.
60
CINPUT_ACCEPT_SYM
Accepts symbols.
CINPUT_ACCEPT_ALL
Accepts all. Equals to CINPUT_ACCEPT_NUMERIC
|CINPUT_ACCEPT_LETTER |CINPUT_ACCEPT_SYM
CINPUT_ACCEPT_ALPHA
Accepts alphanumeric characters. Equals to
CINPUT_ACCEPT_NUMERIC |CINPUT_ACCEPT_LETTER
CINPUT_NO_AUTOTRANSLATE
Disables the feature that makes cinput to autodisplay uppercase
characters when standard lowercase character set is selected
and the user enters letters without the SHIFT key, that would
display graphic characters instead of alphabetic ones.
Return Value: Count of successfully read characters in buffer
VIC_BASE
VIC_BASE is a pre-processor macro that provides the base address of the VIC-IV chip,
i.e., $D000.
IS_H640 is a pre-processor macro that returns 0 if the current VIC-III/IV video mode
is set to 320 pixels accross (40 column mode), and non-zero if it is set to 640 pixels
across (80 column mode).
61
62
CHAPTER 9
BASIC Tokenisers
64
Various tokenisers for C64 BASIC exist, e.g., https://github.com/catseye/
hatoucan, https://www.c64-wiki.com/wiki/C64list, or the petcat utility that is
part of VICE. If you are using Ubuntu Linux, you can install petcat by using the fol-
lowing command:
sudo apt - get i nst all vice
We recommend petcat, because it supports both C64 BASIC 2 and C65 BASIC 10.
Some IDEs offer BASIC 65 tokenisers within them, such as:
Eleven
https://files.mega65.org?id=8b189d0b-ea1e-45a7-a4de-87bcb0b11696
C64 Studio
https://www.georg-rottensteiner.de/files/C64StudioRelease.zip
CBM prg Studio
https://www.ajordison.co.uk
65
66
PART III
NATIVE DEVELOPMENT TOOLS
68
CHAPTER 10
C65 Memory Monitor
70
CHAPTER 11
MEGA65 Matrix Mode
72
CHAPTER 12
Turbo Assembler
74
CHAPTER 13
Dealing with C65 and
C64-mode
76
The MEGA65 normally starts in C65-mode, and there is appeal in making programs
that can start directly from C65-mode. However, the different versions of the C65
ROM make this difficult, as there are differences in the memory location of various
system variables and ROM routines. If you are developing a program in assembly lan-
guage or C, it is typically easier to develop it for C64-mode.
But that leaves you with the problem of how to allow it to be started from C65-
mode. Our solution to this is the c65toc65wrapper.asm program. This short program
can be found in the src/utilities directory of the https://github.com/mega65/
mega65-tools repository. When compiled, it produces a short program that you can
pre-pend to your C64-mode oriented MEGA65 program, and have it automatically
detect C64 or C65-mode, switch to C64-mode if required, and set your program go-
ing. It also switches the CPU to 40MHz. The only assumption it makes, is that your
program should be started using SYS 2061
This program is particularly handy when using exomizer, as by having the CPU set to
40MHz before depacking allows depacking to happen almost instantly. This is impor-
tant on the MEGA65, as loading a program often takes only a fraction of a second,
but depacking an exomized program at 1MHz can take several seconds.
Finally, you can use this approach to create bootable disks for the MEGA65, by placing
the file onto the disk with the name AUTOBOOT.C65. This allows you to use C64-mode
programs to autoboot on the MEGA65, which is itself very convenient.
77
78
PART IV
MEGA65 Operating System
80
CHAPTER 14
Developing System
Programmes
• Introduction
• Flash Menu
• Format/FDISK Utility
• Keyboard Test Utility
• MEGA65 Configuration Utility
• Freeze Menu
• Freeze Menu Helper Programmes
• Hypervisor
• OpenROM
82
83
84
INTRODUCTION
The MEGA65 has a number of system programs and utilities that are used at various
times to perform various functions. This includes the utilities accessible via the Utility
Menu , the Freeze Menu and its own helper programs, as well as the Flash Menu .
A number of these system programs are pre-loaded into the MEGA65 bitstream, while
others live on the SD card. For those that are pre-loaded into the MEGA65 bitstream,
this works by having areas of pre-initialised memory, that contain the appropriate
program. For example, the utilities accessible via the Utility Menu are all located in
the colour RAM, while the Flash Menu is located at $50000 – $57FFF.
In one sense, the easiest way to test new versions of these utilities is to generate
a new bitstream with the updated versions. However, synthesising a new bitstream is
very time consuming, typically taking an hour on a reasonably fast computer. Therefore
this chapter explains the procedure for loading an alternate version of each of these
system programs, as well as providing some useful information about these programs,
how they operate, and the environment in which they operate compared with normal
C64 or C65-mode programs.
FLASH MENU
The flash menu is located in pre-initialised RAM at $50000 – $57FFF. It is executed
during the first boot each time the MEGA65 is switched on. It is unusual in that it
executes in the hypervisor context. This is so that it has access to the QSPI flash, which
is not available outside of Hypervisor Mode, so that user programs cannot corrupt the
cores stored in the flash.
It is also important to note that the flash menu program must fit entirely below $8000
when loaded and executing, as the Hypervisor is still mapped at $8000 – $BFFF, and
can easily be corrupted by an ill behaved flash menu program. In this regard, the
flash menu can be regarded as an extension of the hypervisor that is discarded after
the first boot. This is unlike all other system programs, that operate in a dedicated
memory context, from where the Hypervisor is safe from corruption. It also means that
you can’t crunch the flash menu to make it fit, as it would overwrite the Hypervisor
during decrunching.
Also, as the flash menu is executed very early in the boot process, only the pre-included
OpenROM ROM image is available. Thus you must ensure that your flash menu program
is compatible with that ROM.
The Hypervisor maintains a flag that indicates whether the flash menu has been ex-
ecuted or not. This flag is updated at the point where the Hypervisor exits to user
85
mode for the first time, since after that point, the contents of $50000 – $57FFF can
no longer be trusted to contain the flash menu. This means that if you wish to have the
Hypervisor run a new version of the flash menu that you have loaded, you must prevent
the Hypervisor from exiting to user mode first.
The easiest way to achieve this is to hold the ALT key down while powering on the
MEGA65. This will cause the Hypervisor to display the Utility Menu, rather than exiting
to user mode. It is safe at this time to use the m65 utility to load the replacement flash
menu program using a command similar to the following:
m65 -@ newflashmenu.prg@50000
That command would load the file newflashmenu.prg at memory location $50000.
After that, you can simply press the reset button on the side of the MEGA65 while
NO
holding SCROLL down, and it will boot again, and because it never left Hypervisor Mode
during the previous boot cycle, it will run your updated flash menu program.
It should also be possible to completely automate this process, by first using m65 -b to
load a new bitstream, thus simulating a cold boot, and then quickly calling m65 again
to simulate depressing the ALT key (or herhaps simply halting the processor), then m65
-@ ... and finally m65 -F to reset the machine. Writing a script or utility that correctly
implements this automation is left as an exercise for the reader.
FORMAT/FDISK UTILITY
The Format/FDISK utility is accessed as part of the Utility Menu system. These utili-
ties are compiled, crunched and linked using the utilpacker program. If you have
checked out the mega65-core source repository, you can re-build the colour RAM
image by using:
make bin/COLOURRAM.BIN
You will of course need to first have modified the Format/FDISK utility, which is normally
located in the src/mega65-freeze-menu subdirectory.
You need to then load this modified colour RAM image into the running machine. Sim-
ilar to when updating the flash menu, the Hypervisor will only present the utility menu
on the first boot, before exiting to user mode for the first time, because it cannot
otherwise be sure that the colour RAM contains the valid utility programs.
86
So as for the flash menu, you would power the MEGA65 off, and then holding the ALT
key down, you switch the MEGA65 back on, so that it displays the utility menu. At this
point you can use the following command to load your modified COLOURRAM.BIN file:
m65 -c COLOURRAM.BIN
ALT
You can now hold down, and press the reset button on the left-hand side of the
MEGA65, which should again present the utility menu, but this time with your modified
format/fdisk utility in place.
KEYBOARD TEST UTILITY

The process for updating the Keyboard test utility is essentially the same as for the
format/FDISK utility, as it lives in the colour RAM
MEGA65 CONFIGURATION UTILITY

The process for updating the MEGA65 Configuration utility is essentially the same as
for the format/FDISK utility, as it lives in the colour RAM
FREEZE MENU
The Freeze Menu is a normal program, which is stored in FREEZER.M65 on the SD card’s
FAT32 file system.
To updated the Freeze Menu, simply use the m65ftp utility or some other means to
upload your updated FREEZER.M65 file to the SD card’s FAT32 file system. The format
of the program is simply a C64-mode PRG file, just renamed to FREEZER.M65.
FREEZE MENU HELPER PROGRAMMES

The Freeze Menu helper programs are updated in the same way as the Freeze Menu
itself.
87
HYPERVISOR
The Hypervisor is normally built as HICKUP.M65, a 16KB file that contains the com-
plete Hypervisor program. MEGA65 bitstreams contain a pre-build version located at
$FFF8000 – $FFFBFFF. Updated versions of the Hypervisor can be tested using two
main approaches:
• 1. Place the updated HICKUP.M65 file on the FAT32 file system of the SD card,
and then power the MEGA65 off and on. This works because the Hypervi-
sor contains code that checks for an updated version of itself, and if found,
loads it. However this approach is problematic in that if you install a newer bit-
stream, it will still downgrade the Hypervisor to whatever version is found in the
HICKUP.M65 file on the SD card. This method is only recommended for devel-
opers who have a need to test their modified Hypervisor code from a cold start.
Even then, it is recommended to remove the HICKUP.M65 file immediately after
testing to avoid unexpected down-grading in the future.
• 2. Use the m65 command’s -k option to replace the Hypervisor in place, and
then reset the MEGA65 using the reset button on the left-hand side of the case.
This should be done when the Hypervisor is not active, so that corruption of cur-
rent execution cannot occur. However, it must also occur before any ROM has
been loaded to replace the default OpenROM image. This is because the Hy-
pervisor will attempt to call into the ROM on first-boot in prepration for calling
the flash menu, and assumes that the OpenROM is present, because it uses a
special OpenROM-specific call to initialise parts of the system state for the flash
menu. This is best done by using a command like m65 -k bin/HICKUP.M65 -R
bin/MEGA65.ROM to load both a new Hypervisor program and re-load an Open-
ROM image.
OPENROM
To load a new version of a ROM, there are several options, including replacing both
the Hypervisor and ROM at the same time, as described above. However, typically
the easiest is to copy the new ROM onto the FAT32 filesystem of the SD card as ei-
ther MEGA65.ROM, or MEGA65x.ROM, where x is replaced by a digit between 0 and
9. When reseting the MEGA65, MEGA65.ROM will then be loaded as normal, or if
a digit between 0 and 9 is held down on the keyboard while resetting, the Hypervi-
sor will instead load MEGA65x.ROM, where x is the number being held down on the
keyboard.
88
CHAPTER 15
MEGA65 Hyppo Services
• Introduction
• General Services
• Drive/Storage Services
• Disk Image Services
• Task and Process Services
• System Partition Services
• Freezer Services
90
INTRODUCTION
A part of the MEGA65 is the system program called Hyppo that:
• Boots the MEGA65.
• Loads the ROMs and other files from the SD card.
• Makes memory banks 2 and 3 ROM-like by protecting them from being written
to.
• Virtualises the floppy disk controller so you can use disk images.
• Launches various utilities like the freezer and the Matrix Mode Debugger.
• Provides services specific to the MEGA65 that you can use in your programs.
If you know about hypervisors and virtual machines, Hyppo is a very limited hypervisor.
Don’t expect to be able to run multiple virtual machines concurrently with full isolation.
Hyppo runs things that are more akin to the task and processes of a modern operating
system than the virtual machines of a hypervisor as you might know it.
Hyppo provides 3 operating modes.
• The C64-like operating mode runs C64 programs and MEGA65 programs that
run in the MEGA65’s C64 mode. When you boot with ` pressed or use the
GO64 command, Hyppo starts a process in the C64-like operating mode to run
BASIC 2 or the MEGA65 program.
• The C65-like operating mode is the MEGA65’s normal operating mode. This
is where regular MEGA65 program run, including BASIC 65 programs.
• The MEGA65 operating mode runs the MEGA65’s system programs like the
freezer, the configuration utility and the Matrix Mode Debugger. Maybe surpris-
ingly, normal MEGA65 programs do not run in the MEGA65 operating mode.
They run in the C65-like operating mode. The MEGA65 operating mode is de-
signed solely for the MEGA65 and does not attempt to be compatible with or
even be similar to previous systems.
Unlike on the C128, it is possible for a program to effectively change the operat-
ing mode while it’s is running, by simply enabling or disabling the various hardware
features.
91
Hyppo provides very limited virtualisation of the MEGA65’s hardware. It can virtualise
the floppy controller. There are plans to virtualise the serial bus so the MEGA65 can
use disk images for units like the 1541.
There are some parts of the hardware that only Hyppo can access. It is the only com-
ponent that can directly access the internal and external SD cards. You need to use
Hyppo’s services if you want to access the files and directories on the SD cards from
within your programs.
Terminology
When you start to learn about Hyppo, there can be some terminology that might be
confusing if you already know about other parts of the MEGA65.
On the SD card there is likely to be a file called HICKUP.M65. This file updates Hyppo
to new versions without having to install an upgraded core. You might find occasions
where Hyppo might be called Hickup because of this strong association.
There are 3 distinct disk operating systems in the MEGA65.
• Inside Hyppo is Hyppo DOS, or HDOS for short. HDOS is for accessing the FAT32
file system on the SD cards. HDOS does not know anything about Commodore
file systems. It can attach an image of a Commodore file system, but it does not
understand what is inside the image.
• Inside the KERNAL is CBDOS. CBDOS is for accessing 1581-like file systems.
CBDOS uses the 45IO27 multi-function I/O controller to access the sectors of
a physical disk. CBDOS does not know anything about SD cards and the FAT32
file system on them. Hyppo virtualises part of the 45IO27 so CBDOS can access
disk images like they’re physical disks.
• The external disk units attached to the serial bus each have their own DOS. They
are used for accessing the file systems on their respective physical disks.
The word drive means different things for each of these DOS’s.
• The drives in Hyppo are the partitions of the internal and external SD cards. When
the MEGA65 boots, Hyppo assigns numbers to the partitions it can read.
• The drives in CBDOS are the physical disk drives attached to the 45IO27 multi-
function I/O controller — such as the internal disk drive — or the disk images
attached to the virtualised 45IO27. The CBDOS drives are normally seen as
units 8 and 9.
• The drives in an external unit attached to the serial bus are the disk drives inside
that unit.
92
Versions
This chapter describes the services available in Hyppo 1.2.
New Hyppo services may become available and existing Hyppo services may change
or be deprecated. A robust program will use the hyppo_getversion service to check
whether it is compatible with the Hyppo in the MEGA65 it’s running on.
Using
When you want to use a Hyppo service, you don’t use JSR. This is because Hyppo exists
in a space that’s separate from regular code. In order to access it, the CPU needs to
switch into its hypervisor mode.
At addresses $D640 – $D67F are a set of hypervisor traps. Writing to these addresses
are not like writing to other addresses. Instead of writing to memory or I/O, the CPU
switches into the hypervisor mode and starts a Hyppo service. How the CPU does this
is described in the MEGA65 Book, 45GS02 Microprocessor (Appendix J).
Which Hyppo service starts depends on what value from the A register you write and
which trap you write to. Each of the services described in this chapter tells you what
value to write and which trap to use. You have to use the A register when triggering a
trap. Writing the same value from another register won’t work.
When the Hyppo service finishes, the CPU will switch back to your program. Except for
the registers a service uses to return values, the registers are otherwise preserved.
Important The CPU may or may not execute the next byte in your program after the
Hyppo service finishes. Put a CLV instruction after the STA. The CPU executing the CLV
or not shouldn’t matter to your program. If your program does rely on the V flag, you
can use the NOP instruction instead. When you use NOP you must be mindful of when
the CPU interprets the NOP as a prefix for the following instruction. For this reason,
you should prefer using CLV over NOP.
Errors
If the service was successful, it will set the C flag.
If the service was unsuccessful, it will clear the C flag and put an error code in the A
register. There is a table of error codes in the description for hyppo_geterrorcode.
93
Examples
The examples use the ACME assembler. The ACME assembler is not required. The
Hyppo services can be used with any assembler.
The examples are often not complete. They assume an error handler called error is
defined somewhere. They also assume a transfer area has been defined somewhere.
hyppo_setup_transfer_area and hyppo_setname show how to define a transfer area.
94
GENERAL SERVICES
hyppo_geterrorcode
Trap: LDA #$38 : STA $D640 : CLV
Service: Returns the current error code from Hyppo.
Precondition: The previous service used cleared the C flag.
Outputs: A The error code of the previously failed service.
History: Available since Hyppo 1.2
Remarks: The error code is only valid if the previous Hyppo service cleared the
C flag. If the C flag was set there was no error and the Hyppo error
code is undefined.
The meanings here are generic. See the sections for the services for
more specific meanings.
Error codes: This is possibly not an exhaustive list.
Hex Dec Name General meaning

$01 1 partition not The partition is not of a supported type.
interesting
$02 2 bad signature The signature bytes at the end of a partition table or of
the first sector of a partition were missing or incorrect.
$03 3 is small FAT This is partition is FAT12 or FAT16 partition. Only
FAT32 is supported.
$04 4 too many reserved The partition has more than 65,535 reserved sectors.
clusters
$05 5 not two FATs The partition does not have exactly two copies of the
FAT structure.
$06 6 too few clusters The partition contains too few clusters.
$07 7 read timeout It took to long to read from the SD card.
$08 8 partition error An unspecified error occurred while handling a parti-
tion.
$10 16 invalid address An invalid address was supplied in an argument.
95
Hex Dec Name General meaning
$11 17 illegal value An illegal value was supplied in an argument.
$20 32 read error An unspecified error occurred while reading.
$21 33 write error An unspecified error occurred while writing.
$80 128 no such drive The supplied Hyppo drive number does not exist.
$81 129 name too long The supplied filename was too long.
$82 130 not implemented The Hyppo service is not implemented.
$83 131 file too long The file is larger than 16MB.
$84 132 too many All of the file descriptors are in use.
open files
$85 133 invalid cluster The supplied cluster number is invalid.
$86 134 is a directory An attempt was made to operate on a directory,
where a normal file was expected.
$87 135 not a directory An attempt was made to operate on a normal file,
where a directory was expected.
$88 136 file not found The file could not be located in the current directory
of the current drive.
$89 137 invalid file An invalid or closed file descriptor was supplied.
descriptor
$8A 138 image wrong The disk image file has the wrong length.
length
$8B 139 image fragmented The disk image is not stored contiguously on the SD
card.
$8C 140 no space The SD card has no free space for the requested op-
eration.
$8D 141 file exists A file already exists with the given name.
$8E 142 directory full The directory cannot accommodate any more entries.
$FF 255 eof The end of a file or directory was encountered.
$FF 255 no such trap There is no Hyppo service available for the trap. The
program may be incompatible with this version of
Hyppo.
96
hyppo_getversion
Service: Returns the version of Hyppo A.X and HDOS Y.Z.
Outputs: A The major version number of Hyppo
X The minor version number of Hyppo
Y The major version number of HDOS
Z The minor version number of HDOS
Remarks: The HDOS in Hyppo is not related to the CBDOS inside the KERNAL
or the DOS in the disk drive units attached to the serial port.
Example: Tests if Hyppo’s version is ≥ 1.2 and < 2.0.
; Get the version numbers

LDA #$00 : STA $D640 : CLV
; Test if the major version number of Hyppo in A is 1
CMP #1 : BNE incompatible
; Test if the minor version number of Hyppo in X is 2 or more
TXA : CMP #2 : BMI incompatible
; This Hyppo version is compatible
97
hyppo_setup_transfer_area
Trap: LDA #$3A : STA $D640 : CLV
Service: Sets up the area Hyppo uses to transfer data to and from your pro-
gram.
Inputs: Y The MSB of the transfer area’s address
Errors: $10 invalid address The transfer area address in Y > $7E
Remarks: The transfer area must be between $0000 and $7E00. It must also
begin on a page boundary. The LSB of its address must be $00.
The transfer area is 256 bytes long for most services.
The transfer area is indicated using the CPU’s current memory map-
ping at the time that a service is used. However, it is good practice
to always place it in the bottom 32KB of bank 0.
Example: Reserves 256 bytes on a page boundary and sets it up as the transfer
area.
;---------------------------------------------------------------------------------------
; Somewhere in the program’s data area
; Align with the new page boundary

!align 255, 0
transferarea:
; Reserve 256 bytes
!skip 256
;---------------------------------------------------------------------------------------
; Elsewhere in the progrma’s code
setuptransferarea:
; Set the transferarea as the Hyppo transfer area
LDY #>transferarea : LDA #$3A : STA $D640 : CLV : BCC error
98
DRIVE/STORAGE SERVICES
In Hyppo, drives are the partitions of the internal and external SD cards. They are not
the drive 0 and drive 1 of the F011 floppy controller. They are also not the drive 0
and drive 1 of dual-drive units attached to the serial bus.
hyppo_chdir
Trap: LDA #$0C : STA $D640 : CLV
Service: Changes the current working directory.
Preconditions: The FAT dir entry for the directory you want to change to has been
found. hyppo_findfile is typically used to find a FAT dir entry.
hyppo_findfirst , hyppo_findnext and hyppo_readdir can also
be used.
Errors: $87 not a directory The FAT dir entry last found isn’t for a directory.
Bit 4 of the FAT dir entry’s attribute byte is set for directories.
Remarks: You can move up to the parent directory by finding the .. FAT dir
entry.
You cannot move up or down more than one directory at a time.
Use hyppo_cdrootdir to directly change back to the root directory.
Example: Changes to an arbitrary path on the current drive. Call with Y:X be-
ing the address of the path. The last character of each component
in the path needs to have bit 7 set. The whole path is terminated
with a $00. For example, to change into DIR1 and then DIR2 the
path would be !text "DIR", '1'+$80, "DIR" '2'+$80, 0.
If successful, returns with the C flag set. If some part of the path
doesn’t exist, returns with the C flag cleared and the current working
directory will be whatever directory was last successfully navigated
to.
!addr pathptr = $C4

chdirpath:
STX pathptr : STY pathptr+1 ; Set pathptr to Y:Z
@chdirpath10:
… continues on the next page …
99
JSR @copycomponent ; Get the next component of the path
BEQ @chdirpath20 ; Stop at a 0 byte in the path
JSR @trychdir ; Try to change into the directory
BCC @chdirpath30 ; Stop if we cannot change into the directory
BRA @chdirpath10 ; Repeat with the next component
@chdirpath20: SEC
@chdirpath30: RTS
;----------------------------------------------------------------------------------------
@trychdir:
; Set the Hyppo filename from transferbuffer
LDY #>transferbuffer : LDA #$2E : STA $D640 : CLV : BCC @trychdir10
; Find the FAT dir entry
LDA #$34 : STA $D640 : CLV : BCC @trychdir10
; Chdir into the directory
LDA #$0C : STA $D640 : CLV
@trychdir10:
RTS
;----------------------------------------------------------------------------------------
; Copy the next component of the path into transferbuffer
@copycomponent:
LDY #0
@copycomponent10:
LDA (pathptr),Y
BEQ @copycomponent20
TAX
AND #$7F : STA transferbuffer,Y
INY
TXA : BPL @copycomponent10
; Add a 0 terminating byte to transferbuffer
LDA #0 : STA transferbuffer,Y
; Move pathptr
TYA
CLC : ADC pathptr : STA pathptr : LDA #0 : ADC pathptr+1 : STA pathptr+1
@copycomponent20:
RTS
100
hyppo_cdrootdir
Service: Change drive by calling hyppo_selectdrive and set the current
directory to the root directory.
Inputs: X The drive number to become the new current drive
Precondition: None.
Outputs: A Any error code that can be returned by hyppo_selectdrive
101
hyppo_closeall
Service: Closes all the file descriptors.
Postconditions: Using any file descriptor with hyppo_closedir or hyppo_closefile
succeeds.
Using any file descriptor with hyppo_readdir or hyppo_readfile
fails.
hyppo_opendir and hyppo_openfile reuse the file descriptor.
Remarks: You can also close individual file descriptors using hyppo_closedir
or hyppo_closefile .
102
hyppo_closedir
Service: Closes a file descriptor for a directory.
Preconditions: The file descriptor given in the X register was opened using
hyppo_opendir .
Inputs: X The file descriptor for the directory
Postconditions: Using the file descriptor again with hyppo_closedir succeeds.
Using the file descriptor again with hyppo_readdir fails.
Remarks: You can also close all the open file descriptors using hyppo_closeall
.
Example: See the example in hyppo_opendir .
103
hyppo_closefile
Service: Closes a file descriptor for a file.
hyppo_openfile .
Inputs: X The file descriptor for the file
Postconditions: Using the file descriptor again with hyppo_closefile succeeds.
Using the file descriptor again with hyppo_readfile fails.
Remarks: You can also close all the open file descriptors using hyppo_closeall
.
104
hyppo_filedate
Service: Sets time stamp of a file.
Remarks: NOT IMPLEMENTED
105
hyppo_findfile
Service: Finds the first file whose filename matches the current Hyppo file-
name.
Preconditions: The current Hyppo filename has been set using hyppo_setname .
Postconditions: No additional file descriptors are open.
Errors: $88 file not found A matching file was not found in the current
directory of the current drive.
Remarks: Hyppo will only find files whose long filename is all in uppercase.
Hyppo converts the current filename to ASCII uppercase before try-
ing to match it. Bytes $61 – $7B change to $41 – $5A.
Hyppo does not yet support the wildcard characters * and ?. Sup-
port for that is planned in a future version.
This only finds the first matching file. You can find multiple matches
by using hyppo_findfirst and hyppo_findnext .
Example: See the example in hyppo_openfile .
106
hyppo_findfirst
Service: Finds the first file whose filename matches the current Hyppo file-
name.
Outputs: A The file descriptor for reading the current working directory.
You might be responsible for closing this file descriptor using
hyppo_closedir . See the remarks.
Postconditions: hyppo_findnext find the next matching file or fails with a file not
found error.
Side effects: Sets the current file descriptor.
Errors: $88 file not found A matching file was not found in the current
Remarks: If Hyppo finds an initial matching file, it will set the C flag and return
a file descriptor in the A register. This is a file descriptor for reading
the current working directory. You are responsible for closing it using
hyppo_closedir . It’s a standard directory file descriptor. You can
use hyppo_readdir to read the FAT dir entries after the file that
was found.
If Hyppo doesn’t find any matching files, it will fail with a file not
found error. In this case Hyppo will have already closed the file de-
scriptor and you don’t have to close it.
Hyppo will only find files whose long filename is all in uppercase.
Hyppo converts the current filename to ASCII uppercase before try-
ing to match it. Bytes $61 – $7B change to $41 – $5A.
Hyppo does not yet support the wildcard characters * and ?. Sup-
port for that is planned in a future version.
If you are only interested in the first match, you can use
hyppo_findfile instead. hyppo_findfile always closes the file
descriptor for you. But you can’t use it to find multiple matching
files.
Example: See the example in hyppo_findnext .
107
hyppo_findnext
Service: Finds a subsequent file whose filename matches the current Hyppo
filename.
The first matching file has already been found successfully using
hyppo_findfirst .
Postconditions: Using hyppo_findnext again finds the next matching file or fails
with a file not found error.
Errors: $88 file not found A subsequent matching file was not found in the
current directory of the current drive.
Remarks: If Hyppo doesn’t find a subsequent matching file, it will fail with a
file not found error. Hyppo will also close the file descriptor it output
in hyppo_findfirst .
If you don’t exhaust the search by using hyppo_findnext until it
fails with a file not found error, you are required to close the file
descriptor yourself using hyppo_closedir .
Example: Returns with X register containing the number of files matching the
current Hyppo filename in the current working directory of the cur-
rent drive. While a directory can in theory have multiple files with
an indentical name, this example will be more useful once Hyppo
supports * and ? wildcards.
; Assume the current Hyppo filename has already been set.

; Reset the count in X.
LDX #0
; Try to find the first matching file.
LDA #$30
@10:
STA $D640 : CLV : BCC @20
; Increment the count in X
INX
; Try to find the next matching file.
LDA #$32
BRA @10
108
@20:
; If the error code in A is $88 there are no more matching files,
; otherwise an error occurred.
CMP #$88 : BNE error
; No need to close the file handle because the search exhausted.
109
hyppo_fstat
Service: Returns information about a file.
110
hyppo_getcurrentdrive
Service: Returns the number of the currently selected drive (SD card parti-
tion).
Outputs: A The current drive number
Remarks: hyppo_selectdrive changes the current drive number.
hyppo_cdrootdir can also change it.
Example: Prints the number of the currently selected drive in the top-left of
the screen. This example assumes that there aren’t more than 10
drives (drives 0 to 9). It also assumes the screen memory hasn’t
been moved from $800.
; Get the current drive

LDA #$04 : STA $D640 : CLV : BCC error
; Convert the drive number in A into a screen code

CLC : ADC #$30
; Put the screen code into the top-left of screen memory

STA $0800
111
hyppo_getcwd
Service: Returns information on the currently selected directory or sub-
directory.
112
hyppo_getdefaultdrive
Service: Returns the drive number (SD card partition) Hyppo selected while
booting.
Outputs: A The default drive number
Example: Selects the default drive.
; Get the default drive

LDA #$02 : STA $D640 : CLV : BCC @error
; Transfer the drive number in A to X

TAX
; Select the default drive

LDA #$06 : STA $D640 : CLV : BCC @error
113
hyppo_getdrivesize
Service: Returns information on the size of the currently selected drive (SD
card partition).
114
hyppo_loadfile
Service: Loads a file into chip memory.
Preconditions: The name of the file to load has been set using hyppo_setname .
Inputs: X The LSB of the address to start loading from
Y The middle byte of the address to start loading from
Z The MSB of the address to start loading from
Errors: $84 too many open files hyppo_loadfile uses one file descriptor
internally, but all the file descriptors are in use. Close some or all
of the file descriptors using hyppo_closedir , hyppo_closefile or
hyppo_closeall .
$88 file not found The file was not found in the current directory of
the current drive.
Remarks: This service can load files up to 16MB in size into the first 16MB of
chip memory. Chip memory is the 384KB or more of memory inside
the CPU module.
Loading will start at 28-bit address $00ZZYYXX. If loading tries
to go beyond $00FFFFFF, it wraps around and continue at
$00000000.
You can use hyppo_loadfile_attic to load a file into hyper memory.
The hyper memory is the 8MB or more of memory in the external RAM
chips.
Example: Loads a file into memory starting at $48000.

; No need to find the file first.
LDZ #$04 ; Most significant byte
LDY #$80 ; Middle byte
LDX #$00 ; Least significant byte
115
hyppo_loadfile_attic
Trap: LDA #$3E : STA $D640 : CLV
Service: Loads a file into hyper memory.
Preconditions: The name of the file to load has been set using hyppo_setname .
Inputs: X The LSB of the address to start loading from
Y The middle byte of the address to start loading from
Z The MSB of the address to start loading from
Errors: $84 too many open files hos_loadfile_attic uses one file descriptor
internally, but all the file descriptors are in use. Close some or all of
the file descriptors using hyppo_closedir , hyppo_closefile or
hyppo_closeall .
$88 file not found The file was not found in the current directory of
the current drive.
Remarks: This service can load files up to 16MB in size into the first 16MB of
hyper memory. Hyper memory is the 8MB or more of memory in the
external RAM chips.
Loading will start at 28-bit address $08ZZYYXX. If loading tries to
go beyond $08FFFFFF, the loading will wrap around and continue
at $08000000.
You can use hyppo_loadfile to load a file into chip memory. The
chip memory is the 384KB or more of memory inside the CPU module.
116
hyppo_mkdir
Service: Creates a sub-directory.
Errors: $8D file exists A sub-directory or file already exists with the current
Hyppo filename in the current working directory of the current drive.
hyppo_mkfile
Service: Creates a file.
117
hyppo_opendir
Service: Opens the current working directory for reading the file entries in it.
Preconditions: The drive and directory you want to read have already been set up
using hyppo_selectdrive and hyppo_chdir if necessary.
Outputs: A The file descriptor for reading the directory. You are responsible
for closing this file descriptor using hyppo_closedir .
Postconditions: hyppo_readdir reads the first FAT dir entry in the directory.
Errors: $84 too many open files All the file descriptors are in use.
hyppo_opendir and hyppo_openfile share the same very small
pool of file descriptors. Close some or all of the file descriptors us-
ing hyppo_closedir , hyppo_closefile or hyppo_closeall .
$87 not a directory The FAT dir entry last found is for a file. Use
hyppo_openfile for files.
Example: Calls processdirentry for each FAT dir entry in the current working
directory. processdirentry is assumed to be defined elsewhere.
; Open the current working directory

; Transfer the directory file descriptor into X
TAX
; Set Y to the MSB of the transfer area
LDY #>transferarea
@10:
; Read the directory entry
LDA #$14 : STA $D640 : CLV : BCC @20
; Call processdirentry (assumed to be defined elsewhere)
PHX : PHY : JSR processdirentry : PLY : PLX
BRA @10
@20:
; If the error code in A is $85 we have reached the end of the
; directory otherwise there’s been an error
CMP #$85 : BNE error
; Close the directory file descriptor in X
118
hyppo_openfile
Service: Opens a file on a drive.
Preconditions: The file has already been found. Files can be found us-
ing hyppo_findfile , hyppo_findfirst and hyppo_findnext .
hyppo_readdir can also be used to find a file.
Outputs: A The file descriptor for accessing the file. You are responsible for
closing this file descriptor using hyppo_closefile .
Postconditions: Using hyppo_readfile with this file descriptor reads the first sector
of the file.
Side effects: Sets the current file to the newly opened file. hyppo_readfile
reads from the current file.
Errors: $84 too many open files All the file descriptors are in use.
hyppo_opendir and hyppo_openfile share the same very small
pool of file descriptors. Close some or all of the file descriptors us-
ing hyppo_closedir , hyppo_closefile or hyppo_closeall .
$86 is a directory The FAT dir entry last found is for a directory. Use
hyppo_opendir for directories.
Remarks: You cannot use this to open a file inside a disk image. To do that
you use hyppo_d81attach0 or hyppo_d81attach1 to attach the
disk image and then use either use the KERNAL to read the file or
program the virtualised F011 floppy controller.
Example: Finds and opens a file.

; Find the file
; Open the file
119
hyppo_readdir
Service: Reads the next FAT dir entry into a destination area.
hyppo_opendir and hyppo_closedir hasn’t since been used to
close it.
The destination area is on a page boundary between $0000 and
$7E00 and is at least 87 bytes.
Inputs: X The file descriptor for the directory.
Y The MSB of the destination area.
Outputs: Starting at $YY00, the FAT dir entry has this structure.
Offset Type Description
$00 asciiz The long file name
$40 byte The length of long file name
$41 ascii The ”8.3” file name. The name part is padded
with spaces to make it exactly 8 bytes. The
3 bytes of the extension follow. There is no .
between the name and the extension. There is
no NULL byte.
$4E dword The cluster number where the file begins. For
sub-directories, this is where the FAT dir entries
start for that sub-directory.
$52 dword The length of file in bytes.
$56 byte The type and attribute bits.
This is what the bits in the last byte mean. Bits 6 and 7 are undefined.
Bit Meaning if bit is set
0 Read only
1 Hidden
2 System
3 Volume label
4 Sub-directory
5 Archive
Postconditions: Using hyppo_readdir again reads the next FAT dir entry in the di-
rectory.
Errors: $08 partition error An unspecified error occurred while handling
the currently selected partition.
120
$10 invalid address The Y register is > $7E.
$85 invalid cluster An attempt was made to read past the end of
the directory.
Remarks: If the long file name in the FAT dir entry is too long to copy into the
destination area, Hyppo skips the entry entirely.
The file names in FAT are encoded as UTF-16. Hyppo only reads the
LSB of each 16-bit character. Hyppo does not convert file names
into PETSCII.
See hyppo_setup_transfer_area for more details about the value
for the Y register.
Example: See the example in hyppo_opendir .
121
hyppo_readfile
Service: Reads the next sector of the current file into the sector buffer.
Preconditions: There is a current file open. Files can be opened with
hyppo_openfile .
Outputs: X The LSB of the number of bytes read
Y The MSB of the number of bytes read
Postconditions: The next call to hyppo_readfile will read the next sector of the
current file or signal the end of the file.
Errors: $89 invalid file descriptor There is no current file.
Remarks: To access the data, you need to either:
• map the sector buffer into the 16-bit address space;
• use an enhanced DMA transfer to copy the sector buffer at
$FFD6E00 – $FFD6FFF into a buffer already mapping into the
16-bit address space; or
• use 32-bit load instructions to access the sector buffer directly.
If a full sector was read, Y:X will be $0200. For the last sector of
the file, Y:X may be less than that. Any bytes in the sector buffer
after Y:X are undefined and will not necessarily be zero.
If you read past the end of the last sector, Y:X will be $0000, the A
register will be $FF and the C flag will be set.
While multiple files can be opened simultaneously, only the current
file can be read. The current file is often the last file opened, but
not always.
Example: Maps the sector buffer to $DE00 and then reads each sector of the
file calling proccesssector for each sector read. proccesssector is
assumed to be defined elsewhere.
; Assume the file is already open.

; Unmap the colour RAM from $DC00 because that will prevent us
; from mapping in the sector buffer
LDA $D030 : PHA : AND #%11111110 : STA $D030
122
@10:
; Read the next sector
LDA #$1A : STA $D640 : CLV : BCC @20
; Map the sector buffer to $DE00
LDA #$81 : STA $D680
; Call processsector (assumed to be defined elsewhere)
JSR processsector
; Unmap the sector buffer from $DE00
LDA #$82 : STA $D680
BRA @10
@20:
; If the error code in A is $FF we have reached the end of the file
; otherwise there’s been an error
CMP #$FF : BNE error
; Map the colour RAM at $DC00 if it was previously mapped
PLA : STA $D030
123
hyppo_rename
Service: Renames a file or sub-directory.
hyppo_rmdir
Service: Removes a sub-directory.
hyppo_rmfile
Service: Removes a files.
hyppo_seekfile
Service: Seeks to a given sector in a file.
124
hyppo_selectdrive
Service: Sets the currently selected drive (SD card partition).
Preconditions: Hyppo has assigned a drive number to the SD card partition.
Inputs: X The drive number to become the new current drive
Postconditions: hyppo_getcurrentdrive returns the value that was in the X register.
Hyppo services operate on the newly selected drive.
Errors: $80 no such drive The drive in the X register does not exist. Hyppo
only assigns drive numbers to the SD card partitions it can read.
Example: Tests if drive 2 exists by trying to select it. Returns with the C flag
set if drive 2 exists.
doesdrive2exist:
; Preserve the current drive so we can restore it later
PHA
; Try to select drive 2
LDX #2 : LDA #$06 : STA $D640 : CLV : BCC @10
; Restore the previously selected drive
PLX
; The C flag was already set by the Hyppo service
RTS
@10:
; If the error code in A is $80, the drive doesn’t exist; otherwise
; some other kind of error occurred
CMP #$80
BNE error
; Forget about the current drive we preserved because it wasn’t
; changed
PLX
; Clear the C flag because the drive doesn’t exist
CLC
RTS
125
hyppo_setname
Service: Sets the current Hyppo filename.
Preconditions: The filename is stored in ASCII and ends with a $00 byte.
The filename starts on a page boundary between $0000 and $7E00
and is less than 63 characters, excluding the $00 byte.
Inputs: Y The MSB of the filename address.
Postconditions: Hyppo has copied the filename into it’s own data area.
The hyppo_find* and hyppo_load* services use this filename.
Side effects: Sets the transfer area to $YY00.
Errors: $10 invalid address The Y register is > $7E.
$81 name too long The filename is longer than 63 characters.
Remarks: The filename must be between $0000 and $7E00. It must also
begin on a page boundary. That is, its address must end with $00.
The current memory mapping is used. However, it is good practice
to place it in the bottom 32KB of bank 0.
The filenames in FAT are encoded in UTF-16. Hyppo only reads the
LSB of each 16-bit character. Hyppo does not convert between
ASCII and PETSCII.
Hyppo accesses the files in the FAT file system on the internal and
external SD cards. It does not access files on disks in floppy drives
or in disk images.
Example: Set the current Hyppo filename to GAME.MAP.

!align 255, 0 ; Align with the next page boundary
filename:
!text "GAME.MAP", 0 ; Must end with a 0 byte

setfilename:
LDY #>filename : LDA #$2E : STA $D640 : CLV : BCC error
126
hyppo_writefile
Service: Writes the sector buffer to the current file.
127
DISK IMAGE SERVICES
The 45IO27 multi-function I/O controller includes a F011-compatible floppy con-
troller. The internal floppy drive is attached to this as drive 0.
Hyppo can virtualise the F011 floppy controller so that disk images can be attached
instead of floppy drives. Once a disk image is attached, Hyppo traps the F011’s I/O
registers and emulates the commands on the disk image.
You can use BASIC, the KERNAL and the F011 I/O registers to operate on a disk image
just as you would a physical disk. The virtualisation does not behave the same as a
floppy drive in all cases. If you intend for your program to work with both disk images
and physical disks, be sure to test it with both.
hyppo_d81attach0
Service: Attach a D81 disk image to virtualised F011 drive 0.
Errors: $88 file not found The disk image file was not found in the current
Remarks: Unless it’s been changed, drive 0 of the virtualised F011 floppy con-
troller is unit 8.
Example: Attaches the disk image DISK2.D81 to virtualised F011 drive 0.

!align 255, 0 ; Align with the next page boundary
disk2name:
!text "DISK2.D81", 0 ; Must end with a 0 byte

attachdisk2:
; Set the Hyppo filename to DISK2.D81
LDY #>disk2name : LDA #$2E : STA $D640 : CLV : BCC error
; Attach the disk image
128
hyppo_d81attach1
Service: Attach a D81 disk image to virtualised F011 drive 1.
Remarks: Unless it’s been changed, drive 1 of the virtualised F011 floppy con-
troller is unit 9.
129
hyppo_d81detach
Service: Detaches any disk images from virtualised F011 drives 0 and 1.
130
hyppo_d81write_en
Service: Enables writing to any disk images attached to virtualised F011
drives 0 and 1.
131
TASK AND PROCESS SERVICES
hyppo_create_task_c64
Service: Creates a Hyppo task in the C64-like operating mode.
hyppo_create_task_c65
Service: Creates a Hyppo task in the C65-like operating mode.
hyppo_create_task_native
Service: Creates a Hyppo task in the MEGA65 operating mode.
hyppo_exit_and_switch_to_task
Service: Exits the current Hyppo task and switches context to another Hyppo
task.
hyppo_exit_task
Service: Exits the current Hyppo task.
132
hyppo_get_mapping
Service: Copies the current 45GS02 memory mapping into a destination
area.
Preconditions: The destination area starts on a page boundary between $0000
and $7E00 and is at least 6 bytes.
Inputs: Y The MSB of the destination area.
Outputs: Starting at $YY00, the current mapping info has this structure.
0 word MAPLO
2 word MAPHI
4 byte The megabyte offset for MAPLO
5 byte The megabyte offset for MAPHI
Remarks: MAPLO is the mapping for $0000 - $7FFF.
MAPHI is the mapping for $8000 - $FFFF.
See the MEGA65 Book, 45GS02 Microprocessor (Appendix J) for
more information on MEGA65 memory mapping and banking.
133
hyppo_get_proc_desc
Service: Copies the current task block into a destination area.
Preconditions: The destination area starts on a page boundary between $0000
and $7E00 and is at least 256 bytes.
Inputs: Y The MSB of the destination area.
Outputs: Starting at $YY00, the current task block has this structure.
$00 byte The ID of the current task.
$01 text The name of the current task. A maximum of
16 characters. Padded with $00 bytes. If it’s
16 characters, there are no trailing $00 bytes.
$11 byte Flags for the D81 disk image attached to drive
0 of the virtualised F011 floppy controller.
$12 byte Same as above but for drive 1.
$13 byte The length of the D81 disk image filename at-
tached to drive 0.
$14 byte Same as above but for drive 1.
$15 text The filename of the D81 disk image attached
to drive 0. A maximum of 32 characters.
Padded with $20 bytes. There is no trailing
$00 byte.
$35 text Same as above but for drive 1.
$55 The meaning of these bytes are undefined and
subject to change.
$80 File descriptor 0.
$A0 File descriptor 1.
$C0 File descriptor 2.
$E0 File descriptor 3.
134
Each of the file descriptors has this structure.
$00 byte The number of the SD card partition where the
file resides. $FF means the file descriptor is
closed.
$01 dword The cluster where the file starts
$05 dword The current cluster
$09 byte The current sector within the current cluster
$0A dword The length of the file
$0E dword The current position within the file’s buffer
$12 dword The cluster of the directory in which the file re-
sides
$16 word The index of the file within its directory
$18 dword The absolute 32-bit address of the file’s buffer
$1C word The number of bytes used in the file’s buffer
$1E word The current offset within the file’s buffer
135
hyppo_gettasklist
Service: Gets the list of tasks in Hyppo.
hyppo_load_into_task
Service: Loads a file from an SD card partition into the memory of a Hyppo
task.
hyppo_readoutoftask
Service: Reads from the memory of another Hyppo task.
hyppo_receivemessage
Service: Receives messages sent from other Hyppo tasks.
136
hyppo_reset
Service: Warm boots the MEGA65.
137
hyppo_rom_writeenable
Service: Changes $20000 – $3FFFF to behave like RAM by disabling the
write-protection.
Remarks: $20000 – $3FFFF normally has the KERNAL, BASIC, CBDOS, and
font ROMs.
hyppo_rom_writeprotect enables the write-protection and blocks
writes. hyppo_toggle_rom_writeprotect toggles the write-
protection.
138
hyppo_rom_writeprotect
Service: Changes $20000 – $3FFFF to behave like ROM by enabling the
write-protection.
Remarks: $20000 – $3FFFF normally has the KERNAL, BASIC, CBDOS, and
font ROMs.
hyppo_rom_writeenable disables the write-protection and allows
writes. hyppo_toggle_rom_writeprotect toggles the write-
protection.
139
hyppo_sendmessage
Service: Sends a message to another Hyppo task.
140
hyppo_serial_monitor_wait_and_write
Trap: LDA #$xx : STA $D643 : CLV
Service: Waits for the serial monitor or Matrix Mode Debugger to be ready to
receive and then writes a character to it.
Inputs: A The ASCII character to write.
Remarks: The service waits for the serial monitor to be ready to receive. This
could slow down or hang your program. If you don’t want this and
you are happy for the character to be lost if the serial monitor is not
ready to receive, use hyppo_serial_monitor_write .
141
hyppo_serial_monitor_write
Service: Writes a character to the serial monitor or the Matrix Mode Debug-
ger.
Preconditions: The serial monitor is ready to receive.
Inputs: Y The ASCII character to write.
Remarks: The character will be lost if the serial monitor is not ready
to receive, If you don’t want the character to be lost, use
hyppo_serial_monitor_wait_and_write .
142
hyppo_set_mapping
Service: Copies the source area into the current 45GS02 memory mapping.
Preconditions: The source area starts on a page boundary between $0000 and
$7E00 and is at least 6 bytes.
Inputs: Y The MSB of the source area.
Starting at $YY00, the current mapping info has this structure.
0 word MAPLO
2 word MAPHI
4 byte The megabyte offset for MAPLO
5 byte The megabyte offset for MAPHI
Postconditions: The CPU continues execution with the new memory mapping.
Remarks: You must take care when changing the memory mapping. Hyppo
will not take any steps to ensure the instructions after the STA are
executed regardless of the mapping. If you change the mapping of
the block where the program counter points to, the CPU will resume
with the instructions in the newly mapped block.
MAPLO is the mapping for $0000 - $7FFF.
MAPHI is the mapping for $8000 - $FFFF.
See the MEGA65 Book, 45GS02 Microprocessor (Appendix J) for
more information on MEGA65 memory mapping and banking.
143
hyppo_switch_to_task
Service: Switches context to another Hyppo task.
hyppo_terminateothertask
Service: Terminates another Hyppo task.
144
hyppo_toggle_force_4502
Service: Toggles the CPU personality between 45GS02 and 6502.
Outputs: A If bit 5 is set, the CPU is in the 45GS02 personality. If bit 5 is
clear, the CPU is in the 6502 personality.
Remarks: The others bits of the A register are undefined. Do not expect them
to be zero.
In the 6502 personality, none of the new opcodes of the 65C02,
65CE02, 4510 or 45GS02 are available. These are replaced with
the original — and often strange — behaviour of the undefined op-
codes of the 6502.
Warning This feature is incomplete and untested. Most undocu-
mented 6502 opcodes do not operate correctly when the 6502
personality is enabled.
Example: Enables the 45GS02 personality regardless of the CPU’s current
personality.
@10
; Toggle the CPU personality
; Toogle again if bit 5 of A is clear
AND #%00100000 : BEQ @10
145
hyppo_toggle_rom_writeprotect
Service: Toggles the write-protection for $20000 – $3FFFF.
Outputs: A If bit 2 is set, $20000 – $3FFFF cannot be written to.
Remarks: The others bits of the A register are undefined. Do not expect them
to be zero.
If you simply want to disable or enable the protection, you can use
hyppo_rom_writeenable and hyppo_rom_writeprotect .
146
hyppo_writeintotask
Service: Writes into the memory of another Hyppo task.
147
SYSTEM PARTITION SERVICES
hyppo_configsector_apply
Service: Applies the system configuration sector currently loaded into mem-
ory.
hyppo_configsector_read
Service: Reads the system configuration sector into memory.
hyppo_configsector_write
Service: Writes the system configuration sector from memory.
hyppo_dmagic_autoset
Service: Sets the DMAgic revision based on the loaded ROM.
148
FREEZER SERVICES
hyppo_freeze_self
Trap: LDA #$xx : STA $D67F : CLV
Service: Launches the freezer.
hyppo_get_slot_count
Service: Gets the number of freeze slots.
hyppo_locate_freeze_slot
Service: Locates the first sector of a freeze slot.
hyppo_read_freeze_region_list
Service: Reads the freeze region list.
hyppo_unfreeze_from_slot
Service: Unfreezes from a freeze slot.
149
150
PART V
MULTI-MEDIA AND DATA
CONVERSION
152
PART VI
GEOS Development
154
PART VII
HARDWARE
156
CHAPTER 16
Using Nexys4 boards as a
MEGA65
• Building your own MEGA65 Compatible
Computer
• Working Nexys4 Boards

• Power, Jumpers, Switches and Buttons
• Keyboard
• Preparing microSDHC card
• Loading the bitstream from QSPI
• Widget Board
• PMOD-to-Joystick Adapter
• Useful Tips
158
159
160
BUILDING YOUR OWN MEGA65
COMPATIBLE COMPUTER
You can build your own MEGA65-compatible computer by using either a Nexys4DDR
(aka. Nexys A7) or the older Nexys4 (Non-DDR) FPGA development boards. This ap-
pendix describes the process to set up a Nexys4DDR (Nexys A7) board for this pur-
pose (which is the newer, preferred board). The older non-DDR Nexys4 board is also
supported, and the instructions are the same, except that you must use a bitstream
designed for that board. Using a Nexys4DDR bitstream on a non-DDR Nexys4 board,
or vice versa, may cause irreparable damage to your board, so make sure you have
the correct bitstream to suit your board.
DISCLAIMER: M.E.G.A cannot take any responsibility for any damage that may occur
to your Nexys4DDR/NexysA7/Nexys4 boards.
161
WORKING NEXYS4 BOARDS
There are currently 3 Nexys FPGA boards which can be setup as a MEGA65:
The Nexys4 board

No longer manufactured but still available for sale on some websites with old stock.
Documentation:
• https://reference.digilentinc.com/reference/programmable-logic/
nexys-4/reference-manual
• https://reference.digilentinc.com/_media/reference/
programmable-logic/nexys-4/nexys4_rm.pdf
The Nexys4DDR board

No longer manufactured but still available for sale on some websites with old stock.
Documentation:
nexys-4-ddr/reference-manual
programmable-logic/nexys-4-ddr/nexys4ddr_rm.pdf
162
The Nexys A7
This is the re-branded version of the above Nexys4 DDR board:
Documentation:
nexys-a7/reference-manual
programmable-logic/nexys-a7/nexys-a7_rm.pdf
163
POWER, JUMPERS, SWITCHES AND
BUTTONS
This top-down picture highlights the key jumper positions of interest on the Nexys4
board:
The Nexys4 boards can be powered in two ways: using an external power supply, or
from a standard USB port.
164
Micro-USB Power
Connect your micro-usb cable to a USB port on a USB charger or PC to provide power.
Connect the other end to the Nexys4’s micro-usb connector. Place the JP3 jumper on
pins 1 and 2 to select USB power. Use the switch to power up the Nexys4.
External Power Supply
The MEGA65 core can consume a lot of power, and a standard USB port could poten-
tionally be too little for the Nexys4 board. In particular, writing to the SD card might
hang or perform odd behaviour. Therefore you should consider a 5V power supply.
Digilent sell a power supply for the Nexys4 board, and we recommend you use this to
ensure you avoid the risk of damage to your Nexys4 board. The chosen power supply
should be center positive, 2.1mm internal diameter plug, and should deliver 4.5VDC
to 5.5VDC rated at least 1 Amp.
165
Connect the power supply cable to the supply plug of the Nexys4. Place the JP3
jumper on pins 2 and 3 to select WALL power. Use the switch to power up the Nexys4.
Other Jumpers and Switches

For your initial set up, we’d suggest you set the following jumpers on your Nexys4 board
to these positions:
• JP1 - USB/SD
• JP2 - SD
This will assure that the bitstream files will get loaded from your SD card on start-up.
At some later stage, you may prefer to load the bitstream from the on-board QSPI
flash, and at that point, you can revisit your JP1 jumper setting and adjust it to the
QSPI position.
All 16 switches on the lower edge of the board must be set to the off position.
166
Connections and Peripherals
A USB keyboard can be connected to the USB port. Only a keyboard that lacks a USB
hub will work with the Nexys4 board. Generally, extremely cheap keyboards will work,
while more expensive keyboards tend to have a USB hub integrated, and will not work.
You may need to try several keyboards before you find one that works.
You can connect a VGA monitor to the VGA port.
The mono audio-out jack can be connected to the line-in of an amplifier.
Communicating with your PC

There may be occasions where you wish to communicate with your Nexys4 board from
your PC, in order to perform activities such as:
• Flash your QSPI flash chip via Vivado
167
• Upload bitstream files directly from your PC (via m65 tool)
• Make use of support tools such as M65Connect, m65, mega65_ftp, m65dbg,
etc
On such occasions, you will need to connect your micro-usb cable up to your PC.
Onboard buttons
The “CPU RESET” button will reset the MEGA65 when pressed, while the “PROG” button
will cause the FPGA itself to reload the MEGA65 core. The main difference between
the two is that CPU RESET is faster, and does not clear the contents of memory, while
the FPGA button is slower, and does reset the contents of memory.
Two of the five buttons in the cross arrangement can also be used: BTND acts as though
RESTORE
you have pressed , while BTNC will trigger an IRQ, as though the IRQ line had
been pulled to ground.
168
KEYBOARD
The keyboard layout is positional rather than logical. This means that keys in similar
positions to the keys on a C65 keyboard will have similar function. This relationship
assumes that your USB keyboard uses a US keyboard layout.
To help you locate what the various MEGA65 keys are mapped to, the MEGA65 has a
built-in virtual keyboard test feature. This can be accessed in two ways.
ALT
The easiest way is to keep held down in while switching on the Nexys4, or reset-
ting the Nexys4 with the “PROG” button. The configure menu will be presented and
by pressing 3, the virtual keyboard will be presented on a black background.
Pressing a key on the USB keyboard will show the highlighted key on the virtual key-
board to help you identify the key mapping.
The other way to access the virtual keyboard is from within the MEGA65. Hold
TAB
` and press to access the Matrix Mode Debugger. From here, enter the
following:
s ffd3615 ff
This will open a semi-transparent virtual keyboard at the top of the screen. Alterna-
tively:
s ffd3615 ff ff
This will open a semi-transparent virtual keyboard in the centre of the screen.
TAB
Hold ` and press to exit Matrix Mode Debugger and return to the MEGA65.
169
Some key mappings with a USB key-
board
RESTORE
is mapped to the PAGE UP key.
RUN ESC
STOP is mapped to .
170
PREPARING MICROSDHC CARD
The MEGA65 requires an SDHC card of between 4GB and 64GB capacity. Some
SDXC cards may work, however, this is not officially supported.
Preparation steps for the Nexys4 board’s SD card share much in common with the
steps needed for real MEGA65 hardware, and as such, it is worth having a look over
the MEGA65 Book, Configuring Your MEGA65 (section 4) if you ever need details.
So in this section, we’ll provide more details on the distinctive steps, and be more brief
on the common steps.
One point of distinction between the Nexys board and the real MEGA65 hardware is
that the latter already has a default bitstream/core provided, which permits you to
format your SD card in the specific style required by the MEGA65.
For Nexys4 board owners however, you have no such default bitstream, so see the
MEGA65 Book for more details on where the appropriate ”nexys4.bit” or ”nexys4ddr-
widget.bit” files for your device can be downloaded from.
Preparation Steps
The steps are:
• Format the SD card in a convenient computer using the FAT32 file-system. The
MEGA65 and Nexys4 boards do not understand other file systems, especially the
exFAT file system.
• Copy your bitstream file (with name ending in “.bit”) onto the SD card.
• Insert the SD card into the SD card slot on the under-side of the Nexys4 board.
• Switch on the Nexys4 board.
ALT
• Enter the Utility Menu by holding down on the USB keyboard you have
connected to the Nexys4 board.
• Enter the FDISK/FORMAT tool by pressing 2 when the option appears on the
MEGA65 boot screen.
• Follow the prompts in the FDISK/FORMAT program to again format the SD card
for use by the MEGA65.
The FDISK tool will partition your SD card into two partitions and format
them.
171
– One is type $41 = MEGA65 System Partition, where the save slots, config-
uration data and other files live.
(This partition is invisible in i.e. Win PCs).
– The other partition with type $0C = VFAT32, where KERNAL, support files,
games, and so on, will be copied to later.
(This partition is visible on i.e. Win PCs).
• Once formatting is complete, switch off the Nexys4 board and remove the mi-
croSDHC card from the Nexys board and put it back into your PC
• This time, copy the following items onto the SD card:
– The bitstream file
– The extracted files from within either the ”SD essentials.rar” or ”SD es-
sentialsNoROM.rar” file that you downloaded from the MEGA65 filehost.
(See the MEGA65 Book, ?? (??) for more details).
– If you have sourced your own preferred ROM file (e.g. ”911001.BIN”), copy
it onto the SD card also, and rename it to ”MEGA65.ROM” (uppercase is
essential).
– Any .D81 disk image files you wish to make use of.
* Note that if a file named MEGA65.D81 is added to the SD card, it will

be mounted automatically on startup.
* Make sure that all .D81 files have names that fit the old DOS 8.3 char-
acter limit, and are upper case. This restriction will be removed in a
future release.
• Remove the SD card and reinsert it into your Nexys4 board.
• Power the Nexys4 board back on. The MEGA65 should boot within 15 seconds.
• On first start up, you will find yourself at the on-boarding screen, of which more
details can be found in the MEGA65 Book, Configuring Your MEGA65 (section 4)
.
Congratulations. Your MEGA65 has been set up and is ready to use.
Please note that the above method of copying the bitstream file to the SD card means
that the bitstream is loaded into the Nexys FPGA each time on boot - which takes
around 13 seconds for the system to start. The bitstream can also be flashed using
Vivado software into the QSPI flash to deliver a boot up time of 0.3 seconds.
For more detailed information on preparing and configuring your MEGA65, please
refer to the MEGA65 Book, Configuring Your MEGA65 (section 4) chapter.
172
LOADING THE BITSTREAM FROM QSPI
While loading the bitstream from the SD card is the suggested (and well-trodden)
path this document has chosen, of late, more nexys4 users have been exploring the
alternative pathway of loading the bitstream from the QSPI flash. Some potential
reasons they have chosen this pathway are:
• Faster loading times (0.3 seconds versus 13 seconds)
• Some people were interested in the possibility of flashing multiple cores onto
their QSPI (via steps described in the the MEGA65 Book, How a MEGA65 Can
Be Upgraded (section 5) Chapter)
• Some people have experienced niggling issues with the SD card pathway, such
as:
– System unable to reboot from on-boarding screen
– System unable to reboot from freeze-menu after switching between
PAL/NTSC
In time, if this proves to be a more popular pathway, we can revise our documentation
here to suit it. Here are some steps in brief.
Preparation Steps
For users that want to try this pathway, you will need to adjust the JP1 jumper setting
to use QSPI and then follow the steps in the Flashing the FPGAs and CPLDs in the
MEGA65 chapter in relation to Installing Vivado and Flashing the main FPGA using
Vivado.
Be forewarned that the installation of Vivado is a lengthy process (both in terms of
download time, and installation time).
Once you have flashed Slot0 of your QSPI chip via Vivado, you can then follow the
steps described in the MEGA65 Book, Configuring Your MEGA65 (section 4) to perform
the custom SD card formatting, installing of ROM and support files and on-boarding.
WIDGET BOARD
For Nexys board owners (all models), you may be interested in adding a widget board
to your nexys device, in order to allow you to connect to:
• a genuine C64 or C65 keyboard
173
• 2 DB-9 joysticks
• Paddles or a 1351 Mouse
• Cartridges (not functioning as yet)
The widget board connects to your nexys board via its PMOD connectors.
It presently is only available as an unpopulated PCB, purchasable from here:
• https://oshpark.com/shared_projects/Y37xg9N7
The firmware, pcb diagram, schematic diagram and bill of materials can be found
within the following github project:
• https://github.com/sy2002/DM65PIC
You will need to purchases parts from the bill of materials separately and populate the
board yourself.
You may find this forum64.de thread of interest, if you would like to read on the expe-
riences of others that undertook this process, or if you have questions of your own to
ask:
• https://www.forum64.de/index.php?thread/
90465-mega-65-ports-add-on-card-still-available-if-where
The pcb (c65Keyb.brd) and schematic (c65Keyb.sch) files can be found within the ’ea-
gle/’ subfolder of the DM65PIC project, and can be viewed via the free tool ’AutoDesk
Eagle’, available here:
• https://www.autodesk.com/products/eagle/free-download
Here are some photos of the widget board in use:
174
175
For convenience, the pcb and schematics diagrams for the widget board have also
been provided in Chapter/Appendix C on page 289.
Some additional backstory notes for the board are:
• The widget board is originally meant to sit inside a c65 case
• Expansion port is not usable and a bit needs to be cut out for c64 case
• Would be reasonable to adapt it for c64 case use (which definitely will be the
more regular use)
PMOD-TO-JOYSTICK ADAPTER
As an alternate (and cheaper) option for those that just want to add a DB9 joystick
port via the PMOD connectors, a user from the community, TheChief, has devised a
means to do so. More information can be found in the following Discord thread:
• https://discord.com/channels/719326990221574164/
903079038015389716/929369283119685643
176
PMOD-JA
Joystick action DB9 Connections
Connections
Fire jahi(9) pin 6
Up jalo(1) pin 1
Left jalo(2) pin 3
Down jahi(7) pin 2
Right jahi(8) pin 4
USEFUL TIPS
The following are some useful tips for getting familiar with the MEGA65:
177
• Press & hold ` (or the Commodore key if using a Commodore 64 or 65 key-
board) during boot to start up in C64-mode instead of C65-mode
RUN
• Press & hold STOP during boot to enter the machine language monitor, instead
of starting BASIC.
RESTORE
• Press for approximately 1/2 - 1 second to enter the MEGA65 Freeze
Menu. From this menu you have convenient tools to change the CPU speed,
switch between PAL & NTSC video mode, change Audio settings, manage
freeze-states, select D81 disk images, examine and modify memory of the frozen
program, among other features. This is in many ways the heart of the MEGA65,
so it is well worth exploring and getting familiar with.
• Type POKE0,65 in C64-mode to switch the CPU to full speed (40MHz). Some soft-
ware may behave incorrectly in this mode, while other software will work very
well, and run many times faster than on a C64.
• Type POKE0,64 in C64-mode to switch the CPU to 1MHz.
• Type SYS58552 in C64-mode to switch to C65-mode.
• Type GO64 in C65-mode and confirm, by pressing Y, to switch to C64-mode, which
is the same as on a C128.
• The C65 ROM makes device 8 the default, so you can normally leave off the ,8
from the end of LOAD and SAVE commands.
SHIFT RUN
• Pressing + STOP from either C64 or C65-mode will attempt to boot from
disk.
Have fun! The MEGA65 has been lovingly crafted over many years for your enjoyment.
We hope you have as much fun using it as we have had creating it!
The MEGA Museum of Electronic Games & Art welcomes your feedback, suggestions
and contributions to this open-source digital heritage preservation project.
178
PART VIII
APPENDICES
180
APPENDIX A
Flashing the FPGAs and CPLDs
in the MEGA65
• Suggested PC specifications
• Warning
• Installing Vivado
• Installing the FTDI drivers
• Flashing the main FPGA using Vivado
• Flashing the CPLD in the MEGA65’s
Keyboard with Lattice
Diamond
• Flashing the MAX10 FPGA on the
MEGA65’s Mainboard
with INTEL QUARTUS
182
183
184
The MEGA65 is an open-source and open-hardware computer. This means you are
free, not only to write programs that run on the MEGA65 as a finished computer, but
also to use the re-programmable chips in the MEGA65 to turn it into all sorts of other
things.
If you just want to install an upgrade core for the MEGA65, or a core that lets you use
your MEGA65 as another type of computer, you probably want to look in the MEGA65
Book, How a MEGA65 Can Be Upgraded (section 5) instead.
This chapter is more intended for people who want to help develop cores for the
MEGA65. This chapter may also be of interest to Nexys4 board owners that are inter-
ested booting their devices from the on-board QSPI flash memory chip (rather than a
bitstream file on the SD card). This will require flashing an .mcs file onto their board’s
QSPI chip, so as to provide an initial bistream in the ’Slot 0’ position.
These re-programmable chips are called Field Programmable Gate Arrays (FPGAs) or
Complex Programmable Logic Devices (CPLDs), and can implement a wide variety of
circuits. They are normally programmed using a language like VHDL or Verilog. These
are languages that are not commonly encountered by most people. They are also
quite different in some ways to “normal” programming languages, and it can take a
while to understand how they work. But with some effort and perseverance, exciting
things can be created with them.
SUGGESTED PC SPECIFICATIONS
Be prepared to install many gigabytes of software on a Linux or Windows PC, before
you will be able to write programs for the FPGAs and CPLDs in the MEGA65. Also,
”compiling” complex designs can take up to several hours, depending on the speed
and memory capacity of your computer. We recommend a computer with at least
12GB RAM (preferably 16GB) if you want to write programs for FPGAs and CPLDs. On
the other hand, if all you want to do is load programs onto your MEGA65’s FPGAs and
CPLDs that other people have written, then most computers running a recent version
of Windows or Linux should be able to cope.
• OS: Linux or Windows
• CPU Speed: As fast as you can get your hands on!
• Number of cores: Ideally, 8 or more, as the free license of Vivado can make use
of a max of 8 cores.
• Hard disk space: Have about 70GB or more. The exact amount used depends
on how many components within Vivado you install (bear in mind that the full
install file is about 50GB in itself)
185
• Memory: minimum of 12GB (ideally, have more, to play it safe)
WARNING
Before we go any further, we do have to provide a warning about reprogramming the
FPGAs and CPLDs in the MEGA65. Re-programming the MEGA65 FPGA can poten-
tially cause damage, or leave your MEGA65 in an unresponsive state from which it is
very difficult to recover, i.e., “bricked”. Therefore if you choose to open your MEGA65
and reprogram any of the FPGAs it contains, it is no longer possible to guarantee its
correct operation. Therefore, we cannot reasonably honour the warranty of the device
as a computer. You have been warned!
INSTALLING VIVADO
Installation of Vivado is required to flash the QSPI flash memory within
your MEGA65 target device, whether it be a MEGA65 R2/R3/R3A/R4,
Nexys4/Nexys4DDR/NexysA7, MEGAphone or other.
Vivado is also the tool used to perform compilation (synthesis, as it is preferably called)
of FPGA bitstreams.
To get started, connect to https://www.xilinx.com/support/download.html
186
Select 2020.2 version
NOTE : Some users still have success with using older versions, as the main aim here
is to install a version that supports the FPGA of your target hardware.
I.e., the Artix7 100T (for Nexys and R2) or 200T (R3/R3A/R4).
Click on Xilinx Unified Installer 2020.2: Windows Self Extracting Web Installer EXE -
248.44MB
187
You will be asked to create an account in order to sign in and be able to download
the installation program.
Your credentials will also be requested when doing the installation.
After having signed in, you have to provide some personal information and then click
on Download
188
Execute the installer as Administrator (Xilinx_Unified_2020.2_1118_1232_Win64.exe).
Click on Allow Access.
Click on Next.
189
Enter your credentials and click on Next.
Select Vivado and click on Next.
190
Select ”Vivado HL WebPACK” and click on ”Next”
We’d suggest selecting only the ”7 Series” devices, as our chosen FPGA is within this
series, and de-selecting the other series will save you about 6GB in download size.
Then click on ”Next”
Warning: As stated, disconnect any USB cable that would be connected to your PC
from the Nexys board.
191
Agree with all the End User Licence Agreement and Terms and conditions and click
on ”Next”.
Choose the location where you want to install the software and click on ”Next”.
Warning : You are about to download 20GB of software and you need 70GB to per-
form the installation.
192
Click on ”Yes”
Click on ”Install”
193
Wait for the installation to complete. At the very end of the installation you will be
asked if you want to install Xilinx device software.
Click on ”Install”
Let the installation complete.
194
The installation is completed. Click on ”OK”
You end up with the following icons on your desktop:
Note: Ubuntu users might need to install one missing dependency with: sudo apt
install libtinfo5
195
Launch Vivado 2020.2
Click on ”Help”->”Obtain a licence Key”
196
This launches the Vivado licence manager
Select ”Get Free ISE WebPACK, ISE/Vivado IP or PetaLinux Licenses”
Click on ”Connect Now”
197
Connect with the user account you have created to be able to download the Vivado
software. If you were not already connected to Xilinx website, this will take you to the
main webpage. Go back in the licence manager (which is not closed)
Click again on ”Connect Now” (ensure ”Get Free ISE WebPACK, ISE/Vivado IP or
PetaLinux Licenses” is still selected)
198
You then register your personal information on the Vivado website, and click on ”Next”.
Select ”ISE WebPACK Licence” and ”Vivado Design Suite: HL WebPACK 2015 and
Earlier License”
Then click on ”Generate Node-Locked Licence”
199
Click on ”Next”
Click on ”Next”
200
Check your email box : You should have received an email from Xilinx, Inc. with a
licence file attached and named ”Xilinc.lic”.
Retrieve this file on your PC and keep it in safe place.
Go back to the licence manager (which is still running).
Set ”Load License” and click on ”Copy License”
201
Browse to the location where you saved ”Xilinc.lic” file, select it and click on ”Open”.
Click on ”OK” and close the Vivado licence manager.
Your Vivado software is registered and you can now use it.
INSTALLING THE FTDI DRIVERS

The FTDI drivers are needed in order for your PC to communicate with the hardware’s
JTAG port and serial comms port (note that the single physical USB connection made
to your PC actually provides these two ports).
202
Linux drivers
Some Linux users have reported that they have found the FTDI drivers to be installed
within their Linux distributions out-of-the-box, while others have found they needed to
run this extra command after installing Vivado:
cd /opt/Xilinx/Vivado/2018.3/data/xicom/cable_drivers/lin64/install_script/install_drive
sudo ./install_drivers
Windows drivers
Download the following archive to install the drivers:
• https://www.ftdichip.com/Drivers/CDM/CDM21228_Setup.zip
Unzip the file CDM21228_Setup.zip, you get the file CDM21228_Setup.exe.
Warning:
Before installing the drivers, it is imperative to switch off the Nexys4 board and to
disconnect the USB cable from the PC.
Review the devices already installed before the installation:
203
Run the file CDM21228_Setup.exe as administrator:
Confirm that you want to run the program.

Click on ”Extract”.
204
Click on ”Next >”
Accept the agreement and click on ”Next >”.
The installation of the drivers starts.
205
Click on ”Finish”.
Connect the USB cable to a USB port on the PC without turning on the Nexys4 board.
Connecting the USB cable triggers the appearance of new devices.
• An additional COM port has been installed: This is the COM port that will be
used to communicate with the Nexys4 board.
• An additional USB composite device has been installed.
206
• Two USB serial converter devices have been installed.
At this point the Nexys4 board has still not been powered up.
For more information about the installed drivers, you can download the corresponding
documentation:
• https://ftdichip.com/wp-content/uploads/2020/08/AN_
396-FTDI-Drivers-Installation-Guide-for-Windows-10.pdf
• https://ftdichip.com/wp-content/uploads/2021/01/AN_119_FTDI_
Drivers_Installation_Guide_for_Windows7.pdf
FLASHING THE MAIN FPGA USING

VIVADO
Firstly, to clarify that when we say ’flashing the FPGA’, in reality, what we mean is that
we are flashing the QSPI flash memory chip that the FPGA makes use of upon startup
in order to quickly load the bitstream from.
The diagram below shows two common pathways that the FPGA can load bitstreams
at startup:
• We can first flash a bitstream/core-file onto the QSPI flash memory chip, and
the FPGA can load this quickly at power-up. Flashing the QSPI is quite slow, but
the reward of a fast boot-up time is an advantage.
207
• Nexys board users can drop a bitstream file onto our SD card and let the FPGA
load it (somewhat more slowly) from there at power-up. This allows them to
swap/upgrade bitstreams quickly without the need for a TE0790-03 JTAG pro-
gramming module. This feature is planned to be added to the MEGA65 later,
though.
In this section, we describe the pathway that makes use of the QSPI.
Many of the following steps in this section are applicable not only to MEGA65
R2/R3/R3A/R4 owners, but Nexys4 board owners too. There are a few points of
distinction along the way that readers will be made aware of.
If you choose to proceed, you will need a functioning installation of Xilinx’s Vivado
software, and the FTDI drivers installed, as described in the earlier sections.
You will also need to download or build an .mcs bitstream file (and optional .prm check-
sum verification file) that you intend to flash onto the QSPI chip via Vivado. See the
MEGA65 Book for more details on where such files can be downloaded.
208
For MEGA65 R2/R3/R3A/R4 owners:
You will need a TE0790-03 JTAG programming module. It is also neces-

sary to have dip-switches 1 and 3 in the ON position and dip-switches 2 and 4
in the OFF position on the TE-0790. With your MEGA65 disconnected from the
power, the TE-0790 must be installed on the JB1 connector which is located
between the floppy data cable and the audio jack. The gold-plated hole of the
TE-0790 must line up with the screw hole below. The mini-USB cable will then
connect on the side towards the 3.5” floppy drive. The following image shows
the correct position: The TE0790 is surrounded by the yellow box, and the dip-
switches by the red box. Dip-switch 1 is the one nearest the floppy data cable.
209
For Nexys4 board owners:
Simply connect your micro-usb cable between your Nexys4 board and
your PC via the port labeled ’PROG UART’ (J6), as shown:
Also, set J1 jumper to the QSPI position:
• Connect your non-8-bit computer to the FPGA programming device using the
appropriate USB cable.
• Switch the MEGA65 computer ON.
• Open Vivado.
210
Step 1a: Create a new Vivado project with ”File”, ”Project”, ”New...”.
NOTE: On future occasions that you need to flash the QSPI, just re-open this project
(no need to create a new project each time).
Step 1b: The ’New Project’ wizard appears. Click on ”Next”:
211
Step 1c: Name your project and choose the location you like, then click on ”Next”:
Step 1d: Keep the default selected options and click on ”Next”:
212
Step 1e: Do not add any sources, keep the default selected options and click on
”Next”:
Step 1f: Keep the default selected options and click on ”Next”:
213
Step 1g: Click on ”Finish”:
Step 2: In the left column, select ”Open Hardware Manager” at the very bottom.
214
Step 3: Connect to the FPGA:
Under ”Open Hardware Manager”, choose ”Open Target”, then ”Auto Connect”.
Step 4: Wait a moment, ”Connecting to server...” should automatically close without

dropping an error to the console.
215
Step 5: Under ”Open Hardware Manager”, choose ”Add Configuration Memory De-
vice”, then:
• For MEGA65R3/R3A/R4: ”xc7a200t_0”
• For Nexys4 and MEGA65R2: ”xc7a100t_0”.
Step 6a: Select Memory Part:
In the newly opened dialogue:

• For MEGA65R2/R3: type ”S25fl256s” (without quotes), then select
”s25fl256sxxxxxxx0-spi-x1_x2_x4” (the upper one) and click ”OK”.
• For MEGA65R3A/R4: Vivado cannot flash the larger flash part on these boards.
Use the flash menu on the MEGA65.
• For Nexys4: type ”S25fl128s” (without quotes), then select ”s25fl128sxxxxxxx0-
spi-x1_x2_x4” (the upper one) and click ”OK”.
216
Step 6b: Click on ”OK” to confirm you want to program the configuration memory
device now.
Step 6c: If you do not see such a popup, or wish to reprogram the QSPI on a future
occasion, in ”Hardware” window, right click on the memory configuration and select
”Program Configuration Memory Device”:
217
Step 7: Set programming options:
In the next dialogue, set the ”Configuration file” to the path of your ”.mcs” bitstream
file. You can also optionally set the ”PRM file” field to the path of your ”.prm” file.
Leave all other parameters as they are (see screenshot below).
Step 8: Patiently wait for the programming to finish. This can take several minutes
as the Vivado software erases and then reprograms the flash memory that is used to
initialise the FPGA on power-up.
218
Step 9: If your screen looks like the screenshot below, your new bitstream has been
successfully flashed into Slot0 of your QSPI flash memory!
Step 10: If you want to reflash the FPGA, you might find the ”Add Configuration
Memory Device” option in step 5 greyed out. Instead, select ”s25fl256sxxxxxxx0-spi-
x1_x2_x4” in the ”Hardware” window, press right mouse button and select ”Program
Configuration Memory Device” to flash.
219
FLASHING THE CPLD IN THE MEGA65’S
KEYBOARD WITH LATTICE DIAMOND
If you choose to proceed, you will need a TE0790-03 JTAG programming module and
a functioning installation of Lattice Diamond Programmer software. This can be done
on either Windows or Linux, but in both cases you will need to install any necessary
USB drivers. It is also necessary to have dip-switches 1 and 3 in the ON position
and dip-switches 2 and 4 in the OFF position on the TE-0790. With your MEGA65
disconnected from the power, the TE-0790 must be installed on the JB1 connector,
which is located between the floppy data cable and the audio jack. The gold-plated
hole of the TE-0790 must line up with the screw hole below. The mini-USB cable will
then connect on the side towards the 3.5” floppy drive. The following image shows the
correct position: The TE0790 is surrounded by the yellow box, and the dip-switches
by the red box. Dip-switch 1 is the one nearest the floppy data cable.
220
221
On the PCB of a R2/R3/R3A/R4 MEGA65 mainboard, dip switch 1 (the one nearest to
the user sitting in front of the machine) must be in the ON position. The other switches
must be OFF. The keyboard will go into “ambulance mode” (blue flashing lights) when
set correctly.
Connect your non-8-bit computer to the FPGA programming device using a mini-USB
cable. Switch the MEGA65 computer ON. Open the Diamond Programmer which can
be downloaded from the Internet.
Step 1: Open DIAMOND PROGRAMMER:
Select ”Create a new project from a JTAG scan”. If entry under ”Cable:” is empty,
click ”Detect Cable”.
Step 2: Create a new project:

If dialog ”Programmer: Multiple Cables Detected” appears, select the first entry (”Lo-
cation 0000”) and click ”OK”.
222
Step 3: Select cable:
You have now created a new project which should display ”MachXO2” under ”Device
Family” and ”LCMXO2-1200HC” under ”Device”
Step 4: New Diamond Programmer project:

Choose ”File” then ”Open File” to load the Diamond Pprogrammer project with the
MEGA65 keyboard firmware update.
223
Step 5: Open project:
Navigate into the folder with the extracted MEGA65 keyboard firmware files you have
received and select the file ending with ”.xcf”.
Step 6: Select project file:

Click the three dots under ”File Name” to set the correct path and find the file ending
with ”.jed”.
224
Step 7: Choose correct path of .jed file:
Select the file ending with ”.jed” and click ”OK”.
Step 8: Select .jed file:

Click on the icon with the green arrow facing down ”PROGRAM”, which looks similar
to the Diamond Programmer program icon.
225
Step 9: Select cable:
After a moment the Output window should display ”INFO - Operation: successful.”
and the ”Status” cell should go green (does not always happen).
Step 10: Operation successful:

You have now successfully flashed the MEGA65 keyboard. If you wish you can now
save the project for later use.
226
FLASHING THE MAX10 FPGA ON THE
MEGA65’S MAINBOARD WITH INTEL
QUARTUS
If you choose to proceed, you will need a TEI0004 - Arrow USB Programmer2 module
with TEI0004 driver installed and a functioning installation of Quartus Prime Program-
mer Lite Edition. This can be done on either Windows or Linux, but in both cases you
will need to install any necessary USB drivers. With your MEGA65 disconnected from
the power, the TEI0004 must be installed on the J17 connector, which is located be-
tween the floppy data cable and the ARTIX 7 FPGA on the Mainboard. The micro-USB
port of the TEI0004 must face in the opposite direction of the HDMI and LAN sockets,
towards the trap door. The following image shows the correct position.
On the PCB R2/R3/R3A/R4 MEGA65 mainboard, all dip switches must be in the OFF
position. The main FPGA of the MEGA65 must not contain a valid bitstream. The
easiest way to do this is if you have a TE0790 JTAG adapter: you can then use the
m65 tool from a connected computer to begin sending a bitstream via JTAG, and then
using control-C to abort the m65 tool before it can finish loading the bitstream.
227
228
Connect your non-8-bit computer to the FPGA programming device using a micro-USB
cable. Open Quartus Prime Programmer Lite Edition, which can be downloaded from
the Internet.
Step 1: Open Quartus Prime Programmer Lite Edition:
Click the ”Hardware Setup” button in the top left corner of the Quartus Prime Pro-
grammer window.
Step 2: Enter Hardware Setup:

In the newly appeared window under ”Currently selected hardware” choose ”Arrow-
USB-Blaster”. If ”Arrow-USB-Blaster” does not appear, verify cable and drivers being
correctly installed.
229
Step 3: Select Arrow USB-Blaster:
Click the ”Add File” button from the left row and choose the latest ”.pof” file. Then
click ”Open”.
Step 4: Select Programming File:

Tick at least the three boxes under ”Program/Configure”. Also enabling all boxes under
”Verify” and ”Blank-Check” will make the process more reliable.
230
Step 5: Select Program/Configure Options:
While keeping the Reset-Button pressed, switch the MEGA65 computer ON. The key-
board will go into “ambulance mode” (blue flashing lights). If it does not, the main
FPGA is not empty - restart the whole process.
Now click on ”Start” in the left row of buttons. The progress bar in the top right corner
should quickly go to 100 percent and turn green. You have now successfully updated
your MAX10 FPGA.
If you receive an error message instead, make sure the main FPGA bitstream has been
erased and that you did not release the reset-button on the MEGA65 beforehand.
Switch off the MEGA65 and restart this step.
231
Step 6: Programming successful:
232
APPENDIX B
Trouble shooting
• Hardware
• Vivado
• mega65_ftp
234
HARDWARE
No Digital Video Output
MEGA65 R4, R5, R6
The digital video port has improved back-power isolation, to correct the “No lights
when powering on” problem. A side effect of this is that some digital video cables
incorrectly use only the shell of the connector to provide the ground signal, instead of
using the ground signals from the pins of the connector. Long-story-short: If you don’t
get an image on the digital video port, you can try one of the following solutions:
• Try different digital video cables you have. This problem only occurs with certain
brands of cables, especially thinner ones (see the image in Figure ??), that we
strongly suspect are missing the internal ground wires to save money. This is the
best solution, as it is actually the cable that is the cause of the fault, by being
non-compliant. Even if you use one of the following work-arounds, you should
still go and find a better HDMI cable that solves the problem at the root-cause.
• Connect a VGA cable to the MEGA65 and to the same monitor. This will provide
a ground connection through the VGA connector, and seemingly magically allow
the HDMI to work.
• Connect a TE0790 JTAG adapter. One user reported that this also magically
worked-around the problem.
• Bridge the digital video connector shell to the shell of the internal full-size SD
card shell.
• Connect an splitter or repeater to the digital video port.
No lights when powering on

If there are occasions when your MEGA65 display any lights when powering on, they
relate to having certain Digital Video devices plugged in while the MEGA65 is off,
that don’t provide enough power for the keyboard’s CPLD to be properly powered on,
but enough to stop it properly resetting when the MEGA65 powers on. Removing the
Digital Video cable and switching the machine off and on again fixes the issue.
VIVADO
235
Figure B.1: Example of bad (top) and good (bottom) digital video cables. Note how
the bad cable is suspiciously thinner than the good one. This is a sign that it likely is
missing dedicated ground wires, and will cause problems on the MEGA65 R4 and later
revisions. Any “normal thickness” cable should work fine, though. You don’t need to buy
one of those over-priced “oxygen-free unobtanium-plated hand-assembled in zero-
gravity by world-famous artisans” cables. Those cables offer about as much practical
benefit sprinkling some glitter or drawing a unicorn on one end, but with much less
class.
RAM requirements
INFO: [Synth 8-256] done synthesizing module 'ram32x1024' [/home/....]
INFO: [Synth 8-256] synthesizing module 'charrom' [/home/....]
/opt/Xilinx/Vivado/2019.2/bin/loader: line 280: 2317 killed
WARNING: [Vivado 12-8222] Failed run(s) : 'synth\_1'
ERROR: Application Exception: failed to launch run 'impl\_1'
due to failures in the following run(s):
synth\_1
These failed run(s) need to be reset prior to launching 'impl\
_1' again.
This error is due to Vivado crashing because the machine doesn’t have enough RAM
for Vivado to run. Vivado requires at least 4GB to synthesise the MEGA65 target, but
8GB is better.
236
MEGA65_FTP
Missing Library
/usr/bin/ld: cannot find -lncurses
collect2: error: ld returned 1 exit status
Makefile:474: recipe for target 'bin/mega65_ftp' failed
make: *** [bin/mega65_ftp] Error 1
This error occurs when the ncurses library is missing from the computer when building
the mega65_ftp program. To rectify this issue you will need to ensure that you install
this dependency.
sudo apt-get install libncurses5-dev libncursesw5-dev
237
238
APPENDIX C
Schematics
• MEGA65 R3 Schematics
• MEGA65 R2 Schematics
• Nexys Widget Board Schematics
240
MEGA65 R3 SCHEMATICS
241
1 2 3 4
U_HDMI U_B15 U_POWER
HDMI.SchDoc B15.SchDoc POWER.SchDoc
U_Ethernet U_B16 U_PowerMain COPM1

PM1 COPM2
PM2 COPM3
PM3
Ethernet.SchDoc B16.SchDoc PowerMain.SchDoc
U_B34 U_VGA
B34.SchDoc VGA.SchDoc
A A
U_LED_SW_BUT U_FPGA-CFG U_EXT_HEADER
LED_SW_BUT.SchDoc FPGA-CFG.SchDoc EXT_HEADER.SchDoc FIDU-DOT - small FIDU-DOT - small FIDU-DOT - small
U_SYS_MAX10_CTRL U_FPGA-MGT U_EXP_Slot

SYS_MAX10_CTRL.SchDoc FPGA-MGT.SchDoc EXP_Slot.SchDoc COPM4
PM4 COPM5
PM5 COPM6
PM6
U_SOUND U_FPGA-PWR U_Floppy

SOUND.SchDoc FPGA-PWR.SchDoc Floppy.SchDoc
U_B13 U_JOY
B13.SchDoc JOY.SchDoc
FIDU-DOT - small FIDU-DOT - small FIDU-DOT - small
U_B14 U_KEYBOARD
B14.SchDoc KEYBOARD.SchDoc
B COSerial1 B
Serial1
Serial
Serialnumber 6,3 x 6.3mm
COLOGO1
LOGO1
TE Logo PRINT Layer

LOGO PRINT
C COH5 COH7 COH8 COH1 COH2 COH3 C
PIH501 PIH701 PIH801 PIH10 PIH201 PIH301

GND GND GND GND GND GND
Mount.Hole 3.2mm Mount.Hole 3.2mm Mount.Hole 3.2mm Mount.Hole 3.2mm Mount.Hole 3.2mm Mount.Hole 3.2mm
Title:
Design drawn by: IG
MEGA65
Checked by: MR
D D
Number: Rev.
Assembly variant: [No Variations] A4 TE0765
[No Variations] 03
Created by: VariantCreatedBy
Date: 2020-06-29 Copyright: Trenz Electronic GmbH Page 1 of 23
Modified by: VariantModifiedBy
Modified at: VariantDateModification Filename: TE0765.SchDoc
1 2 3 4
1 2 3 4
Grove CONN
PMOD CONN
COD1
D1
1 PID101 5
PID105 3.3V COD2 COD3
Grove_SCL0 3 PID103 D2 D3
NLB350L20N
B35_L2_N 1 PID201 5
PID205 B35_L5_N 1 PID301 5
PID305
A NLB350L20P 3.3V 3.3V A
Grove_SDA0 4 PID104 B35_L2_P 3 PID203 B35_L5_P 3 PID303
6 PID106
2
PID102 GND NLB350L10P
B35_L1_P 4 PID204 B35_L3_P 4 PID304
WE-TVS-824013 NLB350L10N
B35_L1_N 6 PID206 2
PID202 B35_L3_N 6 PID306 2
PID302
GND GND
WE-TVS-824013 WE-TVS-824013
COJ18
J18
COR128
R128PIR12801 PIR12802 4K7 NLGrove0SCL0
Grove_SCL0 1 PIJ1801 COP1
P1
3.3V COR129 NLGrove0SDA0 NLB350L50N NLB350L50P
R129 PIR12901 PIR12902 4K7 Grove_SDA0 2 PIJ1802 B35_L5_N 1 PIP101 7
PIP107 B35_L5_P
3 PIJ1803 NLB350L30N
B35_L3_N 2 PIP102 8
PIP108
NLB350L30P
B35_L3_P
3.3V
4 PIJ1804 B35_L2_N 3 PIP103
9
PIP109 B35_L2_P
GND
B35_L1_N 4 PIP104 10
PIP1010 B35_L1_P
110990037 5 PIP105 11
PIP1011
GND GND
GND GND
6 12
PIP1012
PMOD1_VCC PIC14501 PIC14601 PIP106 VCC VCC PMOD1_VCC
COC145
C145 COC146
C146 PMod 2x6 SMD Host Socket 90°
10µF
PIC14502 470nF PIC14602
10V
B COP2 B
GND GND P2
B35_L6_P 1 PIP201 7
PIP207
B35_L4_P
B35_L6_N 2 PIP202 8
PIP208 B35_L4_N
NLB350L120P
B35_L12_P 3 PIP203 9
PIP209
NLB350L120N
B35_L12_N
NLB350L100N
B35_L10_N 4 PIP204 10
PIP2010
NLB350L100P
B35_L10_P
CPLD CONFIG 5 PIP205 11
PIP2011
GND GND
GND GND
6 12
PIP2012
PMOD2_VCC PIC16201 PIC16301 PIP206 VCC VCC PMOD2_VCC
COJ17
J17 COC162
C162 COC163
CPLD_JTAGi NLM0TCK
M_TCK 1 PIJ1701 2
PIJ1702
PIC1620
10µF PIC16302 470nF
PIR15602 NLM0TDO
M_TDO 3 PIJ1703 4
PIJ1704
10V
COR156
R156 NLM0TMS
M_TMS 5 PIJ1705 6 PIC13701 3.3V GND GND
PIJ1706
4K7 7 PIJ1707 8 COC137
C137 COD4
D4 COD11
D11
PIJ1708
PIR15601 NLM0TDI
M_TDI 9 PIJ1709 10
PIJ17010 PIC13702 470nF NLB350L40N
B35_L4_N 1 PID401 5
PID405 B35_L10_P 1 PID1101
5
PID1105
NLB350L60N 3.3V 3.3V
B35_L6_N 3 PID403 B35_L10_N 3 PID1103
GND SMD-254-9132-14-10 GND GND
NLB350L60P
B35_L6_P 4 PID404
B35_L12_P 4 PID1104
NLB350L40P
B35_L4_P 6 PID406 PID402
2 B35_L12_N 6 PID1106
2
PID1102
GND GND
C C
WE-TVS-824013 WE-TVS-824013
COU35
U35
7 PIU3507 8
PIU3508
3.3V IN OUT1 PMOD2_VCC
PIC16401
COC164
C164 COR146
R146 10K NLPMOD20FLG
PMOD2_FLG2 5
PIR14601 PIR14602 PIU3502 FLG1
OUT2 PIU3505 PMOD1_VCC
PIC16402 10µF COR147
R147
PIR14701 PIR1470210K
NLPMOD10FLG
PMOD1_FLG3 PIU3503
10V NLPMOD20EN FLG2
TE0790-Base SMT PMOD2_EN 1 PIU3501
NLPMOD10EN EN1
GND PMOD1_EN 4 PIU3504
COJB1 EN2
JB1
5
PIJB105 6 PIU3506
3.3V GND
6
PIJB106
TE_JTAGi VIO PIC13801 3.3V
GND AP2196SG-13
UART COC138
NLTE0TCK
TE_TCK 4 PIJB104 3
PIJB103
NLTE0UART0RX
TE_UART_RX C138
NLTE0TDO
C TCK A
NLTE0UART0TX 470nF
PIR15702 TE_TDO 8 PIJB108 7
PIJB107
TE_UART_TX PIC13802
COR157
R157 D TDO B
NLTE0TDI
TE_TDI 10 PIJB1010 9
PIJB109
PIR15802
4K7 F TDI E
COR158
R158
NLTE0TMS
TE_TMS 12 PIJB1012 11
PIJB1011
GND Title:
PIR15701 H TMSG
10K MEGA65
D GND
1 PIJB101
GND
PIR15801 D
GND 2 PIJB102 H1
PIJB10H1
Number: Rev.
GND GND
GND GND TE0765
GND A4 03
[No Variations]
Filename: EXT_HEADER.SchDoc
1 2 3 4
1 2 3 4
5V COU2
U2 COU8
U8
NLC640IRQ
C64_IRQ COR37
R37PIR3701
4K7
PIR3702
31 PIU2031 7
PIU207
31 PIU8031 7
PIU807
NLC640RW COR38 3.3V VCCA VCCB 5V 3.3V VCCA VCCB 5V
C64_RW R38PIR3801 4K7
PIR3802 EXP 42 PIU2042 18
PIU2018 EXP 42 PIU8042 18
PIU8018
NLC640CLOCK COR39 VCCA VCCB VCCA VCCB
C64_CLOCK R39PIR3901 4K7
PIR3902 i EXP i EXP
NLC640IO1
C64_IO1 COR40
R40PIR4001 4K7
PIR4002
A CARTi i i A
C64_GAME COR41
R41PIR4101 4K7
PIR4102
NLF0DATA0DIR
F_DATA_DIR 1 PIU201 48
PIU2048
NLF0DATA0EN
F_DATA_EN NLF0CTRL0DIR
F_CTRL_DIR 1 PIU801 48
PIU8048
NLF0CTRL0EN
F_CTRL_EN
1DIR 1OE i CART 1DIR 1OE i CART
C64_EXROM COR42
R42PIR4201
4K7
PIR4202
NLC640IO2 COR43 NLF0C640D7 CARTi NLF0C640RW
C64_IO2 R43PIR4301 4K7
PIR4302 F_C64_D7 47 PIU2047 2
PIU202 C64_D7 F_C64_RW 47 PIU8047 2
PIU802 C64_RW
NLC640ROMLCOR45 NLF0C640D6 1A1 1B1 NLF0C640ROMH 1A1 1B1
C64_ROML R45PIR4501 4K7
PIR4502 F_C64_D6 46 PIU2046 3
PIU203 C64_D6 F_C64_ROMH 46 PIU8046 3
PIU803 C64_ROMH
NLC640BA COR71 DATAi NLF0C640D5 1A2 1B2 NLF0C640IO1 1A2 1B2
C64_BA R71PIR7101 4K7
PIR7102 F_C64_D5 44 PIU2044 5
PIU205 C64_D5 F_C64_IO1 44 PIU8044 5
PIU805 C64_IO1
NLC640DMA COR90 NLF0C640D4 1A3 1B3 1A3 1B3
C64_DMA R90PIR9001 4K7
PIR9002 F_C64_D4 43 PIU2043 6
PIU206 C64_D4 43 PIU8043 6
PIU806
NLC640D7 COR91 NLF0C640D3 1A4 1B4 1A4 1B4
C64_D7 R91PIR9101
4K7
PIR9102
F_C64_D3 41 PIU2041 8
PIU208
C64_D3 41 PIU8041 8
PIU808
NLC640D6 COR92 NLF0C640D2 1A5 1B5 NLF0C640IO2 1A5 1B5
C64_D6 R92PIR9201 4K7
PIR9202 F_C64_D2 40 PIU2040 9
PIU209 C64_D2 F_C64_IO2 40 PIU8040 9
PIU809 C64_IO2
NLC640D5 COR93 NLF0C640D1 1A6 1B6 NLF0C640ROML 1A6 1B6
C64_D5 R93PIR9301 4K7
PIR9302 F_C64_D1 38 PIU2038 11
PIU2011 C64_D1 F_C64_ROML 38 PIU8038 11
PIU8011 C64_ROML
NLC640D4 COR94 NLF0C640D0 1A7 1B7 NLF0C640BA 1A7 1B7
C64_D4 R94PIR9401 4K7
PIR9402 F_C64_D0 37 PIU2037 12 EXP
PIU2012 C64_D0 F_C64_BA 37 PIU8037 12 EXP
PIU8012 C64_BA
NLC640D3 COR95 1A8 1B8 1A8 1B8
C64_D3 R95PIR9501 4K7
PIR9502 i i
NLC640D2
C64_D2 COR96
R96PIR9601
4K7
PIR9602
NLF0LADDR0DIR
F_LADDR_DIR 24 PIU2024 25
PIU2025
NLF0ADDR0EN
F_ADDR_EN NLF0HADDR0DIR
F_HADDR_DIR 24 PIU8024 25
PIU8025
F_ADDR_EN
NLC640D1 COR97 2DIR 2OE i CART 2DIR 2OE i CART
C64_D1 R97PIR9701 4K7
PIR9702
NLC640D0
C64_D0 COR98
R98PIR9801 4K7
PIR9802
NLF0C640A7
F_C64_A7 36 PIU2036 13
PIU2013 C64_A7 NLF0C640A15
F_C64_A15 36 PIU8036 13
PIU8013 C64_A15
NLF0C640A6 2A1 2B1 NLF0C640A14 2A1 2B1
F_C64_A6 35 PIU2035 14
PIU2014 C64_A6 F_C64_A14 35 PIU8035 14
PIU8014 C64_A14
ADRi NLF0C640A5 2A2 2B2 ADRi NLF0C640A13 2A2 2B2
F_C64_A5 33 PIU2033 16
PIU2016
C64_A5 F_C64_A13 33 PIU8033 16
PIU8016
C64_A13
NLF0C640A4 2A3 2B3 NLF0C640A12 2A3 2B3
F_C64_A4 32 PIU2032 17
PIU2017
C64_A4 F_C64_A12 32 PIU8032 17
PIU8017
C64_A12
NLF0C640A3 2A4 2B4 NLF0C640A11 2A4 2B4
F_C64_A3 30 PIU2030 19
PIU2019 C64_A3 F_C64_A11 30 PIU8030 19
PIU8019 C64_A11
NLF0C640A2 2A5 2B5 NLF0C640A10 2A5 2B5
F_C64_A2 29 PIU2029 20
PIU2020 C64_A2 F_C64_A10 29 PIU8029 20
PIU8020 C64_A10
B NLF0C640A1 2A6 2B6 NLF0C640A9 2A6 2B6 B
F_C64_A1 27 PIU2027 22
PIU2022 C64_A1 F_C64_A9 27 PIU8027 22
PIU8022 C64_A9
NLF0C640A0 2A7 2B7 NLF0C640A8 2A7 2B7
F_C64_A0 26 PIU2026 23
PIU2023
C64_A0 F_C64_A8 26 PIU8026 23
PIU8023
C64_A8
2A8 2B8 2A8 2B8
3.3V COU30
U30 28 PIU2028 4
PIU204 28 PIU8028 4
PIU804
GND GND GND GND
1 PIU3001 5
PIU3005 34 PIU2034 10
PIU2010 34 PIU8034 10
PIU8010
NLC640EXROM OE
VCC 3.3V GND GND GND GND
C64_EXROM2 PIU3002 39 PIU2039 15
PIU2015 39 PIU8039 15
PIU8015
A NLF0C640EXROM GND GND GND GND
3 PIU3003
4
PIU3004
F_C64_EXROM 45 PIU2045 21
PIU2021
45 PIU8045 21
PIU8021
GND GND
Y i EXP GND GND GND GND GND GND GND GND
NC7SZ126P5X SN74LVCH16T245DGV SN74LVCH16T245DGV
COJ8
J8
44 PIJ8044 43
PIJ8043
COU31 COU9 GND GND
3.3V U31 U9 42 PIJ8042 41
PIJ8041
C64_ROMH
1 PIU3101 5
PIU3105
31 PIU9031 7
PIU907
40 PIJ8040 39
PIJ8039
C64_RESET
NLC640GAME OE
VCC 3.3V 3.3V VCCA VCCB 5V 5V
C64_GAME 2 PIU3102 A
42 PIU9042 18
PIU9018
C64_IRQ 38 PIJ8038 37
PIJ8037
C64_NMI
NLF0C640GAME VCCA VCCB
3 PIU3103 4
PIU3104
F_C64_GAME EXP C64_RW 36 PIJ8036 35
PIJ8035
C64_O2
GND GNDY i EXP
i C64_CLOCK 34 PIJ8034 33
PIJ8033 C64_A15
NC7SZ126P5X 1 PIU901 48
PIU9048
C64_IO1 32 PIJ8032 31
PIJ8031
C64_A14
GND 1DIR 1OE GND
C64_GAME 30 PIJ8030 29
PIJ8029
C64_A13
NLF0C640NMI
F_C64_NMI 47 PIU9047 2
PIU902 C64_NMI C64_EXROM 28 PIJ8028 27
PIJ8027 C64_A12
C CARTi NLF0C640IRQ 1A1 1B1 C
F_C64_IRQ 46 PIU9046 3
PIU903 C64_IRQ C64_IO2 26 PIJ8026 25
PIJ8025 C64_A11
CARTi NLF0C640DMA 1A2 1B2
5V F_C64_DMA 44 PIU9044 5
PIU905 C64_DMA C64_ROML 24 PIJ8024 23
PIJ8023 C64_A10
NLC640ROMH COR99 CARTi NLFB0RIGHT 1A3 1B3 NLJB0RIGHT
C64_ROMH R99PIR9901
4K7
PIR9902
FB_RIGHT 43 PIU9043 6
PIU906
JB_RIGHT C64_BA 22 PIJ8022 21
PIJ8021
C64_A9
NLC640RESET COR100 NLFB0LEFT 1A4 1B4 NLJB0LEFT
C64_RESET R100
PIR10001
4K7
PIR10002
FB_LEFT 41 PIU9041 8
PIU908
JB_LEFT C64_DMA 20 PIJ8020 19
PIJ8019
C64_A8
NLC640NMI COR101 NLFB0DOWN 1A5 1B5 NLJB0DOWN
C64_NMI R101
PIR10101
4K7
PIR10102
FB_DOWN 40 PIU9040 9
PIU909
JB_DOWN C64_D7 18 PIJ8018 17
PIJ8017
C64_A7
NLC640O2 COR102 NLFB0FIRE 1A6 1B6 NLJB0FIRE
C64_O2 R102PIR10201
4K7
PIR10202
FB_FIRE 38 PIU9038 11
PIU9011
JB_FIRE C64_D6 16 PIJ8016 15
PIJ8015
C64_A6
NLC640A15 COR103 NLFB0UP 1A7 1B7 NLJB0UP
C64_A15 R103
PIR10301 4K7
PIR10302 FB_UP 37 PIU9037 12
PIU9012 JB_UP C64_D5 14 PIJ8014 13
PIJ8013 C64_A5
NLC640A14 COR104 1A8 1B8
C64_A14 R104
PIR10401
4K7
PIR10402
C64_D4 12 PIJ8012 11
PIJ8011
C64_A4
NLC640A13
C64_A13 COR105
R105
PIR10501
4K7
PIR10502
24 PIU9024 25
PIU9025
C64_D3 10 PIJ8010 9
PIJ809
C64_A3
NLC640A12 COR106 3.3V 2DIR 2OE GND
C64_A12 R106PIR10601
4K7
PIR10602
C64_D2 8 PIJ808 7
PIJ807
C64_A2
NLC640A11
C64_A11 COR107
R107
PIR10701 4K7
PIR10702
NLF0C640RESET
F_C64_RESET 36 PIU9036 13
PIU9013 C64_RESET C64_D1 6 PIJ806 5
PIJ805 C64_A1
CARTi 2A1 2B1
NLC640A10
C64_A10 COR108
R108
PIR10801
4K7
PIR10802
NLF0C640CLOCK
F_C64_CLOCK 35 PIU9035 14
PIU9014
C64_CLOCK C64_D0 4 PIJ804 3
PIJ803
C64_A0
NLC640A9 COR109 CARTi NLF0C640O2 2A2 2B2
C64_A9 R109
PIR10901
4K7
PIR10902
F_C64_O2 33 PIU9033 16
PIU9016
C64_O2 2 PIJ802 1
PIJ801
NLC640A8 COR110 CARTi NLF0SER0ATN 2A3 2B3 NLSER0ATN GND GND
C64_A8 R110
PIR11001
4K7
PIR11002
F_SER_ATN 32 PIU9032 17
PIU9017
SER_ATN
NLC640A7 COR111 NLF0SER0RESET 2A4 2B4 NLSER0RESET
C64_A7 R111
PIR11101
4K7
PIR11102
F_SER_RESET 30 PIU9030 19
PIU9019
SER_RESET 120-044-60
NLC640A6 COR112 NLF0MOTEB 2A5 2B5 NLMOTEB
C64_A6 R112
PIR11201
4K7
PIR11202
F_MOTEB 29 PIU9029 20
PIU9020
MOTEB
2A6 2B6
NLC640A5
C64_A5 COR113
R113
PIR11301
4K7
PIR11302
NLF0DRVSB
F_DRVSB 27 PIU9027 22
PIU9022
NLDRVSB
DRVSB Title:
NLC640A4 COR114 2A7 2B7
C64_A4 R114
PIR11401
4K7
PIR11402
26 PIU9026 23
PIU9023 MEGA65
NLC640A3 COR115 GND 2A8 2B8
C64_A3 R115
PIR11501
4K7
PIR11502
D NLC640A2 COR116 D
C64_A2 R116
PIR11601
4K7
PIR11602
28 PIU9028 4
PIU904
Number: Rev.
NLC640A1 COR117 i GND GND TE0765
C64_A1 R117
PIR11701 4K7
PIR11702 34 PIU9034 10
PIU9010 A4 03
GND GND [No Variations]
NLC640A0
C64_A0 COR118
R118
PIR11801
4K7
PIR11802
EXP 39 PIU9039 15
PIU9015
GND GND
45 PIU9045 21
PIU9021
GND GND GND GND Date: 2020-06-29 Copyright: Trenz Electronic GmbH Page 3 of 23
SN74LVCH16T245DGV
Filename: EXP_Slot.SchDoc
1 2 3 4
1 2 3 4
A A
B13
i
COU1A
U1A
BANK 13 AB11
PIU10AB11
NLB4
B4
IO_L7P_T1_13 NLB2
V16 PIU10V16 AB12
PIU10AB12 B2
3.3V VCCO_13 IO_L7N_T1_13 NLVDAC0CLK
PIC5101 PIC5201 PIC5401 COC1
PIC101C1 PIC50COC50
1C50 PIC201 W13 PIU10W13 AA9
PIU10AA9 VDAC_CLK
COC51
C51 COC52
C52 COC54
C54 COC2
C2 VCCO_13 IO_L8P_T1_13 NLB6
Y10 PIU10Y10 AB10
PIU10AB10 B6
PIC5102 470nF PIC5202 470nF PIC5402 470nF PIC1024.7µF PIC50 24.7µF PIC202 47µF VCCO_13 IO_L8N_T1_13 NLB7
AA17 PIU10AA17
AA10
PIU10AA10
B7
VCCO_13 IO_L9P_T1_DQS_13 NLB3
AB14 PIU10AB14
AA11
PIU10AA11
B3
VCCO_13 IO_L9N_T1_DQS_13 NLVDAC0SYNC0N
GND V10
PIU10V10 VDAC_SYNC_N COR159 3.3V
NLR3 IO_L10P_T1_13 NLB0 NLCPLD0CLK R159
R3 Y17 PIU10Y17 W10
PIU10W10 B0 CPLD_CLK PIR15901 PIR15902 COC77
C77
B B13i IO_0_13 IO_L10N_T1_13 NLB5 B
Y11
PIU10Y11 B5 22R PIC7701 PIC7702
IO_L11P_T1_SRCC_13 NLB1 GND
Y12
PIU10Y12
B1 1%
NLR4 IO_L11N_T1_SRCC_13 470nF
R4 Y16 PIU10Y16
W11 NLVDAC0BLANK0N
PIU10W11
VDAC_BLANK_N
B13i NLR6 IO_L1P_T0_13 IO_L12P_T1_MRCC_13 NLHSYNC COU17
R6 AA16 PIU10AA16 W12
PIU10W12 HSYNC COR126 U17
NLR7 IO_L1N_T0_13 IO_L12N_T1_MRCC_13 NLCLOCK0FPGA0MRCC R126
R7 AB16 PIU10AB16 V13
PIU10V13 CLOCK_FPGA_MRCC PIR12601 PIR12602 3 PIU1703 4
PIU1704
NLR5 IO_L2P_T0_13 IO_L13P_T2_MRCC_13 NLVSYNC CLK VDD
R5 AB17 PIU10AB17 V14
PIU10V14 VSYNC 22R
NLG6 IO_L2N_T0_13 IO_L13N_T2_MRCC_13 NLR0
G6 AA13 PIU10AA13
U15
PIU10U15
R0 1% 2 PIU1702
1
PIU1701
NLG7 IO_L3P_T0_DQS_13
IO_L14P_T2_SRCC_13 NLR1 GND
OE/ST
G7 AB13 PIU10AB13
V15
PIU10V15
R1
NLG2 IO_L3N_T0_DQS_13
IO_L14N_T2_SRCC_13 NLR2
G2 AA15 PIU10AA15 T14
PIU10T14 R2 GND
NLG3 IO_L4P_T0_13 IO_L15P_T2_DQS_13 NLVGA0SDA
G3 AB15 PIU10AB15 T15
PIU10T15 VGA_SDA SiT8008BI-73-XXS-100.000000E
NLG4 IO_L4N_T0_13 IO_L15N_T2_DQS_13 NLVGA0SCL
G4 Y13 PIU10Y13 W15
PIU10W15 VGA_SCL
NLG5 IO_L5P_T0_13 IO_L16P_T2_13
G5 AA14 PIU10AA14
W16
PIU10W16
RSVD2
NLG1 IO_L5N_T0_13 IO_L16N_T2_13
G1 W14 PIU10W14
T16
PIU10T16
RSVD0
G0 Y14 PIU10Y14
U16
PIU10U16
RSVD1
IO_L6N_T0_VREF_13 IO_L17N_T2_13
XC7A200T-2FBG484C
i COU18
U18
B13 1 PIU1801 5
PIU1805
3.3V OE
VCC 3.3V
HSYNC 2 PIU1802
C A NLVGA0HSync C
3 PIU1803 4
PIU1804 VGA_HSync
GND GND Y
COTP1 NC7SZ126P5X
NLRSVD0 TP1
RSVD0 PITP101
Testpoint 0.8mm
COTP2 COU19
U19
NLRSVD1 TP2
RSVD1 PITP201
1 PIU1901 5
PIU1905
3.3V OE
VCC 3.3V
VSYNC 2 PIU1902
Testpoint 0.8mm A NLVGA0VSync
3 PIU1903 4
PIU1904
VGA_VSync
GND GND Y
COTP3
TP3
NLRSVD2
RSVD2 PITP301
NC7SZ126P5X
Testpoint 0.8mm
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Filename: B13.SchDoc
1 2 3 4
1 2 3 4
A A
B14
i
COU1B
U1B
NLF0SER0RESET COR58
R58
BANK 14 AB21
PIU10AB21 F_SER_RESET PIR5802 PIR5801
3.3V IO_L10P_T1_D14_14 NLF0SER0DATA0I GND
PIC5801 PIC5901 PIC60 1 PIC6101 PIC5 0COC55
1C55 PIC570COC57
1C57 PIC5302 M14 PIU10M14
VCCO_14 IO_L10N_T1_D15_14
AB22
PIU10AB22 F_SER_DATA_I 1K
COC58
C58 COC59
C59 COC60
C60 COC61
C61 COC53
C53 P18 PIU10P18 U20 NLF0SER0SRQ0O
F_SER_SRQ_O
VCCO_14 IO_L11P_T1_SRCC_14 PIU10U20 1%
PIC5802 470nF PIC5902 470nF PIC60 2 470nF PIC6102 470nF PIC5 024.7µF PIC57024.7µF PIC5301 47µF R15 PIU10R15 V20
PIU10V20
VCCO_14 IO_L11N_T1_SRCC_14 NLFB0UP
T22 PIU10T22 W19
PIU10W19 FB_UP
VCCO_14 IO_L12P_T1_MRCC_14 NLF0C640D6
GND U19 PIU10U19 W20
PIU10W20 F_C64_D6
VCCO_14 IO_L12N_T1_MRCC_14 NLF0SER0CLK0I
Y20 PIU10Y20 Y18
PIU10Y18 F_SER_CLK_I
VCCO_14 IO_L13P_T2_MRCC_14 NLF0SER0CLK0O
Y19
PIU10Y19
F_SER_CLK_O
NLF0C640D2 IO_L13N_T2_MRCC_14 NLF0C640D5
F_C64_D2 P20 PIU10P20 V18
PIU10V18
F_C64_D5
B14i IO_0_14 IO_L14P_T2_SRCC_14
V19
PIU10V19
NLF0C640IO1 IO_L14N_T2_SRCC_14 NLF0C640CLOCK
F_C64_IO1 N15 PIU10N15 AA19
PIU10AA19 F_C64_CLOCK
B B14i IO_25_14 IO_L15P_T2_DQS_RDWR_B_14 NLF0SER0SRQ0EN B
AB20
PIU10AB20 F_SER_SRQ_EN
NLSPI0DQO IO_L15N_T2_DQS_DOUT_CSO_B_14 NLF0C640O2
SPI-DQO P22 PIU10P22 V17
PIU10V17
F_C64_O2
NLSPI0DQ1 IO_L1P_T0_D00_MOSI_14 IO_L16P_T2_CSI_B_14 NLF0C640NMI
SPI-DQ1 R22 PIU10R22 W17
PIU10W17
F_C64_NMI
NLSPI0DQ2 IO_L1N_T0_D01_DIN_14 IO_L16N_T2_A15_D31_14 NLF0SER0SRQ0I
SPI-DQ2 P21 PIU10P21 AA18
PIU10AA18 F_SER_SRQ_I
NLSPI0DQ3 IO_L2P_T0_D02_14 IO_L17P_T2_A14_D30_14 NLF0C640ROML
SPI-DQ3 R21 PIU10R21 AB18
PIU10AB18 F_C64_ROML
IO_L2N_T0_D03_14 IO_L17N_T2_A13_D29_14 NLF0CTRL0DIR
ULED U22 PIU10U22 U17
PIU10U17 F_CTRL_DIR
NLF0DATA0DIR IO_L3P_T0_DQS_PUDC_B_14 IO_L18P_T2_A12_D28_14 NLF0C640D4
F_DATA_DIR V22 PIU10V22 U18
PIU10U18
F_C64_D4
IO_L3N_T0_DQS_EMCCLK_14 IO_L18N_T2_A11_D27_14 NLF0C640IRQ
T21 PIU10T21 P14
PIU10P14
F_C64_IRQ
NLF0DATA0EN IO_L4P_T0_D04_14 IO_L19P_T3_A10_D26_14 NLETH0LED2
F_DATA_EN U21 PIU10U21 R14
PIU10R14 ETH_LED2
IO_L4N_T0_D05_14 IO_L19N_T3_A09_D25_VREF_14 NLF0C640RW
P19 PIU10P19 R18
PIU10R18 F_C64_RW
NLF0C640EXROM IO_L5P_T0_D06_14 IO_L20P_T3_A08_D24_14 NLF0C640ROMH
F_C64_EXROMR19 PIU10R19 T18
PIU10T18 F_C64_ROMH
NLSPI0CS IO_L5N_T0_D07_14 IO_L20N_T3_A07_D23_14 NLF0SER0ATN
SPI-CS T19 PIU10T19 N17
PIU10N17
F_SER_ATN
IO_L6P_T0_FCS_B_14 IO_L21P_T3_DQS_14 NLFB0DOWN
T20 PIU10T20 P17
PIU10P17
FB_DOWN
NLF0C640D7 IO_L6N_T0_D08_VREF_14 IO_L21N_T3_DQS_A06_D22_14 NLF0C640DMA
F_C64_D7 W21 PIU10W21 P15
PIU10P15
F_C64_DMA
NLF0C640GAME IO_L7P_T1_D09_14 IO_L22P_T3_A05_D21_14 NLF0C640D3
F_C64_GAME W22 PIU10W22 R16
PIU10R16
F_C64_D3
NLF0C640IO2 IO_L7N_T1_D10_14 IO_L22N_T3_A04_D20_14 NLF0C640BA
F_C64_IO2 AA20 PIU10AA20 N13
PIU10N13 F_C64_BA
NLF0SER0CLK0EN IO_L8P_T1_D11_14 IO_L23P_T3_A03_D19_14 NLF0C640RESET
F_SER_CLK_ENAA21 PIU10AA21 N14
PIU10N14
F_C64_RESET
B14i NLF0SER0DATA0EN IO_L8N_T1_D12_14 IO_L23N_T3_A02_D18_14 NLF0C640D0
F_SER_DATA_ENY21 PIU10Y21 P16
PIU10P16
F_C64_D0
NLF0SER0DATA0O IO_L9P_T1_DQS_14 IO_L24P_T3_A01_D17_14 NLF0C640D1
F_SER_DATA_O Y22 PIU10Y22 R17
PIU10R17 F_C64_D1
C IO_L9N_T1_DQS_D13_14 IO_L24N_T3_A00_D16_14 C
XC7A200T-2FBG484C
COD9
D9
NLULED
ULED
COR67
R67
PID90A PID90K PIR6701 PIR6702 GND
240R 1%
LED Red LTST-C191KRKT
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
1 2 3 4
1 2 3 4
B15
i
COU1C
U1C
3.3V BANK 15
G19 PIU10G19 M21
PIU10M21
PIC6401 PIC6501 PIC6 01 PIC6701 PIC401 VCCO_15 IO_L10P_T1_AD11P_15 NLF0LADDR0DIR
PIC6201COC62
C62 COC63
PIC6301C63 H16 PIU10H16 L21
PIU10L21 F_LADDR_DIR
COC64
C64 COC65
C65 COC66
C66 COC67
C67 COC4
C4 VCCO_15 IO_L10N_T1_AD11N_15 NLF0C640A5
J13 PIU10J13 J20
PIU10J20 F_C64_A5
A PIC6402 470nF PIC6502 470nF PIC6 02 470nF PIC6702 470nF PIC62024.7µF PIC63024.7µF PIC402 47µF VCCO_15 IO_L11P_T1_SRCC_15 NLF0C640A6 A
K20 PIU10K20 J21
PIU10J21 F_C64_A6
VCCO_15 IO_L11N_T1_SRCC_15 NLRSVD0MRCC COTP4
L17 PIU10L17 J19
PIU10J19
RSVD_MRCC PITP401
TP4
VCCO_15 IO_L12P_T1_MRCC_15 NLF0C640A12
GND N21 PIU10N21 H19
PIU10H19 F_C64_A12
VCCO_15 IO_L12N_T1_MRCC_15 NLF0C640A1
K18
PIU10K18 F_C64_A1
IO_L13P_T2_MRCC_15 NLF0C640A0
K19
PIU10K19 F_C64_A0
IO_L13N_T2_MRCC_15 NLF0ADDR0EN
J16 PIU10J16 L19
PIU10L19 F_ADDR_EN
IO_0_15 IO_L14P_T2_SRCC_15 NLF0C640A4
L20
PIU10L20
F_C64_A4
B15i IO_L14N_T2_SRCC_15 NLF0C640A14
M17 PIU10M17 N22
PIU10N22 F_C64_A14
IO_25_15 IO_L15P_T2_DQS_15 NLF0C640A3
M22
PIU10M22 F_C64_A3
IO_L15N_T2_DQS_ADV_B_15
CP0 H13 PIU10H13 M18
PIU10M18
IO_L1P_T0_AD0P_15 IO_L16P_T2_A28_15 NLF0HADDR0DIR
G13 PIU10G13 L18
PIU10L18 F_HADDR_DIR
IO_L1N_T0_AD0N_15 IO_L16N_T2_A27_15
CP1 G15 PIU10G15 N18
PIU10N18
IO_L2P_T0_AD8P_15 IO_L17P_T2_A26_15 COTP6
G16 PIU10G16 N19
PIU10N19 PITP601 TP6
NLCP2 IO_L2N_T0_AD8N_15 IO_L17N_T2_A25_15 COTP7
CP2 J14 PIU10J14 N20
IO_L3P_T0_DQS_AD1P_15 IO_L18P_T2_A24_15 NLF0C640A13
H14 PIU10H14 M20
PIU10M20 F_C64_A13
NLF0DRVSB IO_L3N_T0_DQS_AD1N_15 IO_L18N_T2_A23_15
F_DRVSB G17 PIU10G17 K13
PIU10K13
NLF0CTRL0EN IO_L4P_T0_15 IO_L19P_T3_A22_15
F_CTRL_EN G18 PIU10G18 K14
PIU10K14
NLF0C640A11 IO_L4N_T0_15 IO_L19N_T3_A21_VREF_15 NLFPGA0RESET0N
F_C64_A11 J15 PIU10J15 M13
PIU10M13 FPGA_RESET_N
NLF0MOTEB IO_L5P_T0_AD9P_15 IO_L20P_T3_A20_15 NLDBG0UART0TX
F_MOTEB H15 PIU10H15 L13
PIU10L13 DBG_UART_TX
B NLF0C640A8 IO_L5N_T0_AD9N_15 IO_L20N_T3_A19_15 COTP5 B
F_C64_A8 H17 PIU10H17 K17
PIU10K17 PITP501 TP5
NLF0C640A15 IO_L6P_T0_15 IO_L21P_T3_DQS_15
F_C64_A15 H18 PIU10H18 J17
PIU10J17
NLCP3 IO_L6N_T0_VREF_15 IO_L21N_T3_DQS_A18_15 NLDBG0UART0RX
CP3 J22 PIU10J22 L14
PIU10L14
DBG_UART_RX
IO_L7P_T1_AD2P_15 IO_L22P_T3_A17_15
Pulse-discharge H22 PIU10H22 L15
PIU10L15
NLF0C640A9 IO_L7N_T1_AD2N_15 IO_L22N_T3_A16_15 NLFPGA0TX GND
F_C64_A9 H20 PIU10H20 L16
PIU10L16 FPGA_TX
NLF0C640A10 IO_L8P_T1_AD10P_15 IO_L23P_T3_FOE_B_15 NLFPGA0RX
F_C64_A10 G20 PIU10G20 K16
PIU10K16 FPGA_RX
NLF0C640A2 IO_L8N_T1_AD10N_15 IO_L23N_T3_FWE_B_15 NLCT0HPD
GND F_C64_A2K21 PIU10K21 M15
PIU10M15
CT_HPD
NLF0C640A7 IO_L9P_T1_DQS_AD3P_15 IO_L24P_T3_RS1_15
F_C64_A7 K22 PIU10K22 M16
PIU10M16
IO_L9N_T1_DQS_AD3N_15 IO_L24N_T3_RS0_15
PIC7801
COC78
C78 XC7A200T-2FBG484C
PIC7802 1.2nF i
50V COU41
U41 B15
1 PIU4101 5
PIU4105
NLJA0AX COR14
R14 3.3V OE
VCC 3.3V
JA_AX PIR1401 PIR1402
2 PIU4102
A NLCP0
1K 3 PIU4103 4
PIU4104
CP0
GND PIT803 GND
Y
1% GND GND
COT8
T8 NC7SZ126P5X
2N7002,215 PIC7901 PIC80 1
NLPulse0discharge
Pulse-discharge
PIT801
COC79
C79 COC80
C80
C 1.2nF 1.2nF C
PIC7902 PIC80 2
50V COU6
U6 50V COU40
U40
PIT802 COR22
R22 3.3V
1 PIU601
OE
VCC
5
PIU605 3.3V COR23
R23 3.3V
1 PIU4001 VCC
OE
5
PIU4005 3.3V
NLJB0AX
JB_AX PIR2201 PIR2202
2 PIU602 NLJB0AY
JB_AY PIR2301 PIR2302
2 PIU4002
A A
GND 1K 3 PIU603 4
PIU604
CP2 1K 3 PIU4003
4
PIU4004
CP3
GNDPIT703 GND
Y GNDPIT903 GND
Y
1% COT7 1% COT9
GND T7 NC7SZ126P5X T9 NC7SZ126P5X
2N7002,215 2N7002,215
PIC8101 Pulse-discharge PIT701 Pulse-discharge PIT901
COC81
C81
PIC8102 1.2nF PIT702 PIT902
50V COU42
U42
1 PIU4201 5
PIU4205
NLJA0AY COR46
R46 3.3V OE
VCC 3.3V
JA_AY PIR4601 PIR4602
2 PIU4202 GND GND
A NLCP1
1K 3 PIU4203 4
PIU4204
CP1
GND PIT10 3 GNDY
1% COT10
T10 NC7SZ126P5X Title:
2N7002,215 MEGA65
Pulse-discharge
PIT1001
D D
Number: Rev.
A4 TE0765
PIT10 2 [No Variations] 03
GND
1 2 3 4
1 2 3 4
COU1D
U1D
BANK 16
NLKB0IO2 i B16
A17 PIU10A17 A13
PIU10A13 KB_IO2
3.3V PIC9101 PIC9201 PIC9301 PIC9801 PIC501 VCCO_16 IO_L10P_T1_16 NLKB0IO1
PIC680COC68
1C68 PIC90COC90
1C90 B14 PIU10B14 A14
PIU10A14 KB_IO1
COC91
C91 COC92
C92 COC93
C93 COC98
C98 COC5
C5 VCCO_16 IO_L10N_T1_16 NLSD20CLK
C21 PIU10C21 B17
PIU10B17 SD2_CLK
A PIC9102 470nF PIC9202 470nF PIC9302 470nF PIC9802 470nF PIC68024.7µF PIC90 24.7µF PIC502 47µF VCCO_16 IO_L11P_T1_SRCC_16 NLSD20D0 A
D18 PIU10D18 B18
PIU10B18 SD2_D0
VCCO_16 IO_L11N_T1_SRCC_16 NLSD20CD
E15 PIU10E15
D17
PIU10D17
SD2_CD
VCCO_16 IO_L12P_T1_MRCC_16 NLSD20WP
GND F22 PIU10F22 C17
PIU10C17 SD2_WP
VCCO_16 IO_L12N_T1_MRCC_16 NLSD20D1
C18
PIU10C18 SD2_D1
IO_L13P_T2_MRCC_16 NLSD20D2
C19
PIU10C19 SD2_D2
NLFB0FIRE IO_L13N_T2_MRCC_16 NLAUDIO0BCLK
FB_FIRE F15 PIU10F15 E19
PIU10E19 AUDIO_BCLK
IO_0_16 IO_L14P_T2_SRCC_16
D19
PIU10D19
NLFB0LEFT IO_L14N_T2_SRCC_16 NLnSD0AUDIO
FB_LEFT F21 PIU10F21 F18
PIU10F18 nSD_AUDIO
IO_25_16 IO_L15P_T2_DQS_16
E18
PIU10E18
NLFA0RIGHT IO_L15N_T2_DQS_16
FA_RIGHT F13 PIU10F13 B20
PIU10B20 DQ4
NLFA0LEFT IO_L1P_T0_16 IO_L16P_T2_16
FA_LEFT F14 PIU10F14 A20
PIU10A20 DQ3
NLFA0DOWN IO_L1N_T0_16 IO_L16N_T2_16
FA_DOWN F16 PIU10F16
A18
PIU10A18
NLFA0FIRE IO_L2P_T0_16 IO_L17P_T2_16
FA_FIRE E17 PIU10E17 A19
PIU10A19 DQ5
NLFA0UP IO_L2N_T0_16 IO_L17N_T2_16 NLAUDIO0LRCLK
FA_UP C14 PIU10C14 F19
PIU10F19 AUDIO_LRCLK
NLFB0RIGHT IO_L3P_T0_DQS_16 IO_L18P_T2_16
FB_RIGHT C15 PIU10C15 F20
PIU10F20
NLKB0TCK IO_L3N_T0_DQS_16 IO_L18N_T2_16 COTP8
KB_TCK E13 PIU10E13
D20
PIU10D20 PITP801
TP8
NLKB0TDO IO_L4P_T0_16 IO_L19P_T3_16
KB_TDO E14 PIU10E14
C20
PIU10C20
DQ2
NLAUDIO0SDATA IO_L4N_T0_16 IO_L19N_T3_VREF_16
AUDIO_SDATAE16 PIU10E16 C22
PIU10C22 CS0
NLAUDIO0MCLK IO_L5P_T0_16 IO_L20P_T3_16
3.3V AUDIO_MCLKD16 PIU10D16 B22
PIU10B22 H_RES
B COU39 NLKB0TMS IO_L5N_T0_16 IO_L20N_T3_16 B
U39 KB_TMS D14 PIU10D14 B21
PIU10B21 RWDS
NLKB0TDI IO_L6P_T0_16 IO_L21P_T3_DQS_16
1 PIU3901 8
PIU3908
KB_TDI D15 PIU10D15
A21
PIU10A21
DQ0
GND A0
VCC NLFPGA0SDA NLSD20D3 IO_L6N_T0_VREF_16 IO_L21N_T3_DQS_16
2 PIU3902 5
PIU3905
FPGA_SDA SD2_D3 B15 PIU10B15
E22
PIU10E22
DQ7
A1
SDA NLFPGA0SCL NLSD20CMD IO_L7P_T1_16 IO_L22P_T3_16
3 PIU3903 6
PIU3906 FPGA_SCL SD2_CMD B16 PIU10B16 D22
PIU10D22 H_CLK
3.3V A2
SCL NLKB0IO3 IO_L7N_T1_16 IO_L22N_T3_16
7 PIU3907 4
PIU3904 KB_IO3 C13 PIU10C13 E21
PIU10E21 DQ6
WP
VSS GND B16i NLKB0JTAGEN IO_L8P_T1_16 IO_L23P_T3_16
KB_JTAGEN B13 PIU10B13 D21
PIU10D21 DQ1
IO_L8N_T1_16 IO_L23N_T3_16 NLGrove0SCL0
GND 24LC128-I/ST FPGA_SCL A15 PIU10A15
G21
PIU10G21
Grove_SCL0
IO_L9P_T1_DQS_16 IO_L24P_T3_16 NLGrove0SDA0
FPGA_SDA A16 PIU10A16
G22
PIU10G22
Grove_SDA0
I2C addr: 0x54 IO_L9N_T1_DQS_16 IO_L24N_T3_16
XC7A200T-2FBG484C
3.3V
3.3V COU36
U36 COU38
U38
6 PIU3606
1
PIU3601
FPGA_SCL COR151
R151PIR15101 PIR15102
4K7 NLX2
X2
1 PIU3801 20 NLX1
X1
PIU38020
VCC
SCL X2 X1
PIC17501 5 PIU3605
2
PIU3602
3V 2 PIU3802 19
PIU38019
COC175
C175 A0VSS GND COR152 COD14 X2 X1
4 PIU3604 3
PIU3603 FPGA_SDA R152PIR15201 PIR15202 4K7 D14 3 PIU3803 18
PIU38018
PIC17502 470nF A1SDA COB1 X2 X1
B1 4 PIU3804 17
PIU38017
X2 X1
GND 24AA025E48T-I/OT PID1401
5 PIU3805 16
PIU38016
X2 X1
GND 3.3V
C C
I2C addr: 0x50 -
PIB100 +
PIB100 PID1403 7 PIU3807 14
PIU38014
VBAT VDD
PIC18401 PIR16302 PIC18501
COU29
U29 GND COC184
C184 6 COR163
R163 COC185
C185
PID1402 PIU3806 NC
B1 PIU290B1 B4
PIU290B4
PIC18402 470nF9 PIU3809 4K7 PIC18502 470nF
NLH0CLK CK VCC 3.3V NC 6.3V
H_CLK B2 PIU290B2 D1
PIU290D1
Batteriehalter CR1220 6.3V10 PIU38010 13
PIU38013 PIR16301
CK VCCQ NC
IRQ/FOUT
E4
PIU290E4
BAT54C GND 15 PIU38015 GND
VCCQ NC
21 PIU38021 12
PIU38012 FPGA_SCL
NLH0RES NC SCL
A4
PIU290A4
H_RES
NLRWDS RESET
RWDS C3 PIU290C3 8 PIU3808 11
PIU38011
FPGA_SDA
RWDS NLCS0 GND SDA
A3
PIU290A3
CS0
CS
A2
PIU290A2 GND ISL12020MIRZ
RFU
A5
PIU290A5
NLDQ0 RFU
DQ0 D3 PIU290D3 C2
PIU290C2
I2C addr: 0x6F for RTC
NLDQ1 DQ0 RFU
DQ1 D2 PIU290D2 B5
PIU290B5
NLDQ2 DQ1 RFU
DQ2 C4 PIU290C4 C5
PIU290C5
I2C addr: 0x57 for SRAM
NLDQ3 DQ2 RFU
DQ3 D4 PIU290D4 3.3V
DQ3
NLDQ4
DQ4 D5 PIU290D5 B3
PIU290B3
Title:
NLDQ5 DQ4 VSS PIC2501 PIC2601
DQ5 E3 PIU290E3 A1
PIU290A1 MEGA65
NLDQ6 DQ5 NC/VSS COC25
C25 COC26
C26
DQ6 E2 PIU290E2 C1
PIU290C1
D NLDQ7 DQ6 VSSQ D
DQ7 E1 PIU290E1 E5
PIU290E5
PIC2502 470nF PIC2602 470nF Number: Rev.
DQ7 VSSQ TE0765
A4 03
IS66WVH8M8BLL-100B1LI GND GND [No Variations]
GND
1 2 3 4
1 2 3 4
3.3V
3.3V 1
PIC120COC12 PIC15901COC159 PIC16 01 PIC16701 PIC16801 PIC16901 PIC160 1COC160 PIC16 COC161
C12 C159 C160 01C161
COC166
C166 COC167
C167 COC168
C168 COC169
C169
2
PIC1204.7µF PIC159024.7µF PIC16 02 470nF PIC16702 470nF P IC16 802 470nF PI C16 902 470nF PIC160 24.7µF PIC16 024.7µF
B35
A A
GND GND i
COU1E
COU1F
U1E U1F
BANK 34 BANK 35
R5 PIU10R5 AA5 NLHDMI0TX20P
HDMI_TX2_P J5 NLB350L100P
B35_L10_P
3.3V VCCO_34 IO_L10P_T1_34 PIU10AA5 3.3V
C1 PIU10C1
VCCO_35 IO_L10P_T1_AD15P_35 PIU10J5
T2 PIU10T2 AB5
PIU10AB5
NLHDMI0TX20N
HDMI_TX2_N F2 PIU10F2 H5
PIU10H5
NLB350L100N
B35_L10_N
VCCO_34 IO_L10N_T1_34 VCCO_35 IO_L10N_T1_AD15N_35 NLSD0D1
V6 PIU10V6 Y4
PIU10Y4
H6 PIU10H6 H3
PIU10H3
SD_D1
VCCO_34 IO_L11P_T1_SRCC_34 VCCO_35 IO_L11P_T1_SRCC_35
W3 PIU10W3 AA4
PIU10AA4 J3 PIU10J3 G3
PIU10G3
VCCO_34 IO_L11N_T1_SRCC_34 VCCO_35 IO_L11N_T1_SRCC_35 NLB350L120P
AA7 PIU10AA7 V4
PIU10V4 M4 PIU10M4 H4
PIU10H4 B35_L12_P
VCCO_34 IO_L12P_T1_MRCC_34 VCCO_35 IO_L12P_T1_MRCC_35 NLB350L120N
AB4 PIU10AB4 W4
PIU10W4 N1 PIU10N1 G4
PIU10G4 B35_L12_N
VCCO_34 IO_L12N_T1_MRCC_34 VCCO_35 IO_L12N_T1_MRCC_35 NLETH0CRS0DV
R4
PIU10R4 K4
PIU10K4 ETH_CRS_DV
IO_L13P_T2_MRCC_34 IO_L13P_T2_MRCC_35 NLETH0TX0EN
T4
PIU10T4
J4
PIU10J4
ETH_TX_EN
IO_L13N_T2_MRCC_34 NLPWM0R IO_L13N_T2_MRCC_35 NLETH0TX0D0
T3 PIU10T3 T5
PIU10T5 PWM_R F4 PIU10F4 L3
PIU10L3 ETH_TX_D0
IO_0_34 IO_L14P_T2_SRCC_34 IO_0_35 IO_L14P_T2_SRCC_35 NLETH0TX0D1
U5
PIU10U5 K3
PIU10K3 ETH_TX_D1
IO_L14N_T2_SRCC_34 NLPWM0L IO_L14N_T2_SRCC_35 NLF0SIDE1
U7 PIU10U7 W6
PIU10W6 PWM_L L6 PIU10L6 M1
PIU10M1 F_SIDE1
IO_25_34 IO_L15P_T2_DQS_34 IO_25_35 IO_L15P_T2_DQS_35 NLETH0RX0D1
W5
PIU10W5
L1
PIU10L1
ETH_RX_D1
IO_L15N_T2_DQS_34 NLB350L10P IO_L15N_T2_DQS_35 NLF0STEP
T1 PIU10T1 U6
PIU10U6 B35_L1_P B1 PIU10B1 M3
PIU10M3
F_STEP
IO_L1P_T0_34 IO_L16P_T2_34 NLB350L10N IO_L1P_T0_AD4P_35 IO_L16P_T2_35 NLF0INDEX
U1 PIU10U1 V5
PIU10V5 B35_L1_N A1 PIU10A1 M2
PIU10M2 F_INDEX
IO_L1N_T0_34 IO_L16N_T2_34 NLB350L20P IO_L1N_T0_AD4N_35 IO_L16N_T2_35 NLETH0RST
U2 PIU10U2 R6
PIU10R6 B35_L2_P C2 PIU10C2 K6
PIU10K6 ETH-RST
B IO_L2P_T0_34 IO_L17P_T2_34 NLB350L20N IO_L2P_T0_AD12P_35 IO_L17P_T2_35 NLETH0MDC B
V2 PIU10V2 T6
PIU10T6 B35_L2_N B2 PIU10B2 J6
PIU10J6 ETH_MDC
IO_L2N_T0_34 IO_L17N_T2_34 NLB350L30P IO_L2N_T0_AD12N_35 IO_L17N_T2_35 NLETH0MDIO
R3 PIU10R3 Y6
PIU10Y6
B35_L3_P E1 PIU10E1 L5
PIU10L5
ETH_MDIO
IO_L3P_T0_DQS_34 IO_L18P_T2_34 NLB350L30N IO_L3P_T0_DQS_AD5P_35 IO_L18P_T2_35 NLETH0CLK
R2 PIU10R2 AA6
PIU10AA6 B35_L3_N D1 PIU10D1 L4
PIU10L4
ETH_CLK
IO_L3N_T0_DQS_34 IO_L18N_T2_34 NLB350L40P IO_L3N_T0_DQS_AD5N_35 IO_L18N_T2_35 NLF0WDATE
W2 PIU10W2 V7
PIU10V7 B35_L4_P E2 PIU10E2 N4
PIU10N4 F_WDATE
IO_L4P_T0_34 IO_L19P_T3_34 NLB350L40N IO_L4P_T0_35 IO_L19P_T3_35 NLF0WGATE
Y2 PIU10Y2 W7
PIU10W7 B35_L4_N D2 PIU10D2 N3
PIU10N3 F_WGATE
NLHDMI0TXC0P IO_L4N_T0_34 IO_L19N_T3_VREF_34 NLSCL0A NLB350L50P IO_L4N_T0_35 IO_L19N_T3_VREF_35 NLF0DSCKCHG
HDMI_TXC_P W1 PIU10W1 AB7
PIU10AB7 SCL_A B35_L5_P G1 PIU10G1 R1
PIU10R1 F_DSCKCHG
NLHDMI0TXC0N IO_L5P_T0_34 IO_L20P_T3_34 NLB350L50N IO_L5P_T0_AD13P_35 IO_L20P_T3_35 NLF0RDATA1
HDMI_TXC_N Y1 PIU10Y1 AB6
PIU10AB6
B35_L5_N F1 PIU10F1 P1
PIU10P1
F_RDATA1
IO_L5N_T0_34 IO_L20N_T3_34 NLSDA0A NLB350L60P
IO_L5N_T0_AD13N_35 IO_L20N_T3_35 NLF0DIR
U3 PIU10U3 V9
PIU10V9 SDA_A B35_L6_P F3 PIU10F3 P5
PIU10P5
F_DIR
IO_L6P_T0_34 IO_L21P_T3_DQS_34 NLB350L60N IO_L6P_T0_35 IO_L21P_T3_DQS_35 NLETH0RX0D0
V3 PIU10V3 V8
PIU10V8 B35_L6_N E3 PIU10E3 P4
PIU10P4 ETH_RX_D0
NLHDMI0TX00P IO_L6N_T0_VREF_34 IO_L21N_T3_DQS_34 NLSD0CD IO_L6N_T0_VREF_35 IO_L21N_T3_DQS_35 NLF0WPT
HDMI_TX0_P AA1 PIU10AA1 AA8
PIU10AA8 SD_CD K1 PIU10K1 P2
PIU10P2 F_WPT
IO_L7P_T1_34 IO_L22P_T3_34 NLSD0D2 IO_L7P_T1_AD6P_35 IO_L22P_T3_35 NLF0TRCK0
NLHDMI0TX00N
HDMI_TX0_N AB1 PIU10AB1 AB8
PIU10AB8
NLLS0OE
LS_OE SD_D2 J1 PIU10J1 N2
PIU10N2 F_TRCK0
NLHDMI0TX10P IO_L7N_T1_34 IO_L22N_T3_34 NLHPD0A NLSD0D0 IO_L7N_T1_AD6N_35 IO_L22N_T3_35 NLETH0RXER
HDMI_TX1_P AB3 PIU10AB3 Y8
PIU10Y8
HPD_A SD_D0 H2 PIU10H2 M6
PIU10M6
ETH_RXER
NLHDMI0TX10N IO_L8P_T1_34 IO_L23P_T3_34 NLSD0CLK IO_L8P_T1_AD14P_35 IO_L23P_T3_35 NLF0MOTEA
HDMI_TX1_N AB2 PIU10AB2 Y7
PIU10Y7
SD_CLK G2 PIU10G2 M5
PIU10M5
F_MOTEA
IO_L8N_T1_34 IO_L23N_T3_34 NLCEC0A NLSD0D3 IO_L8N_T1_AD14N_35 IO_L23N_T3_35 NLF0REDWC
Y3 PIU10Y3 W9
PIU10W9 CEC_A SD_D3 K2 PIU10K2 P6
PIU10P6
F_REDWC
IO_L9P_T1_DQS_34 IO_L24P_T3_34 NLSD0CMD IO_L9P_T1_DQS_AD7P_35 IO_L24P_T3_35 NLF0DRVSA
AA3 PIU10AA3 Y9
PIU10Y9
SD_CMD J2 PIU10J2 N5
PIU10N5
F_DRVSA
IO_L9N_T1_DQS_34 IO_L24N_T3_34 IO_L9N_T1_DQS_AD7N_35 IO_L24N_T3_35
XC7A200T-2FBG484C XC7A200T-2FBG484C
i i i
B34 B34 B35
C C
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
1 2 3 4
1 2 3 4
3.3V
COU1G
U1G
BANK0
COC170
C170F12 PIU10F12 K10
PIU10K10
A VCCO_0 VCCADC_0 AVCC A
GND PIC17001 PIC17002
T12 PIU10T12
VCCO_0
M10
PIU10M10
4.7µF VREFP_0 AGND
E12 PIU10E12 L9
PIU10L9
GND VCCBATT_0 VREFN_0 AGND
NLSPI0SCK
SPI-SCK L12 L10 NLV0P
V_P PIC12 01
PIU10L12 CCLK_0 VP_0 PIU10L10
M9 NLV0N
V_N COC122
C122
VN_0 PIU10M9
3.3V
U11 PIU10U11
M0_0
PIC12 02 10nF
3.3V BOOTMODE = MASTER SPI U10 PIU10U10 N10
PIU10N10
16V
M1_0 DXP_0 X7R
CFG U9 PIU10U9 N9
PIU10N9
GND M2_0 DXN_0
PIR6801 1%
COR3
R3 i
COR68
R68 NLFPGA0DONE K9
PIR301 PIR302 FPGA_DONEG11 PIU10G11
DONE_0 GNDADC_0 PIU10K9 AGND
4K873.3V
1K
FPGA_PROG_B PIR6802 1% NLFPGA0PROG0B
FPGA_PROG_B
N12 PIU10N12
PROGRAM_B_0
i U8 PIU10U8
3.3V CFGBVS_0 COL3
L3
CFG PIL302 PIL301
NLFPGA0TDI 1.8V AVCC
FPGA_TDI R13 PIU10R13
NLFPGA0TDO TDI_0 BKP0603HS121-T
FPGA_TDO U13 PIU10U13
FPGA_JTAGi NLFPGA0TCK TDO_0
B
FPGA_TCK V12 PIU10V12
TCK_0
301
2C23
PICCOC23 B
NLFPGA0TMS
FPGA_TMS T13 PIU10T13 TMS_0
COR8
R8
302
PIC2470nF
PIR802 PIR801
NLFPGA0INIT
FPGA_INIT U12 PIU10U12 COL2
3.3V INIT_B_0 L2
4K87 GND PIL202 PIL201
i XC7A200T-2FBG484C
1% BKP0603HS121-T
CFG AGND
SPIFLASH
i
3.3V COC14
C14
COU5A
COU5B
U5A PIC1401 PIC1402
COR7
R7 NLSPI0CS GND
PIR702 PIR701
SPI-CS C2 PIU50C2 B4
PIU50B4
3.3V CS VCC 100nF
4K87 SPI-SCK B2 PIU50B2
NLSPI0DQO CLK NLSPI0DQ1
COR1
1% SPI-DQO D3 PIU50D3 D2
PIU50D2 SPI-DQ1
R1 NLSPI0DQ3 DI/IO0
DO/IO1 i SPIFLASH
PIR102 PIR101 SPI-DQ3 D4 PIU50D4
3.3V HOLD/RESET/IO3
4K87 NLSPI0DQ2
SPI-DQ2 C4 PIU50C4 B3
PIU50B3
WP/IO2GND GND
1%
S25FL256SAGBHI20
C C
U5B
A2 PIU50A2
NC
A3 PIU50A3 3.3V 3.3V
NC COS2
A4 PIU50A4 S2
NC NLRESET
A5 PIU50A5 PIR14502 PIR14802 RESET
NC COR145
R145 COR148
R148
B1 PIU50B1 1 PIS201
NC 4K87 4K87 PIV102
B5 PIU50B5 2 PIS202
NC COR134
R134 NLCPLD0JTAGEN
C1 PIU50C1 3
PIS203 PIR13401 PIR13402 PIR14501 1% PIR14801 1% PIV101COV1 CPLD_JTAGEN
NC
C3 PIU50C3
NC 49R9 PIC7501
C5 PIU50C5 4 COC75
C75 PIT603
NC PIS204
D1 PIU50D1 5 PIS205 10nF
PIC7502 COT6
T6
NC 16V 2N7002,215
D5 PIU50D5 6
PIS206
NC
E1 PIU50E1 GND X7R PIT601
NC
E2 PIU50E2 SPUJ191500 PIJ20 2
NC COJ20
J20
E3 PIU50E3 GND
NC PIT602
E4 PIU50E4 Title:
NC PIJ20 1
E5 PIU50E5 JUMPER2.54-2 MEGA65
NC
D D
S25FL256SAGBHI20 GND GND Number: Rev.
A4 TE0765
[No Variations] 03
Filename: FPGA-CFG.SchDoc
1 2 3 4
1 2 3 4
A A
COU1H
U1H
D6 PIU10D6 B5
PIU10B5
GND MGTAVCC MGTAVTT GND
D10 PIU10D10 B7
PIU10B7
MGTAVCC MGTAVTT
E8 PIU10E8 B9
PIU10B9
MGTAVCC MGTAVTT
F7 PIU10F7 B11
PIU10B11
MGTAVCC MGTAVTT
F9 PIU10F9 C4
PIU10C4
MGTAVCC MGTAVTT
C8
PIU10C8
MGTAVTT
B B
F6 PIU10F6 F8
PIU10F8
MGTREFCLK0P_216MGTRREF_216 GND
E6 PIU10E6
MGTREFCLK0N_216
F10 PIU10F10
MGTREFCLK1P_216
E10 PIU10E10
MGTREFCLK1N_216
B8 PIU10B8 B4
PIU10B4
MGTPRXP0_216 MGTPTXP0_216
A8 PIU10A8 A4
PIU10A4
MGTPRXN0_216 MGTPTXN0_216
D11 PIU10D11 D5
PIU10D5
C11 PIU10C11 C5
PIU10C5
B10 PIU10B10 B6
PIU10B6
A10 PIU10A10 A6
PIU10A6
D9 PIU10D9 D7
PIU10D7
C9 PIU10C9 C7
PIU10C7
GND MGTPRXN3_216 MGTPTXN3_216
XC7A200T-2FBG484C
C C
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Filename: FPGA-MGT.SchDoc
1 2 3 4
1 2 3 4
1V VCCINT CAPS
PIC901 PIC10 1 PIC1 01 PIC20 1 PIC2401 PIC4201 PIC4301 PIC4901 PIC5601 PIC140 1 PIC14 01 PIC14201 PIC14301
COC9
C9 COC10
C10 COC11
C11 COC20
C20 COC24
C24 COC42
C42 COC43
C43 COC49
C49 COC56
C56 COC140
C140 COC141
C141 COC142
C142 COC143
C143
PIC902 470nF PIC10 2 470nF PIC1 02 470nF PIC20 2 470nFPIC2402 470nF PIC4202 470nF PIC4302 470nF PIC4902 470nF PIC5602 470nF PIC140 2 470nF PIC14 02 470nF PIC1420 470nF PIC14302 470nF
GND
A A
1V
U1J
PIC690COC69
1C69 PIC70 COC70
1C70 PIC710COC71
1C71 PIC7401COC74
C74 PIC4 0COC44
1C44 PIC760COC76
1C76 A2 PIU10A2 H7
PIU10H7
GND GND
A3 PIU10A3 H9
PIU10H9
PIC69024.7µF PIC70 24.7µF PIC71024.7µF PIC74024.7µF PIC4 024.7µF PIC76024.7µF GND GND
A5 PIU10A5 H11
PIU10H11
GND GND
A7 PIU10A7
H21
PIU10H21
GND GND
GND A9 PIU10A9 J8
PIU10J8
GND GND
A11 PIU10A11 J10
PIU10J10
COU1I
COU1J GND GND
1V U1I A12 PIU10A12 J12
PIU10J12
GND GND
H10 PIU10H10 H12
PIU10H12 A22 PIU10A22 J18
PIU10J18
PIC147COC147 2 1V VCCINT VCCAUX 1.8V GND GND
02C147 PIC1480COC148
2C148 PIC1490COC149
C149 H8 PIU10H8 K12
PIU10K12
AA2 PIU10AA2
K5
PIU10K5
VCCINT VCCAUX GND GND
J7 PIU10J7 M12
PIU10M12 AA12 PIU10AA12 K7
PIU10K7
1
PIC14701100µF PIC14801100µF PIC1490100µF J9 PIU10J9 P12
PIU10P12 AA22 PIU10AA22 K11
PIU10K11
K8 PIU10K8 R11
PIU10R11 AB9 PIU10AB9 K15
PIU10K15
GND L7 PIU10L7 AB19 PIU10AB19
L2
PIU10L2
VCCINT GND GND
M8 PIU10M8 B3 PIU10B3
L8
PIU10L8
VCCINT GND GND
1V VCCBRAM CAPS N7 PIU10N7 B12 PIU10B12 L22
PIU10L22
VCCINT GND GND
P8 PIU10P8 B19 PIU10B19 M7
PIU10M7
B VCCINT GND GND B
PIC150 1 PIC15101 PIC15201 P10 PIU10P10
VCCINT
C3 PIU10C3 GND GND
M11
PIU10M11
COC150
C150 COC151
C151 COC152
C152 R7 PIU10R7 C6 M19
VCCINT PIU10C6 GND GND PIU10M19
PIC150 2 470nF PIC15102 470nF PIC15202 470nF R9 PIU10R9
VCCINT VCCBRAM
J11
PIU10J11 1V
C10 PIU10C10 GND GND
N6
PIU10N6
T10 PIU10T10 L11
PIU10L11 C12 PIU10C12 N8
PIU10N8
VCCINT VCCBRAM GND GND
GND T8 PIU10T8 N11
PIU10N11 C16 PIU10C16 N16
PIU10N16
VCCINT VCCBRAM GND GND
D3 PIU10D3 P3
PIU10P3
GND GND
XC7A200T-2FBG484C D4 PIU10D4
P7
PIU10P7
GND GND
1.8V VCCAUX CAPS D8 PIU10D8
P9
PIU10P9
GND GND
D12 PIU10D12 P11
PIU10P11
GND GND
PIC15301 PIC15401 PIC15 01 PIC15601 PIC15701 PIC460COC46
1C46 PIC470COC47
1C47 PIC480COC48
1C48 PIC15801 D13 PIU10D13 P13
PIU10P13
COC153
C153 COC154
C154 COC155
C155 COC156
C156 COC157
C157 COC158
C158 GND GND
E4 PIU10E4 R8
PIU10R8
PIC15302 470nF PIC15402 470nF PIC15 02 470nF PIC15602 470nF PIC15702 470nF PIC46024.7µF PIC47024.7µF PIC48024.7µF PIC15802 47µF GND GND
E5 PIU10E5
R10
PIU10R10
GND GND
E7 PIU10E7
R12
PIU10R12
GND GND
GND E9 PIU10E9
R20
PIU10R20
GND GND
E11 PIU10E11
T7
PIU10T7
GND GND
F5 PIU10F5 T9
PIU10T9
GND GND
F11 PIU10F11
T11
PIU10T11
GND GND
F17 PIU10F17
T17
PIU10T17
GND GND
E20 PIU10E20 U4
PIU10U4
C GND GND C
G5 PIU10G5 U14
PIU10U14
GND GND
G6 PIU10G6 V1
PIU10V1
GND GND
G7 PIU10G7
V11
PIU10V11
GND GND
G8 PIU10G8
V21
PIU10V21
GND GND
G9 PIU10G9
W8
PIU10W8
GND GND
G10 PIU10G10
W18
PIU10W18
GND GND
G12 PIU10G12 Y5
PIU10Y5
GND GND
G14 PIU10G14
Y15
PIU10Y15
GND GND
H1 PIU10H1 GND
GND XC7A200T-2FBG484C GND
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Filename: FPGA-PWR.SchDoc
1 2 3 4
1 2 3 4
Bank8
COL10
L10 i
PIC16501
COC165
PIC16502C165
NL303V0REF
3.3V_REF PIL1001 PIL1002 3.3V U32C 3.3V U32F
3.3V
4.7µF MPZ1608S221A BANK 3 BANK 8
L8 PIU320L8 L4
PIU320L4 C8 PIU320C8 C10
PIU320C10
VCCIO3 IO_3/DIFFIO_TX_RX_B1P VCCIO8 IO_8/DIFFIO_RX_T14P
COC202
C202 L7 PIU320L7
VCCIO3 IO_3/DIFFIO_TX_RX_B1N
L5
PIU320L5
C7 PIU320C7 VCCIO8 IO_8/DIFFIO_RX_T14N
C9
PIU320C9
PIC20201 PIC20202
COU32A
COU32B
COU32C
COU32D
COU32E
COU32F
COU32G
U32A L6 PIU320L6 M5
PIU320M5
NLCPLD0DBG10
CPLD_DBG10 C6 PIU320C6 A8
PIU320A8
NLCPLD0ADC1 PIC24 01 VCCIO3 IO_3/DIFFIO_RX_B2P PIC24501 VCCIO8 IO_8/DIFFIO_RX_T15P
D3 PIU320D3 D2
PIU320D2 CPLD_ADC1 M4
PIU320M4 A9
PIU320A9
470nF ADC_VREF ANAIN1 COC244
C244 IO_3/DIFFIO_RX_B2N NLFPGA0TCK COC245
C245 IO_8/DIFFIO_RX_T15N
E2 PIU320E2 J5
PIU320J5 FPGA_TCK B10
PIU320B10
A REFGND 470nF
PIC24 02 IO_3/DIFFIO_TX_RX_B3P PIC24502 470nF IO_8/DIFFIO_RX_T16P A
K5
PIU320K5 B9
PIU320B9
IO_3/DIFFIO_TX_RX_B3N NLCPLD0DBG11 IO_8/DEV_CLRN/DIFFIO_RX_T16N
GND 3.3V BANK 1A N11 PIU320N11 N5
PIU320N5
CPLD_DBG11 B7 PIU320B7 A10
PIU320A10
NLCPLD0ADC2 VREFB3N0 IO_3/DIFFIO_RX_B4P VREFB8N0 IO_8/DIFFIO_RX_T17P NLCPLD0CFG2
F2 PIU320F2 C2
PIU320C2 CPLD_ADC2 GND N4
PIU320N4 GND A11
PIU320A11 CPLD_CFG2
VCCIO1A
IO_1A/ADC1IN2/DIFFIO_RX_L1P NLCPLD0ADC3 IO_3/DIFFIO_RX_B4N NLCPLD0DBG9 IO_8/DIFFIO_RX_T17N
D1
PIU320M7 CPLD_DBG9 D8
PIU320D8
PIC24601 IO_1A/ADC1IN1/DIFFIO_RX_L1N IO_3/DIFFIO_TX_RX_B5P NLCPLD0DBG8 IO_8/DEV_OE/DIFFIO_RX_T18P
E4
PIU320E4 N6
PIU320N6 CPLD_DBG8 E8
PIU320E8
COC246
C246 IO_1A/ADC1IN4/DIFFIO_RX_L3P IO_3/DIFFIO_TX_RX_B5N NLCPLD0DBG5 IO_8/DIFFIO_RX_T18N
E3
PIU320E3 N8
PIU320N8 CPLD_DBG5 D7 PIU320D7 A7
PIU320A7
PIC24602 470nF IO_1A/ADC1IN3/DIFFIO_RX_L3N IO_3/DIFFIO_RX_B6P NLCPLD0DBG7 GND IO_8/CONFIG_SEL IO_8/DIFFIO_RX_T19P
B1
PIU320B1
N7
PIU320N7
CPLD_DBG7 A6
PIU320A6
IO_1A/ADC1IN6/DIFFIO_RX_L5P IO_3/DIFFIO_RX_B6N NLFPGA0INIT IO_8/DIFFIO_RX_T19N
C1
PIU320C1 K6
PIU320K6 FPGA_INIT E7 PIU320E7 B6
PIU320B6
IO_1A/ADC1IN5/DIFFIO_RX_L5N IO_3/DIFFIO_TX_RX_B7P NLFPGA0DONE I_8/NCONFIG IO_8/DIFFIO_RX_T20P NLTE0TCK
GND E1
PIU320E1 J6
PIU320J6 FPGA_DONE B5
PIU320B5 TE_TCK
IO_1A/ADC1IN8/DIFFIO_RX_L7P IO_3/DIFFIO_TX_RX_B7N NLCPLD0DBG4 IO_8/DIFFIO_RX_T20N NLTE0TDO
F1
PIU320F1 M9
PIU320M9 CPLD_DBG4 A4
PIU320A4 TE_TDO
IO_1A/ADC1IN7/DIFFIO_RX_L7N i Bank1 IO_3/DIFFIO_RX_B8P NLCPLD0DBG6 IO_8/DIFFIO_RX_T21P NLTE0TDI
M8
PIU320A3 TE_TDI
IO_3/DIFFIO_RX_B8N NLFPGA0TDO IO_8/DIFFIO_RX_T21N
3.3V BANK 1B K7
PIU320K7 FPGA_TDO E6
PIU320E6
NLCPLD0JTAGEN IO_3/DIFFIO_TX_RX_B9P NLFPGA0TDI IO_8/DIFFIO_RX_T22P
G3 PIU320G3 E5
PIU320E5 CPLD_JTAGEN J7
PIU320J7 FPGA_TDI D6
PIU320D6
VCCIO1B IO_1B/JTAGEN NLM0TCK IO_3/DIFFIO_TX_RX_B9N NLK0TCK IO_8/CRC_ERROR/DIFFIO_RX_T22N NLTE0TMS
G2
PIU320G2 M_TCK M12
PIU320M12 K_TCK NLM10nCONF B3
PIU320B3 TE_TMS
IO_1B/TCK/DIFFIO_RX_L11P NLM0TMS IO_3/DIFFIO_TX_RX_B10P NLK0TDI IO_8/DIFFIO_RX_T23P NLTE0UART0TX
TE_UART_TX
M10_nCONF
PIC24701 H1 PIU320H1 G1
PIU320G1 M_TMS M13
PIU320M13 K_TDI B4
PIU320B4
COC247
C247 VREFB1N0 IO_1B/TMS/DIFFIO_RX_L11N NLM0TDO IO_3/DIFFIO_TX_RX_B10N NLCPLD0DBG3 IO_8/DIFFIO_RX_T23N NLM100nSTATUS
F6
PIU320F6
M_TDO N9
PIU320N9
CPLD_DBG3 C4
PIU320C4
M10_nSTATUS
PIC24702 470nF IO_1B/TDO/DIFFIO_RX_L12P NLM0TDI IO_3/DIFFIO_RX_B11P NLCPLD0DBG1 IO_8/NSTATUS/DIFFIO_RX_T24P NLM100CONF0DONE
F5
PIU320F5 M_TDI N10
PIU320N10
CPLD_DBG1 C5
PIU320C5
M10_CONF_DONE
IO_1B/TDI/DIFFIO_RX_L12N IO_3/DIFFIO_RX_B11N NLFPGA0RX IO_8/CONF_DONE/DIFFIO_RX_T24N NLM0TX
G4
PIU320G4 L11
PIU320L11 FPGA_RX A2
PIU320A2 M_TX
IO_1B/DIFFIO_RX_L14P IO_3/DIFFIO_TX_RX_B12P NLK0JTAGEN IO_8/DIFFIO_RX_T26P NLM0RX
GND F4
PIU320F4 M11
PIU320M11 K_JTAGEN B2
PIU320B2 M_RX
B IO_1B/DIFFIO_RX_L14N IO_3/DIFFIO_TX_RX_B12N NLFPGA0TMS IO_8/DIFFIO_RX_T26N NLTE0UART0RX B
H3
PIU320H3 K8
PIU320K8 FPGA_TMS A5
PIU320A5 TE_UART_RX
IO_1B/DIFFIO_RX_L16P IO_3/DIFFIO_TX_RX_B14P i Bank3 IO_8
H2
PIU320H2
J8
PIU320J8
IO_1B/DIFFIO_RX_L16N IO_3/DIFFIO_TX_RX_B14N NLCPLD0DBG0
L10
PIU320L10
CPLD_DBG0 10M08SAU169C8G
IO_3/DIFFIO_TX_RX_B16P NLCPLD0DBG2
10M08SAU169C8G M10
PIU320M10 CPLD_DBG2 3.3V U32G
IO_3/DIFFIO_TX_RX_B16N NLK0TMS
Bank2 N12
PIU320N12 K_TMS H7 PIU320H7 A1
PIU320A1
IO_3 VCC_ONE GND
U32B i PIC24801 G8 PIU320G8
VCC_ONE GND
A13
PIU320A13
3.3V 10M08SAU169C8G COC248
C248 G6 B8
BANK 2 VCC_ONE GND PIU320B8
K3 PIU320K3 H6
PIU320H6
NLCPLD0CLK
CPLD_CLK U32E PIC24802 470nF F7 PIU320G6
PIU320F7
C3
PIU320C3
VCCIO2 IO_2/CLK0P/DIFFIO_RX_L18P i Bank6 VCC_ONE GND
J3 PIU320J3 G5
PIU320G5 3.3V D5
PIU320D5
VCCIO2 IO_2/CLK0N/DIFFIO_RX_L18N BANK 6 NLKB0IO2 GND
PIC24901 J2
PIU320J2 G11 PIU320G11 G9
PIU320G9 KB_IO2 GND K4 PIU320K4 E11
PIU320E11
COC249
C249 IO_2/DIFFIO_RX_L19P VCCIO6 IO_6/CLK2P/DIFFIO_RX_R14P i KB VCCA1 GND
J1
PIU320J1 F11 G10
PIU320G10
NLKB0TCK
KB_TCK D10 PIU320D10 F3
PIU320F3
PIC24902 470nF IO_2/DIFFIO_RX_L19N PIC250 1 PIU320F11 VCCIO6 IO_6/CLK2N/DIFFIO_RX_R14N NLKB0IO3 i KB VCCA2 GND
H4
PIU320H4
F13
PIU320F13
KB_IO3 D4 PIU320D4 G7
PIU320G7
IO_2/CLK1P/DIFFIO_RX_L20P COC250
C250 IO_6/CLK3P/DIFFIO_RX_R16P i KB VCCA3 GND
L1 PIU320L1 H5
PIU320H5
E13
PIU320E13
K9 PIU320K9 H12
PIU320H12
VREFB2N0IO_2/CLK1N/DIFFIO_RX_L20N IO_6/CLK3N/DIFFIO_RX_R16N NLKB0TMS 3.3V VCCA4 GND
GND M2
PIU320M2 PIC250 2 470nF F12
PIU320F12 KB_TMS PIC17301 J4
PIU320J4
IO_2/DIFFIO_RX_L21P IO_6/DIFFIO_RX_R18P i KB COC173
C173 GND
M1
PIU320M1
D13 PIU320D13 E12
PIU320E12
L9
PIU320L9
IO_2/DIFFIO_RX_L21N VREFB6N0 IO_6/DIFFIO_RX_R18N NLKB0JTAGEN GND
IO_2/DPCLK1/DIFFIO_RX_L22P
N3
PIU320N3 GND
IO_6/DPCLK3/DIFFIO_RX_R26P
F9
PIU320F9 KB_JTAGEN
i KB
PIC17302 470nF GND
M6
PIU320M6
N2
PIU320N2
NLVDAC0PSAVE0N
VDAC_PSAVE_N F10
PIU320F10
NLKB0TDO
KB_TDO N1
PIU320N1
IO_2/DPCLK0/DIFFIO_RX_L22N IO_6/DPCLK2/DIFFIO_RX_R26N i KB GND
L3
PIU320L3
F8
PIU320F8
GND N13
PIU320N13
IO_2/PLL_L_CLKOUTP/DIFFIO_RX_L27P IO_6/DIFFIO_RX_R27P NLKB0IO1 COJ21 GND
M3
PIU320M3 E9
PIU320E9 KB_IO1 J21
C IO_2/PLL_L_CLKOUTN/DIFFIO_RX_L27N IO_6/DIFFIO_RX_R27N i KB C
K2
PIU320K2 B12
PIU320B12 LED_R CPLD_DBG01 PIJ2101 10M08SAU169C8G GND
IO_2/DIFFIO_RX_L28P IO_6/DIFFIO_RX_R28P NLCPLD0CFG3
K1
PIU320K1 B11
PIU320B11 CPLD_CFG3 CPLD_DBG12 PIJ2102
IO_2/DIFFIO_RX_L28N IO_6/DIFFIO_RX_R28N NLPMOD20EN
L2
PIU320L2
C12
PIU320C12
PMOD2_EN CPLD_DBG23 PIJ2103
IO_2 IO_6/DIFFIO_RX_R29P NLCPLD0CFG1
C11
PIU320C11
CPLD_CFG1 CPLD_DBG34 PIJ2104
IO_6/DIFFIO_RX_R29N COR28
R28
10M08SAU169C8G B13
PIU320B13
LED_G CPLD_DBG45 PIJ2105 M10_nCONF PIR2801 PIR2802
IO_6/DIFFIO_RX_R30P NLCPLD0CFG0
A12
PIU320A12
CPLD_CFG0 CPLD_DBG56 PIJ2106 10K
IO_6/DIFFIO_RX_R30N
U32D E10
PIU320E10 CPLD_DBG67 PIJ2107
3.3V
i Bank5 IO_6/DIFFIO_RX_R31P NLKB0TDI COR29
BANK 5 D9
PIU320D9
KB_TDI CPLD_DBG78 PIJ2108 M10_CONF_DONE PIR2901R29 PIR2902
NLDBG0UART0TX IO_6/DIFFIO_RX_R31N NLPMOD10FLG i KB
J11 PIU320J11 K10
PIU320K10
DBG_UART_TX D12
PIU320D12
PMOD1_FLG CPLD_DBG89 PIJ2109 10K
VCCIO5 IO_5/DIFFIO_RX_R1P NLDBG0UART0RX IO_6/DIFFIO_RX_R33P NLPMOD10EN
H11 PIU320H11 J10
PIU320J10
DBG_UART_RX D11
PIU320D11
PMOD1_EN CPLD_DBG9
10 PIJ21010
VCCIO5 IO_5/DIFFIO_RX_R1N NLFPGA0TX IO_6/DIFFIO_RX_R33N NLPMOD20FLG COR30
R30
PIC25 01 K11
PIU320K11 FPGA_TX C13
PIU320C13 PMOD2_FLG CPLD_DBG10
11 PIJ21011 M10_nSTATUS PIR3001 PIR3002
COC252
C252 IO_5/DIFFIO_RX_R2P IO_6 3.3V
L12
PIU320L12
NLK0TDO
K_TDO 10M08SAU169C8G CPLD_DBG11
12 PIJ21012 10K
PIC25 02 470nF IO_5/DIFFIO_RX_R2N NLK0IO2
K12
PIU320K12
K_IO2 13 PIJ21013
IO_5/DIFFIO_RX_R7P NLK0IO3
K13 PIU320K13 J12
PIU320J12
K_IO3 14 PIJ21014
VREFB5N0 IO_5/DIFFIO_RX_R7N NLFPGA0RESET0N COD10
D10
GND J9
PIU320J9
FPGA_RESET_N
IO_5/DIFFIO_RX_R8P COR70
R70 NLLED0G
H10
PIU320H10 PID100A PID100K PIR7001 PIR7002
LED_G GND Pin Header 2.54 2Row 14Pins
IO_5/DIFFIO_RX_R8N 3.3V
J13
PIU320J13
NLRESET
RESET 240R Title:
IO_5/DIFFIO_RX_R9P NLEN05V0JOY0N
H13
PIU320H13
EN_5V_JOY_N LED Green LTST-C191KGKT1% MEGA65
IO_5/DIFFIO_RX_R9N
H9
PIU320H9
D IO_5/DIFFIO_RX_R10P COD12
D12 D
H8
PIU320H8
Number: Rev.
IO_5/DIFFIO_RX_R10N NL5V0JOY0PG COR130
R130 NLLED0R TE0765
G13
PIU320G13 5V_JOY_PG PID120A PID120K PIR13001 PIR13002 LED_R A4 03
IO_5/DIFFIO_RX_R11P 3.3V [No Variations]
G12
PIU320G12
NLFPGA0PROG0B
FPGA_PROG_B 240R
IO_5/DIFFIO_RX_R11N NLK0IO1
L13
PIU320L13
K_IO1 LED Red LTST-C191KRKT
1%
IO_5 Date: 2020-06-29 Copyright: Trenz Electronic GmbH Page 12 of 23
10M08SAU169C8G
Filename: SYS_MAX10_CTRL.SchDoc
1 2 3 4
1 2 3 4
COU15
U15 COJ7
J7
NLF0SER0CLK0EN
F_SER_CLK_EN 1 PIU1501 5 5 NLJA0AY
JA_AY
OE
VCC PIU1505 5V PIJ705
IEC - 1541 style Diskdrive NLF0SER0CLK0O
F_SER_CLK_O 2 PIU1502 9
PIJ709
NLJA0AX
JA_AX
A COR87
R87 COR164
3 PIU1503 4
PIU1504
SER_CLK PIR8702 PIR8701
4
PIJ704
JA_RIGHT R164PIR16402 PIR16401
4K7
COJ6 GND GND
Y 5V
J6 4K7 GND 8
PIJ708
NLSER0SRQ GND COR165
1
PIJ601 SER_SRQ NC7SZ126P5X GND 3
PIJ703 JA_LEFT R165PIR16502 PIR16501 4K7
5
PIJ605
NLSER0DATA
SER_DATA COU16
U16 7
PIJ707
A NLF0SER0DATA0EN PIR8602 COR166 PIC4502 5V_JOY A
F_SER_DATA_EN1 PIU1601 OE 5
PIU1605 2
PIJ702 JA_DOWN R166PIR16602 PIR16601 4K7
NLSER0RESET NLF0SER0DATA0O VCC 5V PIC13502 COR86
R86 COR167 COC45
C45
6
PIJ606
SER_RESET F_SER_DATA_O 2 PIU1602 COR168 6
PIJ706
JA_FIRE R167PIR16702 PIR16701
4K7
A R168 COC135
C135 1M COR169 PIC4501 10µF
3 PIU1603 4
PIU1604 SER_DATA PIR16802 PIR16801 1
PIJ701 JA_UP R169PIR16902 PIR16901 4K7
NLSER0CLK GND GND
Y 5V PIC13501 100pF PIR8601 5%
4
PIJ604 SER_CLK 4K7
3 NLSER0ATN
SER_ATN NC7SZ126P5X 1000V GND
PIJ603 PIJ70H2 PIJ70H1
2
PIJ602
COU27
U27 X7R
GND NLF0SER0SRQ0EN
7
PIJ607
F_SER_SRQ_EN 1 PIU2701 5
PIU2705 DSUB-9-M UNC 4-40 rivet, w/o bolts
GND OE
VCC 5V
H2
H1
8
PIJ608
NLF0SER0SRQ0O
F_SER_SRQ_O 2 PIU2702
GND A COR170
R170
3 PIU2703 4
PIU2704 SER_SRQ PIR17002 PIR17001
GND GND
Y 5V COJ3
J3
61PC6F 4K7
NC7SZ126P5X 5
PIJ305
NLJB0AY
JB_AY
GND COU20
U20 9
PIJ309
NLJB0AX
JB_AX
1 PIU2001 5
PIU2005 4
PIJ304
NLJB0RIGHT
JB_RIGHT COR171
R171PIR17102 PIR17101 4K7
3.3V VCC
OE 3.3V
SER_CLK 2 PIU2002 8
PIJ308
A NLF0SER0CLK0I GND NLJB0LEFT COR172
3 PIU2003 4
PIU2004 F_SER_CLK_I 3
PIJ303 JB_LEFT R172PIR17202 PIR17201 4K7
GND GND
Y
7
PIJ307
NLJB0DOWN COR173 PIC7202 5V_JOY
NC7SZ126P5X 2
PIJ302
JB_DOWN R173PIR17302 PIR17301
4K7
COU21
U21 6 NLJB0FIRE
JB_FIRE COR174 4K7 COC72
C72
PIJ306 R174PIR17402 PIR17401
1 PIU2101 5
PIU2105 1
PIJ301
NLJB0UP
JB_UP COR175
R175PIR17502 PIR17501 4K7 PIC7201 10µF
B 3.3V VCC
OE 3.3V B
SER_DATA 2 PIU2102
A NLF0SER0DATA0I
3 PIU2103 4
PIU2104
F_SER_DATA_I GND
GND GND
Y PIJ30H2 PIJ30H1
NC7SZ126P5X DSUB-9-M UNC 4-40 rivet, w/o bolts
H2
H1
COU28
U28
1 PIU2801 5
PIU2805
3.3V OE
VCC 3.3V
SER_SRQ 2 PIU2802 3.3V
A NLF0SER0SRQ0I
3 PIU2803 4
PIU2804
F_SER_SRQ_I
GND GND Y COU33
U33
NC7SZ126P5X PIR12702 11 PIU33011 1
PIU3301
COR127
R127 5V VCC SOURCE 5V_JOY
PIR12 02 SOURCE
2
PIU3302
COU22
U22 4K7 COR122
R122 6 PIU3306 3
NC SOURCE PIU3303
1 PIU2201 5
PIU2205
NL5V0JOY0PG
5V_JOY_PG PIR12701 DNP 4
PIU3304
3.3V
NLJA0RIGHT VCC
OE 3.3V SOURCE
JA_RIGHT 2 PIU2202 PIR12 01 8 PIU3308 5
PIU3305
A NLFA0RIGHT PIT203 Enable/Fault
SOURCE
3 PIU2203 4
PIU2204
FA_RIGHT PIR12302 COC73
C73 PIR12401
GND GND
Y COR123
R123 COR124
R124
GND PIC7301 PIC7302
9 PIU3309
dv/dt
NC7SZ126P5X COT2
T2 200K 22R
COU23
U23 2N7002,215 1%
PIR 1230 1 1nF 7 PIR12402 1%
PIT201
10 PIU33010 PIU3307
50V GND I-Limit
1 PIU2301 5
PIU2305 PIR12502
C NLJA0LEFT3.3V VCC
OE 3.3V COR125
R125 X7R C
JA_LEFT 2 PIU2302 MP5010BDQ-LF-Z
A NLFA0LEFT PIT20 200K
3 PIU2303 4
PIU2304 FA_LEFT
GND GND
Y PIR12501 1% GND
NC7SZ126P5X GND PIT103
COU24
U24 GND COT1
T1
1 PIU2401 5 2N7002,215
3.3V OE
VCC PIU2405 3.3V
NLJA0DOWN
JA_DOWN 2 PIU2402 NLEN05V0JOY0N
EN_5V_JOY_NPIT101
A NLFA0DOWN
3 PIU2403 4
PIU2404
FA_DOWN
GND GND Y
3.3V 5V
NC7SZ126P5X PIT102
PIC17902 PIC180 2
COC179
C179 COC180
C180 COU25
U25 GND
PIC17901 10µF PIC180 1 10µF 1 PIU2501 5
PIU2505
10V NLJA0FIRE 3.3V VCC
OE 3.3V
JA_FIRE 2 PIU2502
A NLFA0FIRE
GND GND 3 PIU2503 4
PIU2504
FA_FIRE
GND GND
Y
NC7SZ126P5X Title:
MEGA65
COU26
U26
D D
1 PIU2601 5
PIU2605
Number: Rev.
NLJA0UP 3.3V VCC
OE 3.3V TE0765
JA_UP 2 PIU2602 A4 03
A [No Variations]
3 PIU2603 4
PIU2604
NLFA0UP
FA_UP
GND GND
Y
NC7SZ126P5X
Filename: JOY.SchDoc
1 2 3 4
1 2 3 4
A A
COJ5
J5
KBi i KB
1 PIJ501 2
PIJ502
NLK0JTAGEN GND 3.3V NLK0TMS
K_JTAGEN 3 PIJ503 4
PIJ504 K_TMS
NLK0TCK
K_TCK 5 PIJ505 6
PIJ506
NLK0TDI
K_TDI
NLK0TDO
K_TDO 7 PIJ507 8
PIJ508
NLK0IO1
K_IO1
NLK0IO2
K_IO2 9 PIJ509 10
PIJ5010
NLK0IO3
K_IO3
SMD-254-9132-14-10
B B
COJ12
J12
1 PIJ1201 2
PIJ1202
GND 3.3V
3 PIJ1203 4
PIJ1204
5 PIJ1205 6
PIJ1206
7 PIJ1207 8
PIJ1208
9 PIJ1209 10
PIJ12010
1-338069-0
C C
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Filename: KEYBOARD.SchDoc
1 2 3 4
1 2 3 4
A A
COU7
U7
COJ13
J13 31 PIU7031 7
PIU707
3.3V VCCA VCCB 5V
1 PIJ1301 42 PIU7042 18
PIU7018
12V_FUSED VCCA VCCB
2 PIJ1302 FLOPPY
GND
3 PIJ1303 i
GND
4 PIJ1304 1 PIU701 48
PIU7048
5V 3.3V 1DIR 1OE GND
Stiftleiste 4 Pol. 2,54mm NLF0REDWC
F_REDWC 47 PIU7047 2
PIU702 REDWC
COJ16 NLF0MOTEA 1A1 1B1
J16 F_MOTEA 46 PIU7046 3
PIU703
MOTEA
NLF0DRVSA 1A2 1B2
1 PIJ1601 F_DRVSA 44 PIU7044 5
PIU705
DRVSA
12V_FUSED NLF0DIR 1A3 1B3
2 PIJ1602 F_DIR 43 PIU7043 6
PIU706 DIR
GND NLF0STEP 1A4 1B4
3 PIJ1603 F_STEP 41 PIU7041 8
PIU708 STEP
B GND NLF0WDATE 1A5 1B5 B
4 PIJ1604 F_WDATE 40 PIU7040 9
PIU709 WDATE
5V NLF0WGATE 1A6 1B6
F_WGATE 38 PIU7038 11
PIU7011
WGATE
NLF0SIDE1 1A7 1B7
Stiftleiste 4 Pol. 2,54mm F_SIDE1 37 PIU7037 12
PIU7012
SIDE1
1A8 1B8
24 PIU7024 25
PIU7025
GND 2DIR 2OE GND
NLF0INDEX
F_INDEX 36 PIU7036 13
PIU7013
INDEX
NLF0TRCK0 2A1 2B1
F_TRCK0 35 PIU7035 14
PIU7014
TRCK0
NLF0WPT 2A2 2B2
F_WPT 33 PIU7033 16
PIU7016 WPT
NLF0RDATA1 2A3 2B3
F_RDATA1 32 PIU7032 17
PIU7017 RDATA1
NLF0DSCKCHG 2A4 2B4
F_DSCKCHG 30 PIU7030 19
PIU7019 DSCKCHG
2A5 2B5
29 PIU7029 20
PIU7020
2A6 2B6
27 PIU7027 22
PIU7022
COJ14 2A7 2B7
J14 26 PIU7026 23
PIU7023
NLREDWC 2A8 2B8
1 PIJ1401
2
PIJ1402
REDWC
3 PIJ1403 4
PIJ1404 28 PIU7028 4
PIU704
GND GND
5 PIJ1405
6
PIJ1406
34 PIU7034 10
PIU7010
NLINDEX COR176
R176 GND GND
7 PIJ1407
8
PIJ1408
INDEX PIR17602 PIR17601
39 PIU7039 15
PIU7015
NLMOTEA 5V GND GND
9 PIJ1409 10
PIJ14010 MOTEA 4K7 45 PIU7045 21
PIU7021
C NLDRVSB GND GND GND GND C
11 PIJ14011 12
PIJ14012 DRVSB
13 PIJ14013 14
PIJ14014
NLDRVSA
DRVSA SN74LVCH16T245DGV
15 PIJ14015
16
PIJ14016
NLMOTEB
MOTEB
17 PIJ14017
18
PIJ14018
NLDIR
DIR
19 PIJ14019
20
PIJ14020
NLSTEP
STEP
21 22 NLWDATE
WDATE
PIJ14021 PIJ14022
23 PIJ14023 24
PIJ14024
NLWGATE
WGATE
NLTRCK0
TRCK0
COR177
R177
25 PIJ14025
26
PIJ14026 PIR17702
NLWPT COR178
R178PIR17701 5V
27 PIJ14027
28
PIJ14028
WPT PIR17802
4K7
NLRDATA1 COR179
R179PIR17801 5V
29 PIJ14029
30
PIJ14030
RDATA1 PIR179024K7 PIR17901
NLSIDE1 5V
31 PIJ14031 32
PIJ14032 SIDE1 4K7
33 34 NLDSCKCHG
DSCKCHG
COR180
R180
PIJ14033 PIJ14034 PIR18002 PIR18001 5V
4K7
WANNE2,54-34 GERADE
GND
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Filename: Floppy.SchDoc
1 2 3 4
1 2 3 4
GND
COU3A
COU3B
U3A
NLG0
G0 3 PIU303 31
PIU3031
A NLG1 G0 IOG NLVGA0Green0Out A
G1 4 PIU304 32
PIU3032 VGA_Green_Out
NLG2 G1 IOG PIR1301
G2 5 PIU305
NLG3 G2 COR13
R13
G3 6 PIU306
NLG4 G3 75R COJ1
J1
G4 7 PIU307 DSUB-15-F-HD 8.89
NLG5 G4 PIR1302 1%
G5 8 PIU308 VGA_Red_Out 1 PIJ101
NLG6 G5
G6 9 PIU309 GND 6 PIJ106
NLG7 G6 GND
G7 10 PIU3010 GND 11 PIJ1011
G7
VGA_Green_Out 2 PIJ102
NLB0
B0 16 PIU3016 27
PIU3027 7 PIJ107
NLB1 B0 IOB NLVGA0Blue0Out GND
B1 17 PIU3017 28
PIU3028 VGA_Blue_Out VGA_ID1/SDA 12 PIJ1012
NLB2 B1 IOB PIR1501
B2 18 PIU3018 VGA_Blue_Out 3 PIJ103
NLB3 B2 COR15
R15
B3 19 PIU3019 8 PIJ108
NLB4 B3 75R NLVGA0HSync COR44
R44 GND
B4 20 PIU3020 VGA_HSync PIR4401 PIR4402 13 PIJ1013
NLB5 B4
B5 21 PIU3021 PIR1502 1% 49R9 4 PIJ104
NLB6 B5
B6 22 PIU3022 GND 9 PIJ109
NLB7 B6 NLVGA0VSync COR53
R53
B7 23 PIU3023 GND VGA_VSync PIR5301 PIR5302
14 PIJ1014
B7
49R9 GND 5 PIJ105
NLR0
R0 41 PIU3041 33
PIU3033 10 PIJ1010
NLR1 R0 IOR NLVGA0Red0Out GND
R1 42 PIU3042 34
PIU3034 VGA_Red_Out VGA_ID3/SCL 15 PIJ1015
B NLR2 R1 IOR B
R2 43 PIU3043
R2
PIR1601
NLR3
R3 44 PIU3044 COR16
R16
NLR4 R3 75R PIJ10H1 PIJ10H2
R4 45 PIU3045
NLR5 R4 1%
R5 46 PIU3046 PIR1602
R5
H1
H2
NLR6
R6 47 PIU3047
NLR7 R6
R7 48 PIU3048 GND
R7
ADV7125BCPZ170
5V PIR8501 PIC13401
3.3V COR85
R85 COC134
C134
U3B VAA COL7 1M PIC13402 100pF
NLVDAC0CLK L7 PIR6902 PIR13 02 PIR8502 5% 1000V
VDAC_CLK 24 PIU3024 13
PIU3013 PIL701 PIL702
CLOCK VAA 3.3V COR69
R69 PIT301 COR131
R131 X7R
29
PIU3029 PIC3401 PIC3501
NLVDAC0BLANK0N VAA COC34
C34 COC35
C35 MPZ1608S221A 10K 10K
VDAC_BLANK_N 11 PIU3011 30
PIU3030
BLANK VAA NLVGA0SDA NLVGA0ID10SDA
PIC3402 100nF PIC3502 10nF VGA_SDA PIR6901 PIT302
PIR13 01
PIT303 VGA_ID1/SDA GND GND
NLVDAC0SYNC0N
VDAC_SYNC_N 12 PIU3012 1
PIU301
25V 16V
SYNC GND X5R X7R
2
PIU302
NLVDAC0PSAVE0N GND COT3
VDAC_PSAVE_N 38 PIU3038 14
PIU3014
T3
C PSAVEGND C
COC36
C36 15
PIU3015
2N7002,215
GND
PIC3601 PIC3602 36 PIU3036 25
PIU3025 GND 5V
VAA VREF GND
COC118
C118 26
PIU3026
3.3V
100nF GND
PIC11801 PIC11802
35 PIU3035 39
PIU3039
25V VAA COMP GND
40
PIU3040 PIR1320 PIR13 02
X5R 100nF GND COR132
R132 PIT401 COR133
R133
37 PIU3037 49
PIU3049
25V RSET EP 10K 10K
X5R PIR1801 ADV7125BCPZ170 GND NLVGA0SCL
VGA_SCL PIR13201 PIR13 01 NLVGA0ID30SCL
VGA_ID3/SCL
PIT402 PIT403
COR18
R18
560R
PIR1802 1% COT4
T4
2N7002,215
GND
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Filename: VGA.SchDoc
1 2 3 4
1 2 3 4
3.3V
A A
PIR4802 PIR7302
COR48
R48 COR73
R73 GND
4K7 4K7
PIR4801 PIR7301 PIC106 2 COJ4
J4
COC106
C106 3.3V HDMI_TX2_P 1 PIJ401
COU10 PIC106 1 100nF Data2+
U10 2 PIJ402
NLCEC0A Data2 Shield
CEC_A 1 PIU1001 24
PIU10024 HDMI_TX2_N 3 PIJ403
NLSCL0A CEC_A VCCA NLHDMI0TX20P Data2-
SCL_A 2 PIU1002 23
PIU10023 HDMI_TX2_P HDMI_TX1_P 4 PIJ404
NLSDA0A SCL_A D2+ NLHDMI0TX20N Data1+
SDA_A 3 PIU1003 22
PIU10022 HDMI_TX2_N 5 PIJ405
NLHPD0A SDA_A D2- NLHDMI0TX10P Data1 Shield
HPD_A 4 PIU1004 21
PIU10021 HDMI_TX1_P HDMI_TX1_N 6 PIJ406
NLLS0OE HPD_A D1+ NLHDMI0TX10N Data1-
LS_OE 5 PIU1005 20
PIU10020 HDMI_TX1_N HDMI_TX0_P 7 PIJ407
LS_OE D1- Data0+
6 PIU1006 19
PIU10019 8 PIJ408
GND GND GND GND Data0 Shield
NLCEC0B
CEC_B 7 PIU1007 18
PIU10018
NLHDMI0TX00P
HDMI_TX0_P HDMI_TX0_N 9 PIJ409
NLSCL0B CEC_B D0+ NLHDMI0TX00N Data0-
SCL_B 8 PIU1008 17
PIU10017
HDMI_TX0_N HDMI_TXC_P 10 PIJ4010
NLSDA0B SCL_B D0- NLHDMI0TXC0P Clock+
SDA_B 9 PIU1009 16
PIU10016 HDMI_TXC_P 11 PIJ4011
NLHPD0B SDA_B CLK+ NLHDMI0TXC0N Clock Shield
HPD_B 10 PIU10010 15
PIU10015 HDMI_TXC_N HDMI_TXC_N 12 PIJ4012
HPD_B CLK- Clock-
11 PIU10011 14
PIU10014 CEC_B 13 PIJ4013
B 5V NLCT0HPD VCC5V GND GND NL5V0HDMI CEC B
CT_HPD 12 PIU10012 13
PIU10013 5V_HDMI 14 PIJ4014
CT_HPD5V_OUT NC
SCL_B 15 PIJ4015
PIC1 701 PIC17 01 SCL
TPD12S016PWR SDA_B 16 PIJ4016
COC117
C117 COC171
C171 SDA
17 PIJ4017
100nF DDC/CEC GND
PIC1 702 100nF PIC17 02 5V_HDMI 18 PIJ4018
+5V
HPD_B 19 PIJ4019
Hot Plug Detect
GND GND H1 PIJ40H1
FRAME
H2 PIJ40H2
FRAME
H3 PIJ40H3
FRAME
H4 PIJ40H4
FRAME
HDMI Connector
GND
C C
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Filename: HDMI.SchDoc
1 2 3 4
1 2 3 4
COU4A
COU4B
U4A
23
PIU4023 ETH_LED
NLETH0RD0P LED0/ANEN_SPEED
3.3V ETH_RD_P4 PIU404
NLETH0RD0N RXP NLETH0CRS0DV
ETH_RD_N 3 PIU403 15
PIU4015 ETH_CRS_DV
RXM CRS_DV/PHYAD[1:0] i ETH
PIR501 PIR601 NLETH0TD0P
ETH_TD_P6 PIU406
A COR5
R5 COR6
R6 NLETH0TD0N TXP A
ETH_TD_N 5 PIU405
1K 1K TXM
7
PIU407
PIR502 1%PIR602 1% XO
NLETH0MDIO
ETH_MDIO 10 PIU4010 8
PIU408
NLETH0CLK
ETH_CLK
NLETH0MDC MDIO XI i ETH
ETH_MDC 11 PIU4011
MDC NLETH0RST COJ10A
COJ10B
COJ10C
24
PIU4024 ETH-RST J10A
RST
ETH_TD_P 1 PIJ1001
COR9
R9 6K4991% TD+ J1
GND PIR901 PIR902
PIU409 REXT
NLETH0INT
ETH_INT 18 PIU4018 16
PIU4016
INTRP REF_CLK NLETH0RXER 75R 75R
J4
17
PIU4017 ETH_RXER 4 PIJ1004
NLETH0TX0EN RXER i ETH PIC1802 TCT
ETH_TX_EN 19 PIU4019
ETHi TXEN COC18
C18 J5
NLETH0TX0D0
ETH_TX_D0 20 PIU4020 13
PIU4013
NLETH0RX0D0
ETH_RX_D0 100nF
PIC1801 ETH_TD_N 2 PIJ1002
ETHi NLETH0TX0D1 TXD0 RXD0 NLETH0RX0D1 i ETH 25V TD- J2
ETH_TX_D1 21 PIU4021 12
PIU4012 ETH_RX_D1
ETHi TXD1 RXD1 i ETH
GND X5R
KSZ8081RNDCA ETH_RD_P 3 PIJ1003
RD+ J3
75R 75R
J7
5 PIJ1005
B RCT B
PIC1902 J8
1% COC19
C19
COR10
R10 NLETH0LED 100nF
PIC1901
J10B
PIJ1009 PIJ10010 PIR1001 PIR1002
ETH_LED ETH_RD_N 6 PIJ1006
3.3V 25V RD- J6
L-GN 220R
GND X5R
RJ45 - 7499011222A
8 PIJ1008
COR11
R11 GND GND
PIR1101 PIR1102 GND
10K 7 PIJ1007
NC
1%
1% 15 PIJ10015
J10C COR72
R72 NLETH0LED2
ETH_LED2
Frame
3.3V PIJ10011 PIJ10012 PIR7201 PIR7202 16 PIJ10016
Frame
R-GN 220R
RJ45 - 7499011222A
RJ45 - 7499011222A
GND
PIR1201 PIC2901
PIC2101 PIC2801 COR12
R12 COC29
C29
COC21
C21 COC28
C28 1M PIC2902 100pF
C 22µF 470nF 1000V C
PIC2102 PIC2802 PIR1202 5%
6.3V 6.3V X7R
X5R X5R U4B
14 PIU4014 1
PIU401
NLVDD0102V
VDD_1.2V GND GND
3.3V VDDIO VDD_1.2
PIC30 1 PIC3101
COC30
C30 COC31
C31
22
PIU4022
PIC30 2 2.2µF PIC3102 470nF
COL4
L4 GND
PIL401 PIL402
2 PIU402 25
PIU4025
6.3V 6.3V
VDDA_3.3 GND X7R X5R
BKP0603HS121-T PIC3201 PIC3 01 KSZ8081RNDCA
COC32
C32 COC33
C33
PIC3202 22µF PIC3 02 470nF GND
6.3V 6.3V
X5R X5R
GND Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Filename: Ethernet.SchDoc
1 2 3 4
1 2 3 4
A A
http://linux-sunxi.org/MicroSD_Breakout
3.3V
COJ2 COR27
R27 NLM0TCK
J2 SD_D2 PIR2701 PIR2702 M_TCK
COR52
R52PIR5202
12K1
PIR5201
1% NLSD0D2
SD_D2 1
PIJ201 DAT2 0R
COR55
R55PIR5502 12K1
PIR5501 1% NLSD0D3
SD_D3 2
PIJ202
COR56 NLSD0CMD CD/DAT3 1%
R56PIR5602 12K1
PIR5601 1% SD_CMD 3
PIJ203 CMD
4
PIJ204
NLSD0CLK VDD COR32
R32 NLM0TMS
SD_CLK 5
PIJ205 SD_D1 PIR3201 PIR3202 M_TMS
CLK
6
PIJ206 GND 0R
COR57
R57PIR5702 12K1
PIR5701 1% NLSD0D0
SD_D0 7
PIJ207
COR88 NLSD0D1 DAT0 1%
R88PIR8802 12K1
PIR8801 1% SD_D1 8
PIJ208 DAT1
COR33
R33 NLM0TDO
G1
PIJ20G1 GND
SD_CMD PIR3301 PIR3302
M_TDO
G2
PIJ20G2 GND 0R
G3
PIJ20G3 GND 1%
G4
B GND PIJ20G4 GND B
COR89 NLSD0CD COR34
R34 NLM0TDI
R89PIR8902
12K1
PIR8901
1% SD_CD 9
PIJ209 Card
SD_D0 PIR3401 PIR3402
M_TDI
Detect 0R
Switch 1%
COC22
C22 10
PIJ2010
GND
3.3V PIC2201 PIC2202 GND COR35
R35
Micro SD Socket SD_D3 PIR3501 PIR3502
NLM0RX
M_RX
10µF
10V 0R
X5R 1%
COR36
R36 NLM0TX
3.3V SD_CLK PIR3601 PIR3602
M_TX
COJ15
J15
COR119 0R
R119 12K1
PIR11901
NLSD20D3
SD2_D3 1 PIJ1501
COR21
R21 PIR11902 NLSD20CMD CD/DAT3 1%
PIR2101
12K1
PIR2102
SD2_CMD 2 PIJ1502
CMD
3 PIJ1503
GND VSS1
4 PIJ1504
3.3V
NLSD20CLK VDD COS3A
COS3B
COS3C
COS3D
S3A
SD2_CLK 5 PIJ1505
CLK COR142 NLCPLD0CFG0
6 PIJ1506 R142
PIR14202 12K1
PIR14201 1% CPLD_CFG0 8 PIS308 1
PIS301
C COR24
R24 GND
NLSD20D0 VSS2 3.3V C
PIR2401COR25 12K1 SD2_D0 7 PIJ1507 CHS-04TA
R25 PIR2402 NLSD20D1 DAT0
PIR2501COR26 12K1 SD2_D1 8 PIJ1508
R26 PIR2502 NLSD20D2 DAT1 S3B
PIR2601
12K1
PIR2602
SD2_D2 9 PIJ1509
DAT2 COR143 NLCPLD0CFG1
R143
PIR14302
12K1
PIR14301
1% CPLD_CFG1 7 PIS307 2
PIS302
COR120
R120 NLSD20CD
PIR12001
12K1
PIR12002
SD2_CD 10 PIJ15010 CHS-04TA
CD Card
COR121 Detect
R121 12K1
PIR12101 PIR12102
NLSD20WP
SD2_WP 11 PIJ15011 Switch
S3C
WP COR144 NLCPLD0CFG2
R144
PIR14402
12K1
PIR14401
1% CPLD_CFG2 6 PIS306 3
PIS303
CHS-04TA
COC27
C27 12 PIJ15012
GND
PIC2701 PIC2702
S3D
3.3V GND
MMC SD Socket COR31
R31PIR3102
12K1
PIR3101
1% NLCPLD0CFG3
CPLD_CFG3 5 PIS305 4
PIS304
10µF
CHS-04TA
10V GND
X5R
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Filename: LED_SW_BUT.SchDoc
1 2 3 4
1 2 3 4
COU12
U12
1 PIU1201 7
PIU1207 VOUT
12V_FUSED PIC302 PIC702 Vin Vout PIR201 PIC802 PIC1301 PIC1501 PIC1601 PIR15 01 5V
4.67V
COC3
C3 COC7
C7 2 PIU1202 5 COR2
R2 COC8
C8 COC13
C13 COC15
C15 COC16
C16 COR155
R155
GND SYNC FB PIU1205
PIC301 22µF PIC701 47nF 5K6 PIC801 47nF PIC1302 100µF PIC1502 100µF PIC1602 100µF 27K
A 25V 50V PIR202 1% 50V 10V 10V 10V PIR15 02 1% A
3 PIU1203 6
PIU1206
AGND
GND
X7R EN SS/TRK PIC1701 X7R X5R X5R X5R PIC18 01 PIR160 1
X5R
GND GND COC17
C17 PIR401 COC181
C181 COR160
R160
PIU1204 PIU1208 PIC1702 470nF COR4
R4 GND 10nFPIC18 02 27K
50V 1K15 50V PIR160 2 1%
4
8
171050601
GND GND X7R PIR402 1% NLCPLD0ADC1
CPLD_ADC1 X7R
GND GND GND
GND
COU14
U14
1 PIU1401 7
PIU1407 VOUT
12V_FUSED PIC3702 PIC3802 Vin Vout PIR1901 PIC3902 PIC40 1 PIC9 01 PIC10 01 3.3V
3.30V
COC37
C37 COC38
C38 2 PIU1402 5 COR19
R19 COC39
C39 COC40
C40 COC99
C99 COC100
C100
GND SYNC FB PIU1405
PIC3701 22µF PIC3801 47nF 3K3 PIC3901 47nF PIC40 2 100µF PIC9 02 100µF PIC10 02 100µF
25V 50V 3 PIU1403 6
PIU1406 PIR1902 1% 50V 10V 10V 10V
AGND
GND
X7R 1.8V EN SS/TRK X7R X5R X5R X5R
X5R PIC102 1
GND GND COC102
C102 PIR20 1
PIU140 PIU1408 PIC102 470nF COR20
R20 GND
50V 1K05
4
8
171050601
GND GND X7R PIR20 2 1%
B B
GND
AO4832 AO4832 GND
T5B COT5A
COT5B
T5A
8 PIT508 6
PIT506
7 PIT507 13
PIT501
PIT503 5
PIT505
PIT502 PIT504
2
4
PIR13501 PIR13601
COR135
R135 COR136
R136
10R 10R
PIR13502 PIR13602 SR= 2V/ms
COR137
R137
COC139
C139
PIR13701 PIR13702
PIC13901 PIC13902
5K1 10nF
GND
50V
Fuse 3A 35V SMD 1206 fast X7R
C COS1 C
HV S1
8
COJ11
J11 COF1
F1 i COL5
L5 NLVIN
1 VIN
PIS101
COU34
U34 PIU3408
1
PIJ1101 PIF101 PIF102
1 PIL501
4 2
PIL504 PIS102
1 7
PIU3407
PID501 PIR13801 PIR13901 PIU3401 Vin Vout PIC14 01 12V_FUSED
3
PIS103
3
PIJ1103
COD5
D5 2 PIL502 PIL503
3 COR138
R138 COR139
R139 COC144
C144
1M 470K GATE PIC14 02 10µF
2
PIJ1102 9µH PIS10F1 PIS10F2 PIR13802 1% PIR139502 1%
PIU3405 SHDN FAULT
6
PIU3406
16V
NLPOWER0GND
POWER_GND PID502 2 PIU3402 GND X5R
UV
F1
F2
Power Jack 2.1mm 90° SMD GND PIR140 1
SMBJ20A, 20V, 600W GND COR140
R140
A101J1AV2Q004 27K
OV = 14V
PIR14032 1% OV
UV = 10V
PIR14 01 PIU3403
COR141
R141
37K4
PIR14402 1% PIU3404 GND
Title:
GND LTC4365ITS8#TRMPBF MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Filename: PowerMain.SchDoc
1 2 3 4
1 2 3 4
5V 1V
COU11
U11 COC6
C6
COR17
R17
PIR1701 PIR1702
PG_1V0 28 PIU11028
5
PIU1105 PIC601
X5R
PIC602
5V POK VOUT GND
10K COC41
C41 6
PIU1106 6.3V
VOUT 47µF
PIC4101 PIC4102 19 PIU11019 7
PIU1107
GND PVIN VOUT
20 PIU11020 8
PIU1108
A 22µF PVIN VOUT PIR4901 PIC1 101 A
21 PIU11021 9
PIU1109
25V PVIN VOUT COR49
R49 COC111
C111
10
PIU11010
X5R VOUT 200K PIC1 102 22pF
33 PIU11033 11
PIU11011
AVIN VOUT PIR4902
1% 6.3V
27 PIU11027 31
PIU11031 NP0
ENABLE VFB
1 PIU1101 NC(SW)
PIR50 1
2 COR50
R50
PIU1102 NC(SW)
12 PIU11012 26
PIU11026
604K
NC(SW) LLM/SYNC
3 PIU1103 NC
02
PIR51%
4 PIU1104 NC
22 PIU11022 NC
23 PIU11023 NC
24 PIU11024 29
PIU11029
NC RLLM
25 PIU11025 NC
34 PIU11034 NC(SW)
35 PIU11035
30
PIU11030
NC(SW) SS Soft-start 3.8ms
36 PIU11036
PIC1 901
NC(SW) COC119
C119
37 PIU11037 32
PIU11032
B NC(SW) AGND 47nF B
38 PIU11038 NC(SW)
PIC1 902
13
PIU11013
6.3V
PGND
17 PIU11017
14
PIU11014
GND X5R
PGND PGND
18 PIU11018 15
PIU11015
PGND PGND
16 PIU11016 39
PIU11039
PGND PGND
GND EN6347QI GND
1V
C C
PIR16 02
5V COR161
R161
COU13
U13 10K
14 PIU13014 7
PIU1307
NLCPLD0ADC3
CPLD_ADC3 PIR16 01
PVIN VOUT 1.8V
PIC120 1 8
PIU1308
PIC12101 PIR1620 PIC18201
COC120
C120 VOUT COC121
C121 COR162
R162 COC182
C182
10µF
PIC120 2 COR51
R51 PIC12102 10µF 10K PIC1820 10nF
PIR5101 PIR5102
13 PIU13013 5
PIU1305
10V AVIN VSENSE 10V NLCPLD0ADC2 50V
100R CPLD_ADC2 PIR16201
GND X5R 12 PIU13012 4 GND X5R PIC18301 X7R
1% ENABLE NC PIU1304
1 COC183
C183 GND
NC(SW) PIU1301
NLPG01V0
PG_1V0 3 PIU1303 15 PIC18302 10nF
LLM NC(SW) PIU13015
16
PIU13016
50V
NC(SW) X7R
11 PIU13011
VS0
10 PIU13010 6
PIU1306
GND
VS1 AGND
9 PIU1309 2
PIU1302
5V VS2 PGND GND
Title:
EP53A7HQI MEGA65
D D
Number: Rev.
A4 TE0765
[No Variations] 03
Date: 2020-06-29 Copyright: Trenz Electronic GmbH / TT Page 21 of 23
Filename: POWER.SchDoc
1 2 3 4
1 2 3 4
NLV0P
V_P
COR54
R54 COR59
R59
PIR5401 PIR5402 PIR5901 PIR5902 1V
240R 1%
PIC12301 2K61
COC123
C123
PIR60 2 PID602 PID601 PIC12302 4.7µF
COR60
R60 COD6
D6
A 200K GND A
PIR60 1 1% PIC12402
BAV199LT1G COC124
C124 COC125
C125
NLV0N COR66
R66 COR61
33nF R61
V_N PIR6601 PIR6602
PID603 PIC12401 PIR6101 PIR6102 PIC12502 PIC12501
240R 1% 240R 1% 10µF

3.3V GND
10V
PID702 PID701 BAV199LT1G X5R
COJ9
J9
1 PIJ901
COD7
D7
PID703 GND
2 PIJ902
COR62
R62
COC126
C126
NLPWM0R
PWM_R PIR6201 PIR6202 PIC12602 PIC12601 3 PIJ903
240R
PIC12701 PIR6301 COR64
R64
COC128
C128
COC127
C127 COR63
R63 10µF NLPWM0L
PWM_L PIR6401 PIR6402 PIC12802 PIC12801
1% 4 PIJ904
PIC12702 33nF 150R 10V PIC12901 PIR6501
X5R 240R COC129 COR65 10µF
25V 02
PIR631% C129 R65
B 1% 10V B
X7R PIC12902 33nF 150R 3.5RCA
25V 02
PIR651% X5R
GND COD8
D8 PID803 X7R
GND
COL11
L11
NL5V0PVDD
5V_PVDD PIL1102 PIL1101
PID801 PID802 BAV199LT1G
5V
PIC8201 PIC8301 PIC8401 PIC8501 MPZ1608S221A
COC82
C82 COC83
C83 COC84
C84 COC85
C85 GND 3.3V
PIC8202 47µF PIC8302 47µF PIC8402 470pF PIC8502 470pF
6.3V 6.3V 50V 50V
GND GND GND GND
3.3V
PIC8601
COC86
C86 COJ22
J22
I2S PIC8602 470nF COU37
U37 NLSPKL0P
SPKL_P 1 PIJ2201
i 12 PIU37012 16
PIU37016
PIL101 NLSPKL0N
SPKL_N 2 PIJ2202
DVDD PVDD COL1
GND 20
PIU37020 L1 PIL601
C PVDD COL6 C
2A L6 PIC8701 PIC8 01 JST-S2B-XH-A
NLAUDIO0MCLK
AUDIO_MCLK 6 PIU3706 BLM15PX121SN1D 2A COC87
C87 COC88
C88
NLAUDIO0SDATA MCLK PIL102 PIC8702 470pF PIC8 02 470pF
AUDIO_SDATA 10 PIU37010 1
PIU3701
BLM15PX121SN1D
SDATA OUTL+ PIL602 50V 50V
2
PIU3702
NLAUDIO0BCLK OUTL-
AUDIO_BCLK 7 PIU3707 GND GND
NLAUDIO0LRCLK BCLK
AUDIO_LRCLK 9 PIU3709 15
PIU37015
LRCLKOUTR+
OUTR-
14
PIU37014
PIL801
NLFPGA0SCL
FPGA_SCL 5 PIU3705 PIL901 COL8
L8
NLFPGA0SDA SCL
FPGA_SDA 4 PIU3704 BLM15PX121SN1D 2A
SDA COL9 COJ19
21
PIU37021
L9 BLM15PX121SN1D J19
EP NLSPKR0P
11 PIU37011 8
PIU3708 2A PIL802 SPKR_P 1 PIJ1901
SAMOD GND
3 PIU3703 17
PIU37017
PIL902 NLSPKR0N
SPKR_N 2 PIJ1902
GND ADDR GND
18
PIU37018
NLnSD0AUDIO GND
nSD_AUDIO 13 PIU37013 19
PIU37019
PIC8901 PIC9401 JST-S2B-XH-A
SD GND COC89
C89 COC94
C94
PIR4702
COR47
R47 SSM2518CPZ-R7 NOT CHECKED!!! GND PIC8902 470pF PIC9402 470pF
4K7 50V 50V Title:
PIR4701 I2C addr: 0x34 GND GND MEGA65
D D
GND Number: Rev.
A4 TE0765
[No Variations] 03
Filename: SOUND.SchDoc
1 2 3 4
1 2 3 4
REVISION HISTORY
REV Description
-03 IG
1. Added a VRP resistor on bank 65;
A A
2. LDO U33 is changed on ADP7102ACPZ;
3. Signal FPGA IO0 is connected on AE18 pin of FPGA;
4. Signal DBG_LED3 is connected on AD18 pin of FPGA;
5. Signal MIO13_25 connected to J1 pin 33 instead MIO25.
6. Resistor R84 is removed;
7. LED D1 moved on edge of PCB;
8. Added THT testpoints J4 on CPLD_JTAGEN, R76 was removed;
9. Signals B49_XX_X are renamed in B88_XX_X;
10. C241 is changed on 1nF;
11. Length of CLK signals on RFADC and RFDAC are adjusted;
12. Wrong connection on U8 is fixed (PCB);
13. Wrong connection PGOOD1 pin of U7 is fixed;
B B
C C
Title:
MEGA65
D D
Number: Rev.
A4 TE0835
[No Variations] 03
Filename: Revision_Changes.SchDoc
1 2 3 4
COJ9 COH7
PAJ902 PAC12601 PAC12602

PAR6301
COC126 COR63 PAR6302
PAJ130H1
PAJ1403 PAJ14031 PAJ14029 PAJ14027 PAJ14025 PAJ14023 PAJ14021 PAJ14019 PAJ14017 PAJ14015 PAJ14013 PAJ1401 PAJ1409 PAJ1407 PAJ1405 PAJ1403 PAJ1401
PAJ90H1 PAJ90H2
PAC12801 PAC12802 PAC12701
COC128 COC127 PAC12702
COJ14
PAJ901 PAJB10H1 COJ13 PAJ1301 PAJ1302 PAJ1303 PAJ1304
PAR6501 PAR6502 COR65 PAJ14034 PAJ14032 PAJ14030 PAJ14028 PAJ14026 PAJ14024 PAJ14022 PAJ14020 PAJ14018 PAJ14016 PAJ14014 PAJ14012 PAJ14010 PAJ1408 PAJ1406 PAJ1404 PAJ1402 PAH701
PAJ904 PAJ903 PAC12901 PAC12902 COR62
PAD702 PAD701
CO 129 PAD703 COD7 COPM2
COPM4
COJ2 PAD803 PAR6202
PAR6201
PAJB102 PAJB101 COR180 COR179COR178COR177 COR176 PAPM200
PAPM400
PAJ20G3 PAJ20G4 PAR6402 PAR6401
PAC12501
PAR18002 PAR17902 PAR17802 PAR17702 PAR17602
PAJ160H1
PAJ208 PAD802 PAD801
PAR3601 PAR3602 PAR18001 PAR17901 PAR17801 PAR17701 PAR17601
PAJ207
COR36
COD8COR64 PAJB104
COC138
PAJB103 COC124
COR61 COR59
PAC12502COC123
COJ16 PAJ1601 PAJ1602 PAJ1603 PAJ1604 COR130COD12
PAR8801
PAR3201 PAR8802
PAR3202
PAJ206 COR88 COC125 COD6 PAR6102 PAC12402 PAC12302 PAR5902 PAD120K PAD120A
PAR13002 PAR13001
PAC13802 COR70
COR34 PAR6101 PAC12401 PAC12301 PAR5901
PAR537401 PAR354702 PAC13801
PAJ205 COR57
COR89
COR32 PAJB106 PAJB105 PAD601 PAR7002 PAR70 1 PAD100K PAD100A
PAJ204 PAR5601
PAR3301 PAR5602
PAR3302
AR8901 PAR8902
PAJ209 PCOR56
COR33 PAD603 COD10
PAJ203 PAJB108
COR35 COR158PAJB107
PAR53 01 PAR35 02
COR55 PAD602
PAJ202 PAR15801 PAR15802
PAJ201 COR52
COR27 PAR5201
PAR2701 PAR5202
PAR2702 COR66
COR54 PAR6001 PAR6002
COR60 PAU7024 PAU7023 PAU702 PAU7021 PAU702 PAU7019 PAU7018 PAU701 PAU7016 PAU7015 PAU7014 PAU7013 PAU7012 PAU701 U701 PAU709 PAU708 U70 PAU706 PAU705 U704PAU703PAU702PAU701
PAC2202 PAJB1010 PAJB109 PAR6602 PAR5402
PAR6601 PAR5401
PAJ2010 COU7
PAC2201
PAJB1012 PAJB1011
PAJ20G1 PAJ20G2
COC22 PAU7025 PAU7026 PAU702 PAU7028 PAU7029 PAU703 PAU7031 PAU7032 PAU703 PAU7034 PAU7035 PAU7036 PAU703 PAU7038 U7039 PAU704 PAU7041 U7042PAU7043 PAU704 U7045PAU7046PAU7047PAU7048 PAS304 PAS303 PAS302 PAS301 COP2
PAJ10015 COJ10 PAR902 PAR901
COJB1 COD4
PAJ1009 COC32 COR9 PAR502 PAR501
PAJ100H1 COR5 COS3 PAD406 PAD405 PAD404 PAP201 PAP207
PAJ10010 PAJ1001 COC21
COU4 PAP20H1
PAJ1002 PAC3202 PAU407 PAU408 PAU409PAU4010PAU401 PAU4012 COC28
PAU406 PAU4013 PAS305 PAS306 PAS307 PAS308 PAD401 PAD402 PAD403
PAR10 1 PAR10 2 COR10 PAC3201PAU405 PAU4014 PAC2802 PAC2102
COR31
COR144
COR143
COR142 PAP202 PAP208
PAU404
PAC3301PAC3302COC33 PAU4015 PAC2801 COD11
PAR1 01 PAR1 02 COR11 PAJ1003 PAU403
PAL402PAL401
PAU402
PAU4025 PAU4016
PAU4017 PAC2101 PAR3101 PAR14401 PAR14301 PAR14201
PAJ1004 PAC1802PAC3101 PAU401
COL4 PAU4018
PAP203 PAP209
PAR3102 PAR14402 PAR14302 PAR14202 PAD1 06 PAD1 05 PAD1 04
PAC3001PAC1801PAC3102 PAU4024 PAU4023 PAU402 PAU4021PAU4020 PAU4019
PAJ1005 PAC3002PAC1902COC31
COC18 PAR601 PAR602 COR6
PAJ1006 PAC1901
COR157 PAD1 01 PAD1 02 PAD1 03 PAP204 PAP2010
PAR15701
PAJ1007 COC30 COC19 PAR15702 COC162
PAJ10 1 PAJ1008
COC163
PAC16202 PAP205 PAP2011
PAC16302 PAP20H2
PAJ10 12 PAC16301 PAC16201 PAP206 PAP2012
COR72 COR162
PAJ100H2 PAJ10016
PAR7201 COC183
COR30COR29
PAR16202 PAR16201
COC164
COR147 PAU3501 PAU3508
PAR7202 COR161 PAR30 2 PAR2902
PAJ17010 PAJ1709 PAC18302 PAC18301 PAC16401
PAC2902 PAC2901 PAR1201 COC182 PAU320A1 PAU320A2 PAU320A3 PAU320A4 PAU320A5 PAU320A6 PAU320A7 PAU320A8 PAU320A9 PAU320A10 PAU320A11 PAU320A12 PAU320A13 PAR14602 PAU3502 PAU3507
COC165 COC245
COC202
COC29 PAR3001 PAR2901 PAC24702
PAR1202 COR12 PAR16102 PAR16101 PAC16501
PAU320B1 PAU320B2 PAU320B3 PAU320B4 PAU320B5 PAU320B6 PAU320B7 PAU320B8 PAU320B9 PAU320B10 PAU320B11 PAU320B12
COR28COC247COC173 PAU320B13
COR146 PAR14601 PAR14701
PAC201 PAC24501 PAC24701 PAU3503 PAU3506
COR155 COL10
AC18202 PAC18201 PAC16502 PAC16402
PCOR160 PAU320C1 PAU320C2 PAU320C3 PAU320C4 PAU320C5 PAU320C6 PAU320C7 PAU320C8 PAU320C9 PAU320C10 PAU320C11 PAU320C12 PAU320C13 PAR14702
PAC20 PAR2802 PAC24502 COC250 PAC16101 PAC17301
PAJ1708 PAJ1707 PAU320D1 PAU320D2 PAU320D3COC248
AR15 01 PAR15502COC246
PCOC181 PAU320D4 PAU320D5 PAU320D6 PAU320D7 PAU320D8 PAU320D9 PAU320D10 PAU320D11 PAU320D12 PAU320D13
PAJ40H4 PAJ40H3 PAL10 1 PAL10 2 PAR2801 PAC16102 PAC17302 PAU3504 PAU3505
PAR16002 PAR16001 PAU320E1 PAU320E2 PAU320E3 PAU320E4 PAU320E5 PAU320E6 PAU320E7 PAU320E8 PAU320E9 PAU320E10 PAC25002
PAU320E11 PAU320E12 PAU320E13
COR68 PAC25001
PAC18102 PAC18101 PAU320F1 PAC2460PAU320F2 PAU320F3 PAU320F4 PAU320F5 PAU320F6PAC24801PAC24802
PAU320F7 PAU320F8 PAU320F9 COV1 PAU320F10 PAU320F11 PAU320F12 PAU320F13
PAC24601 PAC16602 PAC160 COC161 COP1
COJ17 PAJ1706 PAJ1705 COR156 PAU320G1
COC249 PAU320G2 PAU320G3 PAU320G4 PAU320G5 PAU320G6 PAU320G7 PAU320G8 PAU320G9 PAU320G10 PAU320G11 PAU320G12 PAU320G13
PAR6802
PAJ4019
PAJ4018 PAR15602 PAR15601
PAU320H1 PAU320H2 PAU320H3 PAU320H4 PAU320H5 PAU320H6
PAR302PAU320H7PAR301PAU320H8 COR3 PAU320H9 PAU320H10 PAU320H11 PAV102PAU320H12 PAU320H13
PAR6801
COU35 COD3
PAJ4017 COU10 COC117 COC137 PAU320J1 PAU320J2 PAU320J3PAC24901PAU320J4PAC2490 PAU320J5
COC16 PAU320J6 PAU320J7 PAU320J8 PAU320J9 PAU320J10 PAU320J11 PAU320J12 PAU320J13
PAJ4016 PAJ1704 PAJ1703 PAU320K1 PAU320K2
COC244COC252
PAU320K3 PAU320K4 PAU320K5 PAU320K6 PAU320K7 PAU320K8 PAU320K9 PAU320K10 PAU320K11 PAU320K12 PAU320K13 PAD30 PAD302 PAD301 PAP101 PAP107
PAJ40H6 PAJ4015 PAC17101 PAC11702
PAJ4014 PAU10013 PAU10012 PAU320L1 PAU320L2 PAU320L3 PAU320L4 PAU320L5 PAC2401 PAU320L6 PAU320L7 PAU320L8 PAC25201
PAU320L9 PAU320L10 PAU320L11 PAU320L12 PAU320L13
PAJ4013 PAU10014 PAU10011
PAC11701 PAC1370 PAC25202 PAP10H1
PAC17102 PAC13702 PAU320M1 PAU320M2 PAU320M3 PAU320M4 PAU320M5 PAC240 PAU320M6 PAU320M7 PAU320M8 PAU320M9 PAU320M10 PAU320M11 PAU320M12 PAU320M13
PAJ4012 PAU10015 PAU10010
PAJ4011
PAJ4010 PAU10016 COC171 PAU1009
PAJ1702 PAJ1701
COU32 PAU320N1 PAU320N2 PAU320N3 PAU320N4 PAU320N5 PAU320N6 PAU320N7 PAU320N8 PAU320N9 PAU320N10 PAU320N11 PAU320N12 PAU320N13 PAD304 PAD305 PAD306 PAP102 PAP108
PAJ409 PAU10017 PAU1008 COD2
PAJ408 PAU10018 PAU1007
PAJ407 COR73
PAJ406 PAU10019 PAU1006 PAP103 PAP109
PAJ40H5 PAJ405 PAU10020 PAU1005 COR48 PAD203 PAD20 PAD201
PAJ404 PAU10021 PAU1004 PAR7302
PAJ403 PAU10022 PAU1003 PAR7301
PAJ402
PAJ401 PAU10023 PAU1002 PAR4801 PAD204 PAD205 PAD206
PAU10024
PAC10601 PAC10602
CO 106 PAU1001 PAP104 PAP1010
PAR4802
PAJ40H2 PAJ40H1 COJ4 COC145PAP105 PAP1011

COC146 PAC14502 PAP10H2
PAJ21013 PAJ2101 PAJ2109 PAJ2107 PAJ2105 PAJ2103 PAJ2101 PAC14602
PAC14601
COJ21 PAC14501 PAP106 PAP1012

PAJ21014 PAJ21012 PAJ21010 PAJ2108 PAJ2106 PAJ2104 PAJ2102
COR85 COC134
PAR8501 PAC13401
COR132
COT4
PAR13202 PAR13201
PAJ10H2 PAR8502 PAC13402
PAT401 PAT402
COR133 COR26 PAR2601PAR2602 PAJ1509 PAJ150H2
PAT403 PAU1904 PAU1903 PAU10AB1 PAU10AA1 PAU10Y1 PAU10W1 PAU10V1 PAU10U1 PAU10T1 PAU10R1 PAU10P1 PAU10N1 PAU10M1 PAU10L1 COC167
PAU10K1 PAU10J1 PAU10H1 PAU10G1PAC16002PAU10F1
PAC16001PAU10E1 PAU10D1 PAU10C1
PAC1201PAU10B1 PAU10A1
COU1
PAU1902
PAR13302 PAR13301 PAJ1015 PAJ105 COR53 PAR5302 PAR5301 PAU1905 PAU1901
COU19 PAU10AB2 PAU10AA2 PAU10Y2 PAU10W2 PAU10V2 PAU10U2 PAU10T2 PAU10R2 PAU10P2 PAU10N2 PAU10M2 PAU10L2
COC160 COC12 PAU10K2 PAU10J2 PAC16702
PAU10H2
PAC16701
PAU10G2 PAU10F2 PAU10E2 PAU10D2 PAU10C2PAC1202PAU10B2 PAU10A2
PAR11901PAR11902 PAJ1501
PAU10AB3 PAU10AA3 PAU10Y3 PAU10W3 PAU10V3 PAU10U3 PAU10T3 PAU10R3 PAU10P3 PAU10N3 PAU10M3 PAU10L3 PAU10K3 PAU10J3 PAU10H3 PAU10G3 PAU10F3 PAU10E3 PAU10D3 PAU10C3 PAU10B3 PAU10A3
PAJ1010 PAR4 02 PAR4 01 PAU1804 PAU1803
COR1 9
PAU1802 PAU10AB4 PAU10AA4 PAU10Y4 PAU10W4 PAU10V4 PAU10U4 PAU10T4 PAU10R4 PAU10P4 PAU10N4 PAU10M4 PAU10L4 PAU10K4 PAU10J4 PAU10H4 PAU10G4 PAU10F4 PAU10E4 PAU10D4 PAU10C4 PAU10B4 PAU10A4
PAJ1014 PAJ104 PAR1501
COR44 PAU1805 PAU1801 COU18 PAU10AB5 PAU10AA5 PAU10Y5 PAU10W5 PAU10V5 PAU10U5 PAU10T5 PAU10R5 PAU10P5 PAU10N5 PAU10M5 PAU10L5 PAU10K5 PAU10J5 PAU10H5 PAU10G5 PAU10F5 PAU10E5 PAU10D5 PAU10C5 PAU10B5 PAU10A5 PAR2101PAR2102 PAJ1502
PAJ109 PAC16801 PAC16802 COR21
COR131 COR15 COC150
PAU10AB6 PAU10AA6 PAU10Y6 PAU10W6 PAU10V6 PAU10U6 PAU10T6 PAU10R6PAC4202
PAC4201 PAU10P6 PAC15201PAC15202
PAU10N6 PAU10M6 PAC70 2PAU10L6 PAC5601PAC5602PAU10K6 PAU10J6 PAC14301PAC14302
PAU10H6 PAU10G6 PAU10F6
PAC6901 PAU10E6 PAU10D6 PAU10C6 PAU10B6 PAU10A6
COT3 PAJ1013 PAJ103
CO 152 COC70 COC56 COC143COC168
PAR13101 PAR13102 PAR1502 PAU10AB7 PAU10AA7 PAU10Y7 PAU10W7 PAU10V7 PAU10U7PAC1502 PAU10T7 PAU10R7
COC24COC42 PAU10P7 PAU10N7 PAU10M7 PAC70 1PAU10L7 PAU10K7 PAU10J7 PAU10H7 PAU10G7 PAU10F7
PAC6902 PAU10E7 PAU10D7 PAU10C7 PAU10B7 PAU10A7
PAJ108 PAC150 PAC2401 PAC240 PAC1001 PAC1002 PAC4902 PAC4901 COC69 PAC901 PAC902
PAU3024 PAU3023PAU302 PAU3021 PAU302 PAU3019PAU3018PAU3017 PAU3016 PAU3015PAU3014PAC3401PAU3013 PAC7102COC23 COC141 COC147 COC148 PAC2702 PAJ1503
PAJ1012 PAJ102 PAR1301 PAU3025
PAU3026
PAC3402PAU3012
PAU3011
PAU10AB8 PAU10AA8 PAU10Y8 PAU10W8 PAU10V8
PAC16901
PAC16902
PAU10U8 PAC20PAU10T8PAC201 PAU10R8 PAU10P8 PAU10N8
PAC7402
PAU10M8 PAU10L8
PAC7101
PAL202PAU10K8PAC14101PAU10J8PAC1402 PAC14202
PAL201
PAU10H8 PAC14201 PAU10G8 PAU10F8PAC7601 PAU10E8 PAU10D8 PAU10C8 PAU10B8 PAU10A8
COU11
PAT303 COU3COC35 COC77 PAU10AB9 PAU10AA9 PAU10Y9 PAU10W9
COC10 COC140
PAU10V9
COL2 COC9
PAU10U9PAC102 PAU10T9 PAC15101PAC15102
PAU10R9 PAU10P9 PAU10N9 PAU10M9 PAU10L9 PAU10K9 PAC2302PAU10J9 PAU10H9 PAU10G9 PAU10F9 PAC7602 PAU10E9 PAU10D9 PAU10C9 PAU10B9 PAU10A9 PAC14702 PAC14802 PAU1106 PAU105 PAU1104PAU1103 PAU102 PAU10
COR13 PAU3027 PAU3010 COC20 COC11 PAC10 PAC12202 PAC12201 PAC2301 PAC4301 PAC4302 PAC14902 PAU1107 PAU11038
PAJ107 PAR1302 PAU3028 COC34
PAU309 PAC7702 PAC701 COR8
COC169
COC48
COC154
COC157COC44COC155
COC156 PAC7401 PAC14002 PAC15801 PAU1108 PAU11037
COC27 PAC2701 PAJ1504
CO 15 COC74 COC49COCC7O1142 COC76 COC43
PAC3501 PAU3029 PAU308 COC2 PAC201 PAU10AB10 PAU10AA10PAC5401PAU10Y10 PAU10W10 PAU10V10 PAU10U10 PAC15302PAU10T10PAC1530 PAU10R10 PAU10P10 PAU10N10 PAU10M10 PAU10L10 PAU10K10 PAU10J10 PAU10H10 PAU10G10 PAU10F10 PAU10E10 PAU10D10 PAU10C10 PAU10B10 PAU10A10
COR69
PAT302 PAT301 PAU3030 PAU307 PAU1704 PAU1701 PAC14001 PAC601 PAU1109 PAU11036 COR49COC1 1
PAJ1011 PAJ101 PAC3502 PAU3031 PAU306 PAU10AB11 PAU10AA11PAC5402PAU10Y11 PAU10W11 PAR802PAU10U11
PAU10V11 PAU10T11 PAU10R11 PAU10P11 PAU10N11 PAU10M11 PAU10L11 PAU10K11 PAU10J11 PAU10H11 PAU10G11 PAU10F11 PAU10E11 PAU10D11 PAU10C11 PAU10B11 PAU10A11 PAU11010 PAU11035
PAR1601 COU17 PAC202 PAC4802 PAC4801 PAC15402 PAC15702PAC4402 PAC4401 COC66 PAC15602PAL301 PAC15502 PAC15802 PAU11011 PAU11034
PAR6901 PAR6902 PAU3032 PAU305 PAC15501 PAC4701 PAC4702 PAC170 2 PAC170 1 PAC14701 PAU11012 PAU11033 PAR5002 PAR4901
PAU3033 COR159COR126
PAU304 PAU1703 PAU1702 PAU10Y12 PAU10W12 PAR801 PAU10G12 PAU10F12 PAU10E12 PAU10D12 PAU10C12 PAU10B12 PAU10A12 PAU11013 PAU11032 PAC11101
PAJ106
PAR1602
COR16 PAC1 802 PAC3602
PAU3034
PAU3035
PAU3036
PAU3049 PAU303
PAU302
PAR15901 PAR15902
PAU301
PAR12602 PAR12601
PAU10AB12 PAU10AA12COC54 PAU10V12 PAU10U12 PAU10T12 PAU10R12 PAC15401PAU10P12 PAU10N12 PAC15701PAC4601
COC50PAU10AB13 PAU10AA13 PAU10Y13PAC5201 PAU10W13 PAU10V13 PAU10U13COC60 PAU10T13 PAU10R13 PAU10P13 PAU10N13
PAU10M12 PAU10L12PAC4602 PAU10K12PAC15601PAL302PAU10J12 PAU10H12
PAU10M13 PAU10L13
COC153 COC12 COL3 COC170 CO 158 PAU10K13 PAU10J13 PAU10H13
PAC6602
PAC6601 COC47 PAU10G13 PAU10F13 PAU10E13 PAU10D13 PAU10C13 PAU10B13 PAU10A13
CO 149 PAC14801
PAC14901 PAC602
PAU11014
PAU11015
PAU11016 PAU11039
PAU11031
PAU11030
PAU11029
PAC11901
PAR5001 PAR4902
PAC1902
COC119
COR50 PAC11102
COJ15
PAJ1505
PAU10AB14 PAU10AA14 PAC5202PAU10Y14 PAU10W14 PAU10V14 PAU10U14 PAU10T14 PAU10R14 PAU10P14 PAU10N14 PCOC46 AU10M14 PAU10L14 PAU10K14 PAU10J14 PAU10H14 PAU10G14 PAU10F14 PAU10E14 PAU10D14 PAU10C14 PAU10B14 PAU10A14 COC92 PAC4101
COC6 PAU11017 PAU11028 PAR1702
PAC11801 PAC3601 PAU307 PAU3038PAU3039 PAU304 PAU3041 PAU3042PAU3043PAU304 PAU3045 PAU3046PAU3047PAU3048 PAC5002 PAC5001 PAC5801 PAC15901 PAC9201PAC9202
PAJ1506
PAU10AB15 PAU10AA15 PAU10Y15 PAU10W15 PAU10V15 PAU10U15 PAU10T15 PAU10R15
PAC6002 PAU10P15 PAU10N15 PAU10M15 PAU10L15 PAU10K15 PAU10J15 PAU10H15 PAU10G15 PAU10F15 PAU10E15 PAU10D15 PAU10C15 PAU10B15 PAU10A15 PAU11018 PAU11027 PAR1701
PAL701 COC52 PAC6001 COC62 PAC5802 PAC15902 PAU11019 PAU11026
PAR1802 PAR1801 PAU10AB16 PAC102PAU10AA16 PAU10Y16 PAU10W16 PAU10V16 PAU10U16 PAU10T16 PAU10R16 PAU10P16 PAU10N16 PAU10M16 PAU10L16 PAU10K16 PAU10J16 PAU10H16 PAU10G16 PAU10F16 PAU10E16 PAU10D16 PAU10C16 PAU10B16 PAU10A16 COC41 PAU1 020 PAU102 PAU1 02 PAU1 023 PAU1024 PAU1025
PAL702 CO 1 8COC36 COR18 PAU10AB17 PAU10AA17
PAC101 PAU10Y17COC1PAU10W17PAC5102PAC5101 PAU10V17 PAU10U17 PAU10T17 PAU10R17 PAU10P17 PAU10N17COC58
PAC6202PAU10M17COC159
PAC6201PAU10L17 PAU10K17 PAU10J17 PAU10H17PAC6501PAC6502PAU10G17 PAU10F17 PAU10E17 PAU10D17 PAU10C17 PAU10B17 PAU10A17
COC65 PAC910 PAC9102
COR17
PATP301 PATP201 PATP101 COC51 PAC4102 COR24 PAR2401PAR2402 PAJ1507
COJ1 COL7 PAU10AB18 PAU10AA18 PAU10Y18 PAU10W18 PAU10V18 PAU10U18 PAU10T18 PAU10R18 PAU10P18 PAU10N18 PAU10M18 PAU10L18 PAU10K18 PAU10J18 PAU10H18 PAU10G18 PAU10F18 PAU10E18 PAU10D18 PAU10C18 PAU10B18 PAU10A18 COC91
PAC5901
COU27 PAU10AB19 PAU10AA19 PAU10Y19 PAU10W19 PAU10V19 PAU10U19 PAU10T19 PAU10R19PAC5902 PAU10P19 PAU10N19 PAU10M19 PAU10L19 PAU10K19 PAU10J19 PAU10H19 PAU10G19 PAU10F19 PAU10E19
COC64 PAU10D19PAC9801PAU10C19
PAC9802
COC98
PAU10B19 PAU10A19
PAU1306PAU1305 PAU1304 PAU1303PAU1302PAU1301
COR120
PAR2501PAR2502 PAJ1508
COTP3 COTP2COTP1 PAC6402
PAU10M20 PAU10L20 PAU10K20 PAU10J20 PAU10H20 PAU10G20PAC6401PAU10F20 PAU10E20 PAU10D20 PAU10C20 PAU10B20 PAU10A20 PAC12102 COR121
PAU2705 PAU2701 AU10R20 PAU10P20 PAU10N20 PAC6302 PAR12001PAR12002 PAJ15010
PAJ10H1 PAU2702
COU20 PAR8702 COU15
PAR8701
PAU10AB20 PAU10AA20 PAU10Y20 PAU10W20 PAU10V20 PAU10U20PAC5501 PAC5502PAU10T20 PCOC59
PAU10AB21 PAU10AA21 PAU10Y21 PAU10W21 PAU10V21 PAU10U21 PAU10T21 PAU10R21 PAU10P21 PAU10N21 PAU10M21 PAU10L21
COC63 COC67 PAU1307
PAU1308
PAU13016
PAU13015
PAC12002 COR25 PAJ150H1
COC55 PAC6102 PAC5702 PAC6301 PAU10K21PAC6701PAC6702PAU10J21 PAU10H21 PAU10G21 PAU10F21 PAU10E21 PAU10D21 PAU10C21 PAU10B21 PAU10A21 COC120 PAR12101PAR12102 PAJ15011
PAU2704 PAU2703 PAU2005 PAU2001
COR87 PAU1505 PAU1501 COC61COC57 COC121PAC12101
COR170 PAU10AB2 PAU10AA22 PAU10Y2 PAU10W2 PAU10V2 PAU10U2 PAC6101PAU10T2 COC53 PAC5701
PAU10R2 PAU10P2 PAU10N2 PAU10M2 PAU10L2 PAU10K2 PAU10J2 PAU10H22 PAU10G2 PAU10F22 PAU10E2 PAU10D22 PAU10C2 PAC9301PAU10B22 PAU10A2 PAU1309PAU13010 PAU130 PAU13012PAU13013PAU13014 PAC12001
PAU2002 PAU1502 PAC501 PAC9302
PAU2004 PAU2003 PAU1504 PAU1503 COC5 PAC6801 PAJ15012
PAU2805 PAU2801 PAR5102 PAR5101
PAU2802 COU28 PAR17002 PAC5302 PAC5301 COC4 COR152
COR151
PAU2804 PAU2803
PAR170 1
COR58 COD9
COC68 PAC6802 PAC502 COC93
COC25 PAR15202 PAR15102
COU13 COR51
COH1 PAR5802 PAC402 PAC401 PAU290A5 PAU290B5 PAU290C5 PAU290D5 PAU290E5 PAR15201 PAR15101 COH3
PAU1605 PAU1601 PAC2502
COU16 PAR5801 PAD90K PAD90A PAC2501
PAU1602 COR1 PAU290A4 PAU290B4 PAU290C4 PAU290D4 PAU290E4
PAU1604 PAU1603 PAR6701 PAU3603 PAU3602 PAU3601 PAU3905 PAU3904
PAR16801 PAU290A3 PAU290B3 PAU290C3 PAU290D3 PAU290E3
PAR6702 PAU3906 PAU3903
PAJ60F1 PAJ605 PAR16802
COR67 PAR702 PAR701 PAR102 PAR101 COU29
PAU290A2 PAU290B PAU290C2 PAU290D2 PAU290E2
COU36 COU39 PAU3907 PAU3902
PAU2103 PAU2104 PAU3604 PAU3COC175
605 PAU360 PAU3908 PAU3901
PAU2102 PAU290A1 PAU290B1 PAU290C1PAC2602PAU290D1
PAC2601 PAU290E1
COR168 COR7
PAJ604 PAU2101 PAU2105 PAU50E1 PAU50D1 PAU50C1 PAU50B1 PAC17502 PAC17501
PAU50E2 PAU50D2 PAU50C2 PAU50B2 PAU50A2
COU21
PAH101 COC26 PAH301
PAU50E3 PAU50D3 PAU50C3 PAU50B3 PAU50A3 COU5
PAJ607 PAC1402
PAU50E4 PAU50D4 PAU50C4 PAU50B4 COC14 PAU50A4
PAC1401 COJ5
PAU50E5 PAU50D5 PAU50C5 PAU50B5 PAU50A5 COTP8 PATP801
PAJ603 PAJ606 PAJ501 PAJ502 PAJ1201
PAJ1202
PAJ608 PATP701 COTP7 PATP601 COTP6 PATP401 PAJ1203
COTP4 PAJ503 PAJ504 PAJ1204
PAJ602 COH8 PAJ1205 COC37 PAC3702 PAC3701
PATP501
PAJ505 PAJ506
COTP5 PAJ1206
PAJ60F2 PAJ601 PAJ507 PAJ508 PAJ1207 PAC3802 PAU1401
COJ6 PAJ1208 COC38 PAC3801
PAU1402
PAJ509 PAJ5010 PAJ1209 PAU1403
PAH801 PAJ12010 COR20 PAU1404 COU14
PAR2002
PAR1901 PAR1902 PAR2001 PAU1405
COU2
COR19
COC102 PAC10202 PAC10201 PAU1406
PAU1408
PAU2024 PAU2025 COJ12 PAC3901
PAU2023 PAU2026 PAU1407
PAU2022 PAU2027 PAC3902
PAU2021 PAU2028 COC39
PAU2020 PAU2029
PAU2019 PAU2030
PAU2018 PAU2031
PAU2017 PAU2032
PAU2016 PAU2033
PAU2015 PAU2034
PAU2014 PAU2035 COC185 PAR16302 PAR1630 COR163 PAC10 01 COR128
PAU2013 PAU2036 PAC18502 PAC18501 PAR12801
PAJ801 PAJ802 PAU2012
PAU2011
PAU2037
PAU2038 PAU38019 PAU38018PAU38017 PAU38016 AU38015P PAU38014PAU38013PAU38012 PAU3801
COC10 PAC10 02 COD1 PAR12802 COJ18
PAU2010 PAU2039
PAU209 PAU2040 PAU38020
PAU208 PAU2041
PAU207 PAU2042
PAR1 802 PAR1 801 PAJ803 PAJ804 PAU206
PAU205
PAU2043
PAU2044
PAU38021 COU38 COC99 PAC9 02 PAC9 01 PAD103PAD102 PAD10 PAJ1801
PAU204 PAU2045
PAR9802 PAR9801 PAU203 PAU2046 PAU3801PAU3805
PAU202 PAU2047 PAU3802 PAU3803PAU3804 PAU3806 PAU3807PAU3808PAU3809 PAU3801
COR1 8
COR98 PAR11702 PAR11701 PAJ805 PAJ806 PAU201 PAU2048
COC40 PAC40 2 PAC40 1 PAD104PAD105 PAD106
COR129 PAJ1802
PAC18402 PAC18401
PAR9702 PAR9701 PAR12902
COC184 PAD1403 PAJ1803
PAR12901
PAR11602 PAR11601
COR97COR1 7 PAJ807 PAJ808 COD14 PAJ1804
COR1 6 PAR9602 PAR9601 PAD1401 PAD1402
COR96 PAR1 502 PAR1 501 PAJ809 PAJ8010
COR1 5 PAR9502 PAR9501 COC3 PAC302 PAC301
COR95 PAR11402 PAR11401 PAJ8011 PAJ8012
COR94COR1 4 PAR9402
PAR11302
PAR9401
PAR11301
PAB100 PAC702
PAJ8013 PAJ8014 PAU1201
COR1 3 PAR9302 PAR9301
COC7 PAC701 PAU1202
COR93 PAR1 202 PAR1 201 PAJ8015 PAJ8016 PAB10H1 PAU1203
COR1 2 PAR9202 PAR9201 PAR402 PAU1204 COU12
COR92 PAR1 102 PAR1 101 PAJ8017 PAJ8018 COU8 COR4 PAR401
PAU1205 PAU1208
PAU8024 PAU8025 COB1
COR1 1 PAR9102 PAR9101 PAU8023 PAU8026 COU30 PAC801 PAR202 PAU1206
PAU8022 PAU8027
COR91 PAU8021 PAU8028 PAC802 PAR201
PAR11002 PAR11001 PAJ8019 PAJ8020 PAU8020 PAU8029 PAU1207
PAU8019 PAU8030 PAU3004 PAU3003
PAU8018 PAU8031 PAU3002
PAR9002 PAR9001 PAU8017 PAU8032 COC8COR2
PAU8016 PAU8033 PAU3005 PAU3001 PAB10H2
PAU8015 PAU8034
COR90COR1 0 PAR10902 PAR10901 PAU8014 PAU8035 PAC1701
PAJ8021 PAJ8022 PAU8013 PAU8036
PAU8012 PAU8037
PAR7102 PAR7101 PAU8011 PAU8038 PAC1702
COR109
COR71 PAU8010
PAU809
PAU8039
PAU8040
PAU3104 PAU3103
COC16 PAC1601 PAC1602 COC17
PAR10802 PAR10801 PAU808 PAU8041 PAU3102 COJ2
PAJ8023 PAJ8024 PAU807 PAU8042 PAU3105 PAU3101
PAU806 PAU8043 COC15 PAC1501 PAC1502
PAU805 PAU8044
PAR4502 PAR4501 PAU804 PAU8045 PAB100
COR108 PAU803 PAU8046 COU31
COR45 PAU802 PAU8047
PAR10702 PAR10701 PAJ8025 PAJ8026 PAU801 PAU8048 COC13 PAC1301 PAC1302
COR43 PAR10602 PAR10601
COC88
COL6 COC87 PAJ2202
COL1
PAJ8027 PAJ8028 PAU9024 PAU9025
PAU9023 PAU9026 COC89 PAJ2201 PAC8801PAL601 PAL101 PAC8701 COL11
PAL1101
PAR4202 PAR4201 PAU9022 PAU9027
PAU9021 PAU9028 PAC8802PAL602 PAL102 PAC8702
COL8
PAU9019 PAU9030 PAL1102
COR42COR106 PAR10502 PAR10501 PAJ8029 PAJ8030 PAU9018
PAU9017
PAU9031
PAU9032
COLOGO1 COU37 COC83
COC82
COL9 PAU3705PAU3704PAU3703 PAU3702 PAU3701
COC94 PAC8401
PAR4102 PAR4101 PAU9015 PAU9034 PAU3706 PAU37020
PAU9014 PAU9035 PAU3707 PAU37019 PAC8402
COR105
COR41 PAR10402 PAR10401 PAJ8031 PAJ8032 PAU9013
PAU9012
PAU9036
PAU9037 COC86 PAU3708
PAU3709
PAU37018
PAU37017 PAC8502
PAU9011 PAU9038
PAR4002 PAR4001
PAU9010
PAU909
PAU9039
PAU9040
COR47 PAU37021 PAC8201PAC8301 PAC83202 PAU37010 PAU37016 PAC8501
PAU908 PAU9041 PAU3701 PAU37012PAU37013 PAU37014 PAU37015
PAU907 PAU9042 PAR4701 PAC8602PAC8601
PAR10302 PAR10301 PAU906 PAU9043 PAR4702
COR40COR104 PAJ8033 PAJ8034 PAU905
PAU904
PAU9044
PAU9045
PAC9402 PAL901 PAL801 PAC8902
PAJ1902
PAU903 PAU9046
PAR3902 PAR3901 PAU902 PAU9047 COC179 PAC9401 PAL902 PAL802 PAC8901
PAU901 PAU9048
COR39COR103 PAR10202 PAR10201 PAJ8035 PAJ8036 COU9
COSerial1 PAC17902 PAC17901 PAJ1901
COR38 PAR10102 PAR10101 PAJ8037 PAJ8038 COH5
COR37 PAR10002 PAR10001 PAJ8039 PAJ8040 PAU2504 PAU250
PAC9001 COU25 COJ19
COR10 PAC90 2 COC90
PAU2503PAU2502 PAU2501
PAR9902 PAR9901
COR99 PAJ8041 PAJ8042 PAH501

PAU2 04 PAU2 05 PAU2404 PAU2405 COR127 COR148
PAJ8043 PAJ8044 COJ8 COT5 COU22 COU24 COT2 COT1 COT6
PAU4204 PAU4205 PAR12702 PAR12701 PAR14801 PAR14802
COC144 PAU2 03 PAU2 02 PAU2 01 PAU2403 PAU2402PAU2401 PAU4104 PAU4105
PAT508 PAT507 PAT506 PAT505 PAC14401

PAT203 PAT102 PAT101 PAT603
PAU2604 PAU2605 PAU2304 PAU2305 PAU4203 PAU4202PAU4201 COU42 PAU4103PAU4102 PAU4101 COU41
PAS103 PAC14402 COU26 COT8PAT10 2 COR125 PAT201 PAT202 COR123 PAT103 PAT601
COC75PAT602
PAU2603 PAU2602 PAU2601 PAU2303 PAU2302PAU2301 COT10COU23PAT101 PAT801 PAT802 PAR12501 PAR12502 COR122
PAR12301 PAR12302
COR145
PAC7501 PAC7502
COR134 COC73 PAR14501 PAR14502
PAU40 4 PAU40 5 PAU604 PAU605 COR46 PAT10 3 COR14 PAT803 PAR12 02 PAR12201 COS2
COC180 PAR13402 PAR13401
COR138PAT501 COR135
PAT502 COR136
PAT503 PAT504COC139 PAC7301 PAC7302
PAC8102PAR4602 PAC7802 PAR1402 COJ20
PAS102 PAR17501 PAR17401 PAR17301 PAR17201 PAR17101
PAR13801 PAR13501 PAR13502COR137
PAR13602 PAR13601PAC13902 PAU40 3PAU40 2 PAU40 1 PAU603PAU602 PAU601
COU40 COU6 PAC8101PAR4601 COC81 PAC7801 PAR1401
COC78 PAC18001 PAU3 010PAU3 09 PAU308 PAU307 PAU3 06 COR124 PAS203 PAS206
PAR17502 PAR17402 PAR17302 PAR17202 PAR17102 COR140 PAR12402
PAR13802 PAU3401 PAU3408 PAR13701 PAR13702PAC13901 COT9 PAT901 COT7PAT902 PAT701 PAT702
COS1 PAU33011 PAR12401 PAJ2002 PAJ2001
PAR14001 PAU3402 PAU3407 PAR16901 PAR16701 PAR16601 PAR16501 PAR16401 PAC18002
COD5 COR175
COR174
COR173
COR172
COR171
COR141 PAU3 01PAU3 02 PAU30 PAU304 PAU3 05 PAS202 PAS205
PAF102 PAR14002 PAU3403 PAU3406 COU34 PAR16902 PAR16702 PAR16602 PAR16502 PAR16402
PAD502 PAD501 PAL501 PAL504 PAU3404 COR139
PAU3405 PAT903
PAR14101
PAS101 COC135 COR86 PAR14102
COR23
PAR13901 PAR13902
PAT703 COR22
COC45 COR166
COR169COR167 COR165
COR164 COC72 COU33
PAC80 2 PAR2302 PAC7902PAR2202 PAS201 PAS204
COC80 PAC8001 PAR2301 PAC7901PAR2201
COJ11 PAF101COL5 PAC13502 PAC13501 PAR8601 PAR8602 PAC4502COC79PAC4501 PAC7202 PAC7201

PAJ1101 COF1
COJ3 COJ7
PAL502 PAL503 PAJ301 PAJ302 PAJ303 PAJ304 PAJ305 PAJ701 PAJ702 PAJ703 PAJ704 PAJ705
COH2
PAJ110H1 PAJ110H2
PAJ30H2 PAJ306 PAJ307 PAJ308 PAJ309
PAJ30H1 PAJ70H2 PAJ706 PAJ707 PAJ708 PAJ709
PAJ70H1
COPM5
COPM6 PAS10F1 PAS10F2 COPM1
COPM3
PAJ1102 PAJ1103 PAPM650

PAH201 PAPM100
PAPM300
MEGA65 R2 SCHEMATICS
266
1 2 3 4
U_HDMI U_B15 U_POWER
HDMI.SchDoc B15.SchDoc POWER.SchDoc
U_Ethernet U_B16 U_PowerMain COPM1

PM1 COPM2
PM2 COPM3
PM3
Ethernet.SchDoc B16.SchDoc PowerMain.SchDoc
U_B34 U_VGA
B34.SchDoc VGA.SchDoc
A A
U_LED_SW_BUT U_FPGA-CFG U_EXT_HEADER
LED_SW_BUT.SchDoc FPGA-CFG.SchDoc EXT_HEADER.SchDoc FIDU-DOT - small FIDU-DOT - small FIDU-DOT - small
U_SYS_MAX10_CTRL U_FPGA-MGT U_EXP_Slot

SYS_MAX10_CTRL.SchDoc FPGA-MGT.SchDoc EXP_Slot.SchDoc COPM4
PM4 COPM5
PM5 COPM6
PM6
U_SOUND U_FPGA-PWR U_Floppy

SOUND.SchDoc FPGA-PWR.SchDoc Floppy.SchDoc
U_B13 U_JOY
B13.SchDoc JOY.SchDoc
FIDU-DOT - small FIDU-DOT - small FIDU-DOT - small
U_B14 U_KEYBOARD
B14.SchDoc KEYBOARD.SchDoc
B COSerial1 B
Serial1
Serial
Serialnumber 6,3 x 6.3mm
COS0N1
S/N1
1
PIS0N101 0R 2
PIS0N102
Serialnumber
C C
COH5 COH7 COH8 COH1 COH2 COH3
Title:
MEGA65
D D
Number: Rev.
PIH501 PIH701 PIH801 PIH10 PIH201 PIH301 A4 TE0765
Default 02
GND GND GND GND GND GND
Date: 2019-03-11 Copyright: Trenz Electronic GmbH Page1 of 23
Mount.Hole 3.2mm Mount.Hole 3.2mmMount.Hole 3.2mm Mount.Hole 3.2mm Mount.Hole 3.2mm Mount.Hole 3.2mm
Filename: TE0765.SchDoc
1 2 3 4
1 2 3 4
PMOD CONN
COD1
D1
1PID101 5
PID105 3.3V COD2 COD3
GROVE_SCL0 3PID103 D2 D3
Grove CONN NLB350L20N
B35_L2_N 1
PID201 5
PID205 B35_L5_N 1
PID301 5
PID305
A NLB350L20P 3.3V 3.3V A
GROVE_SDA0 4PID104 B35_L2_P 3
PID203 B35_L5_P 3
PID303
6PID106 2
PID102 GND NLB350L10P
B35_L1_P 4
PID204 B35_L3_P 4
PID304
WE-TVS-824013 NLB350L10N
B35_L1_N 6
PID206 2
PID202 B35_L3_N 6
PID306 2
PID302
COJ18 GND GND
J18
COR128
R128PIR12801 PIR12802 4K7 NLGrove0SCL0
GROVE_SCL0 1
PIJ1801 WE-TVS-824013 WE-TVS-824013
3.3V COR129 NLGrove0SDA0
R129PIR12901 PIR12902
4K7 GROVE_SDA0 2
PIJ1802
3
PIJ1803
3.3V COP1
4
PIJ1804 P1
GND NLB350L50N NLB350L50P
B35_L5_N 1
PIP101 7
PIP107 B35_L5_P
110990037 NLB350L30N
B35_L3_N 2
PIP102 8
PIP108
NLB350L30P
B35_L3_P
B35_L2_N 3
PIP103
9
PIP109 B35_L2_P
B35_L1_N 4
PIP104 10
PIP1010 B35_L1_P
5
PIP105 11
PIP1011
GND GND GND GND
6
PIP106 12
PIP1012
PMOD1_VCC PIC14501 PIC14601 VCC VCC PMOD1_VCC
COC145
C145 COC146
10µF 470nF
PIC14502 PIC14602
10V
B COP2 B
GND GND P2
B35_L6_P 1
PIP201
7
PIP207
B35_L4_P
B35_L6_N 2
PIP202
8
PIP208 B35_L4_N
NLB350L120P
B35_L12_P 3
PIP203 9
PIP209
NLB350L120N
B35_L12_N
NLB350L100N
B35_L10_N 4
PIP204 10
PIP2010
NLB350L100P
B35_L10_P
CPLD CONFIG 5 11
GND PIP205 GND GND PIP2011 GND
6 12
PMOD2_VCC PIC16201 PIC16301 PIP206 VCC VCC PIP2012 PMOD2_VCC
COJ17
J17 COC162
C162 COC163
CPLD_JTAG i NLM0TCK
M_TCK 1
PIJ1701 2
PIJ1702
PIC1620
10µF PIC16302 470nF
PIR15602 NLM0TDO
M_TDO 3
PIJ1703 4
PIJ1704
10V
COR156
R156 NLM0TMS
M_TMS 5 6 PIC13701 3.3V GND GND
PIJ1705 PIJ1706
4K7 7 8 COC137
C137 COD4
D4 COD11
D11
PIJ1707 PIJ1708
PIR15601 NLM0TDI
M_TDI 9
PIJ1709 10
PIJ17010 PIC13702 470nF NLB350L40N
B35_L4_N 1PID401 5
PID405 B35_L10_P 1PID1101 PID11055
NLB350L60N 3.3V 3.3V
B35_L6_N 3PID403 B35_L10_N 3PID1103
GND SMD-254-9132-14-10 GND GND
NLB350L60P
B35_L6_P 4PID404 B35_L12_P 4PID1104
NLB350L40P
B35_L4_P 6PID406 PID402
2 B35_L12_N 6PID1106 2
PID1102
GND GND
C C
WE-TVS-824013 WE-TVS-824013
COU35
U35
7
PIU3507
8
PIU3508
3.3V IN OUT1 PMOD2_VCC
PIC16401
COC164
C164 COR146
R146 NLPMOD20FLG
PMOD2_FLG 2 5
PIR14601 PIR1460210K PIU3502 FLG1 OUT2 PIU3505 PMOD1_VCC
10µF
PIC16402 COR147
R147
PIR14701 PIR1470210K
NLPMOD10FLG
PMOD1_FLG 3
PIU3503
10V NLPMOD20EN FLG2
TE0790-Base SMT PMOD2_EN 1
PIU3501
NLPMOD10EN EN1
GND PMOD1_EN 4
PIU3504
COJB1 EN2
JB1
5
PIJB105 6
PIU3506
3.3V GND
6
PIJB106
TE_JTAG i VIO PIC13801 3.3V
GND AP2196SG-13
UART COC138
NLTE0TCK
TE_TCK 4
PIJB104 TCK
3
PIJB103
NLTE0UART0RX
TE_UART_RX C138
NLTE0TDO C A NLTE0UART0TX 470nF
PIR15702 TE_TDO 8
PIJB108 TDO
7 TE_UART_TX PIC13802
COR157
R157 D B PIJB107
NLTE0TDI
TE_TDI 10
PIJB1010 F TDI
9 PIR15802
4K7 E PIJB109 R158
NLTE0TMS
TE_TMS 12
PIJB1012 H TMS
11
PIJB1011
COR158GND Title:
PIR15701 G 10K MEGA65
1
PIJB101 PIR15801
D GND GND D
GND 2
PIJB102 GND GND
H1
PIJB10H1
Number: Rev.
GND GND A4 TE0765
GND 02
Default
Filename: EXT_HEADER.SchDoc
1 2 3 4
1 2 3 4
5V COU2
U2 COU8
U8
NLC640IRQ
C64_IRQ COR37
R37PIR3701
4K7
PIR3702
31
PIU2031
7
PIU207
31
PIU8031
7
PIU807
NLC640RW COR38 3.3V VCCA VCCB 5V 3.3V VCCA VCCB 5V
C64_RW R38PIR3801 4K7
PIR3802 EXP 42
PIU2042 18
PIU2018 EXP 42
PIU8042 18
PIU8018
NLC640CLOCK COR39 VCCA VCCB VCCA VCCB
C64_CLOCK R39PIR3901 4K7
PIR3902 i EXP i EXP
NLC640IO1
C64_IO1 COR40
R40PIR4001 4K7
PIR4002
A CART i i i A
C64_GAME COR41
R41PIR4101 4K7
PIR4102
NLF0DATA0DIR
F_DATA_DIR 1
PIU201 48
PIU2048
NLF0DATA0EN
F_DATA_EN NLF0CTRL0DIR
F_CTRL_DIR 1
PIU801 48
PIU8048
NLF0CTRL0EN
F_CTRL_EN
1DIR 1OE i CART 1DIR 1OE i CART
C64_EXROM COR42
R42PIR4201
4K7
PIR4202
NLC640IO2 COR43 NLF0C640D7 CART i NLF0C640RW
C64_IO2 R43PIR4301 4K7
PIR4302 F_C64_D7 47
PIU2047 2
PIU202 C64_D7 F_C64_RW 47
PIU8047 2
PIU802 C64_RW
NLC640ROMLCOR45 NLF0C640D6 1A1 1B1 NLF0C640ROMH 1A1 1B1
C64_ROML R45PIR4501 4K7
PIR4502 F_C64_D6 46
PIU2046 3
PIU203 C64_D6 F_C64_ROMH 46
PIU8046 3
PIU803 C64_ROMH
NLC640BA COR71 DATA i NLF0C640D5 1A2 1B2 NLF0C640IO1 1A2 1B2
C64_BA R71PIR7101 4K7
PIR7102 F_C64_D5 44
PIU2044 5
PIU205 C64_D5 F_C64_IO1 44
PIU8044 5
PIU805 C64_IO1
NLC640DMA COR90 NLF0C640D4 1A3 1B3 1A3 1B3
C64_DMA R90PIR9001 4K7
PIR9002 F_C64_D4 43
PIU2043 6
PIU206 C64_D4 43
PIU8043 6
PIU806
NLC640D7 COR91 NLF0C640D3 1A4 1B4 1A4 1B4
C64_D7 R91PIR9101
4K7
PIR9102
F_C64_D3 41
PIU2041
8
PIU208
C64_D3 41
PIU8041
8
PIU808
NLC640D6 COR92 NLF0C640D2 1A5 1B5 NLF0C640IO2 1A5 1B5
C64_D6 R92PIR9201 4K7
PIR9202 F_C64_D2 40
PIU2040 9
PIU209 C64_D2 F_C64_IO2 40
PIU8040 9
PIU809 C64_IO2
NLC640D5 COR93 NLF0C640D1 1A6 1B6 NLF0C640ROML 1A6 1B6
C64_D5 R93PIR9301 4K7
PIR9302 F_C64_D1 38
PIU2038 11
PIU2011 C64_D1 F_C64_ROML 38
PIU8038 11
PIU8011 C64_ROML
NLC640D4 COR94 NLF0C640D0 1A7 1B7 NLF0C640BA 1A7 1B7
C64_D4 R94PIR9401 4K7
PIR9402 F_C64_D0 37
PIU2037 12
PIU2012 EXP C64_D0 F_C64_BA 37
PIU8037 12
PIU8012 EXP C64_BA
NLC640D3 COR95 1A8 1B8 1A8 1B8
C64_D3 R95PIR9501 4K7
PIR9502 i i
NLC640D2
C64_D2 COR96
R96PIR9601
4K7
PIR9602
NLF0LADDR0DIR
F_LADDR_DIR 24
PIU2024
25
PIU2025
NLF0ADDR0EN
F_ADDR_EN NLF0HADDR0DIR
F_HADDR_DIR 24
PIU8024
25
PIU8025
F_ADDR_EN
NLC640D1 COR97 2DIR 2OE i CART 2DIR 2OE i CART
C64_D1 R97PIR9701 4K7
PIR9702
NLC640D0
C64_D0 COR98
R98PIR9801 4K7
PIR9802
NLF0C640A7
F_C64_A7 36
PIU2036 13
PIU2013 C64_A7 NLF0C640A15
F_C64_A15 36
PIU8036 13
PIU8013 C64_A15
NLF0C640A6 2A1 2B1 NLF0C640A14 2A1 2B1
F_C64_A6 35
PIU2035 14
PIU2014 C64_A6 F_C64_A14 35
PIU8035 14
PIU8014 C64_A14
ADR i NLF0C640A5 2A2 2B2 ADR i NLF0C640A13 2A2 2B2
F_C64_A5 33
PIU2033
16
PIU2016
C64_A5 F_C64_A13 33
PIU8033
16
PIU8016
C64_A13
NLF0C640A4 2A3 2B3 NLF0C640A12 2A3 2B3
F_C64_A4 32
PIU2032
17
PIU2017
C64_A4 F_C64_A12 32
PIU8032
17
PIU8017
C64_A12
NLF0C640A3 2A4 2B4 NLF0C640A11 2A4 2B4
F_C64_A3 30
PIU2030 19
PIU2019 C64_A3 F_C64_A11 30
PIU8030 19
PIU8019 C64_A11
NLF0C640A2 2A5 2B5 NLF0C640A10 2A5 2B5
F_C64_A2 29
PIU2029 20
PIU2020 C64_A2 F_C64_A10 29
PIU8029 20
PIU8020 C64_A10
B NLF0C640A1 2A6 2B6 NLF0C640A9 2A6 2B6 B
F_C64_A1 27
PIU2027 22
PIU2022 C64_A1 F_C64_A9 27
PIU8027 22
PIU8022 C64_A9
NLF0C640A0 2A7 2B7 NLF0C640A8 2A7 2B7
F_C64_A0 26
PIU2026
23
PIU2023
C64_A0 F_C64_A8 26
PIU8026
23
PIU8023
C64_A8
2A8 2B8 2A8 2B8
3.3V COU30
U30 28
PIU2028 4
PIU204 28
PIU8028 4
PIU804
GND GND GND GND
1
PIU3001 5
PIU3005 34
PIU2034 10
PIU2010 34
PIU8034 10
PIU8010
NLC640EXROM OE VCC 3.3V GND GND GND GND
C64_EXROM 2
PIU3002 39
PIU2039 15
PIU2015 39
PIU8039 15
PIU8015
A NLF0C640EXROM GND GND GND GND
3 4
PIU3004
F_C64_EXROM 45
PIU2045
21
PIU2021
45
PIU8045
21
PIU8021
GND PIU3003 GND Y i EXP GND GND GND GND GND GND GND GND
NC7SZ126P5X SN74LVCH16T245DGV SN74LVCH16T245DGV
COJ8
J8
44 43
PIJ8043
COU9 GND PIJ8044 GND
3.3V COU31
U31 U9 42
PIJ8042
41
PIJ8041
C64_ROMH
1
PIU3101 OE VCC
5
PIU3105
31
PIU9031
7
PIU907
40
PIJ8040
39
PIJ8039
C64_RESET
NLC640GAME 3.3V 3.3V VCCA VCCB 5V 5V
C64_GAME 2
PIU3102 42
PIU9042 18
PIU9018 C64_IRQ 38
PIJ8038 37
PIJ8037 C64_NMI
A NLF0C640GAME VCCA VCCB
3 4
PIU3104 F_C64_GAME EXP C64_RW 36
PIJ8036 35
PIJ8035 C64_O2
GND PIU3103 GND Y i EXP
i C64_CLOCK 34
PIJ8034 33
PIJ8033 C64_A15
NC7SZ126P5X 1
PIU901
48
PIU9048
C64_IO1 32
PIJ8032
31
PIJ8031
C64_A14
GND 1DIR 1OE GND
C64_GAME 30
PIJ8030
29
PIJ8029
C64_A13
NLF0C640NMI
F_C64_NMI 47
PIU9047 2
PIU902 C64_NMI C64_EXROM 28
PIJ8028 27
PIJ8027 C64_A12
C CART i NLF0C640IRQ 1A1 1B1 C
F_C64_IRQ 46
PIU9046 3
PIU903 C64_IRQ C64_IO2 26
PIJ8026 25
PIJ8025 C64_A11
CART i NLF0C640DMA 1A2 1B2
5V F_C64_DMA 44
PIU9044 5
PIU905 C64_DMA C64_ROML 24
PIJ8024 23
PIJ8023 C64_A10
NLC640ROMH COR99 CART i NLFB0RIGHT 1A3 1B3 NLJB0RIGHT
C64_ROMH R99PIR9901
4K7
PIR9902
FB_RIGHT 43
PIU9043
6
PIU906
JB_RIGHT C64_BA 22
PIJ8022
21
PIJ8021
C64_A9
NLC640RESET COR100 NLFB0LEFT 1A4 1B4 NLJB0LEFT
C64_RESET R100
PIR10001
4K7
PIR10002
FB_LEFT 41
PIU9041
8
PIU908
JB_LEFT C64_DMA 20
PIJ8020
19
PIJ8019
C64_A8
NLC640NMI COR101 NLFB0DOWN 1A5 1B5 NLJB0DOWN
C64_NMI R101
PIR10101 4K7
PIR10102 FB_DOWN 40
PIU9040 9
PIU909 JB_DOWN C64_D7 18
PIJ8018 17
PIJ8017 C64_A7
NLC640O2 COR102 NLFB0FIRE 1A6 1B6 NLJB0FIRE
C64_O2 R102PIR10201 4K7
PIR10202 FB_FIRE 38
PIU9038 11
PIU9011 JB_FIRE C64_D6 16
PIJ8016 15
PIJ8015 C64_A6
NLC640A15 COR103 NLFB0UP 1A7 1B7 NLJB0UP
C64_A15 R103
PIR10301 4K7
PIR10302 FB_UP 37
PIU9037 12
PIU9012 JB_UP C64_D5 14
PIJ8014 13
PIJ8013 C64_A5
NLC640A14 COR104 1A8 1B8
C64_A14 R104
PIR10401
4K7
PIR10402
C64_D4 12
PIJ8012
11
PIJ8011
C64_A4
NLC640A13
C64_A13 COR105
R105
PIR10501
4K7
PIR10502
24
PIU9024
25
PIU9025
C64_D3 10
PIJ8010
9
PIJ809
C64_A3
NLC640A12 COR106 3.3V 2DIR 2OE GND
C64_A12 R106PIR10601
4K7
PIR10602
C64_D2 8
PIJ808
7
PIJ807
C64_A2
NLC640A11
C64_A11 COR107
R107
PIR10701 4K7
PIR10702
NLF0C640RESET
F_C64_RESET 36
PIU9036 13
PIU9013 C64_RESET C64_D1 6
PIJ806 5
PIJ805 C64_A1
NLC640A10 COR108 CART i NLF0C640CLOCK 2A1 2B1
C64_A10 R108
PIR10801
4K7
PIR10802
F_C64_CLOCK 35
PIU9035
14
PIU9014
C64_CLOCK C64_D0 4
PIJ804
3
PIJ803
C64_A0
NLC640A9 COR109 CART i NLF0C640O2 2A2 2B2
C64_A9 R109
PIR10901
4K7
PIR10902
F_C64_O2 33
PIU9033
16
PIU9016
C64_O2 2 1
PIJ801
NLC640A8 COR110 CART i NLF0SER0ATN 2A3 2B3 NLSER0ATN GND PIJ802 GND
C64_A8 R110
PIR11001
4K7
PIR11002
F_SER_ATN 32
PIU9032
17
PIU9017
SER_ATN
NLC640A7 COR111 NLF0SER0RESET 2A4 2B4 NLSER0RESET
C64_A7 R111
PIR11101 4K7
PIR11102 F_SER_RESET 30
PIU9030 19
PIU9019 SER_RESET 120-044-60
NLC640A6 COR112 NLF0MOTEB 2A5 2B5 NLMOTEB
C64_A6 R112
PIR11201
4K7
PIR11202
F_MOTEB 29
PIU9029
20
PIU9020
MOTEB
2A6 2B6
NLC640A5
C64_A5 COR113
R113
PIR11301
4K7
PIR11302
NLF0DRVSB
F_DRVSB 27
PIU9027
22
PIU9022
NLDRVSB
DRVSB Title:
NLC640A4 COR114 2A7 2B7
C64_A4 R114
PIR11401
4K7
PIR11402
26
PIU9026
23
PIU9023 MEGA65
NLC640A3 COR115 GND 2A8 2B8
C64_A3 R115
PIR11501
4K7
PIR11502
D NLC640A2 COR116 D
C64_A2 R116
PIR11601
4K7
PIR11602
28
PIU9028
4
PIU904
Number: Rev.
NLC640A1 COR117 i GND GND A4 TE0765
C64_A1 R117
PIR11701 4K7
PIR11702 34
PIU9034 10
PIU9010 02
GND GND Default
NLC640A0
C64_A0 COR118
R118
PIR11801
4K7
PIR11802
EXP 39
PIU9039
15
PIU9015
GND GND
45
PIU9045
21
PIU9021
GND GND GND GND Date: 2019-03-11 Copyright: Trenz Electronic GmbH Page3 of 23
SN74LVCH16T245DGV
Filename: EXP_Slot.SchDoc
1 2 3 4
1 2 3 4
A A
B13
i
COU1A
U1A
BANK 13 AB11
PIU10AB11
NLB4
B4
IO_L7P_T1_13 NLB2
V16
PIU10V16 AB12
PIU10AB12 B2
3.3V VCCO_13 IO_L7N_T1_13 NLVDAC0CLK
PIC5101 PIC5201 PIC5401 COC1
PIC101C1 PIC50COC50
1C50 PIC201 W13
PIU10W13 AA9
PIU10AA9 VDAC_CLK
COC51
C51 COC52
C52 COC54
C54 COC2
C2 VCCO_13 IO_L8P_T1_13 NLB6
Y10
PIU10Y10 AB10
PIU10AB10 B6
PIC5102 470nF PIC5202 470nF PIC5402 470nF PIC1024.7µF PIC50 24.7µF PIC202 47µF VCCO_13 IO_L8N_T1_13 NLB7
AA17
PIU10AA17
AA10
PIU10AA10
B7
VCCO_13 IO_L9P_T1_DQS_13 NLB3
AB14
PIU10AB14
AA11
PIU10AA11
B3
VCCO_13 IO_L9N_T1_DQS_13 NLVDAC0SYNC0N
GND V10
PIU10V10 VDAC_SYNC_N COR159 3.3V
NLR3 IO_L10P_T1_13 NLB0 NLCPLD0CLK R159
R3 Y17
PIU10Y17 W10
PIU10W10 B0 CPLD_CLK PIR15901 PIR15902 COC77
C77
B B13 i IO_0_13 IO_L10N_T1_13 NLB5 B
Y11
PIU10Y11 B5 22R PIC7701 PIC7702
IO_L11P_T1_SRCC_13 NLB1 GND
Y12
PIU10Y12
B1 1%
NLR4 IO_L11N_T1_SRCC_13 470nF
R4 Y16
PIU10Y16
W11 NLVDAC0BLANK0N
PIU10W11
VDAC_BLANK_N
B13 i NLR6 IO_L1P_T0_13 IO_L12P_T1_MRCC_13 NLHSYNC COU17
R6 AA16
PIU10AA16 W12
PIU10W12 HSYNC COR126 U17
NLR7 IO_L1N_T0_13 IO_L12N_T1_MRCC_13 NLCLOCK0FPGA0MRCC R126
R7 AB16
PIU10AB16 V13
PIU10V13 CLOCK_FPGA_MRCC PIR12601 PIR12602 3
PIU1703 4
PIU1704
NLR5 IO_L2P_T0_13 IO_L13P_T2_MRCC_13 NLVSYNC CLK VDD
R5 AB17
PIU10AB17 V14
PIU10V14 VSYNC 22R
NLG6 IO_L2N_T0_13 IO_L13N_T2_MRCC_13 NLR0
G6 AA13
PIU10AA13
U15
PIU10U15
R0 1% 2
PIU1702
1
PIU1701
NLG7 IO_L3P_T0_DQS_13 IO_L14P_T2_SRCC_13 NLR1 GND OE/ST
G7 AB13
PIU10AB13
V15
PIU10V15
R1
NLG2 IO_L3N_T0_DQS_13 IO_L14N_T2_SRCC_13 NLR2
G2 AA15
PIU10AA15 T14
PIU10T14 R2 GND
NLG3 IO_L4P_T0_13 IO_L15P_T2_DQS_13 NLVGA0SDA
G3 AB15
PIU10AB15 T15
PIU10T15 VGA_SDA SiT8008BI-73-XXS-100.000000E
NLG4 IO_L4N_T0_13 IO_L15N_T2_DQS_13 NLVGA0SCL
G4 Y13
PIU10Y13 W15
PIU10W15 VGA_SCL
G5 AA14
PIU10AA14
W16
PIU10W16
RSVD2
NLG1 IO_L5N_T0_13 IO_L16N_T2_13
G1 W14
PIU10W14
T16
PIU10T16
RSVD0
G0 Y14
PIU10Y14 U16
PIU10U16 RSVD1
IO_L6N_T0_VREF_13 IO_L17N_T2_13
XC7A100T-2FGG484C
i COU18
U18
B13 1
PIU1801
5
PIU1805
3.3V OE VCC 3.3V
HSYNC 2
PIU1802
C A NLVGA0HSync C
3
PIU1803 4
PIU1804 VGA_HSYNC
GND GND Y
COTP1 NC7SZ126P5X
NLRSVD0 TP1
RSVD0 PITP101
Testpoint 0.8mm
COTP2 COU19
U19
NLRSVD1 TP2
RSVD1 PITP201
1
PIU1901
5
PIU1905
3.3V OE VCC 3.3V
VSYNC 2
PIU1902
Testpoint 0.8mm A NLVGA0VSync
3
PIU1903 GND Y
4
PIU1904
VGA_VSYNC
GND
COTP3
TP3
NLRSVD2
RSVD2 PITP301
NC7SZ126P5X
Testpoint 0.8mm
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
1 2 3 4
1 2 3 4
A A
B14
i
COU1B
U1B
NLF0SER0RESET COR58
R58
BANK 14 AB21
PIU10AB21 F_SER_RESET PIR5802 PIR5801
3.3V IO_L10P_T1_D14_14 NLF0SER0DATA0I GND
PIC5801 PIC5901 PIC60 1 PIC6101 PIC5 0COC55
1C55 PIC570COC57
1C57 PIC5302 M14
PIU10M14 VCCO_14 IO_L10N_T1_D15_14
AB22
PIU10AB22 F_SER_DATA_I 1K
COC58
C58 COC59
C59 COC60
C60 COC61
C61 COC53
C53 P18 U20 NLF0SER0SRQ0O
F_SER_SRQ_O
PIU10P18 VCCO_14 IO_L11P_T1_SRCC_14 PIU10U20 1%
PIC5802 470nF PIC5902 470nF PIC60 2 470nF PIC6102 470nF PIC5 024.7µF PIC57024.7µF PIC5301 47µF R15
PIU10R15
V20
PIU10V20
VCCO_14 IO_L11N_T1_SRCC_14 NLFB0UP
T22
PIU10T22 W19
PIU10W19 FB_UP
VCCO_14 IO_L12P_T1_MRCC_14 NLF0C640D6
GND U19
PIU10U19 W20
PIU10W20 F_C64_D6
VCCO_14 IO_L12N_T1_MRCC_14 NLF0SER0CLK0I
Y20
PIU10Y20 Y18
PIU10Y18 F_SER_CLK_I
VCCO_14 IO_L13P_T2_MRCC_14 NLF0SER0CLK0O
Y19
PIU10Y19
F_SER_CLK_O
NLF0C640D2 IO_L13N_T2_MRCC_14 NLF0C640D5
F_C64_D2 P20
PIU10P20
V18
PIU10V18
F_C64_D5
B14 i IO_0_14 IO_L14P_T2_SRCC_14 NLCEC0CLK
V19
PIU10V19 CEC_CLK
NLF0C640IO1 IO_L14N_T2_SRCC_14 NLF0C640CLOCK
F_C64_IO1 N15
PIU10N15 AA19
PIU10AA19 F_C64_CLOCK
B B14 i IO_25_14 IO_L15P_T2_DQS_RDWR_B_14 NLF0SER0SRQ0EN B
AB20
PIU10AB20 F_SER_SRQ_EN
NLSPI0DQO IO_L15N_T2_DQS_DOUT_CSO_B_14 NLF0C640O2
SPI-DQO P22
PIU10P22
V17
PIU10V17
F_C64_O2
NLSPI0DQ1 IO_L1P_T0_D00_MOSI_14 IO_L16P_T2_CSI_B_14 NLF0C640NMI
SPI-DQ1 R22
PIU10R22
W17
PIU10W17
F_C64_NMI
NLSPI0DQ2 IO_L1N_T0_D01_DIN_14 IO_L16N_T2_A15_D31_14 NLF0SER0SRQ0I
SPI-DQ2 P21
PIU10P21 AA18
PIU10AA18 F_SER_SRQ_I
NLSPI0DQ3 IO_L2P_T0_D02_14 IO_L17P_T2_A14_D30_14 NLF0C640ROML
SPI-DQ3 R21
PIU10R21 AB18
PIU10AB18 F_C64_ROML
IO_L2N_T0_D03_14 IO_L17N_T2_A13_D29_14 NLF0CTRL0DIR
ULED U22
PIU10U22 U17
PIU10U17 F_CTRL_DIR
NLF0DATA0DIR IO_L3P_T0_DQS_PUDC_B_14 IO_L18P_T2_A12_D28_14 NLF0C640D4
F_DATA_DIR V22
PIU10V22
U18
PIU10U18
F_C64_D4
IO_L3N_T0_DQS_EMCCLK_14 IO_L18N_T2_A11_D27_14 NLF0C640IRQ
T21
PIU10T21
P14
PIU10P14
F_C64_IRQ
NLF0DATA0EN IO_L4P_T0_D04_14 IO_L19P_T3_A10_D26_14 NLETH0LED2
F_DATA_EN U21
PIU10U21 R14
PIU10R14 ETH_LED2
IO_L4N_T0_D05_14 IO_L19N_T3_A09_D25_VREF_14 NLF0C640RW
P19
PIU10P19 R18
PIU10R18 F_C64_RW
NLF0C640EXROM IO_L5P_T0_D06_14 IO_L20P_T3_A08_D24_14 NLF0C640ROMH
F_C64_EXROM R19
PIU10R19 T18
PIU10T18 F_C64_ROMH
NLSPI0CS IO_L5N_T0_D07_14 IO_L20N_T3_A07_D23_14 NLF0SER0ATN
SPI-CS T19
PIU10T19
N17
PIU10N17
F_SER_ATN
IO_L6P_T0_FCS_B_14 IO_L21P_T3_DQS_14 NLFB0DOWN
T20
PIU10T20
P17
PIU10P17
FB_DOWN
NLF0C640D7 IO_L6N_T0_D08_VREF_14 IO_L21N_T3_DQS_A06_D22_14 NLF0C640DMA
F_C64_D7 W21
PIU10W21 P15
PIU10P15 F_C64_DMA
NLF0C640GAME IO_L7P_T1_D09_14 IO_L22P_T3_A05_D21_14 NLF0C640D3
F_C64_GAME W22
PIU10W22 R16
PIU10R16 F_C64_D3
NLF0C640IO2 IO_L7N_T1_D10_14 IO_L22N_T3_A04_D20_14 NLF0C640BA
F_C64_IO2 AA20
PIU10AA20 N13
PIU10N13 F_C64_BA
NLF0SER0CLK0EN IO_L8P_T1_D11_14 IO_L23P_T3_A03_D19_14 NLF0C640RESET
F_SER_CLK_EN AA21
PIU10AA21
N14
PIU10N14
F_C64_RESET
B14 i NLF0SER0DATA0EN IO_L8N_T1_D12_14 IO_L23N_T3_A02_D18_14 NLF0C640D0
F_SER_DATA_EN Y21
PIU10Y21
P16
PIU10P16
F_C64_D0
NLF0SER0DATA0O IO_L9P_T1_DQS_14 IO_L24P_T3_A01_D17_14 NLF0C640D1
F_SER_DATA_O Y22PIU10Y22 R17
PIU10R17 F_C64_D1
C IO_L9N_T1_DQS_D13_14 IO_L24N_T3_A00_D16_14 C
XC7A100T-2FGG484C
COD9
D9
NLULED
ULED
COR67
R67
PID90A PID90K PIR6701 PIR6702 GND
240R 1%
LED Red LTST-C191KRKT
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
1 2 3 4
1 2 3 4
B15
i
COU1C
U1C
3.3V BANK 15
G19
PIU10G19 M21
PIU10M21
PIC6401 PIC6501 PIC6 01 PIC6701 PIC401 VCCO_15 IO_L10P_T1_AD11P_15 NLF0LADDR0DIR
PIC6201COC62
C62 COC63
PIC6301C63 H16
PIU10H16 L21
PIU10L21 F_LADDR_DIR
COC64
C64 COC65
C65 COC66
C66 COC67
C67 COC4
C4 VCCO_15 IO_L10N_T1_AD11N_15 NLF0C640A5
J13
PIU10J13 J20
PIU10J20 F_C64_A5
A PIC6402 470nF PIC6502 470nF PIC6 02 470nF PIC6702 470nF PIC62024.7µF PIC63024.7µF PIC402 47µF VCCO_15 IO_L11P_T1_SRCC_15 NLF0C640A6 A
K20
PIU10K20 J21
PIU10J21 F_C64_A6
VCCO_15 IO_L11N_T1_SRCC_15 NLRSVD0MRCC COTP4
L17
PIU10L17
J19
PIU10J19
RSVD_MRCC PITP401
TP4
VCCO_15 IO_L12P_T1_MRCC_15 NLF0C640A12
GND N21
PIU10N21 H19
PIU10H19 F_C64_A12
VCCO_15 IO_L12N_T1_MRCC_15 NLF0C640A1
K18
PIU10K18 F_C64_A1
IO_L13P_T2_MRCC_15 NLF0C640A0
K19
PIU10K19 F_C64_A0
IO_L13N_T2_MRCC_15 NLF0ADDR0EN
J16
PIU10J16 L19
PIU10L19 F_ADDR_EN
IO_0_15 IO_L14P_T2_SRCC_15 NLF0C640A4
L20
PIU10L20
F_C64_A4
B15 i IO_L14N_T2_SRCC_15 NLF0C640A14
M17
PIU10M17 N22
PIU10N22 F_C64_A14
IO_25_15 IO_L15P_T2_DQS_15 NLF0C640A3
M22
PIU10M22 F_C64_A3
IO_L15N_T2_DQS_ADV_B_15
AD0_P H13
PIU10H13 M18
PIU10M18
IO_L1P_T0_AD0P_15 IO_L16P_T2_A28_15 NLF0HADDR0DIR
AD0_N G13
PIU10G13 L18
PIU10L18 F_HADDR_DIR
IO_L1N_T0_AD0N_15 IO_L16N_T2_A27_15
AD8_P G15
PIU10G15
N18
PIU10N18
IO_L2P_T0_AD8P_15 IO_L17P_T2_A26_15 COTP6
AD8_N G16
PIU10G16 N19
NLAD10P IO_L2N_T0_AD8N_15 IO_L17N_T2_A25_15 COTP7
AD1_P J14
PIU10J14 N20
NLAD10N IO_L3P_T0_DQS_AD1P_15 IO_L18P_T2_A24_15 NLF0C640A13
AD1_N H14
PIU10H14 M20
PIU10M20 F_C64_A13
NLF0DRVSB IO_L3N_T0_DQS_AD1N_15 IO_L18N_T2_A23_15
F_DRVSB G17
PIU10G17
K13
PIU10K13
NLF0CTRL0EN IO_L4P_T0_15 IO_L19P_T3_A22_15
F_CTRL_EN G18
PIU10G18
K14
PIU10K14
NLF0C640A11 IO_L4N_T0_15 IO_L19N_T3_A21_VREF_15 NLFPGA0RESET0N
F_C64_A11 J15
PIU10J15 M13
PIU10M13 FPGA_RESET_N
NLF0MOTEB IO_L5P_T0_AD9P_15 IO_L20P_T3_A20_15 NLDBG0UART0TX
F_MOTEB H15
PIU10H15 L13
PIU10L13 DBG_UART_TX
B NLF0C640A8 IO_L5N_T0_AD9N_15 IO_L20N_T3_A19_15 COTP5 B
F_C64_A8 H17
PIU10H17 K17
PIU10K17 PITP501 TP5
NLF0C640A15 IO_L6P_T0_15 IO_L21P_T3_DQS_15
F_C64_A15 H18
PIU10H18
J17
PIU10J17
NLAD20P IO_L6N_T0_VREF_15 IO_L21N_T3_DQS_A18_15 NLDBG0UART0RX
AD2_P J22
PIU10J22
L14
PIU10L14
DBG_UART_RX
NLAD20N IO_L7P_T1_AD2P_15 IO_L22P_T3_A17_15
AD2_N H22
PIU10H22 L15
PIU10L15
NLF0C640A9 IO_L7N_T1_AD2N_15 IO_L22N_T3_A16_15 NLFPGA0TX GND
F_C64_A9 H20
PIU10H20 L16
PIU10L16 FPGA_TX
NLF0C640A10 IO_L8P_T1_AD10P_15 IO_L23P_T3_FOE_B_15 NLFPGA0RX
F_C64_A10 G20
PIU10G20 K16
PIU10K16 FPGA_RX
NLF0C640A2 IO_L8N_T1_AD10N_15 IO_L23N_T3_FWE_B_15 NLCT0HPD
F_C64_A2 K21
PIU10K21
M15
PIU10M15
CT_HPD
NLF0C640A7 IO_L9P_T1_DQS_AD3P_15 IO_L24P_T3_RS1_15
F_C64_A7 K22
PIU10K22
M16
PIU10M16
IO_L9N_T1_DQS_AD3N_15 IO_L24N_T3_RS0_15
XC7A100T-2FGG484C
i
B15
C C
NLJA0AX
JA_AX
COR73
R73 NLAD00P
AD0_P NLJB0AX
JB_AX
COR74
R74 AD1_P
PIR7301 PIR7302 PIR7401 PIR7402
47K
PIR7501 PIC130 2 47K
PIR7601 PIC13 02
COR75
R75 COC130
C130 COR76
R76 COC131
C131
1% 1%
10K PIC130 1 33nF 10K PIC13 01 33nF
COR77
R77 PIR7502 1% NLAD00N
AD0_N
COR78
R78 PIR7602 1% AD1_N
GND PIR7702 PIR7701 GND PIR7802 PIR7801
10K 10K
1% 1%
NLJA0AY
JA_AY
COR79
R79 NLAD80P
AD8_P NLJB0AY
JB_AY
COR80
R80 AD2_P
PIR7901 PIR7902 PIR8001 PIR8002
47K
PIR8101 PIC1320 47K
PIR8201 PIC13 02
COR81
R81 COC132
C132 COR82
R82 COC133
C133
1% 1%
10K PIC13201 33nF 10K PIC13 01 33nF
COR83
R83 PIR8102 1% NLAD80N
AD8_N
COR84
R84 PIR8202 1% AD2_N
GND PIR8302 PIR8301 GND PIR8402 PIR8401
10K 10K Title:
1% 1% MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
1 2 3 4
1 2 3 4
COU1D
U1D
BANK 16
NLKB0IO2 i B16
A17
PIU10A17 A13
PIU10A13 KB_IO2
3.3V PIC9101 PIC9201 PIC9301 PIC9801 PIC501 VCCO_16 IO_L10P_T1_16 NLKB0IO1
PIC680COC68
1C68 PIC90COC90
1C90 B14
PIU10B14 A14
PIU10A14 KB_IO1
COC91
C91 COC92
C92 COC93
C93 COC98
C98 COC5
C5 VCCO_16 IO_L10N_T1_16 NLSD20CLK
C21
PIU10C21 B17
PIU10B17 SD2_CLK
A PIC9102 470nF PIC9202 470nF PIC9302 470nF PIC9802 470nF PIC68024.7µF PIC90 24.7µF PIC502 47µF VCCO_16 IO_L11P_T1_SRCC_16 NLSD20D0 A
D18
PIU10D18 B18
PIU10B18 SD2_D0
VCCO_16 IO_L11N_T1_SRCC_16 NLSD20CD
E15
PIU10E15
D17
PIU10D17
SD2_CD
VCCO_16 IO_L12P_T1_MRCC_16 NLSD20WP
GND F22
PIU10F22 C17
PIU10C17 SD2_WP
VCCO_16 IO_L12N_T1_MRCC_16 NLSD20D1
C18
PIU10C18 SD2_D1
IO_L13P_T2_MRCC_16 NLSD20D2
C19
PIU10C19 SD2_D2
NLFB0FIRE IO_L13N_T2_MRCC_16
FB_FIRE F15
PIU10F15 E19
PIU10E19
IO_0_16 IO_L14P_T2_SRCC_16
D19
PIU10D19
NLFB0LEFT IO_L14N_T2_SRCC_16 NLSPEAKER0MUTE0N
FB_LEFT F21
PIU10F21 F18
PIU10F18 SPEAKER_MUTE_N
IO_25_16 IO_L15P_T2_DQS_16
E18
PIU10E18
NLFA0RIGHT IO_L15N_T2_DQS_16
FA_RIGHT F13
PIU10F13 B20
PIU10B20 DQ4
NLFA0LEFT IO_L1P_T0_16 IO_L16P_T2_16
FA_LEFT F14
PIU10F14 A20
PIU10A20 DQ3
NLFA0DOWN IO_L1N_T0_16 IO_L16N_T2_16
FA_DOWN F16
PIU10F16
A18
PIU10A18
NLFA0FIRE IO_L2P_T0_16 IO_L17P_T2_16
FA_FIRE E17
PIU10E17 A19
PIU10A19 DQ5
NLFA0UP IO_L2N_T0_16 IO_L17N_T2_16
FA_UP C14
PIU10C14 F19
PIU10F19
NLFB0RIGHT IO_L3P_T0_DQS_16 IO_L18P_T2_16
FB_RIGHT C15
PIU10C15 F20
PIU10F20
NLKB0TCK IO_L3N_T0_DQS_16 IO_L18N_T2_16 COTP8
KB_TCK E13
PIU10E13
D20
PIU10D20 PITP801
TP8
NLKB0TDO IO_L4P_T0_16 IO_L19P_T3_16
KB_TDO E14
PIU10E14
C20
PIU10C20
DQ2
NLPWM0SPEAKER IO_L4N_T0_16 IO_L19N_T3_VREF_16
PWM_SPEAKER E16
PIU10E16 C22
PIU10C22 CS0
IO_L5P_T0_16 IO_L20P_T3_16
3.3V D16
PIU10D16 B22
PIU10B22 H_RES
B COU39 NLKB0TMS IO_L5N_T0_16 IO_L20N_T3_16 B
U39 KB_TMS D14
PIU10D14 B21
PIU10B21 RWDS
NLKB0TDI IO_L6P_T0_16 IO_L21P_T3_DQS_16
1
PIU3901
8
PIU3908
KB_TDI D15
PIU10D15
A21
PIU10A21
DQ0
GND A0 VCC NLFPGA0SDA NLSD20D3 IO_L6N_T0_VREF_16 IO_L21N_T3_DQS_16
2
PIU3902 A1 SDA
5
PIU3905
FPGA_SDA SD2_D3 B15
PIU10B15
E22
PIU10E22
DQ7
NLFPGA0SCL NLSD20CMD IO_L7P_T1_16 IO_L22P_T3_16
3
PIU3903 6
PIU3906 FPGA_SCL SD2_CMD B16
PIU10B16 D22
PIU10D22 H_CLK
3.3V A2 SCL NLKB0IO3 IO_L7N_T1_16 IO_L22N_T3_16
7
PIU3907 4
PIU3904 KB_IO3 C13
PIU10C13 E21
PIU10E21 DQ6
WP VSS GND B16 i NLKB0JTAGEN IO_L8P_T1_16 IO_L23P_T3_16
KB_JTAGEN B13
PIU10B13 D21
PIU10D21 DQ1
IO_L8N_T1_16 IO_L23N_T3_16 NLGrove0SCL0
GND 24LC128-I/ST FPGA_SCL A15
PIU10A15
G21
PIU10G21
GROVE_SCL0
IO_L9P_T1_DQS_16 IO_L24P_T3_16 NLGrove0SDA0
FPGA_SDA A16
PIU10A16
G22
PIU10G22
GROVE_SDA0
I2C addr: 0x54 IO_L9N_T1_DQS_16 IO_L24N_T3_16
XC7A100T-2FGG484C
3.3V
3.3V COU36
U36 COU38
U38
6
PIU3606 1
PIU3601 FPGA_SCL COR151
R151PIR15101 PIR15102 4K7 NLX2 1
X2PIU3801 20 NLX1
X1
PIU38020
VCC SCL X2 X1
PIC17501 5
PIU3605 2
PIU3602 3V 2
PIU3802 19
PIU38019
COC175
C175 A0 VSS GND COR152 COD14 X2 X1
4
PIU3604 3
PIU3603 FPGA_SDA R152PIR15201 PIR15202 4K7 D14 3
PIU3803 18
PIU38018
PIC17502 470nF A1 SDA COB1 X2 X1
B1 4
PIU3804
17
PIU38017
X2 X1
GND 24AA025E48T-I/OT PID1401
5
PIU3805
16
PIU38016
X2 X1
GND 3.3V
C C
I2C addr: 0x50 -
PIB100 +
PIB100 PID1403 7
PIU3807 14
PIU38014
VBAT VDD
PIC18401 PIR16302 PIC18501
COU29
U29 GND COC184
C184
6 COR163
R163 COC185
C185
PID1402 PIU3806 NC
B1
PIU290B1
B4
PIU290B4
PIC18402 9
470nF PIU3809 4K7 470nF
PIC18502
NLH0CLK CK VCC 3.3V NC 6.3V
H_CLK B2
PIU290B2 D1
PIU290D1 Batteriehalter CR1220 10
6.3V PIU38010 13
PIU38013 PIR16301
CK VCCQ NC IRQ/FOUT
E4
PIU290E4 BAT54C GND 15
PIU38015 GND
VCCQ NC
21
PIU38021 12
PIU38012 FPGA_SCL
NLH0RES NC SCL
A4
PIU290A4
H_RES
NLRWDS RESET
RWDS C3
PIU290C3
8
PIU3808
11
PIU38011
FPGA_SDA
RWDS NLCS0 GND SDA
A3
PIU290A3
CS0
CS
A2
PIU290A2 GND ISL12020MIRZ
RFU
A5
PIU290A5
NLDQ0 RFU
DQ0 D3
PIU290D3
C2
PIU290C2
I2C addr: 0x6F for RTC
NLDQ1 DQ0 RFU
DQ1 D2
PIU290D2
B5
PIU290B5
NLDQ2 DQ1 RFU
DQ2 C4
PIU290C4 C5
PIU290C5
I2C addr: 0x57 for SRAM
NLDQ3 DQ2 RFU
DQ3 D4
PIU290D4
3.3V
DQ3
NLDQ4
DQ4 D5
PIU290D5
B3 PIU290B3
Title:
NLDQ5 DQ4 VSS PIC2501 PIC2601
DQ5 E3
PIU290E3
A1 MEGA65
NLDQ6 DQ5 NC/VSS PIU290A1 COC25
C25 COC26
C26
DQ6 E2
PIU290E2
C1
D NLDQ7 DQ6 VSSQ PIU290C1 D
DQ7 E1
PIU290E1
E5 PIC2502 470nF PIC2602 470nF Number: Rev.
DQ7 VSSQ PIU290E5 A4 TE0765
Default 02
IS66WVH8M8BLL-100B1LI GND GND
GND
1 2 3 4
1 2 3 4
3.3V
3.3V 1
PIC120COC12 PIC15901COC159 PIC16 01 PIC16701 PIC16801 PIC16901 PIC160 1COC160 PIC16 COC161
C12 C159 C160 01C161
COC166
C166 COC167
C167 COC168
C168 COC169
C169
2
PIC1204.7µF PIC159024.7µF PIC16 02 470nF PIC16702 470nF P IC16 802 470nF PI C16 902 470nF PIC160 24.7µF PIC16 024.7µF
B35
A A
GND GND i
COU1E
COU1F
U1E U1F
BANK 34 BANK 35
R5 AA5 NLHDMI0D31
HDMI_D31 C1 J5 NLB350L100P
B35_L10_P
3.3V PIU10R5 VCCO_34 IO_L10P_T1_34 PIU10AA5 3.3V PIU10C1 VCCO_35 IO_L10P_T1_AD15P_35 PIU10J5
T2
PIU10T2 AB5
PIU10AB5
NLHDMI0D32
HDMI_D32 F2
PIU10F2 H5
PIU10H5
NLB350L100N
B35_L10_N
VCCO_34 IO_L10N_T1_34 NLHDMI0D29 VCCO_35 IO_L10N_T1_AD15N_35 NLSD0D1
V6
PIU10V6
Y4
PIU10Y4 HDMI_D29 H6
PIU10H6
H3
PIU10H3
SD_D1
VCCO_34 IO_L11P_T1_SRCC_34 NLHDMI0D30 VCCO_35 IO_L11P_T1_SRCC_35
W3
PIU10W3 AA4
PIU10AA4 HDMI_D30 J3
PIU10J3 G3
PIU10G3
VCCO_34 IO_L11N_T1_SRCC_34 NLHDMI0D10 VCCO_35 IO_L11N_T1_SRCC_35 NLB350L120P
AA7
PIU10AA7 V4
PIU10V4 HDMI_D10 M4
PIU10M4 H4
PIU10H4 B35_L12_P
VCCO_34 IO_L12P_T1_MRCC_34 NLHDMI0D18 VCCO_35 IO_L12P_T1_MRCC_35 NLB350L120N
AB4
PIU10AB4 W4
PIU10W4 HDMI_D18 N1
PIU10N1 G4
PIU10G4 B35_L12_N
VCCO_34 IO_L12N_T1_MRCC_34 NLHDMI0HS VCCO_35 IO_L12N_T1_MRCC_35 NLETH0CRS0DV
R4
PIU10R4 HDMI_HS K4
PIU10K4 ETH_CRS_DV
IO_L13P_T2_MRCC_34 NLHDMI0D1 IO_L13P_T2_MRCC_35 NLETH0TX0EN
T4
PIU10T4 HDMI_D1 J4
PIU10J4
ETH_TX_EN
NLHDMI0SCL IO_L13N_T2_MRCC_34 NLHDMI0D0 NLPWM0R IO_L13N_T2_MRCC_35 NLETH0TX0D0
HDMI_SCL T3
PIU10T3 T5
PIU10T5 HDMI_D0 PWM_R F4
PIU10F4 L3
PIU10L3 ETH_TX_D0
IO_0_34 IO_L14P_T2_SRCC_34 NLHDMI0D6 IO_0_35 IO_L14P_T2_SRCC_35 NLETH0TX0D1
U5
PIU10U5 HDMI_D6 K3
PIU10K3 ETH_TX_D1
NLHDMI0SDA IO_L14N_T2_SRCC_34 NLHDMI0D23 NLPWM0L IO_L14N_T2_SRCC_35 NLF0SIDE1
HDMI_SDA U7
PIU10U7 W6
PIU10W6 HDMI_D23 PWM_L L6
PIU10L6 M1
PIU10M1 F_SIDE1
IO_25_34 IO_L15P_T2_DQS_34 NLHDMI0D19 IO_25_35 IO_L15P_T2_DQS_35 NLETH0RX0D1
W5
PIU10W5
HDMI_D19 L1
PIU10L1
ETH_RX_D1
NLHDMI0D3 IO_L15N_T2_DQS_34 NLHDMI0D7 NLB350L10P IO_L15N_T2_DQS_35 NLF0STEP
HDMI_D3 T1
PIU10T1
U6
PIU10U6 HDMI_D7 B35_L1_P B1
PIU10B1
M3
PIU10M3
F_STEP
NLHDMI0D5 IO_L1P_T0_34 IO_L16P_T2_34 NLHDMI0D13 NLB350L10N IO_L1P_T0_AD4P_35 IO_L16P_T2_35 NLF0INDEX
HDMI_D5 U1
PIU10U1 V5
PIU10V5 HDMI_D13 B35_L1_N A1
PIU10A1 M2
PIU10M2 F_INDEX
NLHDMI0D8 IO_L1N_T0_34 IO_L16N_T2_34 NLHDMI0VS NLB350L20P IO_L1N_T0_AD4N_35 IO_L16N_T2_35 NLETH0RST
HDMI_D8 U2
PIU10U2 R6
PIU10R6 HDMI_VS B35_L2_P C2
PIU10C2 K6
PIU10K6 ETH-RST
B NLHDMI0D11 IO_L2P_T0_34 IO_L17P_T2_34 NLHDMI0D4 NLB350L20N IO_L2P_T0_AD12P_35 IO_L17P_T2_35 NLETH0MDC B
HDMI_D11 V2
PIU10V2 T6
PIU10T6 HDMI_D4 B35_L2_N B2
PIU10B2 J6
PIU10J6 ETH_MDC
NLHDMI0D2 IO_L2N_T0_34 IO_L17N_T2_34 NLHDMI0D33 NLB350L30P IO_L2N_T0_AD12N_35 IO_L17N_T2_35 NLETH0MDIO
HDMI_D2 R3
PIU10R3
Y6
PIU10Y6
HDMI_D33 B35_L3_P E1
PIU10E1
L5
PIU10L5
ETH_MDIO
NLHDMI0DE IO_L3P_T0_DQS_34 IO_L18P_T2_34 NLHDMI0D34 NLB350L30N IO_L3P_T0_DQS_AD5P_35 IO_L18P_T2_35 NLETH0CLK
HDMI_DE R2
PIU10R2
AA6
PIU10AA6 HDMI_D34 B35_L3_N D1
PIU10D1
L4
PIU10L4
ETH_CLK
NLHDMI0D15 IO_L3N_T0_DQS_34 IO_L18N_T2_34 NLHDMI0D20 NLB350L40P IO_L3N_T0_DQS_AD5N_35 IO_L18N_T2_35 NLF0WDATE
HDMI_D15 W2
PIU10W2 V7
PIU10V7 HDMI_D20 B35_L4_P E2
PIU10E2 N4
PIU10N4 F_WDATE
NLHDMI0CLK IO_L4P_T0_34 IO_L19P_T3_34 NLHDMI0D25 NLB350L40N IO_L4P_T0_35 IO_L19P_T3_35 NLF0WGATE
HDMI_CLK Y2
PIU10Y2 W7
PIU10W7 HDMI_D25 B35_L4_N D2
PIU10D2 N3
PIU10N3 F_WGATE
NLHDMI0D14 IO_L4N_T0_34 IO_L19N_T3_VREF_34 NLSCL0A NLB350L50P IO_L4N_T0_35 IO_L19N_T3_VREF_35 NLF0DSCKCHG
HDMI_D14 W1
PIU10W1 AB7
PIU10AB7 SCL_A B35_L5_P G1
PIU10G1 R1
PIU10R1 F_DSCKCHG
NLHDMI0D16 IO_L5P_T0_34 IO_L20P_T3_34 NLHDMI0D35 NLB350L50N IO_L5P_T0_AD13P_35 IO_L20P_T3_35 NLF0RDATA1
HDMI_D16 Y1
PIU10Y1
AB6
PIU10AB6
HDMI_D35 B35_L5_N F1
PIU10F1
P1
PIU10P1
F_RDATA1
NLHDMI0D9
IO_L5N_T0_34 IO_L20N_T3_34 NLSDA0A NLB350L60P
IO_L5N_T0_AD13N_35 IO_L20N_T3_35 NLF0DIR
HDMI_D9 U3
PIU10U3
V9
PIU10V9 SDA_A B35_L6_P F3
PIU10F3
P5
PIU10P5
F_DIR
NLHDMI0D12 IO_L6P_T0_34 IO_L21P_T3_DQS_34 NLHDMI0D21 NLB350L60N IO_L6P_T0_35 IO_L21P_T3_DQS_35 NLETH0RX0D0
HDMI_D12 V3
PIU10V3 V8
PIU10V8 HDMI_D21 B35_L6_N E3
PIU10E3 P4
PIU10P4 ETH_RX_D0
NLHDMI0SPDIF IO_L6N_T0_VREF_34 IO_L21N_T3_DQS_34 NLHDMI0SPDIFOUT NLSD0CD IO_L6N_T0_VREF_35 IO_L21N_T3_DQS_35 NLF0WPT
HDMI_SPDIF AA1
PIU10AA1 AA8
PIU10AA8 HDMI_SPDIFOUT SD_CD K1
PIU10K1 P2
PIU10P2 F_WPT
NLHDMI0D22 IO_L7P_T1_34 IO_L22P_T3_34 NLLS0OE NLSD0D2 IO_L7P_T1_AD6P_35 IO_L22P_T3_35 NLF0TRCK0
HDMI_D22 AB1
PIU10AB1 AB8
PIU10AB8 LS_OE SD_D2 J1
PIU10J1 N2
PIU10N2 F_TRCK0
NLHDMI0D28 IO_L7N_T1_34 IO_L22N_T3_34 NLHPD0A NLSD0D0 IO_L7N_T1_AD6N_35 IO_L22N_T3_35 NLETH0RXER
HDMI_D28 AB3
PIU10AB3
Y8
PIU10Y8
HPD_A SD_D0 H2
PIU10H2
M6
PIU10M6
ETH_RXER
NLHDMI0D24 IO_L8P_T1_34 IO_L23P_T3_34 NLHDMI0D27 NLSD0CLK IO_L8P_T1_AD14P_35 IO_L23P_T3_35 NLF0MOTEA
HDMI_D24 AB2
PIU10AB2
Y7
PIU10Y7 HDMI_D27 SD_CLK G2
PIU10G2
M5
PIU10M5
F_MOTEA
NLHDMI0D17 IO_L8N_T1_34 IO_L23N_T3_34 NLCEC0A NLSD0D3 IO_L8N_T1_AD14N_35 IO_L23N_T3_35 NLF0REDWC
HDMI_D17 Y3
PIU10Y3 W9
PIU10W9 CEC_A SD_D3 K2
PIU10K2 P6
PIU10P6 F_REDWC
NLHDMI0D26 IO_L9P_T1_DQS_34 IO_L24P_T3_34 NLHDMI0INT NLSD0CMD IO_L9P_T1_DQS_AD7P_35 IO_L24P_T3_35 NLF0DRVSA
HDMI_D26 AA3
PIU10AA3 Y9
PIU10Y9 HDMI_INT SD_CMD J2
PIU10J2 N5
PIU10N5 F_DRVSA
IO_L9N_T1_DQS_34 IO_L24N_T3_34 IO_L9N_T1_DQS_AD7N_35 IO_L24N_T3_35
XC7A100T-2FGG484C XC7A100T-2FGG484C
i i i
B34 B34 B35
C C
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
1 2 3 4
1 2 3 4
A A
3.3V
COU1G
U1G
BANK0
COC170
C170 F12 PIU10F12 K10
PIU10K10
VCCO_0 VCCADC_0 AVCC
GND PIC17001 PIC17002 T12
PIU10T12 VCCO_0
M10
PIU10M10
4.7µF E12 VREFP_0 AGND
PIU10E12 L9
PIU10L9
GND VCCBATT_0 VREFN_0 AGND
SPI-SCK L12 L10 NLV0P
V_P PIC12 01
PIU10L12 CCLK_0 VP_0 PIU10L10
M9 NLV0N
V_N COC122
C122
VN_0 PIU10M9
3.3V
U11
PIU10U11 M0_0
PIC12 02 10nF
3.3V BOOTMODE = MASTER SPI U10
PIU10U10 M1_0 N10
PIU10N10
16V
DXP_0 X7R
CFG U9
PIU10U9 N9
PIU10N9
GND M2_0 DXN_0
PIR6801 1%
COR3
R3 i
COR68
R68 NLFPGA0DONE
FPGA_DONE G11 K9
3.3V PIR301 PIR302 PIU10G11 DONE_0 GNDADC_0 PIU10K9 AGND
4K87
1K
FPGA_PROG_B PIR6802 1% NLFPGA0PROG0B
FPGA_PROG_B N12
PIU10N12 PROGRAM_B_0
B i B
U8
PIU10U8
3.3V CFGBVS_0
CFG
NLFPGA0TDI
FPGA_TDI R13
PIU10R13 TDI_0
NLFPGA0TDO
FPGA_TDO U13
PIU10U13 TDO_0
FPGA_JTAG i NLFPGA0TCK
FPGA_TCK V12
PIU10V12 TCK_0
NLFPGA0TMS
FPGA_TMS T13
PIU10T13 TMS_0
COR8
R8 NLFPGA0INIT
PIR802 PIR801 FPGA_INIT U12
PIU10U12
3.3V INIT_B_0
4K87 i
1% XC7A100T-2FGG484C
CFG
SPIFLASH
i
3.3V C14 COC14

COU5A
COU5B
U5A PIC1401 PIC1402
COR7
R7 NLSPI0CS
GND
PIR702 PIR701 SPI-CS C2
PIU50C2 B4 COL3
C 3.3V NLSPI0SCK CS VCC PIU50B4 100nF L3 C
4K87 SPI-SCK B2
PIU50B2 PIL302 PIL301
NLSPI0DQO CLK NLSPI0DQ1 1.8V AVCC
1% SPI-DQO D3
PIU50D3 D2
PIU50D2 SPI-DQ1
COR1
R1 NLSPI0DQ3 DI/IO0 DO/IO1 i SPIFLASH BKP0603HS121-T
PIR102 PIR101
SPI-DQ3 D4
PIU50D4 HOLD/RESET/IO3
3.3V NLSPI0DQ2 301
PICCOC23
4K87 SPI-DQ2 C4
PIU50C4 WP/IO2
B3 2C23
GND PIU50B3 GND
1%
S25FL256SAGBHI20 302
PIC2470nF
U5B COL2
L2
A2
PIU50A2 PIL202 PIL201
NC GND
A3
PIU50A3
3.3V 3.3V
NC COS2 BKP0603HS121-T
A4
PIU50A4 NC
S2 AGND
A5
PIU50A5 NC
PIR14502 PIR14802
B1 1 COR145
R145 COR148
R148
PIU50B1 NC PIS201
B5 2
PIS202
4K87 4K87
PIU50B5 NC COR134
R134 NLRST0BTN NLCPLD0JTAGEN0RESET0BTN
C1
PIU50C1 NC
3
PIS203 PIR13401 PIR13402
RST_BTN PIR14501 1% PIR14801 1% CPLD_JTAGEN/RESET_BTN
C3
PIU50C3 NC 49R9 PIC7501
C5 4 COC75
C75 PIT603
PIU50C5 NC PIS204
D1 5 10nF
PIC7502 COT6
T6 Title:
PIU50D1 NC PIS205
D5
PIU50D5 NC
6
PIS206
16V 2N7002,215 MEGA65
E1 GNDX7R PIT601
D PIU50E1 NC D
E2
PIU50E2 NC
SPUJ191500 PIJ20 2 Number: Rev.
E3 GND COJ20
J20 A4 TE0765
PIU50E3 NC PIT602 02
E4
PIU50E4 NC
Default
E5
PIU50E5 NC
JUMPER2.54-2 PIJ20 1 Date: 2019-03-11 Copyright: Trenz Electronic GmbH Page9 of 23
S25FL256SAGBHI20 GND GND
Filename: FPGA-CFG.SchDoc
1 2 3 4
1 2 3 4
A A
COU1H
U1H
D6
PIU10D6 B5
PIU10B5
GND MGTAVCC MGTAVTT GND
D10
PIU10D10 MGTAVCC B7
PIU10B7
MGTAVTT
E8
PIU10E8 B9
PIU10B9
MGTAVCC MGTAVTT
F7
PIU10F7 MGTAVCC
B11
PIU10B11
MGTAVTT
F9
PIU10F9 MGTAVCC
C4
PIU10C4
MGTAVTT
C8
PIU10C8
MGTAVTT
B B
F6
PIU10F6 F8
PIU10F8
MGTREFCLK0P_216 MGTRREF_216 GND
E6
PIU10E6 MGTREFCLK0N_216
F10
PIU10F10 MGTREFCLK1P_216
E10
PIU10E10 MGTREFCLK1N_216
B8
PIU10B8 B4
PIU10B4
A8
PIU10A8
A4
PIU10A4
D11
PIU10D11
D5
PIU10D5
C11
PIU10C11 C5
PIU10C5
B10
PIU10B10 B6
PIU10B6
A10
PIU10A10 A6
PIU10A6
D9
PIU10D9
D7
PIU10D7
C9
PIU10C9
C7
PIU10C7
GND MGTPRXN3_216 MGTPTXN3_216
XC7A100T-2FGG484C
C C
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
Filename: FPGA-MGT.SchDoc
1 2 3 4
1 2 3 4
1V VCCINT CAPS
PIC901 PIC10 1 PIC1 01 PIC20 1 PIC2401 PIC4201 PIC4301 PIC4901 PIC5601 PIC140 1 PIC14 01 PIC14201 PIC14301
COC9
C9 COC10
C10 COC11
C11 COC20
C20 COC24
C24 COC42
C42 COC43
C43 COC49
C49 COC56
C56 COC140
C140 COC141
C141 COC142
C142 COC143
C143
PIC902 470nF PIC10 2 470nF PIC1 02 470nF PIC20 2 470nFPIC2402 470nF PIC4202 470nF PIC4302 470nF PIC4902 470nF PIC5602 470nF PIC140 2 470nF PIC14 02 470nF PIC1420 470nF PIC14302 470nF
GND
A A
1V
U1J
PIC690COC69
1C69 PIC70 COC70
1C70 PIC710COC71
1C71 PIC7401COC74
C74 PIC4 0COC44
1C44 PIC760COC76
1C76 A2
PIU10A2 H7
PIU10H7
GND GND
A3
PIU10A3 H9
PIU10H9
PIC69024.7µF PIC70 24.7µF PIC71024.7µF PIC74024.7µF PIC4 024.7µF PIC76024.7µF GND GND
A5
PIU10A5 H11
PIU10H11
GND GND
A7
PIU10A7
H21
PIU10H21
GND GND
GND A9
PIU10A9 J8
PIU10J8
GND GND
A11
PIU10A11 J10
PIU10J10
COU1I
COU1J GND GND
1V U1I A12
PIU10A12 J12
PIU10J12
GND GND
H10
PIU10H10 VCCINT H12
PIU10H12 A22
PIU10A22 J18
PIU10J18
PIC147COC147 2 1V VCCAUX 1.8V GND GND
02C147 PIC1480COC148
2C148 PIC1490COC149
C149 H8
PIU10H8 VCCINT
K12
PIU10K12
AA2
PIU10AA2
K5
PIU10K5
VCCAUX GND GND
J7
PIU10J7 M12
PIU10M12 AA12
PIU10AA12 K7
PIU10K7
1
PIC14701100µF PIC14801100µF PIC1490100µF J9
PIU10J9 P12
PIU10P12 AA22
PIU10AA22 K11
PIU10K11
K8
PIU10K8 R11
PIU10R11 AB9
PIU10AB9 K15
PIU10K15
GND L7
PIU10L7 VCCINT
AB19
PIU10AB19
L2
PIU10L2
GND GND
M8
PIU10M8 VCCINT
B3
PIU10B3
L8
PIU10L8
GND GND
1V VCCBRAM CAPS N7
PIU10N7 B12
PIU10B12 L22
PIU10L22
VCCINT GND GND
P8
PIU10P8 B19
PIU10B19 M7
PIU10M7
B VCCINT GND GND B
PIC150 1 PIC15101 PIC15201 P10
PIU10P10 VCCINT C3
PIU10C3 GND GND
M11
PIU10M11
COC150
C150 COC151
C151 COC152
C152 R7 C6 M19
PIU10R7 VCCINT PIU10C6 GND GND PIU10M19
PIC150 2 470nF PIC15102 470nF PIC15202 470nF R9
PIU10R9 VCCINT VCCBRAM
J11
PIU10J11 1V
C10
PIU10C10 GND GND
N6
PIU10N6
T10
PIU10T10 VCCINT L11 C12
PIU10C12 N8
PIU10N8
VCCBRAM PIU10L11 GND GND
GND T8
PIU10T8 N11 C16
PIU10C16 N16
PIU10N16
VCCINT VCCBRAM PIU10N11 GND GND
D3
PIU10D3 P3
PIU10P3
GND GND
XC7A100T-2FGG484C D4
PIU10D4
P7
PIU10P7
GND GND
1.8V VCCAUX CAPS D8
PIU10D8
P9
PIU10P9
GND GND
D12
PIU10D12 P11
PIU10P11
GND GND
PIC15301 PIC15401 PIC15 01 PIC15601 PIC15701 PIC460COC46
1C46 PIC470COC47
1C47 PIC480COC48
1C48 PIC15801 D13
PIU10D13 P13
PIU10P13
COC153
C153 COC154
C154 COC155
C155 COC156
C156 COC157
C157 COC158
C158 GND GND
E4
PIU10E4 R8
PIU10R8
PIC15302 470nF PIC15402 470nF PIC15 02 470nF PIC15602 470nF PIC15702 470nF PIC46024.7µF PIC47024.7µF PIC48024.7µF PIC15802 47µF GND GND
E5
PIU10E5
R10
PIU10R10
GND GND
E7
PIU10E7
R12
PIU10R12
GND GND
GND E9
PIU10E9 R20
PIU10R20
GND GND
E11
PIU10E11 T7
PIU10T7
GND GND
F5
PIU10F5 T9
PIU10T9
GND GND
F11
PIU10F11
T11
PIU10T11
GND GND
F17
PIU10F17
T17
PIU10T17
GND GND
E20
PIU10E20 U4
PIU10U4
C GND GND C
G5
PIU10G5 U14
PIU10U14
GND GND
G6
PIU10G6 V1
PIU10V1
GND GND
G7
PIU10G7
V11
PIU10V11
GND GND
G8
PIU10G8
V21
PIU10V21
GND GND
G9
PIU10G9 W8
PIU10W8
GND GND
G10
PIU10G10 W18
PIU10W18
GND GND
G12
PIU10G12 Y5
PIU10Y5
GND GND
G14
PIU10G14
Y15
PIU10Y15
GND GND
H1
PIU10H1 GND
GND XC7A100T-2FGG484C GND
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
Filename: FPGA-PWR.SchDoc
1 2 3 4
1 2 3 4
Bank8
COL10
L10 i
PIC16501
COC165
PIC16502C165
NL303V0REF
3.3V_REF PIL1001 PIL1002 3.3V U32C 3.3V U32F
3.3V
4.7µF MPZ1608S221A BANK 3 BANK 8
L8
PIU320L8 L4
PIU320L4 C8
PIU320C8 C10
PIU320C10
VCCIO3 IO_3/DIFFIO_TX_RX_B1P VCCIO8 IO_8/DIFFIO_RX_T14P
COC202
C202 L7
PIU320L7 VCCIO3 IO_3/DIFFIO_TX_RX_B1N
L5
PIU320L5
C7
PIU320C7 VCCIO8 IO_8/DIFFIO_RX_T14N
C9
PIU320C9
PIC20201 PIC20202
COU32A
COU32B
COU32C
COU32D
COU32E
COU32F
COU32G
U32A L6
PIU320L6 M5
PIU320M5
NLCPLD0DBG10
CPLD_DBG10 C6
PIU320C6 A8
PIU320A8
NLCPLD0ADC1 PIC24 01 VCCIO3 IO_3/DIFFIO_RX_B2P PIC24501 VCCIO8 IO_8/DIFFIO_RX_T15P
D3 PIU320D3 D2
PIU320M4 A9
PIU320A9
470nF ADC_VREF ANAIN1 COC244
C244 IO_3/DIFFIO_RX_B2N NLFPGA0TCK COC245
C245 IO_8/DIFFIO_RX_T15N
E2
PIU320E2 J5
PIU320J5 FPGA_TCK B10
PIU320B10
A REFGND 470nF
PIC24 02 IO_3/DIFFIO_TX_RX_B3P PIC24502 470nF IO_8/DIFFIO_RX_T16P A
K5
PIU320K5 B9
PIU320B9
IO_3/DIFFIO_TX_RX_B3N NLCPLD0DBG11 IO_8/DEV_CLRN/DIFFIO_RX_T16N
GND 3.3V BANK 1A N11
PIU320N11 VREFB3N0
N5
PIU320N5
CPLD_DBG11 B7
PIU320B7
A10
PIU320A10
NLCPLD0ADC2 IO_3/DIFFIO_RX_B4P VREFB8N0 IO_8/DIFFIO_RX_T17P NLCPLD0CFG2
F2
PIU320F2 C2
PIU320C2 CPLD_ADC2 GND N4
PIU320N4 GND A11
PIU320A11 CPLD_CFG2
VCCIO1A IO_1A/ADC1IN2/DIFFIO_RX_L1P NLCPLD0ADC3 IO_3/DIFFIO_RX_B4N NLCPLD0DBG9 IO_8/DIFFIO_RX_T17N
D1
PIU320M7 CPLD_DBG9 D8
PIU320D8
PIC24601 IO_1A/ADC1IN1/DIFFIO_RX_L1N IO_3/DIFFIO_TX_RX_B5P NLCPLD0DBG8 IO_8/DEV_OE/DIFFIO_RX_T18P
E4
PIU320E4 N6
PIU320N6 CPLD_DBG8 E8
PIU320E8
COC246
C246 IO_1A/ADC1IN4/DIFFIO_RX_L3P IO_3/DIFFIO_TX_RX_B5N NLCPLD0DBG5 IO_8/DIFFIO_RX_T18N
E3
PIU320E3 N8
PIU320N8 CPLD_DBG5 D7
PIU320D7 A7
PIU320A7
PIC24602 470nF IO_1A/ADC1IN3/DIFFIO_RX_L3N IO_3/DIFFIO_RX_B6P NLCPLD0DBG7 GND IO_8/CONFIG_SEL IO_8/DIFFIO_RX_T19P
B1
PIU320B1
N7
PIU320N7
CPLD_DBG7 A6
PIU320A6
IO_1A/ADC1IN6/DIFFIO_RX_L5P IO_3/DIFFIO_RX_B6N NLFPGA0INIT IO_8/DIFFIO_RX_T19N
C1
PIU320C1 K6
PIU320K6 FPGA_INIT E7
PIU320E7 B6
PIU320B6
IO_1A/ADC1IN5/DIFFIO_RX_L5N IO_3/DIFFIO_TX_RX_B7P NLFPGA0DONE I_8/NCONFIG IO_8/DIFFIO_RX_T20P NLTE0TCK
GND E1
PIU320E1 J6
PIU320J6 FPGA_DONE B5
PIU320B5 TE_TCK
IO_1A/ADC1IN8/DIFFIO_RX_L7P IO_3/DIFFIO_TX_RX_B7N NLCPLD0DBG4 IO_8/DIFFIO_RX_T20N NLTE0TDO
F1
PIU320F1 M9
PIU320A4 TE_TDO
IO_1A/ADC1IN7/DIFFIO_RX_L7N i Bank1 IO_3/DIFFIO_RX_B8P NLCPLD0DBG6 IO_8/DIFFIO_RX_T21P NLTE0TDI
M8
PIU320A3 TE_TDI
IO_3/DIFFIO_RX_B8N NLFPGA0TDO IO_8/DIFFIO_RX_T21N
3.3V BANK 1B K7
PIU320K7 FPGA_TDO E6
PIU320E6
IO_3/DIFFIO_TX_RX_B9P NLFPGA0TDI IO_8/DIFFIO_RX_T22P
G3
PIU320G3 E5 NLCPLD0JTAGEN0RESET0BTN
PIU320E5 CPLD_JTAGEN/RESET_BTN J7
PIU320J7 FPGA_TDI D6
PIU320D6
VCCIO1B IO_1B/JTAGEN NLM0TCK IO_3/DIFFIO_TX_RX_B9N NLK0TCK IO_8/CRC_ERROR/DIFFIO_RX_T22N NLTE0TMS
G2
PIU320G2 M_TCK M12
PIU320M12 K_TCK
NLM10nCONF B3
PIU320B3 TE_TMS
IO_1B/TCK/DIFFIO_RX_L11P NLM0TMS IO_3/DIFFIO_TX_RX_B10P NLK0TDI IO_8/DIFFIO_RX_T23P NLTE0UART0TX
TE_UART_TX
M10_NCONF
H1
PIC24701 PIU320H1 G1
PIU320G1 M_TMS M13
PIU320M13 K_TDI B4
PIU320B4
COC247
C247 VREFB1N0 IO_1B/TMS/DIFFIO_RX_L11N NLM0TDO IO_3/DIFFIO_TX_RX_B10N NLCPLD0DBG3 IO_8/DIFFIO_RX_T23N NLM100nSTATUS
F6
PIU320F6
M_TDO N9
PIU320N9
CPLD_DBG3 C4
PIU320C4
M10_NSTATUS
PIC24702 470nF IO_1B/TDO/DIFFIO_RX_L12P NLM0TDI IO_3/DIFFIO_RX_B11P NLCPLD0DBG1 IO_8/NSTATUS/DIFFIO_RX_T24P NLM100CONF0DONE
F5
PIU320F5 M_TDI N10
PIU320N10
CPLD_DBG1 C5
PIU320C5
M10_CONF_DONE
IO_1B/TDI/DIFFIO_RX_L12N IO_3/DIFFIO_RX_B11N NLFPGA0RX IO_8/CONF_DONE/DIFFIO_RX_T24N NLM0TX
G4
PIU320G4 L11
PIU320L11 FPGA_RX A2
PIU320A2 M_TX
IO_1B/DIFFIO_RX_L14P IO_3/DIFFIO_TX_RX_B12P NLK0JTAGEN IO_8/DIFFIO_RX_T26P NLM0RX
GND F4
PIU320F4 M11
PIU320M11 K_JTAGEN B2
PIU320B2 M_RX
B IO_1B/DIFFIO_RX_L14N IO_3/DIFFIO_TX_RX_B12N NLFPGA0TMS IO_8/DIFFIO_RX_T26N NLTE0UART0RX B
H3
PIU320H3 K8
PIU320K8 FPGA_TMS A5
PIU320A5 TE_UART_RX
IO_1B/DIFFIO_RX_L16P IO_3/DIFFIO_TX_RX_B14P i Bank3 IO_8
H2
PIU320H2
J8
PIU320J8
IO_1B/DIFFIO_RX_L16N IO_3/DIFFIO_TX_RX_B14N NLCPLD0DBG0
L10
PIU320L10
CPLD_DBG0 10M08SAU169C8G
IO_3/DIFFIO_TX_RX_B16P NLCPLD0DBG2
10M08SAU169C8G M10
PIU320M10 CPLD_DBG2 3.3V U32G
IO_3/DIFFIO_TX_RX_B16N NLK0TMS
Bank2 N12
PIU320N12 K_TMS H7
PIU320H7 A1
PIU320A1
IO_3 PIC24801 VCC_ONE GND
U32B i G8
PIU320G8 A13
PIU320A13
COC248
C248 VCC_ONE GND
3.3V 10M08SAU169C8G G6
PIU320G6
B8
PIU320B8
BANK 2 NLCPLD0CLK PIC24802 470nF VCC_ONE GND
K3
PIU320K3 VCCIO2
H6
PIU320H6
CPLD_CLK U32E F7 C3
PIU320C3
IO_2/CLK0P/DIFFIO_RX_L18P i Bank6 PIU320F7 VCC_ONE GND
J3
PIU320J3 G5
PIU320G5 3.3V D5
PIU320D5
VCCIO2 IO_2/CLK0N/DIFFIO_RX_L18N BANK 6 NLKB0IO2 GND
PIC24901 J2
PIU320J2 G11 G9
PIU320G9 KB_IO2 GND K4
PIU320K4 E11
PIU320E11
COC249
C249 IO_2/DIFFIO_RX_L19P PIU320G11 VCCIO6
IO_6/CLK2P/DIFFIO_RX_R14P NLKB0TCK i KB VCCA1 GND
J1
PIU320J1 F11 G10
PIU320G10 KB_TCK D10 F3
PIU320F3
PIC24902 470nF IO_2/DIFFIO_RX_L19N PIC250 1 PIU320F11 VCCIO6
IO_6/CLK2N/DIFFIO_RX_R14N NLKB0IO3 i KB PIU320D10 VCCA2 GND
H4
PIU320H4
F13
PIU320F13
KB_IO3 D4 G7
PIU320G7
IO_2/CLK1P/DIFFIO_RX_L20P COC250
C250 IO_6/CLK3P/DIFFIO_RX_R16P i KB PIU320D4 VCCA3 GND
L1
PIU320L1 VREFB2N0
H5
PIU320H5
E13
PIU320E13
K9 H12
PIU320H12
IO_2/CLK1N/DIFFIO_RX_L20N 470nF IO_6/CLK3N/DIFFIO_RX_R16N NLKB0TMS 3.3V PIU320K9 VCCA4 GND
GND M2
PIU320M2 PIC250 2 F12
PIU320F12 KB_TMS PIC17301 J4
PIU320J4
IO_2/DIFFIO_RX_L21P NLHDMI0PD IO_6/DIFFIO_RX_R18P i KB COC173
C173 GND
M1
PIU320M1 HDMI_PD D13 E12
PIU320E12 L9
PIU320L9
IO_2/DIFFIO_RX_L21N PIU320D13 VREFB6N0 IO_6/DIFFIO_RX_R18N NLKB0JTAGEN PIC17302 470nF GND
N3
PIU320N3 GND F9
PIU320F9 KB_JTAGEN M6
PIU320M6
IO_2/DPCLK1/DIFFIO_RX_L22P NLVDAC0PSAVE0N IO_6/DPCLK3/DIFFIO_RX_R26P NLKB0TDO i KB GND
N2
PIU320N2
VDAC_PSAVE_N F10
PIU320F10
KB_TDO N1
PIU320N1
IO_2/DPCLK0/DIFFIO_RX_L22N IO_6/DPCLK2/DIFFIO_RX_R26N i KB GND
L3
PIU320L3
F8
PIU320F8
GND N13
PIU320N13
IO_2/PLL_L_CLKOUTP/DIFFIO_RX_L27P IO_6/DIFFIO_RX_R27P NLKB0IO1 COJ21 GND
M3
PIU320M3 E9
PIU320E9 KB_IO1 J21
C IO_2/PLL_L_CLKOUTN/DIFFIO_RX_L27N IO_6/DIFFIO_RX_R27N i KB C
K2
PIU320K2 B12
PIU320B12 LED_R 1
CPLD_DBG0 PIJ2101 10M08SAU169C8G GND
IO_2/DIFFIO_RX_L28P IO_6/DIFFIO_RX_R28P NLCPLD0CFG3
K1
PIU320K1 B11
PIU320B11 CPLD_CFG3 2
CPLD_DBG1 PIJ2102
IO_2/DIFFIO_RX_L28N IO_6/DIFFIO_RX_R28N NLPMOD20EN
L2
PIU320L2
C12
PIU320C12
PMOD2_EN 3
CPLD_DBG2 PIJ2103
IO_2 IO_6/DIFFIO_RX_R29P NLCPLD0CFG1
C11
PIU320C11
CPLD_CFG1 4
CPLD_DBG3 PIJ2104
R28
10M08SAU169C8G B13
PIU320B13 LED_G 5
CPLD_DBG4 PIJ2105 M10_NCONF PIR2801 PIR2802
IO_6/DIFFIO_RX_R30P NLCPLD0CFG0
A12
PIU320A12 CPLD_CFG0 6
CPLD_DBG5 PIJ2106 10K
IO_6/DIFFIO_RX_R30N
U32D E10
PIU320E10 7
CPLD_DBG6 PIJ2107
3.3V
i Bank5 IO_6/DIFFIO_RX_R31P NLKB0TDI COR29
BANK 5 D9
PIU320D9
KB_TDI 8
CPLD_DBG7 PIJ2108 M10_CONF_DONE PIR2901R29 PIR2902
NLDBG0UART0TX IO_6/DIFFIO_RX_R31N NLPMOD10FLG i KB
J11
PIU320J11 VCCIO5
K10
PIU320K10
DBG_UART_TX D12
PIU320D12
PMOD1_FLG 9
IO_5/DIFFIO_RX_R1P NLDBG0UART0RX IO_6/DIFFIO_RX_R33P NLPMOD10EN
H11
PIU320H11 VCCIO5
J10
PIU320J10
DBG_UART_RX D11
PIU320D11
PMOD1_EN 10
CPLD_DBG9 PIJ21010
IO_5/DIFFIO_RX_R1N NLFPGA0TX IO_6/DIFFIO_RX_R33N NLPMOD20FLG COR30
R30
PIC25 01 K11
PIU320K11 FPGA_TX C13
PIU320C13 PMOD2_FLG 11
CPLD_DBG10 PIJ21011 M10_NSTATUS PIR3001 PIR3002
COC252
C252 IO_5/DIFFIO_RX_R2P NLK0TDO IO_6 3.3V
L12
PIU320L12
K_TDO 10M08SAU169C8G 12
PIC25 02 470nF IO_5/DIFFIO_RX_R2N NLK0IO2
K12
PIU320K12
K_IO2 13
PIJ21013
IO_5/DIFFIO_RX_R7P NLK0IO3
K13
PIU320K13 VREFB5N0
J12
PIU320J12
K_IO3 14
PIJ21014
IO_5/DIFFIO_RX_R7N NLFPGA0RESET0N COD10
D10
GND J9
PIU320J9 FPGA_RESET_N
IO_5/DIFFIO_RX_R8P COR70
R70 NLLED0G
H10
PIU320H10 PID100K PIR7001 PIR7002
LED_G GND Pin Header 2.54 2Row 14Pins
IO_5/DIFFIO_RX_R8N 3.3V PID100A
J13
PIU320J13
NL5V0JOY0PG
5V_JOY_PG 240R Title:
IO_5/DIFFIO_RX_R9P NLEN05V0JOY0N
H13
PIU320H13
EN_5V_JOY_N LED Green LTST-C191KGKT 1% MEGA65
IO_5/DIFFIO_RX_R9N
H9
PIU320H9
D IO_5/DIFFIO_RX_R10P COD12
D12 D
H8
PIU320H8
Number: Rev.
R130 NLLED0R A4 TE0765
G13
PIU320G13 PID120A PID120K PIR13001 PIR13002 LED_R 02
IO_5/DIFFIO_RX_R11P 3.3V Default
G12
PIU320G12
NLFPGA0PROG0B
FPGA_PROG_B 240R
IO_5/DIFFIO_RX_R11N NLK0IO1
L13
PIU320L13
K_IO1 LED Red LTST-C191KRKT
1%
IO_5 Date: 2019-03-11 Copyright: Trenz Electronic GmbH Page12 of 23
10M08SAU169C8G
Filename: SYS_MAX10_CTRL.SchDoc
1 2 3 4
1 2 3 4
NLV0P COR54
R54 COR59
R59
V_P PIR5401 PIR5402 PIR5901 PIR5902
PIC12301 1V
240R 1% COC123 2K61
C123
PIR60 2 PID602 PID601 PIC12302 4.7µF
COR60
R60 COD6
D6
200K GND
A PIR60 1 1% PIC12402 A
BAV199LT1G COC124
C124 COC125
C125
NLV0N COR66
R66 PID603 PIC12401 33nF
COR61
R61
V_N PIR6601 PIR6602 PIR6101 PIR6102 PIC12502 PIC12501
240R 1% 240R 1% 10µF

3.3V GND
10V
COJ9
J9
4
PIJ904
COD7
D7
PID703 GND
3
PIJ903
COR62 COC126
C126
NLPWM0R
PWM_R R62 2
PIR6201 PIR6202 PIC12602 PIC12601 PIJ902
240R PIC12701 PIR6301 COR64

R64
COC128
C128
COC127
C127 COR63
R63 10µF NLPWM0L
PWM_L 1
1% PIR6401 PIR6402 PIC12802 PIC12801 PIJ901
PIC12702 33nF 150R 10V PIC12901 PIR6501
X5R 240R COC129 COR65 10µF
25V 02
PIR631% C129 R65
1% 10V
X7R PIC12902 33nF 150R 3.5RCA
B 25V X5R B
502
PIR61%
GND COD8
D8 PID803 X7R
GND
PID801 PID802 BAV199LT1G

COC172
C172
GND 3.3V PIC17201 PIC17202
2.2nF
25V
C0G, NP0
COR153
R153
PIR15301 PIR15302
22K
1%
COC177
C177 COU37
U37
NLPWM0SPEAKER COR149
R149 COR154
R154 COJ19
PWM_SPEAKER PIR14901 PIR14902 PIC17701 PIC17702 PIR15401 PIR15402 4
PIU3704 PIU37055 J19
C VIN- VOUT1 C
240R PIC17401 PIR150 1 22K 3
PIU3703 1
PIJ1901
COC174
C174 COR150
R150 470nF VIN+
1% 1% 2
PIU3702 8
PIU3708 2
PIJ1902
PIC17402 33nF 150R 6.3V BYPASS VOUT2
25V 02
PIR151% X5R NLSPEAKER0MUTE0N
SPEAKER_MUTE_N 1 JST-S2B-XH-A
PIU3701 SB
COD13
D13 PID1303 X7R COC176
C176
PIC17801 6
PIU3706 7
PIU3707
COC178
C178 GND PIC17602 PIC17601 VCC GND
GND
PIC17802 1µF 10µF TS4990IST GND
16V 10V
COL11
L11
3.3V PIL1102 PIL1101
GND 3.3V GND
MPZ1608S221A
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
Filename: SOUND.SchDoc
1 2 3 4
1 2 3 4
COJ6
J6 COU15
U15 COJ7
J7
1 NLSER0SRQ
SER_SRQ NLF0SER0CLK0EN
F_SER_CLK_EN 1 5 5 NLJA0AY
JA_AY
PIJ601 PIU1501 OE VCC PIU1505 5V PIJ705
5
PIJ605
NLSER0DATA
SER_DATA NLF0SER0CLK0O
F_SER_CLK_O 2
PIU1502 9
PIJ709
NLJA0AX
JA_AX
A
3
PIU1503
4
PIU1504
SER_CLK 4
PIJ704
JA_RIGHT
NLSER0RESET GND GND Y
PIJ6066 SER_RESET GND 8
PIJ708 GND
NC7SZ126P5X GND 3
PIJ703 JA_LEFT
PIJ6044 NLSER0CLK
SER_CLK COU16
U16 7
PIJ707
A NLSER0ATN NLF0SER0DATA0EN PIR8602 PIC4502 5V_JOY A
3
PIJ603 SER_ATN F_SER_DATA_EN 1
PIU1601 5
PIU1605 2
PIJ702 JA_DOWN
NLF0SER0DATA0O OE VCC 5V PIC13502 COR86
R86 COC45
C45
2
PIJ602
F_SER_DATA_O 2
PIU1602
6
PIJ706
JA_FIRE
GND A COC135
C135 1M PIC4501 10µF
7
PIJ607 3
PIU1603 4
PIU1604 SER_DATA 1
PIJ701 JA_UP
GND GND GND Y PIC13501 100pF PIR8601 5%
8
GND PIJ608 1000V
NC7SZ126P5X DSUB-9-M GND
COU27 X7R PIJ70H2 PIJ70H1
H2
H1
61PC6F U27
NLF0SER0SRQ0EN
F_SER_SRQ_EN 1
PIU2701
5
PIU2705
NLF0SER0SRQ0O OE VCC 5V
GND F_SER_SRQ_O 2
PIU2702 A
3
PIU2703 4
PIU2704 SER_SRQ
GND GND Y COJ3
J3
NC7SZ126P5X 5
PIJ305
NLJB0AY
JB_AY
COU20
U20 9
PIJ309
NLJB0AX
JB_AX
1
PIU2001 5
PIU2005 4
PIJ304
NLJB0RIGHT
JB_RIGHT
3.3V OE VCC 3.3V
SER_CLK 2
PIU2002 8
PIJ308
A NLF0SER0CLK0I GND NLJB0LEFT
3
PIU2003 4
PIU2004 F_SER_CLK_I 3
PIJ303 JB_LEFT
GND GND Y
7
PIJ307
NLJB0DOWN PIC7202 5V_JOY
NC7SZ126P5X 2
PIJ302
JB_DOWN
COU21
U21 6 NLJB0FIRE
JB_FIRE COC72
C72
PIJ306
1
PIU2101 5
PIU2105 1
PIJ301
NLJB0UP
JB_UP PIC7201 10µF
B 3.3V OE VCC 3.3V B
SER_DATA 2
PIU2102 A NLF0SER0DATA0I
3
PIU2103 GND Y
4
PIU2104
F_SER_DATA_I DSUB-9-M GND
GND PIJ30H2 PIJ30H1
H2
H1
NC7SZ126P5X
COU28
U28
1
PIU2801 5
PIU2805
3.3V OE VCC 3.3V
SER_SRQ 2
PIU2802
3.3V
A NLF0SER0SRQ0I
3
PIU2803
4
PIU2804
F_SER_SRQ_I
GND GND Y COU33
U33
NC7SZ126P5X PIR12702 11
PIU33011 1
PIU3301
COR127
R127 5V VCC SOURCE 5V_JOY
PIR12 02 SOURCE
2
PIU3302
COU22
U22 4K7 COR122
R122 6 3
PIU3306 NC SOURCE PIU3303
1
PIU2201
5
PIU2205
NL5V0JOY0PG
5V_JOY_PG PIR12701 DNP 4
PIU3304
NLJA0RIGHT 3.3V OE VCC 3.3V SOURCE
JA_RIGHT 2
PIU2202 PIR12 01 8
PIU3308 5
PIU3305
A NLFA0RIGHT PIT203 Enable/Fault SOURCE
3
PIU2203 4
PIU2204 FA_RIGHT PIR12302 COC73
C73 PIR12401
GND GND Y COR123
R123 COR124
R124
PIC7301 PIC7302 9
PIU3309
COT2 200K GND dv/dt 22R
NC7SZ126P5X T2
COU23
U23 2N7002,215 1%
PIR 1230 1
PIT201
1nF 10
PIU33010 GND
7
PIU3307
PIR12402 1%
50V I-Limit
1
PIU2301 5
PIU2305 PIR12502
C NLJA0LEFT 3.3V OE VCC 3.3V COR125
R125 X7R C
JA_LEFT 2
PIU2302 MP5010BDQ-LF-Z
A NLFA0LEFT PIT20 200K
3
PIU2303 4
PIU2304 FA_LEFT
GND GND Y PIR12501 1% GND
NC7SZ126P5X GND PIT103
COU24
U24 GND COT1
T1
1
PIU2401 5
PIU2405
2N7002,215
NLJA0DOWN 3.3V OE VCC 3.3V NLEN05V0JOY0N
JA_DOWN 2
PIU2402 EN_5V_JOY_NPIT101
A NLFA0DOWN
3
PIU2403
4
PIU2404
FA_DOWN
GND GND Y
3.3V 5V
NC7SZ126P5X PIT102
PIC17902 PIC180 2
COC179
C179 COC180
C180 COU25
U25 GND
PIC17901 10µF PIC180 1 10µF 1
PIU2501
5
PIU2505
10V NLJA0FIRE 3.3V OE VCC 3.3V
JA_FIRE 2
PIU2502 A NLFA0FIRE
GND GND 3
PIU2503 4
PIU2504 FA_FIRE
GND GND Y
NC7SZ126P5X Title:
MEGA65
COU26
U26
D D
1
PIU2601
5
PIU2605
Number: Rev.
NLJA0UP 3.3V OE VCC 3.3V A4 TE0765
JA_UP 2
PIU2602 02
A Default
3
PIU2603
4
PIU2604
NLFA0UP
FA_UP
GND GND Y
NC7SZ126P5X
Filename: JOY.SchDoc
1 2 3 4
1 2 3 4
A A
COJ5
J5
KB i i KB
1
PIJ501
2
PIJ502
NLK0JTAGEN GND 3.3V NLK0TMS
K_JTAGEN 3
PIJ503 4
PIJ504 K_TMS
NLK0TCK
K_TCK 5
PIJ505 6
PIJ506
NLK0TDI
K_TDI
NLK0TDO
K_TDO 7
PIJ507 8
PIJ508
NLK0IO1
K_IO1
NLK0IO2
K_IO2 9
PIJ509
10
PIJ5010
NLK0IO3
K_IO3
SMD-254-9132-14-10
B B
COJ12
J12
1
PIJ1201 2
PIJ1202
GND 3.3V
3
PIJ1203 4
PIJ1204
5
PIJ1205 6
PIJ1206
7
PIJ1207
8
PIJ1208
9
PIJ1209
10
PIJ12010
1-338069-0
C C
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
Filename: KEYBOARD.SchDoc
1 2 3 4
1 2 3 4
A A
COU7
U7
COJ13
J13 31
PIU7031 7
PIU707
3.3V VCCA VCCB 5V
1
PIJ1301 42
PIU7042 18
PIU7018
12V_FUSED VCCA VCCB
2
PIJ1302 FLOPPY
GND
3
PIJ1303 i
GND
4
PIJ1304 1
PIU701 48
PIU7048
5V 3.3V 1DIR 1OE GND
Stiftleiste 4 Pol. 2,54mm NLF0REDWC
F_REDWC 47
PIU7047 2
PIU702 REDWC
COJ16 NLF0MOTEA 1A1 1B1
J16 F_MOTEA 46
PIU7046
3
PIU703
MOTEA
NLF0DRVSA 1A2 1B2
1
PIJ1601
F_DRVSA 44
PIU7044
5
PIU705
DRVSA
12V_FUSED NLF0DIR 1A3 1B3
2
PIJ1602 F_DIR 43
PIU7043 6
PIU706 DIR
GND NLF0STEP 1A4 1B4
3
PIJ1603 F_STEP 41
PIU7041 8
PIU708 STEP
B GND NLF0WDATE 1A5 1B5 B
4
PIJ1604 F_WDATE 40
PIU7040 9
PIU709 WDATE
5V NLF0WGATE 1A6 1B6
F_WGATE 38
PIU7038
11
PIU7011
WGATE
NLF0SIDE1 1A7 1B7
Stiftleiste 4 Pol. 2,54mm F_SIDE1 37
PIU7037
12
PIU7012
SIDE1
1A8 1B8
24
PIU7024 25
PIU7025
GND 2DIR 2OE GND
NLF0INDEX
F_INDEX 36
PIU7036
13
PIU7013
INDEX
NLF0TRCK0 2A1 2B1
F_TRCK0 35
PIU7035
14
PIU7014
TRCK0
NLF0WPT 2A2 2B2
F_WPT 33
PIU7033 16
PIU7016 WPT
NLF0RDATA1 2A3 2B3
F_RDATA1 32
PIU7032 17
PIU7017 RDATA1
NLF0DSCKCHG 2A4 2B4
F_DSCKCHG 30
PIU7030 19
PIU7019 DSCKCHG
2A5 2B5
29
PIU7029
20
PIU7020
2A6 2B6
27
PIU7027
22
PIU7022
COJ14 2A7 2B7
J14 26
PIU7026 23
PIU7023
NLREDWC 2A8 2B8
1
PIJ1401 2
PIJ1402 REDWC
3
PIJ1403 4
PIJ1404 28
PIU7028 4
PIU704
GND GND
5
PIJ1405
6
PIJ1406
34
PIU7034
10
PIU7010
NLINDEX GND GND
7
PIJ1407
8
PIJ1408
INDEX 39
PIU7039
15
PIU7015
NLMOTEA GND GND
9
PIJ1409 10
PIJ14010 MOTEA 45 21
PIU7021
C NLDRVSB GND PIU7045 GND GND GND C
11
PIJ14011 12
PIJ14012 DRVSB
13
PIJ14013 14
PIJ14014
NLDRVSA
DRVSA SN74LVCH16T245DGV
15
PIJ14015
16
PIJ14016
NLMOTEB
MOTEB
17
PIJ14017
18
PIJ14018
NLDIR
DIR
19
PIJ14019 20
PIJ14020
NLSTEP
STEP
21 22 NLWDATE
WDATE
PIJ14021 PIJ14022
23
PIJ14023 24
PIJ14024
NLWGATE
WGATE
25
PIJ14025
26
PIJ14026
NLTRCK0
TRCK0
27
PIJ14027
28
PIJ14028
NLWPT
WPT
29 30 NLRDATA1
RDATA1
PIJ14029 PIJ14030
31
PIJ14031 32
PIJ14032
NLSIDE1
SIDE1
33
PIJ14033
34
PIJ14034
NLDSCKCHG
DSCKCHG
WANNE2,54-34 GERADE
GND
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
Filename: Floppy.SchDoc
1 2 3 4
1 2 3 4
GND
COU3A
COU3B
U3A
NLG0
G0 3
PIU303 31
PIU3031
A NLG1 G0 IOG NLVGA0Green0Out A
G1 4
PIU304 32
PIU3032 VGA_GREEN_OUT
NLG2 G1 IOG PIR1301
G2 5
PIU305
NLG3 G2 COR13
R13
G3 6
PIU306
NLG4 G3 75R COJ1
J1
G4 7
PIU307 DSUB-15-F-HD 8.89
NLG5 G4 PIR1302 1%
G5 8
PIU308 VGA_RED_OUT 1
PIJ101
NLG6 G5
G6 9
PIU309 GND 6
PIJ106
NLG7 G6 GND
G7 10
PIU3010
GND 11
PIJ1011
G7
VGA_GREEN_OUT 2
PIJ102
NLB0
B0 16
PIU3016 27
PIU3027 7
PIJ107
NLB1 B0 IOB NLVGA0Blue0Out GND
B1 17
PIU3017 28
PIU3028 VGA_BLUE_OUT VGA_ID1/SDA 12
PIJ1012
NLB2 B1 IOB PIR1501
B2 18
PIU3018 VGA_BLUE_OUT 3
PIJ103
NLB3 B2 COR15
R15
B3 19
PIU3019 COR44 8
PIJ108
NLB4 B3 75R NLVGA0HSync R44 GND
B4 20
PIU3020 VGA_HSYNC PIR4401 PIR4402 13
PIJ1013
NLB5 B4
B5 21
PIU3021 PIR1502 1% 49R9 4
PIJ104
NLB6 B5
B6 22
PIU3022 GND 9
PIJ109
NLB7 B6 NLVGA0VSync COR53
R53
B7 23
PIU3023
GND VGA_VSYNC PIR5301 PIR5302
14
PIJ1014
B7
49R9 5
PIJ105
NLR0 GND
R0 41
PIU3041 33
PIU3033 10
PIJ1010
NLR1 R0 IOR NLVGA0Red0Out GND
R1 42
PIU3042 34
PIU3034 VGA_RED_OUT VGA_ID3/SCL 15
PIJ1015
B NLR2 R1 IOR B
R2 43
PIU3043 R2
PIR1601
NLR3
R3 44 COR16
R16
PIU3044 R3
NLR4 75R PIJ10H1 PIJ10H2
H1
H2
R4 45
PIU3045
NLR5 R4 1%
R5 46
PIU3046
PIR1602
NLR6 R5
R6 47
PIU3047
NLR7 R6
R7 48
PIU3048 GND
R7
ADV7125BCPZ170
5V PIR8501 PIC13401
3.3V COR85
R85 COC134
C134
U3B VAA COL7 1M PIC13402 100pF
NLVDAC0CLK L7 PIR6902 PIR13 02 PIR8502 5% 1000V
VDAC_CLK 24
PIU3024
13
PIU3013 PIL701 PIL702
CLOCK VAA 3.3V COR69
R69 PIT301 COR131
R131 X7R
29
PIU3029 PIC3401 PIC3501
NLVDAC0BLANK0N VAA COC34
C34 COC35
C35 MPZ1608S221A 10K 10K
VDAC_BLANK_N 11
PIU3011 30
PIU3030
BLANK VAA PIC3402 100nF PIC3502 10nF NLVGA0SDA PIR6901 PIR13 01 NLVGA0ID10SDA
VGA_SDA PIT302 PIT303 VGA_ID1/SDA GND GND
NLVDAC0SYNC0N
VDAC_SYNC_N 12
PIU3012
1
PIU301
25V 16V
SYNC GND X5R X7R
2
PIU302
NLVDAC0PSAVE0N GND COT3
VDAC_PSAVE_N 38
PIU3038 14
PIU3014
T3
C PSAVE GND C
COC36
C36 15
PIU3015
2N7002,215
GND
PIC3601 PIC3602 36
PIU3036 25
PIU3025 GND 5V
VAA VREF GND
COC118
C118 26
PIU3026
3.3V
100nF GND
PIC11801 PIC11802
35
PIU3035
39
PIU3039
25V VAA COMP GND
40
PIU3040 PIR1320 PIR13 02
X5R 100nF GND COR132
R132 PIT401 COR133
R133
37
PIU3037 49
PIU3049
25V RSET EP 10K 10K
X5R PIR1801 ADV7125BCPZ170 GND NLVGA0SCL
VGA_SCL PIR13201 PIR13 01 NLVGA0ID30SCL
VGA_ID3/SCL
PIT402 PIT403
COR18
R18
560R
PIR1802 1% COT4
T4
2N7002,215
GND
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
Filename: VGA.SchDoc
1 2 3 4
1 2 3 4
COU6A
COU6B
COU6C
U6A U6B
Video HDMI COJ4
J4 Audio
NLHDMI0VS
HDMI_VS 2
PIU602 33
PIU6033 HDMI_TXC_P HDMI_TX2_P 1
PIJ401
NLHDMI0SPDIF
HDMI_SPDIF 10
PIU6010
NLHDMI0SPDIFOUT
46 HDMI_SPDIFOUT
PIU6046
VSYNC TXC+ Data2+ SPDIF SPDIF_OUT
PixelC 32
PIU6032 HDMI_TXC_N 2
PIJ402
NLHDMI0HS TXC– Data2 Shield
HDMI_HS 98
PIU6098 HDMI_TX2_N 3
PIJ403 11
PIU6011
HSYNC Data2- MCLK
36
PIU6036 HDMI_TX0_P HDMI_TX1_P 4
PIJ404
NLHDMI0CLK TX0+ Data1+
HDMI_CLK 79
PIU6079 Blue 35
PIJ405 16
PIU6016
A CLK TX0– Data1 Shield SCLK A
HDMI_TX1_N 6
PIJ406
NLHDMI0DE Data1-
HDMI_DE 97
PIU6097
40
PIU6040 HDMI_TX1_P HDMI_TX0_P 7
PIJ407
17
PIU6017
DE TX1+ Data0+ LRCLK
Green 39
PIJ408
NLHDMI0D0 TX1– Data0 Shield
HDMI_D0 96
PIJ409 9
PIU609
NLHDMI0D1 D0 Data0- DSD_CLK
HDMI_D1 95
PIU6095 43
PIU6043 HDMI_TX2_P HDMI_TXC_P 10
PIJ4010
NLHDMI0D2 D1 TX2+ Clock+ NLHDMI0PD
HDMI_D2 94
PIU6094 Red 42
PIJ4011 HDMI_PD 38
PIU6038
NLHDMI0D3 D2 TX2– Clock Shield PD
HDMI_D3 93
PIU6093 GND GND HDMI_TXC_N 12
PIJ4012
NLHDMI0D4 D3 Clock-
HDMI_D4 92
PIU6092 30
PIU6030 HPD_A CEC_B 13
PIJ4013 12
PIU6012
NLHDMI0D5 D4 HPD CEC I2S0
HDMI_D5 91
PIU6091 PIC9402 PIC9502 14
PIJ4014 13
PIU6013
NLHDMI0D6 D5 COC94 COC95 NC I2S1
HDMI_D6 90
PIU6090 48
PIU6048 CEC_A C94 C95 SCL_B 15
PIJ4015 14
PIU6014
NLHDMI0D7 D6 CEC SCL I2S2
HDMI_D7 89
PIU6089 PIC9401 1µF PIC9501 100nF SDA_B 16
PIJ4016 15
PIU6015
NLHDMI0D8 D7 NLCEC0CLK SDA I2S3
HDMI_D8 88
PIU6088
50
PIU6050 CEC_CLK 6.3V 17
PIJ4017
NLHDMI0D9 D8 CEC_CLK DVDD_HDMI DDC/CEC GND
HDMI_D9 87
PIU6087 5V_HDMI 18
PIJ4018 3
PIU603
NLHDMI0D10 D9 +5V DSD0
HDMI_D10 86
PIU6086 53
PIU6053 SCL_A PIR2 01 PIR2301 HPD_B 19
PIJ4019 4
PIU604
NLHDMI0D11 D10 DDCSCL COR22
R22 COR23
R23 Hot Plug Detect DSD1
HDMI_D11 85
PIU6085 H1
PIJ40H1 5
PIU605
NLHDMI0D12 D11 49R9 49R9 FRAME DSD2
HDMI_D12 84
PIU6084
54
PIU6054
SDA_A H2
PIJ40H2
6
NLHDMI0D13 D12 DDCSDA PIR2 02 PIR2302 FRAME PIU606 DSD3
HDMI_D13 83
PIU6083
H3
PIJ40H3
7
NLHDMI0D14 D13 COC78 FRAME PIU607 DSD4
HDMI_D14 82
PIU6082 52
PIU6052 C78 1µF
PIC7801 PIC7802 H4
PIJ40H4 8
PIU608
NLHDMI0D15 D14 HEAC+ FRAME DSD5
HDMI_D15 81
PIU6081 51
PIU6051 6.3V
B NLHDMI0D16 D15 HEAC- COC79 B
HDMI_D16 80
PIU6080 C79PIC7901 1µF
PIC7902 HDMI Connector ADV7511KSTZ
NLHDMI0D17 D16 NLHDMI0SCL GND
HDMI_D17 78
PIU6078
55
PIU6055
HDMI_SCL PIR4601 PIR4602
6.3V GND
NLHDMI0D18 D17 SCL 3.3V
HDMI_D18 74
PIU6074
1% 2K COR46
NLHDMI0D19 D18 NLHDMI0SDA R46
HDMI_D19 73
PIU6073 56
PIU6056 HDMI_SDA PIR4701 PIR4702
NLHDMI0D20 D19 SDA
HDMI_D20 72
PIU6072 1% 2K COR47
D20 R47
NLHDMI0D21
HDMI_D21 71
PIU6071 45
PIU6045
NLHDMI0INT
HDMI_INT PIR4801 PIR4802
NLHDMI0D22 D21 INT
HDMI_D22 70
PIU6070
1% 2K COR48
NLHDMI0D23
D22 R48
HDMI_D23 69
PIU6069
NLHDMI0D24 D23 COL1
L1
HDMI_D24 68
PIU6068
NLHDMI0D25 D24 PIL101 PIL102 DVDD_HDMI
HDMI_D25 67
PIU6067
NLHDMI0D26 D25 MPZ1608S221A
HDMI_D26 66
PIU6066 PIC80 2 PIC8101 PIC8201 PIC8301 PIC8401 PIC8501 PIC8601 PIC8701 PIC8 01
NLHDMI0D27 D26 U6C
HDMI_D27 65
PIU6065 COC80
C80 COC81
C81 COC82
C82 COC83
C83 COC84
C84 COC85
C85 COC86
C86 COC87
C87 COC88
C88
NLHDMI0D28 D27
HDMI_D28 64
PIU6064 PIC80 1 10µF PIC8102 100nF PIC8202 100nF PIC8302 100nF PIC8402 100nF PIC8502 10nF PIC8602 10nF PIC8702 10nF PIC8 02 10nF Power
NLHDMI0D29 D28
HDMI_D29 63
PIU6063 1
PIU601 28
PIU6028
NLHDMI0D30 D29 DVDD_HDMI DVDD R_EXT
HDMI_D30 62
PIU6062 GND GND GND GND GND GND GND GND GND 19
PIU6019
NLHDMI0D31 D30 COL8
L8 DVDD PIR1401
HDMI_D31 61
PIU6061 49
PIU6049
NLHDMI0D32 D31 PIL801 PIL802 AVDD_HDMI DVDD COR14
R14
HDMI_D32 60
PIU6060
76
PIU6076
NLHDMI0D33
D32 MPZ1608S221A DVDD 887R
HDMI_D33 59
PIU6059 PIC8902 PIC9601 PIC9701 PIC10101 PIC10301 PIC104 1 PIC105 1 77
PIU6077
NLHDMI0D34 D33 DVDD PIR1402
HDMI_D34 58
PIU6058 COC89
C89 COC96
C96 COC97
C97 COC101
C101 COC103
C103 COC104
C104 COC105
C105
C NLHDMI0D35 D34 C
HDMI_D35 57
PIU6057 GND PIC8901 10µF PIC9602 100nF PIC9702 100nF PIC10102 100nF PIC10302 100nF PIC104 2 10nF PIC105 2 10nF 24
PIU6024
D35 AVDD_HDMI PVDD GND
25
PIU6025 18
PIU6018
PIC106 2 PVDD GND
ADV7511KSTZ GND GND GND GND GND GND GND 20
PIU6020
COC106
C106 GND
3.3V 21
PIU6021
22
PIU6022
COU10 100nF COL9
L9 PLVDD_HDMI PLVDD GND
U10 PIC106 1 23
PIU6023
NLCEC0A 1.8V PIL901 PIL902 PLVDD_HDMI GND
CEC_A 1
PIU1001 24
PIU10024 26
PIU6026 27
PIU6027
NLSCL0A CEC_A VCCA NLHDMI0TX20P MPZ1608S221A BGVDD GND
SCL_A 2
PIU1002 23
PIU10023 HDMI_TX2_P PIC107 2 PIC108 1 PIC109 1 PIC1 0 1 PIC1 201 31
PIU6031
NLSDA0A SCL_A D2+ NLHDMI0TX20N GND
SDA_A 3
PIU1003
22
PIU10022
HDMI_TX2_N COC107
C107 COC108
C108 COC109
C109 COC110
C110 COC112
C112 29
PIU6029
37
PIU6037
NLHPD0A
SDA_A D2- NLHDMI0TX10P
AVDD_HDMI AVDD GND
HPD_A 4
PIU1004
21
PIU10021 HDMI_TX1_P PIC107 1 10µF PIC108 2 100nF PIC109 2 100nF PIC1 0 2 10nF PIC1 202 10nF 34
PIU6034
44
PIU6044
NLLS0OE HPD_A D1+ NLHDMI0TX10N AVDD GND
LS_OE 5
PIU1005
20
PIU10020 HDMI_TX1_N 41 75
PIU6075
LS_OE D1- PIU6041 AVDD GND
6
PIU1006 19
PIU10019 GND GND GND GND GND 99
PIU6099
NLCEC0B GND GND GND GNDNLHDMI0TX00P GND
CEC_B 7
PIU1007
18
PIU10018
HDMI_TX0_P 47
PIU6047
100
PIU60100
NLSCL0B CEC_B D0+ NLHDMI0TX00N COL6
L6 MVDD_HDMI MVDD GND
SCL_B 8
PIU1008
17
PIU10017
HDMI_TX0_N
NLSDA0B
SCL_B D0- NLHDMI0TXC0P 3.3V PIL601 PIL602 MVDD_HDMI
SDA_B 9
PIU1009
16
PIU10016 HDMI_TXC_P ADV7511KSTZ
NLHPD0B SDA_B CLK+ NLHDMI0TXC0N MPZ1608S221A
HPD_B 10
PIU10010 15
PIU10015 HDMI_TXC_N
PIC1 302 PIC1 402 PIC1 501 PIC1 601 GND
HPD_B CLK-
11
PIU10011
14
PIU10014 COC113
C113 COC114
C114 COC115
C115 COC116
C116
5V VCC5V GND GND
NLCT0HPD
CT_HPD 12
PIU10012
13
PIU10013
NL5V0HDMI
5V_HDMI PIC1 301 10µF PIC1 401 10µF PIC1 502 100nF PIC1 602 10nF Title:
CT_HPD 5V_OUT
MEGA65
PIC1 701 TPD12S016PWR PIC17 01 GND GND GND GND
D COC117
C117 COC171
C171 D
Number: Rev.
PIC1 702 100nF PIC17 02 100nF A4 TE0765
Default 02
GND GND
Filename: HDMI.SchDoc
1 2 3 4
1 2 3 4
COU4A
COU4B
U4A
23
PIU4023 ETH_LED
NLETH0RD0P LED0/ANEN_SPEED
3.3V 4
ETH_RD_P PIU404
NLETH0RD0N RXP NLETH0CRS0DV
3
ETH_RD_N PIU403 15
PIU4015 ETH_CRS_DV
RXM CRS_DV/PHYAD[1:0] i ETH
PIR501 PIR601 NLETH0TD0P
ETH_TD_P 6
PIU406
A COR5
R5 COR6
R6 NLETH0TD0N TXP A
5
ETH_TD_N PIU405
1K 1K TXM
7
PIU407
PIR502 1%PIR602 1% XO
NLETH0MDIO
ETH_MDIO 10
PIU4010 8
PIU408
NLETH0CLK
ETH_CLK
NLETH0MDC MDIO XI i ETH
ETH_MDC 11
PIU4011 MDC NLETH0RST COJ10A
COJ10B
COJ10C
24
PIU4024 ETH-RST J10A
RST
ETH_TD_P 1
PIJ1001
COR9
R9 6K49 1% 9 TD+ J1
GND PIR901 PIR902
PIU409 REXT
NLETH0INT
ETH_INT 18
PIU4018 16
PIU4016
INTRP REF_CLK NLETH0RXER 75R 75R J4
17
PIU4017 ETH_RXER 4
PIJ1004
NLETH0TX0EN RXER i ETH PIC1802 TCT
ETH_TX_EN 19
PIU4019
ETH i TXEN COC18
C18 J5
NLETH0TX0D0
ETH_TX_D0 20
PIU4020 13
PIU4013
NLETH0RX0D0
ETH_RX_D0 PIC1801
100nF ETH_TD_N 2
PIJ1002
ETH i NLETH0TX0D1 TXD0 RXD0 NLETH0RX0D1 i ETH 25V TD- J2
ETH_TX_D1 21
PIU4021 12
PIU4012 ETH_RX_D1
ETH i TXD1 RXD1 i ETH
GNDX5R
KSZ8081RNDCA ETH_RD_P 3
PIJ1003 RD+ J3
75R 75R J7
5
PIJ1005
B RCT B
PIC1902 J8
1% COC19
C19
COR10
R10 NLETH0LED 100nF
PIC1901
J10B
PIJ1009 PIJ10010 PIR1001 PIR1002
ETH_LED ETH_RD_N 6
PIJ1006
3.3V L-GN 25V RD- J6
220R
GNDX5R
RJ45 - 7499011222A
8
PIJ1008
COR11
R11 GND GND
PIR1101 PIR1102 GND
10K 7
PIJ1007 NC
1%
1% 15
PIJ10015
J10C COR72
R72 NLETH0LED2
ETH_LED2 16
Frame
3.3V PIJ10011 PIJ10012
R-GN PIR7201 PIR7202 PIJ10016 Frame
220R
RJ45 - 7499011222A
RJ45 - 7499011222A
GND
PIR1201 PIC2901
PIC2101 PIC2801 COR12
R12 COC29
C29
COC21
C21 COC28
C28 1M PIC2902 100pF
C 22µF 470nF 1000V C
PIC2102 PIC2802 PIR1202 5%
6.3V 6.3V X7R
X5R X5R U4B
14
PIU4014 VDDIO
1
PIU401
NLVDD0102V
VDD_1.2V GND GND
3.3V VDD_1.2
PIC30 1 PIC3101
COC30
C30 COC31
C31
22
PIU4022
PIC30 2 2.2µF PIC3102 470nF
COL4
L4 GND
PIL401 PIL402 PIU402
2 25
PIU4025
6.3V 6.3V
VDDA_3.3 GND X7R X5R
BKP0603HS121-T PIC3201 PIC3 01 KSZ8081RNDCA
COC32
C32 COC33
C33
PIC3202 22µF PIC3 02 470nF GND
6.3V 6.3V
X5R X5R
GND Title:
MEGA65
D D
Nummer: Rev.
A4 TE0765
Default 02
Datum: 2019-03-11 Zeichner: Trenz Electronic GmbH Blatt 20 von 23
Filename: Ethernet.SchDoc
1 2 3 4
1 2 3 4
A A
http://linux-sunxi.org/MicroSD_Breakout
COJ2 COR27
R27 NLM0TCK
J2 SD_D2 PIR2701 PIR2702 M_TCK
COR52
R52PIR5202
12K1
PIR5201
1% NLSD0D2
SD_D2 1
PIJ201
3.3V DAT2 0R
COR55
R55PIR5502 12K1
PIR5501 1% NLSD0D3
SD_D3 2
PIJ202
3.3V COR56 NLSD0CMD CD/DAT3 1%
R56PIR5602 12K1
PIR5601 1% SD_CMD 3
PIJ203
3.3V CMD
4
PIJ204
3.3V NLSD0CLK VDD COR32
R32 NLM0TMS
SD_CLK 5
PIJ205 SD_D1 PIR3201 PIR3202 M_TMS
CLK
6
PIJ206 GND 0R
COR57
R57PIR5702 12K1
PIR5701 1% NLSD0D0
SD_D0 7
PIJ207
3.3V COR88 NLSD0D1 DAT0 1%
R88PIR8802 12K1
PIR8801 1% SD_D1 8
PIJ208
3.3V DAT1
COR33
R33 NLM0TDO
G1
PIJ20G1
SD_CMD PIR3301 PIR3302
M_TDO
GND
G2
PIJ20G2 0R
GND
G3
PIJ20G3 1%
GND
G4
B GND PIJ20G4 GND B
COR89 NLSD0CD COR34
R34 NLM0TDI
R89PIR8902
12K1
PIR8901
1% SD_CD 9
PIJ209 Card
SD_D0 PIR3401 PIR3402
M_TDI
3.3V
Detect 0R
Switch 1%
COC22
C22 10
PIJ2010
GND
3.3V PIC2201 PIC2202 GND COR35
R35
Micro SD Socket SD_D3 PIR3501 PIR3502
NLM0RX
M_RX
10µF
10V 0R
X5R 1%
COR36
R36 NLM0TX
SD_CLK PIR3601 PIR3602
M_TX
COJ15
J15
COR119 0R
R119 12K1
PIR11901
NLSD20D3
SD2_D3 1
PIJ1501
3.3V COR21
R21 PIR11902 NLSD20CMD CD/DAT3 1%
PIR2101 12K1
PIR2102 SD2_CMD 2
PIJ1502 CMD
3
GND PIJ1503 VSS1
4
NLSD20CLK 3.3V PIJ1504 VDD
COS3A
COS3B
COS3C
COS3D
S3A
SD2_CLK 5
PIJ1505 CLK
6 COR142
R142
PIR14202 12K1
PIR14201 1% NLCPLD0CFG0
CPLD_CFG0 8
PIS308 1
PIS301
C COR24
R24 NLSD20D0 GND PIJ1506 VSS2 3.3V C
PIR2401COR25 12K1 SD2_D0 7
PIJ1507 CHS-04TA
R25 PIR2402 NLSD20D1 DAT0
PIR2501COR26 12K1 SD2_D1 8
PIJ1508
R26 PIR2502 NLSD20D2 DAT1 S3B
PIR2601
12K1
PIR2602
SD2_D2 9
PIJ1509 DAT2
COR143
R143
PIR14302
12K1
PIR14301
1% NLCPLD0CFG1
CPLD_CFG1 7
PIS307
2
PIS302
COR120
R120 NLSD20CD
PIR12001 12K1
PIR12002 SD2_CD 10
PIJ15010 CHS-04TA
CD Card
COR121 Detect
R121 12K1
PIR12101 PIR12102
NLSD20WP
SD2_WP 11
PIJ15011 Switch
S3C
WP COR144 NLCPLD0CFG2
R144
PIR14402
12K1
PIR14401
1% CPLD_CFG2 6
PIS306
3
PIS303
CHS-04TA
COC27
C27 12
PIJ15012 GND S3D
3.3V PIC2701 PIC2702 GND
MMC SD Socket COR31
R31PIR3102
12K1
PIR3101
1% NLCPLD0CFG3
CPLD_CFG3 5
PIS305
4
PIS304
10µF
CHS-04TA
10V GND
X5R
Title:
MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
Filename: LED_SW_BUT.SchDoc
1 2 3 4
1 2 3 4
COU12
U12
PIU1201
1 7
PIU1207 VOUT
12V_FUSED PIC302 PIC702 Vin Vout PIR201 PIC802 PIC1301 PIC1501 PIC1601 PIR15 01 5V
4.67V
COC3
C3 COC7
C7 2 5 COR2
R2 COC8
C8 COC13
C13 COC15
C15 COC16
C16 COR155
R155
GND PIU1202 SYNC FB PIU1205
22µF
PIC301 47nF
PIC701 5K6 PIC801 47nF PIC1302 100µF PIC1502 100µF PIC1602 100µF 27K
A 25V 50V PIR202 1% 50V 10V 10V 10V PIR15 02 1% A
3
PIU1203 6
PIU1206
AGND
GND
X7R EN SS/TRK PIC1701 X7R X5R X5R X5R PIC18 01 PIR160 1
X5R
GND GND COC17
C17 PIR401 COC181
C181 COR160
R160
4
8
PIU1204 PIU1208 470nF
PIC1702 COR4
R4 GND 10nF
PIC18 02 27K
171050601 50V 1K15 50V PIR160 2 1%
GND GND X7R PIR402 1% NLCPLD0ADC1
CPLD_ADC1 X7R
GND GND GND
GND
COU14
U14
1
PIU1401 7
PIU1407 VOUT
12V_FUSED PIC3702 PIC3802 Vin Vout PIR1901 PIC3902 PIC40 1 PIC9 01 PIC10 01 3.3V
3.30V
COC37
C37 COC38
C38 2 5 COR19
R19 COC39
C39 COC40
C40 COC99
C99 COC100
C100
GND PIU1402 SYNC FB PIU1405
PIC3701
22µF PIC3801
47nF 3K3 PIC3901 47nF PIC40 2 100µF PIC9 02 100µF PIC10 02 100µF
25V 50V 3
PIU1403 6
PIU1406 PIR1902 1% 50V 10V 10V 10V
AGND
GND
X7R 1.8V EN SS/TRK X7R X5R X5R X5R
X5R PIC102 1
GND GND COC102
C102 PIR20 1
4
8
PIU140 PIU1408 470nF
PIC102 COR20
R20 GND
171050601 50V 1K05
GND GND X7R PIR20 2 1%
B B
GND
AO4832 AO4832 GND
T5B COT5A
COT5B
T5A
PIT508 8 6
PIT506
PIT507 7 1
PIT501
PIT503 3 5
PIT505
2
4
PIT502 PIT504
PIR13501 PIR13601
COR135
R135 COR136
R136
10R 10R
PIR13502 PIR13602 SR= 2V/ms
COR137
R137
COC139
C139
PIR13701 PIR13702
PIC13901 PIC13902
5K1 10nF GND
50V
X7R
C COS1 C
HV S1
8
COJ11
J11 i COL5
L5 1 VIN
PIS101
NLVIN COU34
U34 PIU3408
1
PIJ1101
1
PIL501
4
PIL504
2
PIS102
1
PIU3401 Vin
7
PIU3407
PID501 PIR13801 PIR13901 Vout PIC14 01 12V_FUSED
3
PIS103
3 COD5
D5 2 3 COR138
R138 COR139
R139 COC144
C144
GATE
PIJ1103 PIL502 PIL503
1M 470K PIC14 02 10µF
PIS10F1 PIS10F2
F1
F2
2
PIJ1102 9µH PIR13802 1% PIR13902 1% 5
PIU3405 6
PIU3406
16V
NLPOWER0GND SHDN FAULT
POWER_GND PID502 2
PIU3402 UV
GNDX5R
Power Jack 2.1mm 90° SMD GND PIR140 1
SMBJ20A, 20V, 600W GND COR140
R140
A101J1AV2Q004 27K
OV = 14V
PIR140 2 1% 3
OV
UV = 10V
PIR14 01 PIU3403
COR141
R141
37K4
PIR14 02 1% 4
PIU3404 GND
Title:
GND LTC4365ITS8#TRMPBF MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
Filename: PowerMain.SchDoc
1 2 3 4
1 2 3 4
5V 1V
COU11
U11 COC6
C6
COR17
R17
PIR1701 PIR1702
PG_1V0 28
PIU11028
5
PIU1105 PIC601
X5R
PIC602
5V POK VOUT GND
10K COC41
C41 6
PIU1106 6.3V
VOUT 47µF
PIC4101 PIC4102 19
PIU11019 7
PIU1107
GND PVIN VOUT
20
PIU11020 8
PIU1108
A 22µF PVIN VOUT PIR4901 PIC1 101 A
21
PIU11021 9
PIU1109
25V PVIN VOUT COR49
R49 COC111
C111
10
PIU11010
X5R VOUT 200K PIC1 102 22pF
33
PIU11033 11
PIU11011
AVIN VOUT PIR4902
1% 6.3V
27
PIU11027 31
PIU11031 NP0
ENABLE VFB
1
PIU1101 NC(SW)
PIR50 1
2 COR50
R50
PIU1102 NC(SW)
12
PIU11012 26
PIU11026
604K
NC(SW) LLM/SYNC
3
PIU1103 NC
02
PIR51%
4
PIU1104 NC
22
PIU11022 NC
23
PIU11023 NC
24
PIU11024 29
PIU11029
NC RLLM
25
PIU11025 NC
34
PIU11034 NC(SW)
35
PIU11035
30
PIU11030
NC(SW) SS Soft-start 3.8ms
36
PIU11036
PIC1 901
NC(SW) COC119
C119
37
PIU11037 32
PIU11032
B NC(SW) AGND 47nF B
38
PIU11038 NC(SW)
PIC1 902
13
PIU11013
6.3V
PGND
17
PIU11017
14
PIU11014
GNDX5R
PGND PGND
18
PIU11018 15
PIU11015
PGND PGND
16
PIU11016 39
PIU11039
PGND PGND
GND EN6347QI GND
1V
C C
PIR16 02
5V COR161
R161
COU13
U13 10K
14
PIU13014 7
PIU1307
NLCPLD0ADC3
CPLD_ADC3 PIR16 01
PVIN VOUT 1.8V
PIC120 1 8
PIU1308
PIC12101 PIR1620 PIC18201
COC120
C120 VOUT COC121
C121 COR162
R162 COC182
C182
10µF
PIC120 2 COR51
R51 PIC12102 10µF 10K 10nF
PIC1820
PIR5101 PIR5102
13
PIU13013
5
PIU1305
10V AVIN VSENSE 10V NLCPLD0ADC2 50V
100R CPLD_ADC2 PIR16201
GNDX5R 12 4 GNDX5R PIC18301 X7R
1% PIU13012 ENABLE NC PIU1304
1 COC183
C183 GND
NLPG01V0 NC(SW) PIU1301 10nF
PG_1V0 3
PIU1303 LLM
15
NC(SW) PIU13015
PIC18302
16 50V
NC(SW) PIU13016 X7R
11
PIU13011 VS0
10
PIU13010 6
PIU1306 GND
VS1 AGND
9
PIU1309 VS2
2
PIU1302
5V PGND GND
Title:
EP53A7HQI MEGA65
D D
Number: Rev.
A4 TE0765
Default 02
Date: 2019-03-11 Copyright: Trenz Electronic GmbH / TT Page23 of 23
Filename: POWER.SchDoc
1 2 3 4
NEXYS WIDGET BOARD SCHEMATICS
289
C65 Keyboard Connector C64 Keyb Con
SV2
1 1
C65_ROW8 2 2
GND C65_REST 3 GND /REST 3
C65_COL8 4 4
C65_ROW7 5 ROW3 5
C65_ROW6 6 +3V3 ROW6 6
C65_ROW5 7 ROW5 7
+3V3
C65_ROW4 8 ROW4 8
C65_ROW3 9 ROW7 9
U1A U1B C65_ROW2 10 ROW2 10
G1 C65_ROW1 11 ROW1 11
C21
33pF
+3V3
- + 6 91 C65_ROW0 12 ROW0 12
VBAT VDD_2
Q1
GND
31 NRST 136 C65_COL7 13 COL0 13
NRST VDD_3
L1
GND CR2032H 36 30 149 C65_COL6 14 COL6 14
VDDA_2 PH1 R4 VDD_4
8Mhz
39 29 127 132 ST_D1 C65_COL5 15 COL5 15
C22
33pF
R3 VDDA PH0 VDD_5 PI1
49 103 131 ST_D0 C65_COL4 16 COL4 16
VDD_2 220R VDD_6 PI0
+3V3
GND
C17 C18 15 5 C65_ROW6 159 130 C64_/RW C65_COL3 17 COL3 17
47R VDD_3 PE6 VDD_7 PH15
23 4 C65_ROW5 114 129 C64_/IRQ C65_COL2 18 COL2 18
VDD_4 PE5 VDD_8 PH14
100nF 1µF 62 3 C65_ROW4 172 128 C64_/DMA C65_COL1 19 COL1 19
VDD_5 PE4 VDD PH13
72 2 C65_ROW3 89 C64_/EXROM C65_COL0 20 COL7 20
VDD_6 PE3 PH12
82 1 C65_ROW2 XADC3_N 92 176 ST_D7 C65_K1 21
VDD PE2 PB12 PI7
GND C20 C19 XADC3_P 93 175 ST_D6 C65_K2 22 SV1
PB13 PI6
PI8 7 88 C64_/GAME XADC4_N 94 174 ST_D5 23
PI8 PH11 PB14 PI5
R39 10k +3V3

100nF 1µF J2_BUTTON 8 87 C64_/ROMH XADC4_P 95 173 ST_D4 PWR_LED R5 POWER_LED 24
PC13 PH10 PB15 PI4 +3V3
/REST 9 86 C64_/ROML COL0 96 171 FDD_LED R6 100R FLOPPY_LED 25
PC14 PH9 PD8 PDR_ON
C65_REST 10 85 C64_I/O1 COL1 97 170 C65_ROW1 100R
PC15 PH8 PD9 PE1
PI9 11 84 C64_I/O2 COL2 98 169 C65_ROW0
PI9 PH7 PD10 PE0
PI10 12 83 C64_/NMI COL3 99 168 XADC1_P
PI10 PH6 PD11 PB9
PI11 13 81 COL4 100 167 XADC1_N
PI11 VCAP_1 PD12 PB8
+3V3
80 XADC2_P C30 COL5 101 166 BOOT0
PB11 PD13 BOOT0
ST_A0 16 79 XADC2_N 165 PB7 Joystick1
PF0 PB10 PB7
+3V3
ST_A1 17 78 C65_COL6 2,2µF COL6 104 164 PB6 R1 1k J1_UP

PF1 PE15 PD14 PB6 X3-1
ST_A2 18 77 C65_COL5 COL7 105 163 PWR_LED R23 1k J1_DOWN
PF2 PE14 PD15 PB5
R28 10k
R29 10k
1k X3-2
ST_A3 19 76 C65_COL4 JA3 106 162 FDD_LED R24 J1_LEFT
PF3 PE13 GND PG2 PB4 X3-3
ST_A4 20 75 C65_COL3 JA4 107 161 /R_W_D0-D7 R25 1k J1_RIGHT
PF4 PE12 PG3 PB3 X3-4
ST_A5 21 74 C65_COL2 JA7 108 160 JB10 POT1_Y
PF5 PE11 PG4 PG15 BOOT0 BOOT1 X3-5
ST_A6 24
PF6 PE10
73 C65_COL1 JA8 109
PG5 PG14
157 JB9 R27 1k J1_BUTTON X3-6
ST_A7 25 70 C65_COL0 JA9 110 156 JB8 R26 47R
PF7 PE9 PG6 PG13 X3-7
ST_A8 26 69 C65_ROW8 JA10 111 155 JB7
ST_A9 27 68 C65_ROW7 JB1 112 154 JB4 POT1_X
ST_A10 28 67 JA2 153 JB3 GND
PF10 PG1 PG10
R31 510R
R30 510R
C65_COL7 32 66 JA1 J1_LEFT 115 152 JB2

PC0 PG0 PC6 PG9
C65_COL8 33 65 ST_A15 J1_RIGHT 116 151 ROW7
PC1 PF15 PC7 PD7
C65_K1 34 64 ST_A14 J2_DOWN 117 150 ROW6
PC2 PF14 PC8 PD6
C65_K2 35 63 ST_A13 J2_UP 118 147 ROW5
PC3 PF13 PC9 PD5 GND GND
60 ST_A12 PA8 119 146 ROW4
PF12 PA8 PD4
38 59 ST_A11 PA9 120 145 ROW3
VREF+ PF11 PA9 PD3
58 BOOT1 PA10 121 144 ROW2 SV8
PB2 PA10 PD2
POT1_Y 40 57 /R_W_A8-15 USB_D_N 122 143 ROW1 1 Joystick2
PA0 PB1 PA11 PD1 VCC
+3V3
POT1_X 41 56 /R_W_A0-7 USB_D_P 123 142 ROW0 USB_D_N 2 R2 1k J2_UP

PA1 PB0 PA12 PD0 DM X5-1
POT2_Y 42 55 J1_DOWN PA13 124 141 J1_BUTTON USB_D_P 3 R7 1k J2_DOWN
PA2 PC5 PA13 PC12 DP X5-2
USB
RESET 43
PH2 PC4
54 J1_UP 125
VCAP_2 PC11
140 J2_RIGHT 4
GND R8 1k J2_LEFT X5-3
PH3 44
PH3 PA7
53 PA7 C29 PC10
139 J2_LEFT R9 1k J2_RIGHT X5-4
52 C64_CLOCK 135 138 PA15 USB-B-G-B POT2_Y
PA6 VSS_2 PA15 X5-5
14 51 C64_02 2,2µF 113 137 PA14 R22 1k J2_BUTTON
VSS_2 PA5 VSS_3 PA14 X5-6
71 50 C64_BA 126 134 ST_D3 R21 47R
VSS_3 PA4 VSS_4 PI3 GND X5-7
22 48 90 133 ST_D2
VSS_4 BYPASS_REG VSS_5 PI2 X5-8
61 47 POT2_X 148 POT2_X
VSS PA3 VSS_6 X5-9
46 C64_/RESET 102 GND
PH5 VSS_7
37 45 158
VSSA PH4 VSS
R38 10k
GND STM32F407IET6__FI__ STM32F407IET6__FI__
GND
GND
R36 100k +3V3
R32 +3V3
47R
NRST 1
PA14 R33 47R 2
C31 3
1 JP1
PA13 R34 47R 4
2
100nF R35 47R 5
GND NRST 6
+3V3
SV4
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16
GND
100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 1µF 1µF
GND
TITLE: c65Keyb
Document Number: REV:
Date: 6/05/2022 10:40 AM Sheet: 1/2

Nexys 4 Input Output Driver Expansion Slot
SV3
GND 1 A GND
VCC 2 B C64_/ROMH
VCC 3 C C64_/RESET GND
+3V3
+3V3
U2 GND VCC C64_/IRQ 4 D C64_/NMI
SV5
C64_A0 3 21 ST_A0 C64_/RW 5 E C64_02
12 11 A1 B1
C64_A1 4 20 ST_A1 C64_CLOCK 6 F C64_A15
10 9 A2 B2
C64_A2 5 19 ST_A2 C64_I/O1 7 H C64_A14
JB4 8 7 JB10 A3 B3
C64_A3 6 18 ST_A3 C64_/GAME 8 J C64_A13
GND JB3 6 5 JB9 GND A4 B4
C64_A4 7 17 ST_A4 C64_/EXROM 9 K C64_A12
JB2 4 3 JB8 A5 B5
C64_A5 8 16 ST_A5 C64_I/O2 10 L C64_A11
JB1 2 1 JB7 A6 B6
C64_A6 9 15 ST_A6 C64_/ROML 11 M C64_A10
A7 B7
C64_A7 10 14 ST_A7 C64_BA 12 N C64_A9
A8 B8
C64_/DMA 13 P C64_A8
/R_W_A0-7 2 C64_D7 14 R C64_A7
DIR
22 C64_D6 15 S C64_A6
OE
+3V3 C64_D5 16 T C64_A5
1 23 C64_D4 17 U C64_A4
VCCA VCCB
13 24 C64_D3 18 V C64_A3
VCC GND2 VCCB1
SV6 12 11 C64_D2 19 W C64_A2
GND1 GND
+3V3
+3V3
12 11 C64_D1 20 X C64_A1
10 9 744245 C64_D0 21 Y C64_A0
JA4 8 7 JA10 GND GND GND 22 Z GND
GND JA3 6 5 JA9 GND
JA2 4 3 JA8 EDGE-CON-44P
JA1 2 1 JA7 U3 GND GND
C64_A8 3 21 ST_A8
A1 B1
C64_A9 4 20 ST_A9
A2 B2
C64_A10 5 19 ST_A10
A3 B3
C64_A11 6 18 ST_A11
A4 B4
C64_A12 7 17 ST_A12
A5 B5
VCC
C64_A13 8 16 ST_A13
A6 B6
SV7 C64_A14 9 15 ST_A14
A7 B7 R11
+3V3
+3V3
C64_A15 10 14 ST_A15 C64_/RW
12 11 A8 B8
VCC
VCC
10 9 3k3 SV9
+3V3
+3V3
/R_W_A8-15 2
XADC4_P 8 7 XADC4_N DIR R12 20 19
22 C64_/IRQ
GND XADC3_P 6 5 XADC3_N GND OE 18 17
4 3 +3V3 3k3 16 15
XADC2_P XADC2_N 1 23 PH3
XADC1_P 2 1 XADC1_N VCCA VCCB R13 PH2 14 13 PI11
13 24 C64_/DMA
VCC GND2 VCCB1 PI10 12 11 PI9
12 11
GND1 GND 3k3 PI8 10 9 PB7
R14 PB6 8 7 PA15
744245 C64_/EXROM 6 5
PA10 PA9
3k3 PA8 4 3 PA7
GND GND R15 2 1
C64_/GAME
U4 3k3
3 21
R16 GND GND
C64_D0 A1 B1 ST_D0 C64_/ROMH
C64_D1 4 20 ST_D1
A2 B2 3k3
C64_D2 5 19 ST_D2
A3 B3 R17
C64_D3 6 18 ST_D3 C64_/ROML
A4 B4
C64_D4 7 17 ST_D4
A5 B5 3k3
C64_D5 8 16 ST_D5
A6 B6 R18
C64_D6 9 15 ST_D6 C64_I/O1
A7 B7
C64_D7 10 14 ST_D7
A8 B8 3k3
VCC
S1
+3V3
2
R19
/R_W_D0-D7 DIR C64_I/O2
22
1 OE 3k3
J2 2 +3V3 R20
3 1 23 C64_/NMI
3 VCCA VCCB
2 X4-3 13 24
B1 VCC GND2 VCCB1 3k3
1 12 11
GND1 GND R10
X4-2 C64_/RESET
GND
744245 3k3
X4-1
MKDS_5/3-6,35 GND GND
C32
100nF
GND
RESET SW1
VCC
+3V3
+3V3
R37 2 1
3k3 C23 C24 C25 C26 C27 C28
3 4
100nF 100nF 100nF 100nF 100nF 100nF
GND GND GND
GND
TITLE: c65Keyb
Document Number: REV:
Date: 6/05/2022 10:40 AM Sheet: 2/2

71R
31R
61R
81R
51R
91R
41R
21R
01R
11R
02R
1R
72R
32R
62R
42R
52R
2R 3R
22R
7R 83R 71C 7C
81C 3C
12R 51C
8R
9R 21C
92R 03R 41C
61C
5C
6C
23C
2C
1C
03C
6R
5R
73R
33R 23R
63R
43R
53R
13C
mottoB
APPENDIX D
Supporters & Donors
• Organisations
• Contributors
• Supporters
294
The MEGA65 would not have been possible to create without the generous support
of many organisations and individuals.
We are still compiling these lists, so apologies if we haven’t included you yet. If you
know anyone we have left out, please let us know, so that we can recognise the con-
tribution of everyone who has made the MEGA65 possible, and into the great retro-
computing project that it has become.
ORGANISATIONS
The MEGA Museum of Electronic Games & Art e.V. Germany
EVERYTHING
Trenz Electronic, Germany
MOTHERBOARD MANUFACTURING SALES
Hintsteiner, Austria
CASE
GMK, Germany
KEYBOARD
KEVAG Telekom, Germany
WEB HOSTING
295
CONTRIBUTORS
Andreas Liebeskind Dr. Canan Hastik
(libi in paradize) (indica)
CFO MEGA eV Chairwoman MEGA eV
Thomas Hertzler Simon Jameson
(grumpyninja) (Shallan)
USA spokesman Platform enhancements
Russell Peake Stephan Kleinert

(ubik)
(rdpeake)
Destroyer of BASIC 10
Bug herding
Wayne Johns
Alexander Nik Petra (sausage)
(n0d) Manual additions
Early case design
L. Kleiss
Ralph Egas (LAK132)
(0-limits) MegaWAT presentation software
Business advisor
Maurice van Gils
Lucas Moss (Maurice)
MEGAphone PCB design BASIC 65 example programs
Daren Klamer Andrew Owen
(Impakt) (Cheveron)
Manual proof-reading Keyboard, Sinclair support
Daniël Mantione Adam Barnes
(dmantione) (amb5l)
C64 hardware guru HDMI expert and board revision
296
SUPPORTERS
3c74ce64 Arne Neumann Christian Gräfe
8-Bit Classics Arne Richard Tyarks Christian Heffner
@11110110100 Axel Klahr Christian Kersting
Aaron Smith Balaz Ondrej Christian Schiller
Achim Mrotzek Barry Thompson Christian Streck
Adolf Nefischer Bartol Filipovic Christian Weyer
Adrian Esdaile Benjamin Maas Christian Wyk
Adrien Guichard Bernard Alaiz Christoph Haug
Ahmed Kablaoui Bernhard Zorn Christoph Huck
Alan Bastian Witkowski Bieno Marti-Braitmaier Christoph Pross
Alan Field Bigby Christopher Christopher
Alastair Paulin-Campbell Bill LaGrue Christopher Kalk
Alberto Mercuri Bjoerg Stojalowski Christopher Kohlert
Alexander Haering Björn Johannesson Christopher Nelson
Alexander Kaufmann Bjørn Melbøe Christopher Taylor
Alexander Niedermeier Bo Goeran Kvamme Christopher Whillock
Alexander Soppart Boerge Noest Claudio Piccinini
Alfonso Ardire Bolko Beutner Claus Skrepek
Amiga On The Lake Brett Hallen Collen Blijenberg
André Kudra Brian Gajewski Constantine Lignos
André Simeit Brian Green Crnjaninja
André Wösten Brian Juul Nielsen Daniel Auger
Andrea Farolfi Brian Reiter Daniel Julien
Andrea Minutello Bryan Pope Daniel Lobitz
Andreas Behr Burkhard Franke Daniel O’Connor
Andreas Freier Byron Goodman Daniel Teicher
Andreas Grabski Cameron Roberton (KONG) Daniel Tootill
Andreas Millinger Carl Angervall Daniel Wedin
Andreas Nopper Carl Danowski Daniele Benetti
Andreas Ochs Carl Stock Daniele Gaetano Capursi
Andreas Wendel Manufaktur Carl Wall Dariusz Szczesniak
Andreas Zschunke Carlo Pastore Darrell Westbury
Andrew Bingham Carlos Silva David Asenjo Raposo
Andrew Dixon Carsten Sørensen David Dillard
Andrew Mondt Cenk Miroglu Miroglu David Gorgon
Andrzej Hłuchyj Chang sik Park David Norwood
Andrzej Sawiniec Charles A. Hutchins Jr. David Raulo
Andrzej Śliwa Chris Guthrey David Ross
Anthony W. Leal Chris Hooper de voughn accooe
Arkadiusz Bronowicki Chris Stringer Dean Scully
Arkadiusz Kwasny Christian Boettcher Dennis Jeschke
Arnaud Léandre Christian Eick Dennis Schaffers
Arne Drews Christian Gleinser Dennis Schierholz
297
Dennis Schneck Frank Haaland Helge Förster
denti Frank Hempel Hendrik Fensch
Dick van Ginkel Frank Koschel Henning Harperath
Diego Barzon Frank Linhares Henri Parfait
Dierk Schneider Frank Sleeuwaert Henrik Kühn
Dietmar Krueger Frank Wolf Holger Burmester
Dietmar Schinnerl FranticFreddie Holger Sturk
Dirk Becker Fredrik Ramsberg Howard Knibbs
Dirk Wouters Fridun Nazaradeh Hubert de Hollain
Domingo Fivoli Friedel Kropp Huberto Kusters
DonChaos Garrick West Hugo Maria Gerardus v.d. Aa
Donn Lasher Gary Lake-Schaal Humberto Castaneda
Douglas Johnson Gary Pearson Ian Cross
Dr. Leopold Winter Gavin Jones IDE64 Staff
Dusan Sobotka Geir Sigmund Straume Igor Ianov
Earl Woodman Gerd Mitlaender Igor Kurtes
Ed Reilly Giampietro Albiero Immo Beutler
Edoardo Auteri Giancarlo Valente Ingo Katte
Eduardo Gallardo Gianluca Girelli Ingo Keck
Eduardo Luis Arana Giovanni Medina Insanely Interested Publishing
Eirik Juliussen Olsen Glen Fraser IT-Dienstleistungen Obsieger
Emilio Monelli Glen R Perye III Ivan Elwood
EP Technical Services Glenn Main Jaap HUIJSMAN
Epic Sound Gordon Rimac Jace Courville
Erasmus Kuhlmann GRANT BYERS Jack Wattenhofer
ergoGnomik Grant Louth Jakob Schönpflug
Eric Hilaire Gregor Bubek Jakub Tyszko
Eric Hildebrandt Gregor Gramlich James Hart
Eric Hill Guido Ling James Marshburn
Eric Jutrzenka Guido von Gösseln James McClanahan
Erwin Reichel Guillaume Serge James Sutcliffe
Espen Skog Gunnar Hemmerling Jan Bitruff
Evangelos Mpouras Günter Hummel Jan Hildebrandt
Ewan Curtis Guy Simmons Jan Iemhoff
Fabio Zanicotti Guybrush Threepwood Jan Kösters
Fabrizio Di Dio Hakan Blomqvist Jan Peter Borsje
Fabrizio Lodi Hans Pronk Jan Schulze
FARA Gießen GmbH Hans-Jörg Nett Jan Stoltenberg-Lerche
FeralChild Hans-Martin Zedlitz Janne Tompuri
First Choice Auto’s Harald Dosch Jannis Schulte
Florian Rienhardt Harri Salokorpi Jari Loukasmäki
Forum64. de Harry Culpan Jason Smith
Francesco Baldassarri Harry Venema Javier Gonzalez Gonzalez
Frank Fechner Heath Gallimore Jean-Paul Lauque
Frank Glaush Heinz Roesner Jeffrey van der Schilden
Frank Gulasch Heinz Stampfli Jens Schneider
298
Jens-Uwe Wessling Kenneth Joensson Marco Cappellari
Jesse DiSimone Kevin Edwards Marco Rivela
Jett Adams Kevin Thomasson Marco van de Water
Johan Arneklev Kim Jorgensen Marcus Gerards
Johan Berntsson Kim Rene Jensen Marcus Herbert
Johan Svensson Kimmo Hamalainen Marcus Linkert
Johannes Fitz Konrad Buryło Marek Pernicky
John Cook Kosmas Einbrodt Mario Esposito
John Deane Kurt Klemm Mario Fetka
John Dupuis Lachlan Glaskin Mario Teschke
John Nagi Large bits collider Mariusz Tymków
John Rorland Lars Becker Mark Adams
John Sargeant Lars Edelmann Mark Anderson
John Traeholt Lars Slivsgaard Mark Green
Jon Sandelin Lasse Lambrecht Mark Hucker
Jonas Bernemann Lau Olivier Mark Leitiger
Jonathan Prosise Lee Chatt Mark Spezzano
Joost Honig Loan Leray Mark Watkin
Jordi Pakey-Rodriguez Lorenzo Quadri Marko Rizvic
Jöre Weber Lorenzo Travagli Markus Bieler
Jörg Jungermann Lorin Millsap Markus Bonet
Jörg Schaeffer Lothar James Foss Markus Dauberschmidt
Jörg Weese Lothar Serra Mari Markus Fehr
Josef Hesse Luca Papinutti Markus Fuchs
Josef Soucek Ludek Smetana Markus Guenther-Hirn
Josef Stohwasser Lukas Burger Markus Liukka
Joseph Clifford Lutz-Peter Buchholz Markus Merz
Joseph Gerth Luuk Spaetgens Markus Roesgen
Jovan Crnjanin Mad Web Skills Markus Uttenweiler
Juan Pablo Schisano MaDCz Martin Bauhuber
Juan S. Cardona Iguina Magnus Wiklander Martin Benke
JudgeBeeb Maik Diekmann Martin Gendera
Juliussen Olsen Malte Mundt Martin Groß
Juna Luis Fernandez Garcia Manfred Wittemann Martin Gutenbrunner
Jürgen Endras Manuel Beckmann Martin Johansen
Jürgen Herm Stapelberg Manzano Mérida Martin Marbach
Jyrki Laurila Marc ”3D-vice” Schmitt Martin Sonnleitner
Kai Pernau Marc Bartel Martin Steffen
Kalle Pöyhönen Marc Jensen Marvin Hardy
Karl Lamford Marc Schmidt Massimo Villani
Karl-Heinz Blum Marc Theunissen Mathias Dellacherie
Karsten Engstler Marc Tutor Mathieu Chouinard
Karsten Westebbe Marc Wink Matthew Adams
katarakt Marcel Buchtmann Matthew Browne
Keith McComb Marcel Kante Matthew Carnevale
Kenneth Dyke Marco Beckers Matthew Palmer
299
Matthew Santos Michele Porcu Paul Jackson
Matthias Barthel Miguel Angel Rodriguez Jodar Paul Johnson
Matthias Dolenc Mikael Lund Paul Kuhnast (mindrail)
Matthias Fischer Mike Betz Paul Massay
Matthias Frey Mike Kastrantas Paul Westlake
Matthias Grandis Mike Pikowski Paul Woegerer
Matthias Guth Mikko Hämäläinen Pauline Brasch
Matthias Lampe Mikko Suontausta Paulo Apolonia
Matthias Meier Mirko Roller Pete Collin
Matthias Mueller Miroslav Karkus Pete of Retrohax.net
Matthias Nofer Morgan Antonsson Peter Eliades
Matthias Schonder Moritz Peter Gries
Maurice Al-Khaliedy Morten Nielsen Peter Habura
Max Ihlenfeldt MUBIQUO APPS,SL Peter Herklotz
Meeso Kim Myles Cameron-Smith Peter Huyoff
Michael Dailly Neil Moore Peter Knörzer
Michael Dötsch Nelson Peter Leswell
Michael Dreßel neoman Peter Weile
Michael Fichtner Nicholas Melnick Petri Alvinen
Michael Fong Nikolaj Brinch Jørgensen Philip Marien
Michael Geoffrey Stone Nils Andreas Philip Timmermann
Michael Gertner Nils Eilers Philipp Rudin
Michael Grün Nils Hammerich Pierre Kressmann
Michael Habel Nils77 Pieter Labie
Michael Härtig Norah Smith Piotr Kmiecik
Michael Haynes Norman King Power-on.at
Michael J Burkett Normen Zoch Przemysław Safonow
Michael Jensen Olaf Grunert Que Labs
Michael Jurisch Ole Eitels R Welbourn
Michael Kappelgaard Oliver Boerner R-Flux
Michael Kleinschmidt Oliver Brüggmann Rafał Michno
Michael Lorenz Oliver Graf Rainer Kappler
Michael Mayerhofer Oliver Smith Rainer Kopp
Michael Nurney Olivier Bori Rainer Weninger
Michael Rasmussen ONEPSI LLC Ralf Griewel
Michael Richmond oRdYNe Ralf Pöscha
Michael Sachse Osaühing Trioflex Ralf Reinhardt
Michael Sarbak OSHA-PROS USA Ralf Schenden
Michael Schneider Padawer Ralf Smolarek
Michael Scholz Patrick Becher Ralf Zenker
Michael Timm Patrick Bürckstümmer Ralph Bauer
Michael Traynor Patrick de Zoete Ralph Wernecke
Michael Whipp Patrick Toal Rédl Károly
Michal Ursiny Patrick Vogt Reiner Lanowski
Michele Chiti Paul Alexander Warren Remi Veilleux
Michele Perini Paul Gerhardt (KONG) Riccardo Bianchi
300
Richard Englert Sigurbjorn Larusson Thomas Niemann
Richard Good Sigurdur Finnsson Thomas Scheelen
Richard Menedetter Simon Lawrence Thomas Schilling
Richard Sopuch Simon Wolf Thomas Tahsin-Bey
Rick Reynolds spreen.digital Thomas Walter
Rico Gruninger Stefan Haberl Thomas Wirtzmann
Rob Dean Stefan Kramperth Thorsten Knoll
Robert Bernardo Stefan Richter Thorsten Nolte
Robert Eaglestone Stefan Schultze Tim Krome
Robert Grasböck Stefan Sonnek Tim Waite
Robert Miles Stefan Theil Timo Weirich
Robert Schwan Stefan Vrampe Timothy Blanks
Robert Shively Stefano Canali Timothy Henson
Robert Tangmar Stefano Mozzi Timothy Prater
Robert Trangmar Steffen Reiersen Tobias Butter
Rodney Xerri Stephan Bielmann Tobias Heim
Roger Olsen Stephen Jones Tobias Köck
Roger Pugh Stephen Kew Tobias Lüthi
Roland Attila Kett Steve Gray Tommi Vasarainen
Roland Evers Steve Kurlin Toni Ammer
Roland Schatz Steve Lemieux Tore Olsen
Rolf Hass Steven Combs Torleif Strand
Ronald Cooper Stewart Dunn Torsten Schröder
Ronald Hunn Stuart Marsh Tuan Nguyen
Ronny Hamida Sven Neumann Uffe Jakobsen
Ronny Preiß Sven Stache Ulrich Hintermeier
Roy van Zundert Sven Sternberger Ulrich Nieland
Rüdiger Wohlfromm Sven Wiegand Ulrik Kruse
Ruediger Schlenter Szabolcs Bence Urban Lindeskog
Rutger WIllemsen Tantrumedia Limited Ursula Förstle
Sampo Peltonen Techvana Operations Ltd. Uwe Anfang
Sarmad Gilani Teddy Turmeaux Uwe Boschanski
SAS74 Teemu Korvenpää Vedran Vrbanc
Sascha Hesse The Games Foundation Verm Project
Scott Halman Thierry Supplisson Wayne Rittimann
Scott Hollier Thieu-Duy Thai Wayne Sander
Scott Robison Thomas Bierschenk Wayne Steele
Sebastian Baranski Thomas Edmister Who Knows
Sebastian Bölling Thomas Frauenknecht Winfried Falkenhahn
Sebastian Felzmann Thomas Gitzen Wolfgang Becker
Sebastian Lipp Thomas Gruber Wolfgang Stabla
Sebastian Rakel Thomas Haidler Worblehat
Şemseddin Moldibi Thomas Jager www.patop69.net
Seth Morabito Thomas Karlsen Yan B
Shawn McKee Thomas Laskowski Zoltan Markus
Siegfried Hartmann Thomas Marschall Zsolt Zsila
Zytex Online Store
301
302
Bibliography
304
[1] L. Soares and M. Stumm, “Flexsc: Flexible system call scheduling with exception-
less system calls.” in Osdi, vol. 10, 2010, pp. 1–8.
[2] N. Montfort, P. Baudoin, J. Bell, I. Bogost, J. Douglass, M. C. Marino, M. Mateas,
C. Reas, M. Sample, and N. Vawter, 10 PRINT CHR $(205.5+ RND (1));: GOTO 10.
MIT Press, 2012.
[3] Actraiser, “Vic-ii for beginners: Screen modes, cheaper by the
dozen,” 2013. [Online]. Available: http://dustlayer.com/vic-ii/2013/4/26/
vic-ii-for-beginners-screen-modes-cheaper-by-the-dozen
305
306
INDEX
308
altpal, 48 gotoy, 53
Apple, 16
highlight, 48
bgcolor, 47 hline, 52
blink, 48 Hyppo Error Codes, 93, 95
bordercolor, 47 $01, 95
box, 51 $02, 95
$03, 95
cellcolor, 49 $04, 95
cgetc, 59 $05, 95
cinput, 60 $06, 95
clearattr, 49 $07, 95
clrscr, 45 $08, 95, 120
conionit, 43 $10, 95, 98, 120, 126, 133,
copyright, ii 135, 143
cprintf, 58 $11, 96
cputc, 56 $20, 96
cputcxy, 55, 57 $21, 96
cputdec, 57 $80, 96, 125
cputhex, 56 $81, 96, 126
cputnc, 56 $82, 96
cputncxy, 58 $83, 96
cputs, 57 $84, 96, 115, 116, 118, 119
cputsxy, 57 $85, 96, 121
$86, 96, 119
emulator, 15 $87, 96, 99, 118
$88, 96, 106–108, 115, 116,
fillrect, 51 128
Flash Menu, 85 $89, 96, 122
flushkeybuf, 60 $8A, 96
Freeze Menu, 85 $8B, 96
$8C, 96
getcharsetaddr, 45 $8D, 96, 117, 124
getcolramoffset, 44 $8E, 96
getkeymodstate, 60 $FF, 96
getmapedpal, 50 Hyppo Move to Root Directory, 101
getpalbank, 50 Hyppo Services, 91
getpalbanka, 50 $D640 $00, 97
getscreenaddr, 44 $D640 $02, 113
getscreensize, 45 $D640 $04, 111
gohome, 52 $D640 $06, 125
gotox, 53 $D640 $08, 114
gotoxy, 52 $D640 $0A, 112
309
$D640 $0C, 99 $D640 $6C, 144
$D640 $0E, 117 $D640 $6E, 132
$D640 $10, 124 $D640 $70, 146
$D640 $12, 118 $D640 $72, 145
$D640 $14, 120 $D640 $74, 133
$D640 $16, 103 $D640 $76, 143
$D640 $18, 119 $D640 $7C, 142
$D640 $1A, 122 $D640 $7E, 137
$D640 $1C, 127 $D641 $00, 139
$D640 $1E, 117 $D641 $02, 138
$D640 $20, 104 $D642 $00, 148
$D640 $22, 102 $D642 $02, 148
$D640 $24, 124 $D642 $04, 148
$D640 $26, 124 $D642 $06, 148
$D640 $28, 110 $D642 $10, 149
$D640 $2A, 124 $D642 $12, 149
$D640 $2C, 105 $D642 $14, 149
$D640 $2E, 126 $D642 $16, 149
$D640 $30, 107 $D643 $xx, 141
$D640 $32, 108 $D67F $xx, 149
$D640 $34, 106
$D640 $36, 115 kbhit, 59
$D640 $38, 95 keyboard, 15
$D640 $3A, 98
macOS, 16
$D640 $3C, 101
MEGA Flash, 85
$D640 $3E, 116
movedown, 54
$D640 $40, 128
moveleft, 54
$D640 $42, 130
moveright, 54
$D640 $44, 131
moveup, 53
$D640 $46, 129
$D640 $48, 134 OpenROMs, 18
$D640 $50, 136
$D640 $52, 140 pcprintf, 59
$D640 $54, 136 pcputc, 55
$D640 $56, 147 pcputs, 56
$D640 $58, 136 pcputsxy, 55
$D640 $60, 144
$D640 $62, 132 Registers
$D640 $64, 136 $D640, 91
$D640 $66, 132 $D641, 91
$D640 $68, 132 $D642, 91
$D640 $6A, 132 $D643, 91
310
$D644, 91 $D66F, 91
$D645, 91 $D670, 91
$D646, 91 $D671, 91
$D647, 91 $D672, 91
$D648, 91 $D673, 91
$D649, 91 $D674, 91
$D64A, 91 $D675, 91
$D64B, 91 $D676, 91
$D64C, 91 $D677, 91
$D64D, 91 $D678, 91
$D64E, 91 $D679, 91
$D64F, 91 $D67A, 91
$D650, 91 $D67B, 91
$D651, 91 $D67C, 91
$D652, 91 $D67D, 91
$D653, 91 $D67E, 91
$D654, 91 $D67F, 91
$D655, 91 revers, 47
$D656, 91 Root directory, 101
$D657, 91
$D658, 91 SD card, 17
$D659, 91 set16bitcharmode, 46
$D65A, 91 setcharsetaddr, 44
$D65B, 91 setcolramoffset, 44
$D65C, 91 setextendedattrib, 46
$D65D, 91 sethotregs, 46
$D65E, 91 setmapedpal, 50
$D65F, 91 setpalbank, 49
$D660, 91 setpalbanka, 49
$D661, 91 setpalentry, 50
$D662, 91 setscreenaddr, 43
$D663, 91 setscreensize, 45
$D664, 91
$D665, 91 textcolor, 47
$D666, 91 togglecase, 46, 47
$D667, 91
$D668, 91 underline, 48
$D669, 91 Utility Menu, 85
$D66A, 91
$D66B, 91 vline, 52
$D66C, 91
$D66D, 91 wherex, 54
$D66E, 91 wherey, 55
311

Mega65 Developer Guide

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Mega65 Developer Guide

Uploaded by

Copyright:

Available Formats

MEGA65 TEAM

Dr. Paul Gardner-Stephen Detlef Hastik

Martin Streit Oliver Graf

Gábor Lénárt Gürçe Işıkyıldız

2 Welcome, and thank you! 3

II CROSS-PLATFORM DEVELOPMENT TOOLS 11

5 Data Transfer and Debugging Tools 21

7 C and C-Like Compilers 37

8 MEGA65 Standard C Library 41

III NATIVE DEVELOPMENT TOOLS 67

10 C65 Memory Monitor 69

11 MEGA65 Matrix Mode 71

13 Dealing with C65 and C64-mode 75

IV MEGA65 Operating System 79

14 Developing System Programmes 81

15 MEGA65 Hyppo Services 89

V MULTI-MEDIA AND DATA CONVERSION 151

VI GEOS Development 153

VII HARDWARE 155

16 Using Nexys4 boards as a MEGA65 157

VIII APPENDICES 179

A Flashing the FPGAs and CPLDs in the MEGA65 181

B Trouble shooting 233

D Supporters & Donors 293

OTHER BOOKS IN THIS SERIES

COME JOIN US!

USING THE XMEGA65 EMULATOR

Please be aware the emulator by default catches F9 F10 F11 as shortcuts

Apple MacOS start problems

The Xemu system folder location varies by operating system:

USING THE LIVE ISO IMAGE

Creating a Bootable USB stick or DVD

Other Features of the Live ISO

M65 COMMAND LINE TOOL

Screenshots using m65 tool

This will create a file called mega65-screeen-000000.png, or if that file already

m65 -F -4 -r foo . prg

Reconfigure the FPGA to run a different bitstream

Remote keyboard entry

This would cause the LIST command to be typed and executed.

Unit testing and logging support

m65 - Fur attic - ram . prg -w tests . log

Using unit tests with C

Using unit tests with BASIC 65

m65 -@ mega65 - tools / bin65 / b 6 5 s u p p o r t . b i n @ 1 5 f e

BLOAD " B 6 5 S U P P O R T . BIN "

After loading, b65support.bin is initialised with

Once initialised, the following functions are provided by b65support.bin:

A = USR ("= < testName >")

A = USR ("/ < logMessage >)

sends a log message to the host computer

A = USR (" P ")

A = USR (" F ")

A = USR (" D ")

sends the ’test done’ signal to the host computer

CONVERTING A BASIC TEXT FILE

C64List program.txt -prg

Name 45GS02 Source Reference

the processor’s features

STRUCTURE AND USAGE

Return Value: The current color RAM start offset value.

Parameters: addr: The address to set as start of character set

Return Value: The current character set start address.

Notes: Color RAM will be cleared with current text color