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40.68 MHz Digital On-Off Delay-Compensated

Active Rectifier for WPT of Biomedical Applications
Soumitra Pal, Student Member, IEEE, and Wing-Hung Ki, Member, IEEE

VDC

Abstract— A digitally controlled on-off delay-compensated 40.68

MHz full-wave active rectifier is proposed for wireless power C1 k MP1 MP2
transfer (WPT) of biomedical applications. It consists of two NMOS
active diodes and a cross-coupled PMOS transistor-pair. High L1 L2 VAC1
CO RL
efficiency is achieved by digital techniques that eliminate turn-on C2
VAC2
delay, reverse current and multiple pulsing. The proposed design VS
and one state-of-the-art design are implemented with 0.13 µm
IAC1 IAC2
CMOS process for comparison. The measured maximum voltage
VGN1 Parasitic VGN2
conversion ratio (VCR) is 0.97, and the measured maximum power CMP1 diode CMP2
conversion efficiency (PCE) is 93.2% for a 500 Ω load resistance. helping
MN1 start-up MN2
Index Terms—Full-wave active rectifier, inductive link, wireless
power transfer, on-off delay, offset control, multiple-pulsing, Active diode 1 Active diode 2
implantable medical devices. Fig. 1. A generic WPT system with a full-wave active rectifier.

1.2
I. INTRODUCTION
0.6
W IRELESS power transfer (WPT) through an inductive link is
able to provide stable and reliable power to implantable
medical devices (IMDs). These IMDs normally need power in
V (V)
0.0
VAC

-0.6
the order of milli-Watt (mW) [1]–[3]. A generic WPT system
with a full-wave active rectifier is shown in Fig. 1. A full-wave -1.2
1.2
rectifier is preferred to a half-wave rectifier because it delivers a VDC
higher DC output voltage (VDC) for the same AC input voltage 0.8
V (V)

(VAC). To enhance voltage conversion ratio (VCR) and power 0.4

conversion efficiency (PCE), passive diodes or diode-connected VAC2 VAC1 VAC2
transistors are replaced by a pair of cross-coupled PMOS 0.0
transistor-pair and two NMOS active diodes, as shown in Fig. 1. -0.4 turn-off
1.2 turn-on
Different frequencies such as 6.78 MHz, 13.56 MHz and 40.68 delay
delay VGN2
MHz for the power link have been proposed in the past [4]–[8]. 0.8 VGN2 VGN1
V (V)

Although the specific absorption rate (SAR) is higher for 40.68 0.4
MHz, the resonant capacitor and the filtering capacitor can be
reduced by almost 9× and 3×, respectively, compared to 13.56 0.0
MHz, and is more suitable for IMDs such as eye implants [8]. -0.4
Therefore, 40.68 MHz is used in this research. At such a high 60
IAC2 IAC1 IAC2
frequency, the power switches (MN1, MN2) cannot be turned on 40
I (mA)

and off at the exact trip points due to delays of the comparators
and buffers. These delays limit the dynamic performance. Due to
turn-on delay, power is not delivered to the load for the required
amount of time, increasing the peak current (Fig. 2) and limiting
the highest operation frequency [7]; and due to turn-off delay,
reverse current could flow back from the output capacitor to
ground through MN1 and MN2 (Fig. 2) [7].
Many on-/off-delay compensated rectifiers have been
suggested in the past [1]–[3], [7]–[10]. In [1] off-delay
compensation is realized by using input transistors with
asymmetric sizes to introduce offset to the comparators at the
expense of further increasing the on-delay. In [2], [7] off-delay
compensation is realized by adding offset currents to the
The authors are with the Department of Electronic and Computer Engineering,
The Hong Kong University of Science and Technology, Clear Water Bay, Hong
Kong (e-mail: spal@connect.ust.hk; eeki@ust.hk).
Corresponding author: Soumitra Pal.
20
0
-20 Reverse current
10.473 10.492 10.511
time (us)
Fig. 2. Simulated waveform of a generic active rectifier at 40.68 MHz.
comparators to reduce the reverse current, but the active rectifiers
still suffer from inherent on-delay caused by the comparators and
buffers. Both on-delay and off-delay are compensated in [3], [9].
However, they suffer from multiple-pulsing problem, which
hurts the efficiency [7]. Besides, the on-delay compensation
current in [9] is unnecessarily added to the comparator for a long
duration, after the power MOS is turned off until it turns back on
again. Another drawback of [9] is to use 2-bit off-chip signals to
control each offset-control block. In [3] both on-delay and off-
delay compensation currents are added for the entire half-cycle

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Ib If Ib In In Ib If Ib VDC Ib If Ib In In Ib If Ib
Vb
Mf1C Mb1D Mn1CMn1D Mf1D Mb1H Mb2H Mf2D Mn2DMn2C Mb2D Mf2C
Mb1C MP1 MP2 Mb2G
Mb1G Mb2C
VON1 VON2
Mn1A Mn1B Mn2B Mn2A
VOUT1 VOUT2
VGN1 VAC1 VAC2 VGN2
Mf1A Mf1B Mf2B Mf2A
BUF1 BUF2
V1A V1B V2B V2A

MN1 MN2
VGN1 VGN2
Md1 Mb1E Mb2E Md2
Mb1A IAC1 IAC2 Mb2F Mb2B
Mb1B VGd1 Mb1F VGd2 Mb2A
VAC1 VAC2

Active diode 1 Active diode 2

(a)
VDC into the comparators just when they are needed, only for short
durations within one cycle, such that both VCR and PCE are
Q D D Q
VON1 Mq1B VGN2 VGN1 Mq2B VON2 enhanced. Push-pull common-gate comparators [11] with input
stages capable of ground-sensing are used. These differential
Mq1A VGd2 RST DFF1 RST VGd1 Mq2A current-mode comparators have bias currents Ib's (= 2 µA)
VAC1 DFF2 VAC2 derived from the bias voltage Vb, which is generated from a
INV1 INV2
peaking current source [7] to minimize sensitivity due to
VGN1 VGN2 variation in |VAC| that affects the rectifier output voltage VDC.
(b) VDC
Fig. 3. (a) Circuit implementation of the proposed digitally controlled on-off
1.2
delay compensated full-wave rectifier, (b) control logic. VGN2 VGN1 VGN2
0.8
V (V)

and PCE is reduced. Adaptive on-off delay-compensated active

0.4
rectifiers are suggested in [8], [10]. They use analog circuits such VAC2 VAC1 VAC2
as sample-and-hold circuit and OTA that consume large 0.0
quiescent power to achieve faster response to fully compensate
for the delays. The only rectifier that works at 40.68 MHz uses 1.2
off chip tuning to compensate for on-delay, and is not a favorable VGd1 VGd2 VGd1 VGd2
0.8
V (V)

feature [8]. In view of the above, we propose a digital on-off

delay-compensated active rectifier, where the compensation 0.4
currents are added to the comparator just before they are
supposed to turn on or off, to reduce the above delays. 0.0
The rest of the paper is organized as follows. The proposed
design is discussed in Sec. II. Measurement results are 1.2
demonstrated in Sec. III. Finally, Sec. IV concludes the paper. 0.8
V (V)

II. DIGITAL CONTROLLED ON/OFF DELAY-COMPENSATION 0.4

The operating principle of an active rectifier is well established, VON2 VON1 VON2
and interested readers could refer to [7]. The proposed digitally 0.0
controlled on-off delay-compensated active rectifier is shown in
Fig. 3. The active rectifier is made up of four power devices. The 20
IAC2 Turn-on and IAC1 Turn-on and IAC2
upper power switches MP1 and MP2 are crossed-coupled and self- 15
-off delays -off delays
biased. The lower power switches MN1 and MN2 are active diodes
I (mA)

10 are fully are fully

that are controlled by the left and right comparators and buffers, compensated compensated
5
respectively (Fig. 3(a)). The comparators are current-mode
comparators with transistors sourcing three sets of currents: the 0
bias currents Ib with subscript "b"; the on-delay compensation No Reverse current
-5
currents In with subscript "n"; and the off-delay compensation 10.473 10.492 10.511
currents If with subscript "f". Unlike the designs of [8] and [10], time (us)
the control circuitry (D flip-flops and inverters (Fig. 3(b))) has no Fig. 4. Simulated waveforms of the proposed active rectifier at 40.68 MHz.
analog circuit, and compensation currents In and If are injected

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1.2 In's are added to the comparator just before MN1/MN2 is supposed
to turn on, unlike [3], [9]. Fig. 4 shows that IAC1/IAC2 goes high as
0.8 soon as VAC1/VAC2 is below ground, and IAC1/IAC2 does not go
V (V)

below zero, meaning that there is no reverse current. The bias

0.4
VGN2 VAC2 VGN1 VAC1 VGN2 VAC2 transistors Mn1C/Mn2C and Mn1D/Mn2D, and thus the In's, should be
0.0 large enough to pull up VOUT1/VOUT2 fast and high.
W/o Md1/Md2 transistor
1.2 C. Multiple-pulsing elimination
VGd1 VGd2 VGd1 VGd2
0.8 If due to process variations, the turn-off compensation current
is large enough to pull-down the comparator output while
V (V)

0.4 VAC1/VAC2 is still below ground, then VOUT1/VOUT2 is being pulled

up again (see Fig. 5). This is the well-known multiple pulsing
0.0
problem [7]. Our remedy is to add transistor Md1/Md2 to be in
1.2 parallel with Mb1E/Mb2E. Its gate is controlled by the VGd1/VGd2
pulse. Once VGN1/VGN2 is pulled down to trigger DFF2/DFF1,
0.8
VGd1/VGd2 goes high and short VOUT1/VOUT2 to ground through
V (V)

0.4
VGN2 VAC2 VGN1 VAC1 VGN2
0.0
W/ Md1/Md2 transistor
10.473 10.492
time (µs)
Fig. 5. Multiple pulsing eliminated by adding Md1 and Md2 and related circuit.
A. Off-delay compensation
Let us first consider that MN1/MN2 has been turned on and off-
delay compensation has to be achieved. For MN1/MN2 to turn on,
VGN1/VGN2 is high, which also turns on the switches Mf1A/Mf2A
and Mf1B/Mf2B to add off-delay compensation currents If's to the
comparator. Therefore, voltages at nodes V1A/V2A and V1B/V2B
increases. As a result, Mb1G/Mb2G conducts less current and
Mb1E/Mb2E conducts more current that help pulling down
VOUT1/VOUT2 faster, and turning off MN1/MN2 faster. Therefore,
reverse current is reduced or even eliminated (see Fig. 4). Note
that If's are added to the comparator just before MN1/MN2 is to be
turned off. Compared to [3], which implements a voltage doubler
rectifier, the off-delay compensation current is kept effective
even after the power MOS of this side is turned off in the present
Md1/Md2, cutting off MN1/MN2 and allow it to conduct only once
VAC2 every cycle. Fig. 5 shows that without Md1 and Md2 multiple-
pulsing exists; and after adding Md1 and Md2 multiple-pulsing is
10.511 eliminated.
III. MEASUREMENT RESULTS
The proposed digitally controlled on-off delay compensated
active rectifier was fabricated in standard 0.13 µm CMOS
process. The chip micrograph is shown in Fig. 6. It measures
0.166 mm2 including the pads. The measurement setup is shown
in Fig. 7. Power is transmitted from the transmitter to the
receiver via a series-parallel inductive link. The measured
inductance of the primary and the secondary coils at 40.68 MHz
were 307 nH and 642 nH, respectively; and the measured series
resistance were 1.22 Ω and 2.4 Ω, respectively. The rectifier's
filtering capacitor was 500 pF.

335 µm
half-cycle, until the power MOS of the other side is turned on in
the next half-cycle. Similarly, in [3], the on-delay compensation
current is also added for a long duration.
B. On-delay compensation
Next, consider on-delay compensation when VAC1/VAC2 goes
from positive to below ground. The on-delay compensation
495 µm
currents are added to the comparator when VON1/VON2 goes low.
Fig. 6. Chip micrograph of the on-off delay compensated active rectifier.
The generation of VON1/VON2 is as follows. For the positive edge-
triggered D flip-flops (DFFs), the D-inputs are VDC and are
always "1"; and the clock-inputs are the inversion of VGN2 and
VGN1 (Fig. 3(b)). In the previous half-cycle, when MN2/MN1 turns
off, meaning that VGN2/VGN1 has been "0", DFF1/DFF2 is
triggered and VGd2/VGd1 is "1". In the present half-cycle, when
VAC1/VAC2 goes below ground, VGN1/VGN2 becomes "1" and
DFF1/DFF2 is reset, as shown in Fig. 4. On-delay compensation
turn-off delay
currents In's must be added to the comparator before VAC1/VAC2 turn-on delay fully fully
goes below ground. However, the duration for VGd2/VGd1 to be compensated compensated
"0" is too long, and adding In's for the whole duration would hurt
Operating
the efficiency. Now, INV1/INV2 is driven by VGd2/VGd1, and the frequency
source of Mq1A/Mq2A is connected to VAC1/VAC2. As VAC1/VAC2 CHIP
L2
decreases, a short pulse VON1/VON2 that goes low is generated, L1
turning on the transistors Mn1A,B/Mn2A,B (Figs. 3 and 4). Hence, Fig. 7. Measurement setup for the 40.68 MHz full-wave rectifier.

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Start-up mode Normal mode The measured VCR and PCE with respect to VAC of the
VDC (0.75V/Div) proposed design along with representative published designs are
2 us shown in Fig. 11. When measuring VCR and PCE w.r.t. VAC, RL
was maintained at 500 Ω. The measured VCR and PCE with
VAC1 (1V/Div)
respect to RL are shown in Fig. 12. When measuring VCR and
PCE w.r.t. RL, VDC was maintained at 0.95 V through adjusting
1.0
VAC2 (1V/Div)
0.9
0.8
Fig. 8. Measured startup waveform. 0.7

VCR
VDC 0.6
Proposed
VAC2 VAC1 turn-off delay fully
compensated 0.5 Lu2014 [7]
0.4 Conventional
turn-on delay 1V
fully compensated 0.3
VAC 2.5 ns
1.0 1.1 1.2 1.3 1.4 1.5
(a) |VAC| (V)
VDC (a)
turn-off delay 95
VAC2 VAC1
fully compensated 90
85
VAC turn-on delay fully 1V 80
compensated 2.5 ns
75

PCE (%)
70 Proposed
(b) 65 Lu2014 [7]
Fig. 9. Measured steady-state waveforms of the on-off delay-compensated active 60 Conventional
rectifier for (a) VAC = 1.0 V, and (b) VAC = 1.2 V.
55
50
Efficiency Power loss Conduction 1.0 1.1 1.2 1.3 1.4 1.5
|VAC| (V)
93.95% 3% loss
6.05% (b)
0.7% Fig. 11. Measured (a) VCR, and (b) PCE at different VAC.
Comparator
1.0
and logic loss
0.9
Fig. 10. Simulated power distribution of the proposed active rectifier for VAC =
1.2 V. 0.8
0.7
For a wireless power receiver, the filtered output of the
VCR

rectifier (VDC) serves as the power supply for all control circuits. 0.6
When the system is relaxed, VDC is 0 V. Parasitic body diodes of 0.5 Proposed
MN1 and MN2 (Fig. 1) serve as passive diodes during the startup Lu2014 [7]
0.4 Conventional
process. During startup, when VAC1/VAC2 is higher than
VAC2/VAC1 by the threshold voltage of PMOS and a diode drop, 0.3
500 1000 1500 2000
MP1/MP2 and the body diode of MN2/MN1 are turned on, charging RL (Ω)
up the output capacitor CL. When CL is charged up to the (a)
minimum supply voltage needed by the comparators (biased by 95
the peaking current source), MN1 and MN2 start switching to 90
become an active rectifier. The measured startup waveform is 85
shown in Fig. 8. 80
The measured steady-state waveforms are shown in Fig. 9. 75
PCE (%)

Note that for both VAC1 and VAC2, the portions that swing below 70
ground are negligibly small, indicating that both on-delay and 65
60 Proposed
off-delay are fully compensated. The simulated power
55 Lu2014 [7]
consumption breakdown of the proposed rectifier is shown in the 50 Conventional
pie chart in Fig. 10. For the measurement purpose, two printed 45
circuit boards (PCBs) were designed to optimize the 40
measurement of VCR and PCE [7]. For fair comparison, the 100 R L ( Ω) 1000
conventional active rectifier and the active rectifier proposed in (b)
[7] were also fabricated and measured. Fig. 12. Measured (a) VCR, and (b) PCE versus load resistance (RL).

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TABLE I
COMPARISON WITH STATE-OF-THE-ART FULL-WAVE ACTIVE RECTIFIERS
Parameter TCAS-II [2] TCAS-I [9] TCAS-II [1] JSSC [3] TBCAS [7] JSSC [10] TCAS-I [8] This Work
Year 2006 2011 2012 2014 2014 2016 2019 2020
Process 0.35 µm 0.5 µm 0.18 µm 0.18 µm 0.35 µm 0.35 µm 0.18 µm 0.13 µm
Frequency 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz 13.56 MHz 40.68 MHz 40.68 MHz
Delay Off Delay On/Off Delay Off Delay On/Off Off Delay On/Off Delay On/Off Delay On/Off Delay
Compensation Delay
Input Range 1.2 - 3.22 V 3.3 - 5 V 0.9 - 2 V 1.15 - 1.35 V 1.5 - 4 V 1.8 - 3.6 V 2.5 - 4 V 1 - 1.5 V
Load Cap 200 pF 10 µF 10 µF 3×100 nF 1.5 nF 2 nF 2 nF 500 pF
O/p Power 5.76 mW 30.42 mW 3.2 mW 40 mW 24.8 mW 64.8 mW 56.6 mW 9 mW
(Max)
VCR 0.78 - 0.92 0.76 - 0.81 0.82 - 0.89 1.4-1.6* 0.873 - 0.93 0.91 - 0.95 0.73 - 0.84 0.91 - 0.97
(RL =1.8 kΩ) (RL =500 Ω) (RL =1 kΩ) (RL =100 Ω) (RL =1.8 kΩ) (RL =2 kΩ) (RL =500 Ω) (RL =500 Ω)
0.79-0.89 0.90-0.92
(RL =500 Ω) (RL =500 Ω)
PCE 65% - 89% 71% - 84.5% N/A N/A 84.2% -90.7% N/A 80% - 84% 92.13% - 94.2%
Simulated (RL =1.8 kΩ) (RL =500 Ω) (RL =500 Ω) (RL =500 Ω) (RL =500 Ω)
PCE N/A 68%-80.2% 60%-81.9% 72.5%-85% 82.2% -90.1% 89.1%-91.4% 70.7%-80.9% 85.3%-93.2%
Measured (RL =500 Ω) (RL =1 kΩ) (RL =500 Ω) (RL =500 Ω) (RL =500 Ω) (RL =500 Ω) (RL =500 Ω)
*
Voltage doubler. pp. 409–413, 2012.
125 [2] Y. Lam, W. Ki, and C. Tsui, “Integrated Low-Loss CMOS Active Recti er
VAC =1.2 V for Wirelessly Powered Devices,” IEEE Trans. Circuits Syst. II Express
No. of Samples

100 Briefs, vol. 53, no. 12, pp. 1378–1382, 2006.

75
Number = 500
50
Mean = 93.7
25
Std Dev = 0.38
0 [4]
90 91 92 93 94
Efficiency (%)
Fig. 13. Spread of efficiency (estimated with 500 sample size Monte Carlo
simulation) for VAC = 1.2 V.
the power to the primary coil. The measured maximum VCR and
PCE of the proposed design were 0.97 and 93.2%, respectively.
PCE at light load decreases very quickly because the losses of
the rectifier become comparable to the output power (PL). Peak
PCE was measured at the optimized RL of 500 Ω. At heavy load
VCR dropped due to the large voltage drop across the power
MOS transistors. Figs. 11 and 12 show that the proposed active
rectifier achieved better VCR and PCE consistently over the
other two designs. Table I summarizes the performance of the
proposed design and other state-of-the-art designs. Furthermore,
to demonstrate the robustness of the proposed design against
process, voltage and temperature (PVT) variations and
mismatches, Monte Carlo simulation was performed with a
sample size of 500 (see Fig. 13). The mean efficiency was
93.7% for VAC = 1.2 V. Therefore, our digitally controlled on-off
delay-compensated active rectifier can switch at the higher
frequency of 40.68 MHz, and achieved excellent VCR and PCE.
[3] C. Y. Wu, X. H. Qian, M. S. Cheng, Y. A. Liang, and W. M. Chen, “A
13.56 MHz 40 mW CMOS high-efficiency inductive link power supply
utilizing on-chip delay-compensated voltage doubler rectifier and multiple
ldos for implantable medical devices,” IEEE J. Solid-State Circuits, vol. 49,
no. 11, pp. 2397–2407, 2014.
X. Li, C. Tsui, and W. Ki, “Power Management Analysis of Inductively-
95
Powered Implants with 1X / 2X Reconfigurable Rectifier,” IEEE Trans.
Circuits Syst. I, vol. 62, no. 3, pp. 617–624, 2015.
[5] B. Smith et al., “An externally powered, multichannel, implantable
stimulator-Telemeter for Control of Paralyzed Muscle,” IEEE Trans.
Biomed. Eng., vol. 45, no. 4, pp. 463–475, 1998.
[6] U. M. Jow and M. Ghovanloo, “Optimization of data coils in a multiband
wireless link for neuroprosthetic implantable devices,” IEEE Trans.
Biomed. Circuits Syst., vol. 4, no. 5, pp. 301–310, 2010.
[7] Y. Lu and W. H. Ki, “A 13.56 MHz CMOS active rectifier with switched-
offset and compensated biasing for biomedical wireless power transfer
systems,” IEEE Trans. Biomed. Circuits Syst., vol. 8, no. 3, pp. 334–344,
2014.
[8] L. Cheng, X. Ge, L. Hu, Y. Yao, W.-H. Ki, and C.-Y. Tsui, “A 40.68-MHz
Active Rectifier With Hybrid Adaptive On/Off Delay-Compensation
Scheme for Biomedical Implantable Devices,” IEEE Trans. Circuits Syst. I
Regul. Pap., pp. 1–10, 2019.
[9] H. M. Lee and M. Ghovanloo, “An integrated power-efficient active
rectifier with offset-controlled high speed comparators for inductively
powered applications,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 58,
no. 8, pp. 1749–1760, 2011.
[10] L. Cheng, W. Ki, Y. Lu, and T.-S. Yim, “Adaptive On/Off Delay-
Compensated Active Rectifiers for Wireless Power Transfer Systems,”
IEEE J. Solid-State Circuits, vol. 51, no. 3, pp. 712–723, Mar. 2016.
[11] S. Guo and H. Lee, “An efficiency-enhanced CMOS rectifier with
unbalanced-biased comparators for transcutaneous-powered high-current
implants,” IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1796–1804,
2009.

IV. CONCLUSION
In this paper a digitally controlled active rectifier switching at
40.68 MHz is proposed for WPT of biomedical applications. The
proposed design eliminates both the turn-on and turn-off delays,
and it also solves the multiple pulsing problem. Measurement
results show that the proposed design achieved very high VCR
and PCE, and is an optimum choice for wireless power transfer
of biomedical applications.
REFERENCES
[1] H. Cha, W. Park, and M. Je, “A CMOS Rectifier With a Cross-Coupled
Latched Comparator for Wireless Power Transfer in Biomedical
Applications,” IEEE Trans. Circuits Syst. II Express Briefs, vol. 59, no. 7,

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