Microelectronics Journal 44 (2013) 576–585

Contents lists available at SciVerse ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

High-voltage high input impedance unity-gain voltage buffer

Mariusz Jankowski n, Andrzej Napieralski
Department of Microelectronics and Computer Science, Lodz University of Technology, Wolczanska 221/223, 90-924 Lodz, Poland

art ic l e i nf o a b s t r a c t

Article history: The paper presents a novel structure of a voltage buffer intended for application in high-voltage
Received 14 September 2012 integrated systems. The presented solution is based on both source-input and gate-input voltage buffer,
Received in revised form so as to get the best of both structures. The resulting circuitry offers high impedance input node without
3 March 2013
any DC-path, and voltage gain close to unity. Simulation results of the proposed circuit designed in
Accepted 11 March 2013
Available online 15 May 2013
0.8 mm HV SoI technology are presented. The buffer has been granted a patent by the Polish Patent Office.
& 2013 Elsevier Ltd. All rights reserved.
Keywords:
High-voltage circuits
Unity gain voltage buffers
Silicon-on-Insulator process
High input impedance

1. Introduction
High-voltage semiconductor processes enable design and
production of integrated circuits that offer extended functionality
over their low-voltage counterparts. Still, many MOS devices
present in high-voltage semiconductor processes tolerate drain-
source and drain-gate voltages up to tens of volts, but only low-
range (up to a few volts) gate-source voltages. Also, high-voltage
MOS devices, due to their structure, provide poor matching, which
may reduce quality of high-voltage integrated system operation.
Thus, some low-voltage-originating topologies cannot be directly
placed into high-voltage applications and expected to function as
well as their low-voltage counterparts.
The research presented in this paper is targeted to develop
possibly simple high-voltage unity-gain buffer that has high input
impedance and is able to work in high-voltage systems. The circuit
idea originated from the need of buffering a current-mode wave-
form generator, presented in [1]. Necessity of proper decoupling
of current-mode outputs from inputs of following voltage-mode
stages is a general rule, as can be seen in [2]. In low-voltage
applications voltage buffer that offers very high input impedance
can be implemented as an operational amplifier [3] or many others
structures [2]. On the other hand, design process of high-voltage
versions of circuits like OPAMPs can be a demanding task, also in
SoI processes [4], and other solutions could be more convenient.
The high-voltage operation requirement, as well as need of circuit
structure simplicity excluded approach either directly based on
n
Corresponding author. Tel.: +48 42 631 26 49, 48 42 631 26 28;
fax: +48 42 636 03 27.
E-mail addresses: jankowsk@dmcs.pl,
mariusz.jankowski@p.lodz.pl (M. Jankowski).
OPAMPs [5,6] or using them in control loops, though there are
presented complementary versions of such solutions [7,8].
2. Simple structures
Structures well-suited for acting as high-voltage unity-gain
buffers are complementary voltage followers. Two main types of
such circuits may be distinguished [9], as basic buffer structures
applicable also for high-voltage applications. Source-input fol-
lowers, like in Fig. 1a, offer higher precision of voltage gain, but
have limited input impedance. Input impedance is limited by
presence of a DC current-path through the buffer input node.
Such current path may easily render current-mode circuits useless,
if they are loaded with such buffers.
Gate-input follower, like in Fig. 1b, seems to provide a solution
to the input impedance problem. But again, its drawback is
imprecise voltage gain value, due to input stage structure of
gate-input followers. This structure does not provide any methods
of precise aligning output voltage with input voltage. Typical gate-
input voltage buffer presented in Fig. 1b shows that its input stage
is made of an MOS transistor with its gate connected to the buffer
input. This transistor is biased with a current source connected to
its source.
Relevant output stage consists of a complementary type MOS
transistor with its gate driven by source of the input MOS
transistor. Source terminal of the output transistor is connected
to the buffer output. Because the input and the output stage MOS
transistors are of opposite conduction types, there is only a rough
way of aligning input and output voltage levels.
Limitations of the gate-input voltage buffers are aggravated
by the fact, that when a drain-source voltage of the input MOS
transistor rises, a drain-source voltage of the relevant output MOS

0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.mejo.2013.03.006
 M. Jankowski, A. Napieralski / Microelectronics Journal 44 (2013) 576–585 577

Fig. 1. Simple source input (a) and gate-input (b) buffers, applicable to both low-voltage and high-voltage systems [9].

Fig. 2. Conversion of a gate-follower (a) and a source-follower (b) into the introductory version of the proposed buffer (c).

transistor falls. This effect makes the input and output transistor to
adjust their gate-source voltage in the opposite ways. This in turn
adds to a difference between input and output voltage. As a result,
the expected unity gain gets reduced in comparison to gain offered
by source-input buffers.
3. Proposed structure
There are attempts to build voltage buffers that use gate-input
structures, but offer control over gain value and DC voltage offset [10].
Some solutions use complex adaptive biasing structures for precise
control of proposed buffer structures [11]. Unfortunately, most of the
structures are designed for low-voltage applications [10,11].
In this paper a high-voltage buffer solutions are considered and
high-voltage device properties are taken into account. Few high-
voltage unity-gain buffer solution have been proposed and due to
their specific application demands, they tend to be quite complex
[4,12]. Possibly effective buffer structure with limited number of
transistors and possibly short signal flow-path is investigated in
this paper.
3.1. Introductory structure
The proposed structure is elaborated in order to keep high
impedance input of the gate-input voltage buffer and gain value
similar to this of a source-input voltage buffer. This goal is
achieved by adjusting gate-source voltage drops of the input stage
transistor possibly close to the output stage transistor gate-source
voltage drops. Or in other words, to make the input stage
transistors of the gate-input buffer provide gate-source voltages
possibly similar to gate-source voltages in the input stage of the
source-input voltage buffer. To achieve proper voltage drop on the
input stage transistors, it is required to get these transistors
properly polarized. This is made with modification of the input
stage bias current sources.
The idea is to provide a bias current that produces input
transistor gate-source voltage drop equal to that of present at
input-stage transistors of source-input voltage buffer. Concept of
the idea is presented in Fig. 2, with help of simple non-
complementary versions of the buffers. Names of the transistors
show how those used in gate- and source-follower are used in the
introductory version of the proposed solutions. Fig. 3 introduces
complementary version of the introductory buffer structure. There
are two current sources, and their currents are equal to input bias
currents of the source-input voltage buffer. Each of these currents
biases one of reference transistors (MNR, MPR), identical to one of
input-stage transistors of the source-input buffer.
These reference transistors are applied in diode connection, just
like the input transistors in the source-input buffer. The bias currents
produce gate-source voltage drops at these two reference transistors
that in turn drive two auxiliary transistors (MNA, MPA), identical
578 M. Jankowski, A. Napieralski / Microelectronics Journal 44 (2013) 576–585
Fig. 3. Introductory version of the proposed buffer [13].
to those used in input of the proposed structure. These two auxiliary
transistors convert gate-source voltage drops into currents used for
input-stage biasing. Next, the input-stage transistors convert devised
bias currents into their gate-source voltage drops, expected to be
identical to voltage drops at the reference transistors.
3.2. Improved structure
Though promising, the solution presented in Fig. 3 has several
drawbacks that severely limit its application. First, the circuit
requires proper matching of several pairs of transistors for proper
operation. All these transistors are high-voltage devices, which
makes matching difficult. Other issue is a fact, that auxiliary and
input transistors, which are expected to work as a voltage–
current–voltage chain of signal transmission, change their drain-
source voltages in opposite ways.
Increase of the drain-source voltage of the auxiliary transistor
causes decrease of drain-source voltage of the relevant input-stage
transistor. If drain-source voltage of the auxiliary transistor drops,
the bias current, which it produces, also drops. Such reduced
current flows through the relevant input transistor, causing its
gate-voltage to be reduced. Furthermore, while drain-source
voltage of the auxiliary transistor drops, drain-source voltage of
the identical input-stage transistor rises.
The input-stage transistor is biased with externally provided
current and is required to stay in saturation. The only way it can
cope with rise of its drain-source voltage, is a slight reduction of its
gate-source voltage, so as to keep its drain-source current con-
stant. Thus, there are two causes of gate-source voltage reduction
in input-stage transistor, as compared to relevant auxiliary tran-
sistor. In complementary pair of the auxiliary and input-stage
transistors the process goes in the opposite way. As a result the
voltage gain of the proposed buffer gets reduced.
An amendment that solves the presented problems is possible.
The basic idea is an application of low-voltage transistors in
critical points of the buffer, and using high-voltage transistors as
both safety and cascode-like devices. The modified structure is
presented in Fig. 4. Again, there are two bias current sources. Now,
each of the currents polarizes a set of two complementary
reference transistors that mimic input-stage of the source-input
buffer. Each of these reference transistor pairs drives one auxiliary
low-voltage transistor, additionally equipped with one of auxiliary
high-voltage cascode transistors (MNAC, MPAC). These high-
Fig. 4. Improved version of the proposed buffer [13].
voltage transistors are driven with help of the previously absent
reference transistors (MNRR, MPRR), now added to form an
imitation of a complete input-stage of the source-input buffer.
Total voltage drop on each of the reference transistor pair (MNR
+MPRR and MPR+MNRR) is made to be equal to the total voltage
drop between source terminals of the input-stage transistors (and
thus between gate terminals of the output stage transistors).
According to this, it is possible to replace each of high-voltage
input-stage transistors with a set of low-voltage input transistors
(MNA or MNA) and cascode high-voltage transistors (MNAC or
MPAC) - both identical to transistors driven with imitations of
source-input type buffer input stages.
These high-voltage auxiliary and input-stage transistors pri-
marily are intended to be safety devices. Their presence and way
of connection enable application of low-voltage transistors as
primary auxiliary and input-stage devices. These low-voltage
transistors are easy to match, which improve quality of their
voltage–current–voltage signal processing path. This in turn pro-
duces closer values of gate-source voltage drop at auxiliary and
then input-stage transistors.
Moreover, these high-voltage auxiliary and input-stage transis-
tors work as cascode devices, keeping drain-source voltages of
primary low-voltage auxiliary (MNA, MPA) and input-stage (MNI,
MPI) transistors almost constant and almost equal one to another.
This additional feature makes the cooperation of auxiliary and
input-stage transistors very precise and their gate-source voltage
drops nearly identical.
The buffer structure presented in Fig. 4 is expected to offer
precision of voltage gain similar to that of source-input buffers, and
high input impedance typical for gate-input voltage buffers. Presented
simulations verify properties of the proposed unity-gain voltage buffer.
3.3. Specifics of the modification
The presented modification is in some its aspects a non-typical
one. It affects operation of the input stage of the buffer and what is
even more important it is focused mainly on the current-bias
circuitry that conveniently remains off the buffer signal-path.
The output stage of both introductory and final versions of the
 M. Jankowski, A. Napieralski / Microelectronics Journal 44 (2013) 576–585 579

presented buffer still have their output stages typical for basic
source-followers and based on common-source connected tran-
sistors. Fig. 5 presents this for simplified non-complementary
substructures of the presented buffer versions.
Such a simple output-stage structure promises high bandwidth
but also offers rather high output impedance, at least for needs of
some applications. There are known several structures derived
from simple common-source connected transistor (sometimes
openly referred to as a source-follower structure), introduced to
cope with limitations of the simple non-modified buffer output-
stages. An original source-follower output-stage and a few typical
output-stage modifications are presented in Fig. 6. Original sim-
plified output-stage is presented in Fig. 6a. One of popular
improvements is known as a voltage-flipped-follower [14] shown
in Fig. 6b, and its several derivatives exploring this structure
[15,16]. This idea has been further modified into a super flipped
follower (Fig. 6c) and its derivatives [17,18]. A kind of general
modifications can be described as an addition of a gain unit in the
feedback loop, as shown in Fig. 6d [16]. Application of such a
general output-stage idea has even been patented [19]. Table 1
presents comparison of output resistance of output stage solutions
presented in Fig. 6. It can be seen, that the one used in the
modified buffer offers highest output resistance, which might be
4. Dedicated application
The proposed buffer has been devised with a specific applica-
tion in mind. It was found that in some HV analog signal
processing circuits it is easier to convert the HV waveforms to
current domain, process current signals and then convert the
processed signals into voltage domain.
Cause of such signal domain change is easiness of performing
various arithmetic operations in current mode in comparison with
voltage mode of signal processing. This property of current mode
signal processing gets especially pronounced in case of HV signal
processing systems. Operations like: summation, subtraction,
multiplication of value and number of outputs, inversion may be
quite challenging for HV voltage-mode systems. In case of current-
mode circuits such operations can be obtained just by current
mirrors or even wire connections (summation).
The mentioned U/I and I/U signal conversion system is presented
in [20] and is shown in Fig. 7. It can be observed that it utilizes
resistive device for signal conversions. In case of one-way U/I or I/U
Table 1
Output resistance comparison for typical buffer output-stages.

considered a drawback. Though, as it is stated earlier, the buffer

Output stage type Output resistance
structure proposed in the paper leaves the output-stage
unchanged. Application of the modified output-stage structures Source follower
1
g MOUT r O
may still improve the buffer operation. Presence of high-quality Voltage flipped follower
1
g MOUT g MIN r O
input-stage and bias circuitry improving gain and limiting voltage Super source follower
1
g MOUT g MIN r O
shift parameters may limit task imposed on the additional output- Enhanced resistance super source follower
1
g MOUT g MIN AV r O
stage modification circuitry.

Fig. 5. Simplified non-complementary subcircuits of the introductory (a) and final (b) versions of the proposed buffer along with their simple output-stage structure (c).

Fig. 6. Set of popular buffer output-stages: a source-follower (a), a flipped follower (b), a super flipped follower (c), the generalized idea of the super flipped follower (d).
580 M. Jankowski, A. Napieralski / Microelectronics Journal 44 (2013) 576–585

signal conversion circuits it is not a good approach. Integrated
resistors are known for poor control of device resistance value and
different solutions of one-way converters are required, e.g. like all-
MOS U/I conversion circuit presented in [21]. In case presented in
Fig. 7 identical resistors are used for U/I and I/U conversion, which
enables elimination of resistor-induced signal processing errors.
Unfortunately, such approach may lead to one significant
difficulty. The current–voltage (I/U) converters are usually con-
structed as single resistors producing voltage drops due to current
flows through them. Such solution makes the conversion resistor
terminal voltage highly volatile to current flows to and from next
signal processing stage. Such current flows are produced by typical
HV source-follower voltage buffers, if connected to the I/U con-
version terminal. Typical gate-follower HV buffer offer much
better input impedance and no DC path through their inputs, but
they distort voltage waveforms they process.
One of task of the current-mode module, inserted into other-
wise voltage-mode signal processing path, may be generation of
inverted waveform so as to finally provide a differential waveform.
The requirement for the output voltage waveform is: precisely
defined and constant total voltage value of simple and inverted
voltage waveform. Such requirement makes application of typical
gate-follower HV buffers at least questionable. New circuitry must
be devised and the presented HV unity gain buffer is the product
of this design effort focused on providing high-quality buffer for
connection of the highly volatile I/U converter terminals with
further purely voltage signal processing paths. U/I and I/U signal
conversion system with built-in current-mode differential signal
generator is presented in Fig. 8. Uniformity and thus simplicity of
the whole circuit is clearly visible.
5. Simulation results
Due to original automotive application requirements, the pre-
sented circuitry is designed to work properly with 24 V of high
supply voltage and 5 V of low supply voltage. These are safe values
for the utilized process, which is HV 0.8 mm BCDMOS SoI. The high
supply voltage is set to be 27 V during simulations, as it is the
maximum practically possible supply.
All the presented simulations are performed for a source-input
buffer, a gate-input buffer and a final version of the proposed

Fig. 7. U/I and I/U signal conversion system presented in [20].

Fig. 8. U/I and I/U signal conversion system application for differential signal generation.
 M. Jankowski, A. Napieralski / Microelectronics Journal 44 (2013) 576–585 581

Fig. 9. Comparison of 1 MHz input currents related to 13.5 V 0-p input voltage waveforms for different voltage buffers: source-input — dashed, gate-input — dotted,
proposed — solid line.

buffer. All presented parameter simulations are performed for

1 MHz sine input waves, amplitudes in range of 0.5–13.5 V. Input
voltage offset is equal to 13.5 V.
Input impedance of the compared buffers are presented in
Figs. 9 and 10. The largest input impedance of the proposed buffer
is clearly visible. Its input impedance is even larger than that of the
gate-input buffer. Both the proposed and the gate-follower buffers
use MOS transistor gates as input nodes, so there are no DC current
path. The higher impedance of the proposed buffer is due to
cascode-like structure in the input stage of the proposed circuit.
This way, auxiliary transistor implemented in order to improve the
buffer gain and minimize voltage shift paid-back with even further
increased input impedance. All this is achieved without application
of extra circuitry (like in [3]), which complicates circuit structure
Fig. 10. Comparison of large signal input impedance for 1 MHz input sine wave-
and can have a degrading influence on operation parameters.
form of voltage buffers: source-input — dotted, gate-input — dashed, proposed —
Total harmonic distortion (THD) values are shown in Fig. 11. solid line.
Their values are small and similar for all checked buffer config-
urations. Of course, increase of input waveform frequency dete-
riorates these values.
Offset voltage errors between output and input voltage are
presented in Fig. 12. The proposed buffer is clearly free from offset
level shift so typical for gate-follower based buffers.
Voltage gain values of the source-input, gate-input and pro-
posed buffer are presented in Fig. 13. The proposed buffer offers
unity-gain precision at least comparable, or even better than the
source-input buffer.
Voltage-range of the buffers are presented in Fig. 14. It can be
seen that it do not reach from rail to rail. It is even more limited
that in case of its ancestral buffers. This is the price to pay due to
the structure of the source-input stage imitations, which in turn
drive auxiliary transistors that form output stage of current
mirrors that polarize input stage of the buffer. Such circuitry can Fig. 11. Comparison of output waveform total harmonic distortion (THD) of buffer
be treated as a kind of a cascade current mirror, and this specific driven with 1 MHz input sine waveforms: source-input — dotted, gate-input —
implementation is not one optimized from the voltage-range point dashed, proposed — solid line.
of view, as is in case of bias current mirrors in gate-follower and
source-follower circuits. When MNAC and MNAC transistors of the follower (Fig. 14). In case of high-voltage systems, usually working
proposed buffer (Fig. 4) leave saturation region, the gain of the with supply voltage levels up to several tens of volts, this
proposed buffer drops to and even below gain value of the gate- limitation may usually be of limited importance. Fig. 15 presents
582 M. Jankowski, A. Napieralski / Microelectronics Journal 44 (2013) 576–585
comparison of bias current mirrors typical for both gate-followers
and source-followers (a, b) and the solution required by the
presented buffer (c). Table 2 presents comparison of output
voltage-range limitations imposed by bias circuitry presented in
Fig. 15. In all these solutions the voltage-range limitations are
present. If rail-to-rail solutions are required, modified structures
based on complementary source-followers [22–24] might be used
to solve the problem and try to use modifications presented in this
paper. There are some such complementary buffer ideas imple-
mented in BiCMOS processes [25], as in fact is the buffer proposed
in this paper. Also some new combined solutions might be
Fig. 12. Comparison of offset voltage errors for 1 MHz input sine waveforms, for
buffers: source-input — dotted, gate-input — dashed line, proposed — solid line.
Fig. 13. Comparison of voltage-gain for 1 MHz input sine waveforms, for buffers:
source-input — dotted, gate-input — dashed line, proposed — solid line.
Fig. 14. Voltage-range of the proposed buffer (solid line) and its ancestors: gate-follower (dashed line) and source-follower (dotted line).
elaborated, with use of low output-resistance buffer output-stage
structure modifications [14–18], in cooperation with modified
input stage as presented in the paper. Interesting modification
of a gate-follower stage used as a starting point of the buffer
described in this paper is presented in [26]. A complementary
version of a unity-gain buffer using similar output-stages is
presented in [27]. A HV SoI technology buffer using both presented
modification of the input/bias buffer stage in connection with
modified output-stages presented in these papers seems feasible.
Bandwidth (for 10 V 0 to peak input) simulation results of the
proposed buffer are similar to those of the gate-input buffer, due
to same input structure and is selected HV SoI process is find to be
equal to about 10 MHz. Due to simple structure of the output stage
of the proposed buffer—still, it is just a source-follower configura-
tion without any feedback mechanisms added (as opposed to
circuits presented in [16–18])—the bandwidth of the proposed
buffer is not expected to be limited due to output stage structure
of the proposed buffer.
Output impedance of the proposed buffer has been simulated
and is very similar to the output resistance of its ancestral buffers,
and is about 19 KΩ, as all these buffers have same outputs based
on common-source connected transistors. Such output impedance
level may be not satisfactory for some applications, as it requires
more robust output stage design—more bias current and larger
transistors—to retain quality of the buffer operation, e.g. the
voltage gain. As it is stated earlier in the paper, the output stage
of the proposed buffer remain a simple common-source stage
typical for source-followers. Such unaltered output stage remains
open for output-resistance-limiting modifications like various
feedback applications [14–18], with or without interaction with
input stage and bias stage oriented buffer modifications presented
in this paper.
6. Possibly required structure adaptations
The structure of modified buffer consists of LV and HV MOS
transistor. Moreover, the proper operation of the buffer requires
proper biasing process between these different devices. In prac-
tice, it is not always a straightforward task to seamlessly inter-
weave LV and HV transistors. Gate-source voltages proper for HV
transistors of the buffer output stage may be not proper for LV
transistors used in the biasing section and input stage of the
proposed buffer. One possibility is that gate-source voltages
 M. Jankowski, A. Napieralski / Microelectronics Journal 44 (2013) 576–585 583

Fig. 15. Comparison of buffer input-stage current-bias mirror outputs typical for both gate-followers and source-followers (a), (b) and required by the proposed buffer (c).

Table 2
Output signal voltage-range limitations for typical bias current-mirrors and the
solution required in the presented buffer.

Bias current source type Voltage-range limitation

Typical optimized cascode mirrors (e.g. Fig. 15a,b.) V DSsat MOUT þ V DSsat MCOUT
Biasing scheme utilized in the presented buffer V DSsat MPA þ V DSsat MPAC þ V T MPA

provided by HV bias stage transistors are too high for LV transis-

tors, which causes the latter to sink or source extensive amount of
current. The other case happens if HV transistors biased with
proper current flow cannot switch the LV transistors on with their
gate-source voltages, at all. In both cases proper operation of the
proposed buffer is no longer present. Therefore, specific buffer
structure adaptations are required in each of presented case in
order to retain proper operation of the proposed circuit.

6.1. Too high gate-source voltage of HV MOS transistors

In case of gate-source voltage of HV MOS transistors too high for

cooperating LV transistors, the buffer modification is quite limited. As
presented in Fig. 16, instead of single LV MOS devices in bias section
of the buffer (MNA, MPA), a series connection of a LV MOS transistors
and resistors (RNA, RPA) are applied. Now, only part of the HV MOS
transistor (MNR, MPR) gate-source voltages is used for driving the
mentioned LV MOS devices. A resistor is the additional device of
choice, because its resistance, and thus its voltage drop, can be
widely and easily adjusted. Such structure, in turn, enables easy
control over current sunk/sourced by MNA and MPA transistors of
the buffer bias section. The complete established series-connections
of MNA-RNA and MPA-RPA devices act as U/I and I/U converters of
HV MOS transistor gate-source voltages.
To maintain proper operation of the proposed buffer, the series
connections of LV MOS transistors and resistors in bias section of
the buffer must be followed by same structures in the input
structure. MNI and MPI transistors are replaced with MNI-RNI
and MPI-RPI series connections (Fig. 16). Side-effects of such
modification are rather limited. One obvious is a slight reduction
of maximum amplitude of input voltage wave that can be properly
processed by the modified buffer.
6.2. Too high gate-source voltage of LV MOS transistors
The case of gate-source voltage of LV MOS transistors being too
high for cooperation HV transistors is the more complicated one.
Fig. 16. Proposed HV buffer modified for case of gate-source voltage of the bias
section HV MOS transistors too high for cooperating LV transistors.
The modifications in the bias section of the buffer are similar as in
previous case and are presented in Fig. 17. The difference is that it
is the HV MOS transistors (MNR, MPR) of the buffer bias section
that are series connected with additional resistors (RNA, RPA),
now. This way, the voltage drop produced by the two series
connected devices is able to properly bias the cooperating LV
MOS transistors (MNA, MPA). The main complication is located in
the input stage of the proposed buffer. There are no HV transistors
in the input stage to equip them with additional series resistors, as
it is in previously presented modification case. There, same series-
connected devices were placed in the bias and input stage sections
of the buffer so that proper voltage levels can be transmitted to the
output stage of the buffer. Now, the only HV transistors relevant to
the HV transistors in the bias section are these placed in the
584 M. Jankowski, A. Napieralski / Microelectronics Journal 44 (2013) 576–585
output stage of the buffer. Such placement excludes any possibility
of equipping these transistors (MNO, MPO) with any series-
connected resistors. Such modification would not serve its pur-
pose, as the output-stage current is, among others, dependent on
the load properties and operation conditions and not only on the
input stage bias current. Thus, proper voltage drop on so-placed
additional resistors could not be obtained and kept. The required
modification must be placed in the input section of the buffer
under remake. What is present in the input stage are LV MOS
transistors (MNI, MPI), which convert their bias currents into
voltage drops equal to these on their relevant series connections
of HV MOS transistors and resistors (MNR-RNA, MPR-RPA). The
problem is that this combined voltage drop at two devices is coded
as a single gate-source voltage of a single LV MOS device. Due to
such structure of the buffer bias section, voltage drops at the
additional resistors must be subtracted from gate potentials of
MNI and MPI input stage transistors. Voltage levels obtained this
way can properly drive the output stage of the re-worked buffer.
Some extra structures must be added to provide required func-
tionality (Fig. 17). Two sets of devices are added in this structure.
First, RNI and RPI resistors identical to these in the bias section are
added between the input and the output stages of the buffer.
These resistors are put between sources of the input stage LV
transistors (MNI, MPI) and gates of the HV output stage transistors
(MNO, MPO). Each such resistor is equipped with a pair of current
sources. The task of the source is to ensure constant current flow
through their relevant resistor, equal to the current flow levels
through the relevant (RNA, RPA) resistors in the bias section of the
buffer. Such current flow levels provide required voltage subtrac-
tions, equal to related voltage drops on the resistors in the bias
section. Both current sources in each par are supposed to provide
identical current flow. It is not possible in reality and possible
current flow inequalities between these current sources can be
removed owing to RNI and RPI resistor connections to the low-
impedance source terminals of input-stage transistors.
Fig. 17. Proposed HV buffer modified for case of gate-source voltage of the bias section LV MOS transistors too high for cooperating HV transistors.
In the latter solution more additional circuitry is required,
which means more silicon area for the buffer. Also, two additional
current flow ways between supply reels are open, which means
more power consumption by the modified buffer. As in previous
case, maximum input wave amplitude gets slightly reduced. Such
side-effects to the modifications are not welcome and may some-
what limit assets of the buffer presented in Section 4. Though, the
most important of them remains unchanged — very high input
impedance with no DC current path. Due to retaining of this
specific property both the re-worked buffers still can find their
application in analog signal processing modules.
7. Conclusions
The unity-gain voltage buffer structure presented in the paper
offers interesting set of properties. In a way, it is a kind of mix a
gate-input and a source-input buffer structures, constructed to get
best of both these structures. The proposed buffer offers precision
of voltage-gain, minimal input–output voltage shift comparable to
those of the source-input buffer. On the other hand it offers input
impedance even superior to that offered by the gate-input buffer.
The interesting property of the new buffer is fact, that the
introduced modifications are related to input stage of the buffer.
Moreover, the modifications are mostly concentrated in the
current bias section — unrelated to signal path of the buffer.
Owing to this, the buffer structure is still open to further
modifications focused on improvements of the buffer output stage,
like e.g. feedback implementation for lowering the output
impedance.
The proposed buffer primary application is interfacing of
current-flow sensitive voltage terminals. Of course, the buffer
can be used as an effective alternative for gate-input and source-
input buffers in numerous applications. Possible incompatibilities
between gate-source voltages of HV and LV MOS transistors
 M. Jankowski, A. Napieralski / Microelectronics Journal 44 (2013) 576–585
can be addressed with application of presented buffer structure
modifications. Owing to this, buffer application is not limited to
any specific HV integrated process.
The novelty of the presented unity-gain buffer has been
acknowledged by the Polish Patent Office by granting it a patent.
Acknowledgment
Presented achievements were obtained during works on pro-
ject for Tritem Technologies Ltd. company.
References
[1] M. Jankowski, A. Napieralski, Current-controlled slew-rate adjustable trape-
zoidal waveform generators for low-and high-voltage applications, MIXDES
Conference: Mixed Design of Integrated Circuits and Systems, Gliwice, Poland,
2011, pp. 289–294.
[2] V. Michal, G. Klisnick, G. Sou, M. Redon, J. Sedlacek, Current conveyor with
very low output impedance voltage buffer for laboratory instrumentation, in:
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS),
May 30 2010–June 2 2010, pp. 1049–1052.
[3] S. Lanyi, M. Pisani, A high-input-impedance buffer, IEEE Trans. Circuits Syst. I:
Fundam. Theory Appl. 49 (8) (2002) 1209–1211, August.
[4] Kishore Penmetsa, Kenneth V. Noren, Herbert L. Hess, Kevin M. Buck, High
voltage operational amplifiers in SOI technology, in: Proceedings of the 12th
NASA Symposium on VLSI Design, Coeur d'Alene, Idaho, USA, Oct. 4–5, 2005.
[5] Guangmao Xing, Stephen H. Lewis, T.R. Viswanathan, Self-biased unity-gain
buffers with low gain error, IEEE Trans. Circuits Syst. 56-II (1) (2009) 36–40.
[6] R. Wojtyna, High-precision low-power voltage follower for hardware signal
processing, in: Proceedings of the International Conference Mixed Design of
Integrated Circuits and System—MIXDES, 22–24 June 2006, pp. 304–309.
[7] B. Sekerkiran, A compact rail-to-rail output stage for cmos operational
amplifiers, IEEE J. Solid-State Circuits 34 (1999) 107–110.
[8] Marius Neag, Oliver McCarthy, High-speed, low-power CMOS voltage buffers,
in: Proceedings of the International Semiconductor Conference CAS '98,
October 1998, ISBN 0-7803-4432-4, Sinaia, Romania, vol I, 1998, pp. 175–180.
[9] M. Jimenez, A. Torralba, R.G. Carvajal, J. Ramirez-Angulo, A new low-voltage
CMOS unity-gain buffer, in: Proceedings of IEEE International Symposium on
Circuits and Systems, ISCAS 2006, 21–24 May 2006, pp. 919–922.
[10] Torralba, R.G. Carvajal, J. Galan, J. Ramirez-Angulo, Compact low power high
slew rate CMOS buffer for large capacitive loads, Electron. Lett. 38 (22) (2002)
1348–1349 24 Oct.
[11] Sawigun J. Mahattanakul A., Demosthenous, D. Pal, A low-power CMOS analog
voltage buffer using compact adaptive biasing, in: Proceedings of the 18th
European Conference on Circuit Theory and Design, ECCTD 2007, 27–30
August 2007, pp. 1–4.
585
[12] Soo-Yang Park, Sang Hee Son, Won Sup Chung, A rail-to-rail unity gain buffer
amplifier for low-cost high resolution TFT LCD panels, IEEE Trans. Consum.
Electron. 55 (4) (2009) 2190–2194, November.
[13] M. Jankowski, A. Napieralski, High-voltage high input impedance unity-gain
voltage buffer, in: Proceedings of the Nanotech Conference & Expo, 18–21 June
2012.
[14] R.G. Carvajal, J. Ramirez-Angulo, A.J. Lopez-Martin, A. Torralba, J.A. Galán,
A. Carlosena, F. Muñoz, The flipped voltage follower: A useful cell for low-
voltage low-power circuit design, IEEE Trans. Circuits Syst. 52 (7) (2005)
1276–1291.
[15] A. Torralba, R.G. Carvajal, M. Jime´nez, F. Muñoz, J. Rami´rez-Angulo, Compact
low-voltage class-AB analogue buffer, Electron Lett. 42 (3) (2006).
[16] Yahoui Kong, Shuzheng Xu, Huazong Yang, An ultra low output resistance and
wide swing voltage follower, in: Proceedings of ICCCAS Conference 2007,
July 2007, pp. 1007–1010.
[17] S. Wangtaphan, V. Kasemsuwan, A 0.6 V class-AB CMOS voltage follower with
bulk-driven quasi-floating gate super source follower, in: Proceedings of the
9th International Conference on Electrical Engineering/Electronics, Computer,
Telecommunications and Information Technology—ECTI-CON 2012, 16–18
May, 2012, pp. 1–4.
[18] Antonio J. Lopez-Martin1, Lucia Acosta, Coro Garcia-Alberdi, Ramon
G. Carvajal, Jaime Ramirez-Angulo, Power-efficient analog design based on
the class AB super source follower, Int. J. Circuit Theory Appl. 40 (11) (2012)
1143–1163, November.
[19] United States Patent no. US 7,944,303 B2, Super source follower output
impedance enhancement, Inventor: Carmine Cozzolino, Original Assignee:
Fairchild Semiconductor Corporation, Primary Examiner: Hieu P Nguyen,
Attorney: Cesari and McKenna, LLP, Current U.S. Classification: 330/277;
330/311, Date of Patent: May 17, 2011.
[20] M. Jankowski, A. Napieralski, Novel Structure of CMOS voltage-to-current
converter for high-voltage applications, in: Proceedings of the Nanotech
Conference & Expo, 18–21 June, 2012, pp. 1007–1010.
[21] Bahram Fotouhi, All-MOS voltage-to-current converter, IEEE J. Solid-State
Circuits 36 (1) (2001) 147–151, January.
[22] P. Boonyaporn, V. Kasemsuwan, A high performance class AB CMOS rail to rail
voltage follower, in: Proceedings of the 2002 IEEE Asia-Pacific Conference on
ASIC, 2002, pp. 161–163.
[23] S. Wongfoo, W. Naklo A. Suadet, V. Kasemsuwan, A simple rail-to-rail cmos
voltage follower, IEEE Region 10 Conference—TENCON 2006, 14–17 Nov. 2006,
pp. 1–4.
[24] A. Kanjanop, A. Suadet, P. Singhanath, T. Thongleam, S. Kuankid, V. Kasemsu-
wan, An ultra low voltage rail-to-rail DTMOS voltage follower, in: Proceedings
of the 4th International Conference on Modeling, Simulation and Applied
Optimization (ICMSAO 2011), 2011, pp. 496–500.
[25] P. Kadanka, A. Rozsypal, Rail-to-rail voltage follower without feedback,
Electron. Lett., vol. 36, Issue 2, 02/2000, pp. 104–105.
[26] G. Xing, S.H. Lewis, T.R. Viswanathan, A unity-gain buffer with reduced offset
and gain error, IEEE Custom Integrated Circuits Conf. (2006) 825–828,
September.
[27] Y. Haga, I. Kale, CMOS buffer using complementary pair of bulk-driven super
source followers, Electron. Lett. 45 (18) (2009).