CHAPTER 3

8085 MICROPROCESSOR

In Chapter 1 and Chapter 2, we have gone through the digital fundamentals and
Now we can start learning about the
organisation of a microcomputer respectively.
microprocessor 8085A or simply 8085.

This chapter deals with the following topics.

3.1 Introduction to Intel processors
3.2 Pin functions of 8085
3.3 Architecture of 8085

3.1INTRODUCTION TO INTEL® PROCESSORS

the CPU.
In a microcomputer, a single microprocessor chip functions as

Microprocessors are categorized in terms of the number of binary bits in the data they
available microprocessor was the Intel 4004, a 4-bit
process. The first commercially
processor, produced in 1971. In 1972-73, Intel came out with 8008, an 8-bit processor.

After further modification, 8080 and 8085 were introduced, which are advanced versions of
8-bit processors. By mid 70s, Intel again introduced a revolutionary 16-bit microprocessor
Intel 8086/88. These chips functioned as CPUs for 16-bit microcomputers, which became

popularly known as personal computers PC and PCIXT. The family of Intel microprocessor

chips continued to grow as 80186,80286,80386 and 80486 and Pentium. 80386 and 80486
are 32-bit microprocessors. Pentium has 64-bit data bus, but only 32-bit registers. In this

book, we will concentrate on 8085.

8085 Microprocessor
Intel 8085 is an 8-bit microprocessor. It operates on 8-bit binary words. That is, it has
8-bit data bus and its arilhmetic and logic unit (ALU) and internal registers use 8-bits. The
8085 system has 16-bit address bus and hence it can address any one of 21" memory
locations. In other words, 8085 can access (21 = 65,536) 64KB of memory. Each
memory location can slore 8-bits (or one byte). A 16-bit word (two bytes) has to be stored
in two consecutive memory locations. Just as any simple CPU, the 8085 microprocessor
consists of registers, an arithmetic and logic unit and control and timing circuits. The 8085
 40
Vcc - o Vcc 5V
39 HOLD

RESET OUT 38 HLOA

CLK O
High-order
SOD Address Bus
CLKOUT
36 RESET IN
SID

TRAP 35 READY AD,

SOD
Multiplexed
RST 75 3410M Address/bata Bus
TRAP
AD,
RST 65
RD RST7.5 ALE
RST 55
INTR | WR RST6.5 8085
8085
INTA ALE RSTS.5

INTR
12
3
INTA

HOLD

HLDA
D,
20
As 10/M

AD, 1 6 READY
RD
AD, 17 J A
RESET IN
D 18
23 A WR
RESET OUJT
AD, 22A
GNND
20
GND The 8085 Microprocessor Pinout Pin-out signal function diagram of 8085
Fig (3.1) Fig (3.2) Coumesy nt
8085 MICROPROCESSOR

in assembly language. The

provides 246 instruction codes using which programs are written
instruction set of 8085 is discussed in detail in Chapter 4. The internal architecture of 8085

the different pin functions of 8085.

is explained in section 3.3. First, we will go through

32 PIN FUNCTIONS OF 8085 in

Intel 8085 is fabricated on a single LSI (Large Scale Integration) chip and packaged
40-pin, dual-in-ine package (DIP). The pin details are given in Fig (3.1) and the pin-out

The functions of different pins are discussed

signal function diagram is given in Fig (3.2).
below.

A As (Pins 21 to 28)
these pins. The
The most significant eight bits of the 16-bit address bus is sent over

8-bit l/O address is also sent along these lines during IN and OUT instructions.

AD- AD, (Pins 12 to 19)

The eight data bits D, to D, and the lower order address bits A, to A, are multiplexed
and sent through these pins. While executing instructions, during the beginning of each
machine cycle, the microprocessor 8085 sends out the address A, to A, and in the later

part of the machine cycle, the processor sends out the data D, to D,.

Consider a 2-input multiplexer. Let one input be A, and the other input be D. Let the

output be marked as AD, as shown in Fig (3.3).

OUTPUT
2-1NPUT

MUX
AD

Fig (3.3) Multiplexing one address and one data line

 FUNDAMENTALSOF MICROPROCESSO

state,
tne Ouput AD equal.
uals A
AS Seen in select line S, is in 0
Chapter 1, when the
and ,
are
inermal to the Ic.
When D. A. D, ang
S, is in "1' state, the
output AD, equals see tnat the addressS Dit A
we can
Thus
the output is
brought out on the pin AD. (pin 12). Similar arrangement may
dnd the data bit come
as AD
D, are multiplexed and d outpur a s AD, to AD.
used to bits and get the
multiplex the remaining address and data
Inese eignt address innes
ne lower eight bits of 16-bit address is sent along A, to A,.
dre also used to send 8-bit address during /0 operaion
NOTE: The 8085 sends the 8-bit address on A, to A, as well as on A, O A,s Wnen it uses IN

and OUT instructions for l/O operations.

Howe the lower order address A, to A, and data D, to D, must oe provided with

lines and therefore, the multiplexed address/data ADg O AD, must be

us
demultiplexed which is explained in the next
pardgioP
ALE (Pin 30)
ALE Stands for Address Latch Enable. We have just seen that AD, AD, are muluplexed
address/data ines. At the begining of each machine cycle (first clock period), 8085 sends
the address A A,over the lines AD,- AD, During the same period, 8085 sends out a pulse
called ALE. Using the ALE pulse and an extenal octal latch, the lower order address
A, to A, and data D, to D, are separated. The octal latch, that is used to separate the address
Is now called as an address latch. The pulse that is used to enable the address latch is

hence called Address Latch Enable pulse, ALE. The arrangement to demultiplex address

A A, and data D,-D, from multiplexed AD, AD, is shown in Fig (3.4).

74LS373
8
AD LOw order ACoress
Octal
AD
Latch

ALEJL

.
Datd

Fig (3.4) Demultiplexing Address and Data bus

8085 MICROPROCESSOR
The multiplexed address/data lines AD,-AD, are connected to the input lines of the octal

latch (Refer Ch.1, sec 1) The output control OC is grounded (OC 0), so that output of
the latch is a valid output. We have already seen thal, for the octal lalch (74LS373). when
OC 1 , the output is tristated. At present, let us take valid lower order address A, Ay, The

ALE signal from 8085 is connected to the enable input (EN) of the octal latch.

During the first clock cycle of each machine cycle, the 8085 outputs the address

A A, over AD,AD, At Ihe same time the 8085 gives out the pulse ALE. This pulse enables
the address latch and the address bits A A, are latched and are available at the eight output
lines of the latch. The eight output lines of the latch forms the lower order address- bus of
8085. The lower order address lines A- A, and higher order address lines A, As together
give the 16-bit address bus A A15
The address bus comprising of A, to A, is unidirectional i.e., the 8085 sends out
only the address of the memory or an l/O port through this bus.

In the later part of machine cycle, the 8085 sends the eight data bits D- D, over
AD-AD. After the first clock cycle, the lines AD, AD, act as data bus.

But the data bus D, to D, is bidirectional i.e., the 8085 can send or receive an 8-bit
data from the memory or /O port.

IO/M (Pin 34)

The logic level of lO/M tells external circuitry whether an l/O or memory transfer is taking
place. When the pin is in 1 state, it indicates an lO related operation and when the pin is in
0 state, it indicates a memory related operation.

RD (Pin 32)

A logic 0 on this pin indicates that the processor is performing either a memory read or
an l/O read operation. In other words, a read bus cycle is in progress.

WR (Pin 31)

A logic 0 on this pin indicates that the processor is performing either a memory writeor
an o write operation. In other words, a write bus cycle is in progress.
48
FUNDAMENTALS OF MICROPROCESSOR
OR-
namely Memory t

Combining IO/M, RD and WR four types

of control
signals,
Rea
Write (1OW)
can be geners
(MEMR), Memory Write (MEMW), IwO Read
and I/0
(iOR) erele
Fig (3.3) and function to
yand /O interface circuits.
The logic circuit, able
are given below.

I0/M MEMR

MEMW
WR

OR

OW

Fig (3.5) Generating control signals

O/M RD WR Machine cycle

Memory Read
Memory Write
Read
VO Write

Function Table
 49
8085MICROPROCESSOR
SS, (Pins 33,29)
and can be used to know the type of
These are status signals sent by microprocessor
current operation the 8085 performs. This is given in Table (3.1).

s,S 0
Status
Halt

write

0 Read

Opcode fetch
Table (3.1)

Combining IO/M with S, and S, more speific information about the machine cycle status
can be obtained. This is shown in Table (3.2).

IOM SS Machine Cycle Status

Memory Read

1 Memory Write

/O Read

O Write

0 Opcode Fetch

1 Interrupt Acknowledge
Z 0 Halt

Table (3.2)

NOTE:
HZ- High Impedance

When the microprocessor reads the memory to take the machine code of an instruction,
the memory read machine cycle is referred to as opcode felch.
 FUNDAMENTALS O F M I C R O P R O C E

OCESSOR-
X,, X, (Pins 1,2) the uired
requir circuit to
crystal,
for the
A crystal is connected at these pins. Except a crystal of fren
Grystal controlled oscillator is integrated
within the
chip.
million
Usuaily

clocK puises per

frequene
second. Thig
secon.

6.144 MHz is 6.144

used. This arrangement generates trequency
or n e 8085 system:
requency is the operating 0.32e
internally divided by two and works out to
be taken as the clock period
3.072 MHz. For this frequency,
second (Period 1/ Frequency)
CLKOUT (Pin 37)
so tnat other periph
ystem clock of frequency 3.072 MHz is output through
this pin,
riphera
chips can make use of this stable clock.

SID (Pin 5)
oerial Input Data line, used with serial communication. The data on this line is loaded

1s bit 8 (D,) in the accumulator when 'RIM instruction is executea.

SOD (Pin 4)
Serial Output Data line, used with serial communication. The output SOD is set or
reset as specified by the instruction.
'SIM
INTR (Pin 10)
This is an Interrupt Request pin. It is used as a general purpose interrupt. When 8085
isinterrupted using this pin, the processor completes the current instruction and diverts to
execute an Interrupt Service Routine (ISR). This interrupt can be enabled or
disabled by
software.

INTA (Pin 11)

It is an Interrupt Acknowledge signal after INTR is received.

RST 5.5,RST 6.5 and RST 7.5 (Pin 9,8 and 7)

Restart Interrupts. These are vectored interrupts and transfer the program control
specific memory locations as shown below.

RST 5.5 Program counter modified to 002C

H
RST 6.5 -

Program cOunter modified to 0034

RST 7.5 -

Program counler modified to 003C

 8085 MICROPROCESsOR

TRAP (Pin 6)
This is a nonmaskable interrupt. When an interrupt occurs through this pin, the program
control is transferred to the memory location 0024

NOTE: 8085 interupts are discussed in detail in Chapter 10.

RESETIN (Pin 36)

An active low signal on this pin resets the microprocessor i.e., the program counter is

made 0000, and execution of instructions start from that point. The buses are also tri-stated.

RESET OUT (Pin 3)

Reset out indicates that the CPU is being reset. It can be used to reset all the peripheral

chips connected to the microprocessor.

HOLD (Pin 39)

A logic 1 on this pin indicates that another master circuit is requesting the use of address

buses. The CPU, upon receiving the HOLD request, will relinquish the use of the
and data
after the current bus transfer. The processor can regain the bus after the
bus completing
HOLD is removed. When HOLD is acknowledged, the address bus, data bus and the control

lines RD, WR and 1O/M are tri-stated.

HLDA (Pin 38)

This is Hold Acknowledge pin. It indicates that the CPU has received the HOLD request

and will relinquish the bus in the next clock cycle.

NOTE: HOLD and HLDA are used in Direct Memory Access (DMA) operation, discussed in

Chapter 8.

READY (Pin 35)

I READY is high during a read or write cycle, it indicates that the memory or

peripheral is ready to send or receive data. If READY is low, the CPU will wait for an integral

number of clock cycles. This is used when the external memory or I/O devices connected

to the microprocessor have a slower response. Using external logic circuits, the READY
pin of 8085 can be made zero tor a fxed number of clock cycles i.e. 8085 can be made
to go into a 'wait' state. The 8085 proceeds with its normal operations once the READY

pin goes high.

 INTA RST 5 A
INTR RST SS pET SIO
S 50

rterupt Control Serial Vo Contror

8-Bin Snternal Oata Dus

Accumuiator Temp Reg

(8)
)
Flag (5)

eg
Keg

thmetie
Instruction
Decoder
Register
ATay
Machine (16)
Cycle Stack Pointer
ALU Encoding
(16)
Program Counter

TIMING AND CONTROL Address Bufer Data l Address Buffer )

- GEN
CLK
Control DMA Re
Status
RESET

RD WR ALE S. S. 1OIM HLDA OUT

CLK OUT
READY HOLD RESET IN Ooress
Bus AD,
Address /Data Bus

Fig (3.6) Internal Architecture of 8085 Courtesy tnte8085 famiy manual

8085 MICROPROCESSOR
Vcc and Gnd (Pins 40, 20)
These are the power
supply pins for 8085. The 8085 operates on a 5 Volts power
supply.

3.3 ARCHITECTURE OF 8085

The internal architecture of the microprocessor 8085 is shown in Fig (3.6). A close
look at the figure shows that it includes the following units.
I.Register Array
II. ALU and associated
circuitry
II. Instruction Register and Decoder
IV. Timing and Control
Unit
V. Interrupts and Serial I/O
We will discuss the above units one by one.

L.REGISTERARRAY
The 8085 has six general purpose registers named as B, C, D, E, H and L. Each
register can hold an 8-bit data. The six registers can also
be combined as register pairs
BC,DE and HL. A register pair now, can hold a 16-bit data or a 16-bit address. When
used as an 8-bit register, each
register can store a data ranging from
00, to FF
(0 to 255). As a register pair, they can store a data ranging from
0000, to FFFF
(0 to 65,535). Since the registers are used for temporary storage of data, these
registers
are also sometimes called as 'scratch pads'
The instruction set of 8085 contains a number of instructions to move (copy) a data
from one register to another register. For example, the instruction MOV B, A moves (copies)
the contents of A to B
register register
Of the register pairs, HL pair has some special functions. For example, the HL pair is
used to address memories or HL pair acts as a memory pointer
If HL 2050, and B =
36,, then
the instruction
MOV MB
transfers the contents of B (36,) to a memory location whose address is 2050,, available
in HL register pair.
54 FUNDAMENTALS OF MICROPROCESSOR B085

Also, 16-bit addition instructions (like DAD B) requires the use of HL pair, The

instructions are discussed in detail in Chapters 4 and 5.

Program Counter (PC)

The program counter is a 16-bit register. The PC holds the 16-bit address of the

memory from which the next byte is to be fetched. The byte may correspond to an opcode

(machine code or binary code) of an instruction or simply an 8-bit data. When a byte is

being fetched, the program counter is automatically incremented by one to point to the next

memory location.

Stack Pointer (SP)

The stack pointer is also a 16-bit register. It holds the address of the stack top.
stack is a group of memory locations in RAM defined by the programmer. The stack is
used to save the contents of the registers and during interrupts and subroutine cals. Stack
and stack related instructions are discussed in Chapter 5.

Address latch - Incrementer/Decrementer

The address latch is useful in selecting the address of the memory to be sent out from
program counter or stack pointer or any of the register pairs. An incrementer and
decrementer allows the contents of any of the 16-bit registers which hold the address, to
be incremented or decremented.
The higher order address A, to A,, is sent out through an address buffer. The lower
order address A, to A, and dat D, to D, are multiplexed and sent out through an address!
data buffer as AD, to AD,.

I. ALU AND ASSOCIATED CIRCUITRY

The Arithmetic Logic Unit (ALU) of 8085 performs arithmetic and logic operations on
two 8-bit data. The ALU combines ith a special register called the accumulator, a temporary
register and five flag fip-flops to carry out the arithmetic and logic functions. Arithmetic
operations like addition, sublraction elc., and logic operations like AND, OR, EX-OR etc.
afe pertormed here

When arithmetic or logic operation is performed on two operands, the ALU of 8085
takes one operand from the accumulator and the second operand from any one of the
8085MICROPROCESSOR_
general purpose registers (B, C, D, E, H, L) or from a memory localion. The result is placed
in the accumulator. Depending on the result in the accumulator, five flags ar flag flip-ilops
are set or reset. The five flag bits are stored in an 8-bit register called as flag register.
Since the lag bits indicate the status of the result in the accumulator, the flag register is

also called as a status register.

Accumulator

The accumulator is a special 8-bit register. This register is used to store 8-bit data as
well as to perform anithmetic and logic operations, This register is identified as A.

While performing arithmetic operation like addition, one of the operands is automatically
assumed to be in A register. Also, the result of the addition is placed in A register. For

example, the instruction

ADD B

adds the contents of A register and B register and sends the result to A register

f (A)= 25, and (B) =

37, then the instruction ADD B, adds 25, and 37,and
stores the result 5 , in the accumulator. After execution of this instruction, the contents of
A is changed but the contents of B is not affected.

i.e. (A)= 5C, and (B) =

37
Data flow'between different registers takes place using an internal data bus within
thechip.

The accumulalor is also used during l/O operalions which use IN and OUT
instructions
VO interface is discussed in Chapter 9.

Temporary Register
The temporary register simply receives one of the operands from the internal data bus

and sends it to the ALU. The other operand is received from the accumulator and the
required
arithmetic logic operalion is carried out. In the
or
example ADD B, the contents of A register
directly goes to ALU but the contents oft B register is lirst sent to the temporary register and

then to the ALU

 F U N D A M E N T A L SO F MICROPROCESSC

operation

anthmetic
or logiC
each
Flag Flip-Flops after
are set or reset
that
here ar five flip-flops
discussed below.
are
The different flags
operation and
Carry Flag- CY anthmetic or logic
an
is produced by result is
is set to 1 if a carry numbers and if the
The carry flag instruction adds
two
For example,
if an other hand, if
is reset to 0.
On the
reset to 0 for no carry.
CY flag
and the
then no carry is
produced
set to 1.
The carry flag
less than FF and the CY flag is
hen a carry is produced is subtracted
the result exceeds FF, when a bigger number
subtraction operation
also serves as a borrow flag during
some compare operations).
from a smaller
number (and during

is zero and
Zero Flag-Z an arithmetic
or a logic operation
result of
The zero flag is set to 1 if the have the same
and B register
is non-zero. For example, if A register
reset to 0 if the result is placed in the
resultis zero which
perform SUB B operation, the
data, and if we are not
When the data in A and.B registers
Z is set to 1.
accumulator. Now the zero flag the zero
result in the accumulator
is not zero and hence
the
equal, after SUB B operation,

flag Z is reset to 0.

Parity Flag-P is said to have

is used to indicate the number
of 1's in a given byte. The byte
Parity
even number of 1's and the byte is said to have 'odd parity' if
even parity if the byte has
The parity flag is set to 1 if the data in the accumulator
the byte has odd number of 1's.

and reset to 0 if the data in the accumulator

has an odd parity. The parity
has even parity
flag is useful for error checking during serial communication.

Sign FlagS
The sign flag is used when working with 8-bit signed (positive and negative) numbers.
When we are using signed numbers, the most significant bit (MSB), D, is used as a sign

bit. f D, bit is 0, then the number is taken as a positive number and if D, bit is 1, the number
Is taken as a negative number in 2's complement form. In 8085, the sign flag is set to 1 if
the MSB D, is 1 and the sign flag is reset to 0 if the MSB D, is 0.
 8085MICROPROCESSOR
Auxiliary Carry Flag - AC

The auxiliary flag is set to 1, when a carry is generated at digit D, position and passed
on to digit D, This flag is used only internally for BCD operations and not available for the

programmer. That is, the programmer cannot use the auxliary cary flag condition to change
the sequence of the program.
The relative bit positions of different flags in an 8-bit flag register is shown in Fig (3.7).

D, DD, D, D D, D, D

Fig (3.7) Bit positions in Flag register

Among the five flags, Z flag and CY flag will be widely used when we start learning
assembly language programs. The sign flag S must be used only with signed numbers. As
mentioned already, the auxiliary carry flag is used internally for BCD operations and not
javailable for the user.

While using the fag condition in our programs, let us remember some points:

D a t a transfer instructions do not affect

flags.
Eg: MOV B,C MVI A,5CSTA 2050
*All logic instructions and most of the arithmetic instructions affect all lags.
Eg: ADD B SUB C ORA B

*Increment and decrement operations involving an 8-bit register do not modify

carry flag
Eg: INR B DCR C

*Increment and decrement operations invoving 16-bit register pairs (BC, DE, HL)
do not affect any flag.
Eg: INX H DCX D

16-bit additions using register pairs modity only carry flag.

Eg DAD B DAD D

The examples given above and all other instructions in the instruction set of 8085 are

explained in Chapters 4 and 5.

58
FUNDAMENTALSOF MICROPROCESSOR 805

Example 3.1
and (B) =

68, After executing ADD B instruction, what will be the

Assume (A) =79,
status of the flags? What will be the content of the flag register?
content of A register and

Solution:
the result in
The instruction ADD B adds the contents of A and B registers and places
Aregister

(A) 0111 1001

(B) 68, 0110 1000

1110 0001

The result in the accumulator is E1

The result is less than F Therefore Carry flag is reset.
The MSB of the result is 1. Therefore the Sign flag is set. The sign flag is used only with
need not be used.
signed numbers. For unsigned numbers, as in
this example, sign flag
The result is not zero. Hence, the Zero flag is reset.
The result has even parity. So the Parity fag is set.
During the addition, a cary is generated at position D, and passed on to D. Therefore the

auxiliary carry flag is set.

The flag register bit position is as shown.

D, D D D, D,D, D, D,

Assuming X = 0, the flag register will have the bit values as

D, D. D, D, D, D, D, D

The content of the flag register is 94, (If we take X = 1, the content of tie flag

registeris BE,)
 59
8085MICROPROCESSOR
I. INSTRUCTION REGISTER AND DECODER
We have seen in Chapter 2, that a microcomputer executes a program by first loading
the machine codes of the instructions in successive locations of memory and then executing
the instructions one by one. The 8085(CPU) sends the address of the memory location,

which holds the machine code of the instruction. The 8085 uses its 16-bit address bus for
The
this. Next, the 8085 sends out a control signal called memory read, to the memory.
to be the machine code of an instruction, now falls
contents of the memory, which happens
it receives the machine
on the data bus and reaches the processor. In 8085, whenever
code of an instruction, the machine code directly goes to the Instruction Register through
is usually referred to as OPCODE FETCH
the internal data bus. This cycle of operation
cycle.
The machine code of the instruction is now transferred to the next section named as

instruction decoder. Some of 8085 instructions are completed in just one machine cycle,

instructions require two machine cycles, namely an Opcode

namely, Opcode Fetch. Some
Fetch followed by Memory Read. Few other instructions take three or four machine cycles.

Chapter7. In this block, named

The timing diagrams of few instructions are explained in

the instructions aYe understood (decoded) and the total number of

instruction decoder,
machine cycles required is decided.

V. TIMING AND CONTROL UNIT

is passed on to the timing and
The instruction is decoded and necessary information
control unit of 8085. Depending on the instruction, the timing and control unit generates
the required timing and control signals for executing the instructions. The follawing signals

are associated with this block.

Control RD WR (Output)

Status S, S. 1O/M (Output)

DMA HOLD (input), HLDA (output)

RESET OUT (output)
RESET RESETIN (input),
The READY pin which is used to introduce 'wait' states is connected to this block. Also,

by using an external crystal, high frequency clock pulses are produced. The crystal frequency
is divided by two and used as system clock. The clock is also sent out through the pin

CLOCK OUT for use with peripheral devices. Also, the timing and control circuit controls
60 FUNDAMENTALS OF MICROPROCESSOR BO8

all the other circuits inside 8085. [Note the line connecting the timing and control circuit with

all other blocks in Fig (3.6).]

V. INTERRUPTS AND SERIAL I/O

The 8085 microprocessor can be interrupted by any one of five interTupt input pins
namely, INTR, RST 5.5, RST 6.5, RST 7.5 and TRAP. Interrupts in 8085 are discussed in
Chapter 10.

Normally, a CPU communicates with the peripherals using the data bus where data
flows in or out in parallel. But, for specific purposes, data transfer can also take place in
serial form. Two pins SID and SOD are used for this purpose. Serial I/O is also done using
a serial communication device 8251.

EXERCISE:
1. Why are the lines AD,- AD, multiplexed? How these lines
are demultiplexed?
Explain the functions of the following pins.
a) ALE b) IO/M c) RD d) WR
3. Explain the use of HOLD and HLDA pins.
4. Mention the use of SID and SOD
pins.
5. What is the use of READY pin in 8085?
6. Discuss the Address, Data and Control bus structure of 8085.

7. What the
are
different registers in 8085? Explain their uses.

8. Discuss the special nature of Accumulator.

9. Explain the function of Instruction
Register in 8085.
10. What do you understand
by machine cycle and instruction
cycle?
11. Discuss the flag structure in 8085.
12. Assuming (A) =
CF, and (B)= 75,, predict the status of all the flags
after ADD B instruction.

13. Explain the function of ALU in 8085.

14. Specify the crystal frequency required for the 8085

system to operate at 1.5 MHz.
15. Draw and explain the funclion table using the status signals
S,. S, and IO/M.
++¢++