MICROPROCESSOR & MICROCONTROLLER REPEATED QUESTIONS

S.NO QUESTIONS & ANSWERS CONCEPTS YEAR

1. Which is lowest priority interrupt of 8086 microprocessor? 2021
1. INTR, 2. NMI, 3. INT, 4. SINGLE‐STEP
Correct Answer :‐
INTR
2. Which of the following are the major steps which are taken to troubleshoot a
microcomputer system? Assume all ICs are in the socket.
A. Identify the symptoms and make a careful visual and tactical inspection.
B. Check the power supply.
C. Switch OFF and ON the system.
D. Check the control signals such as 2021
Choose the correct answer from the options given below:
1. A and C only, 2. A, B and D only
3. A, B and C only, 4. C and D only
Correct Answer :‐
A and C only
3.

2021

4. Arrange the different operations to run instructions in a computer system, from the
beginning to last stage
A. Instruction decode
B. Instruction fetch
C. Operand fetch 2021
D. Execute
1. A, B, C, D, 2. B, A, C, D, 3. C, D, A, B, 4. D, B, C, A
Correct Answer :‐
A, B, C, D
5.

2020
NOV S-1

6. The program written below gives

MOVA #85H
CPLA,
ADDA,# 2020
1). 7BH NOV S-1
2). 78H
3). B7H
4). 87H
7. What happens if Interrupts INTO. TFO and INT 1 -are activated at t he same time?
1) They are latched and kept internally
2020
(2) They are latched and kept externally
NOV S-1
(3) They are unlatched and kept internally
4) They a1·e unlatched and kept externally
8.

2020
NOV S-1
9. Keyboards are organised in a matrix. The CPU of 8051 accesses- both rows and columns
through its ports. So. it can access
(A 4 x 4 matrix of keys
(B) 8 x 8 matrix of keys
C) 16 x 16 matrix of keys
(D) 2 x 2 matrix of keys 2020
(E) 32 x 32 matrix of keys NOV S-1
Choose the most appropriate answer from the options given below :
(B) only
C) only
(A) only
(D) and (E only
10. ANS: 3 2019
DEC S-1

11. What is the value of Register A at the end of program given below
MOV A. !I 3G H
RR.A
RR.I\
2019
RR.I\
DEC S-1
(1) 0110 0011
(2) 1100 0110
(3) 1000 1101
(4) 0011 0001
12. ANS: 3

2019
DEC S-1

13. ANS: 1

2019
DEC S-1

14. ANS: 4

2019
DEC S-1
15. ANS: 3
2019
DEC S-1,
& S-3

16. ANS: 3

2019
DEC S-1

17. In 8086 microprocessor, if DS = 1100 H, BX = 0200 H and SI = 0500 H, the address

accessed
by
MOV CH, [BX + SI] is 2019
(1) 00300 H DEC S-3
(2) 11700 H
(3) 0700 H
(4) 01800 H
18. In 8086 microprocessor, if DS = 1100 H, BX = 0200 H and SI = 0500 H, the address
accessed
by
MOV CH, [BX + SI] is 2019
(1) 00300 H DEC S-3
(2) 11700 H
(3) 0700 H
(4) 01800 H
19. What is the value of Register A at the end of program given below
MOV A,#36H
RRA
RRA
2019
RRA
DEC S-3
(1) 0110 0011
(2) 1100 0110
(3) 1000 1101
(4) 0011 0001
20. What is the value of Register A at the end of program given below
MOV A,#36H
RRA
RRA
2019
RRA
DEC S-3
(1) 0110 0011
(2) 1100 0110
(3) 1000 1101
(4) 0011 0001
21. What will be the status of CY, AC and P flags after implementation of following sets of
instructions in 8051 microcontroller
MOV A,#CCH
ADDA, #A9H 2019
CY= 1, AC = 1, P = 0 DEC S-3
CY = 1, AC = 1, P = 1
CY = 1, AC = 0, P = 0
CY = 0, AC = 1, P = 1
22. Which Register Bank of 8051 1nicrocontroller is used after implementing the following
instruction
SETB PSW.4
2019
Bank 0
DEC S-3
Bank 3
Bank 1
Bank 2
23. In 8086 microprocessor, if DS = 1100 H, BX = 0200 H and SI = 0500 H, the address
accessed
by
MOV CH, [BX + SI] is 2019
(1) 00300 H DEC S-3
(2) 11700 H
(3) 0700 H
(4) 01800 H
24. Contents of which memory location is transferred to register AL after execution of the JUNE 2019
following 8086 program? S-1
MOV ex, 2050H
 MOV DS, CX
MOV AL, [F025)
L OF025
2. F0250
3. 2F525
4. 20500
25. \Vhich of the following is 16 bit register of 8051 microcontrollcr?
I. DPL
JUNE 2019
2. SBUF
S-1
3. SP
4. TCON
26. \Vhicb js invalid 8051 microcontroller instruction?
I. MOVX @DPTR, A
JUNE 2019
2. RA A
S-1
3. MOV DPTR,# 2500
4. DAB
27. If 8051 microcontrollcr is rated at 25 MHz., what is the maximum frcqu~cy that
can be
connected to it?
JUNE 2019
I. 12·5 MHz
S-1
2. 25 MHz
3. 50 MHz
4. 30 MHz
28. \vnich bit address is assigned to PCON register?
I. 8811
JUNE 2019
2. 78H
S-1
3. 80H
4. 87H
29. If the contents of register AX is 4C26H, which of the following instructions clear the
contents of accumulator (AX) in case of 8086 microprocessor?
(a) NOT A){
(b) XOR AX,AX
(c) SUB AX,AX
JUNE 2019
(d) NEG AX
S-1
Choose the correct answer :
1. (a) and (c)
2. (b) and (c)
3. (b), (c) and (d)
4. (a) and (b)
30. Which of the following arc control flags of 8086 microprocessor?
(a) Carry flag
(b) Zero flag
(c) Trap flag
(d} Direction flag JUNE 2019
Choose the correct answer : S-1
I. (a}and(b)
2. (c} and (d)
3. (a} and (c}
4. (b) and (d)
31. Tue pin signals of 805 1 microcontroller as follows :
(a) PSEN
(b) RD
(c) R><D
(d) EA JUNE 2019
Atrange them in ascending order of their pin numbers. Choose the correct option : S-1
L (C), (b), (a), (d)
2. (b), (C), (d), (a)
3. (d), (a), (b), (C)
4. (a), (b), (d), (C)
32. Assertion (A) : 8086 microprocessor is a ttue 16-bit microprocessw.
Reason (R) It consists of two main sections, bus interface unit (BIU) and
execution unit (EU).
Choose the correct answer : JUNE 2019
I. Both (A) and (R) are true and (R) is the correct explanation of(A) S-1
2. Both (A) and (R) are rrue, but (R) is not the correct explanation of(A)
3. (A) is true, but (R) is false
4. (A) is false, but (R) is 1111,
33. Two machine codes 3EH and 32H are stored in memory locations 2000H and 2001H
respectively. The first machine code (3EH) represents the opcode to load a data byte in
the accumulator, and the second code (32H) represents the data byte to be loaded in the
accumulator. The time required executing the Opcode Fetch and the memory Read
Cycles and the entire instruction cycle is, (if clock frequency is 2 MHz) .
Options:- DEC 2018
1. 3.5 μs
2. 3.5 ms
3. 0.5 μs
4. 1.5 μs

34. RAL is an example of

Options:-
1.Register Addressing mode
DEC 2018
2.Register Indirect Addressing mode
3.Immediate Addressing mode
4.Implicit Addressing mode
35. Which of the following statements are correct in respect to 8086 μp ?
(a) The instruction queue size is 8 bytes
 (b) Segment register size is 16 bit while physical address size is 20 bits
(c) Segments are disjoint
(d) Beginning address of a segment must be divisible by (16)10
The correct answer is :
(1) (a) and (b) are correct JULY
(2) (b) and (d) are correct 2018
(3) (b) and (c) are correct
(4) (a) and (c) are correct
36. What happens when RET statement is executed in 8085 μp ?
(a) Program counter is cleared
(b) Control is transferred from the subroutine to the main program
JULY
(c) Returning address is loaded into the accumulator
2018
(d) Returning address is loaded into the program counter from the top of the stack
The correct answer is :
(1) (a) and (c) (2) (b) and (d) (3) (a) and (b) (4) (b) and (c)
37.

JULY
2018

38.

JULY
2018

39.

JULY
2018

40. Arrange the following pins of 8086 μp in the descending order :

(a) INTR (b) ADo (c) MN/MX (d) LOCK
The correct sequence is :
JULY
(1) (b), (c), (a), (d)
2018
(2) (c), (d), (a), (b)
(3) (d), (b), (c), (a)
(4) (a), (d), (b), (c)
41. Assertion (A): A two byte instruction of 8085 has an operation code in first byte and
operand/address in the second byte. JULY
Reason (R): Source and destination addresses are made implicit in order to reduce the 2018
length of an instruction.
42. Assertion (A): In 8086 μp, ALE is provided by the processor to latch the address into the
8282/8283 address latch. JULY
Reason (R): Whenever the processor sends a valid address on the multiplexed AD0- 2018
AD15 lines, it also makes the ALE high.
43. In microprocessor 8086
(a) The 8086 is a 16 bit processor with 16 bit internal and external data bus.
(b) The instruction queue (IQ) length is of 4 bytes.
(c) While entering HLT in minimum mode ALE is delayed. JAN 2017
(d) The control pin in 8086 is M IO P-2
Out of the following which one is correct :
(1) (a) and (b) are correct. (2) (a) and (c) are correct.
(3) (a) and (d) are correct. (4) (b) and (d) are correct.
44.

JAN 2017
P-2

45. Assertion (A) : For data transfer between 8085 microprocessor and memory, CE input of
JAN 2017
memory is connected to IO/-M of microprocessor.
P-2
Reason (R) : Microprocessor is enabled for data transfer when IO/-M goes high.
46. For pushing of flags and popping of flags in 8086, the instructions are :
JAN 2017
(1) Push and Pop (2) Push F and Pop F
P-3
(3) Push and Pop F (4) None of the above
47.

JAN 2017
P-3

48. Consider the following registers :

(a) A and B registers (b) B and C registers
(c) D and E registers (d) H and L registers
JAN 2017
Which of these 8-bit registers of 8085 microprocessor can be paired together to make
P-3
a16 bit register ?
(1) (a), (c) and (d) (2) (a), (b) and (c)
(3) (b), (c) and (d) (4) (b), (d) and (a)
49. Consider the following instructions of 8085 microprocessor :
(a) MOV M, A (b) ADD C
(c) MVI A, FF (d) CMP M JAN 2017
Which of these cause change in the status of flag(s)? P-3
(1) (a) and (b) (2) (b) and (d)
(3) (a) and (c) (4) (b) and (c)
50.

JAN 2017
P-3

51. Arrange the following in descending order w.r.t. their pin numbers of 8251 USART :
(a) CLK (b) DTR
(c) CTS (d) CS
Codes : JAN 2017
(1) (d) (c) (a) (b) P-3
(2) (c) (b) (d) (a)
(3) (a) (d) (b) (c)
(4) (b) (a) (c) (d)
52. Assertion (A) : A low WR means a write operation and a low RD means a read
JAN 2017
operation.
P-3
Reason (R) : WR and RD both cannot be low at the same time.
53. What are the names of 16 - bit registers in 8085?
(a) SP (b) PC (c) Accumulator (d) W
NOV 2017
Options :
P-2
(1) (a) and (b) are correct (2) (c) and (d) are correct
(3) (a), (b) and (c) are correct (4) (b), (c) and (d) are correct
54.

NOV 2017
P-2

55. Assertion (A): Architecturally 8086 μp is totally different from its predecessor 8085 μp
but functionally it is downward compatible with 8085. NOV 2017
Reason (R): The segmented architecture was introduced in 8086 μp to keep compatibility P-2
with 8085 μp.
56.

NOV 2017
P-3

57. Arrange the following operations of DMA to transfer a block of data.

(a) Terminal count register is decremented by one with each byte of data transfer till it
reaches to zero.
(b) DMA controller acquires bus system and starts transferring the data.
NOV 2017
(c) Microprocessor suspends its operations, release the buses and generates HLDA.
P-3
(d) DMA controller sends HOLD
The correct sequence is :
(1) (d), (b), (c), (a) (2) (d), (c), (b), (a)
(3) (d), (c), (a), (b) (4) (c), (d), (b), (a)
58. Assertion (A) :
The address bus size in 8086 is 20 bit. NOV 2017
Reason (R) : P-3
Registers size of 8086 microprocessor is 16 bit.
59. For the counter to count upwards starting from 0000 to 1111, following statement are
given :
(a) LOAD input is high (b)
––––––
JULY 2016
LOAD input is high
P-2
(c) CLEAR is high (d) Enable input is low
Out of the above, the following is the correct answer :
(1) (a), (b) and (d) (2) (b), (c) and (d)
(3) (a), (c) and (d) (4) (b) and (c)
60. Assume that the 8255 gets selected whenever A15 – A11 are high during I/O read or
write
cycles. The A2 and A1 are connected to A1 and A0 of 8255 chip, then the address for
port C of 8255 is
JULY 2016
(a) FEh (b) 03h
P-2
(c) FF03h (d) FFh
Codes :
(1) (a) and (b) are correct (2) (c) and (d) are correct
(3) (a) and (d) are correct (4) (b) and (d) are correct
61.

JULY 2016
P-2

62. Contents of ‘A’ register after execution of the following 8085 microprocessor program is JULY 2016
MVI A, 55 h P-3
 MVI C, 25 h
ADD C
DAA
(1) 22 h (2) 50 h
(3) 80 h (4) 7 Ah
63. The ALE line of an 8085 microprocessor is used to
(1) latch the output of an I/O instruction into an external latch.
JULY 2016
(2) deactivate the chip-select signal from memory devices.
P-3
(3) find the interrupt enable states of the TRAP interrupt.
(4) latch the 8 bits of address lines AD7-AD0 into an external latch.
64. Word 20 contains 40
Word 30 contains 50
Word 40 contains 60
Word 50 contains 70
Which of the following instructions loads 60 into the accumulator ?
(a) load immediate 60 JULY 2016
(b) load direct 30 P-3
(c) load indirect 20
(d) load indirect 30
Which of the above statements are correct ?
(1) (a) and (c) (2) (a) and (b)
(3) (a) and (d) (4) (c) and (d)
65.

JULY 2016
P-3

66. Assertion (A) : The default address for starting the execution of the program is from
JULY 2016
0000H. This is valid for Intel processors.
P-3
Reason (R) : The starting address of RAM is from 0000H.
67. The number of wait states required to interface 8279 to 8086 with 8 MHz clock are
SEP 2016
(1) One (2) Two
P-2
(3) Three (4) None
68. The number of wait states required to interface 8279 to 8086 with 8 MHz clock are
SEP 2016
(1) One (2) Two
P-2
(3) Three (4) None
69. The 8085 μp enters into bus idle machine cycle whenever
(a) INTR interrupt is recognized
(b) RST X.5 is recognized
(c) When content of register B is 00h SEP 2016
(d) DAD rp instruction is executed P-2
Options :
(1) (a) and (c) are correct (2) (b) and (d) are correct
(3) (c) and (d) are correct (4) (b) and (c) are correct
70.

SEP 2016
P-2

71. Assertion (A): Ready pin of 8086 microprocessor is used to introduce wait states.
SEP 2016
Reason (R): Because the WR and ALE signals are not available directly from the
P-2
processor in maximum mode.
72. What will be the contents of register AL after the following has been executed?
MOV BL, 8C
MOV AL, 7E SEP 2016
ADD AL, BL P–3
(1) 0A and carry flag is set (2) 0A and carry flag is reset
(3) 6A and carry flag is set (4) 6A and carry flag is reset
73. A sequence of two instructions that multiplies the contents of the DE register pair by 2
and
stores the result in the HL register pair (in 8085 assembly language) is
(a) XCHG (b) DAD B SEP 2016
(c) XTHL (d) DAD H P–3
Option :
(1) (a) followed by (b) (2) (c) followed by (d)
(3) (a) followed by (d) (4) (c) followed by (b)
74. Assertion (A) : In Intel 8085, the lower byte of address and data are multiplexed. SEP 2016
Reason (R) : This helps to limit the number of external pin terminals. P–3