Pruthvi Benagi

Home Address: #16, Minaxi Nilaya, opp Gurudwara, Despande Nagar, Hubli -580029
LinkedIn: https://www.linkedin.com/in/pruthvi-benagi-5a1a3a193/
Contact Details: pruthvibenagi6@gmail.com | +91 9731074928

CAREER OBJECTIVE
Organized and motivated with good Innovative and grasping Skills, and responsible Design Automation Engineer having
1.2+ years of experience in Design automation and Custom layout. Team oriented individual with good attitude towards
sharing knowledge along with interest to explore. I have a good knowledge in Analog Circuit Design, layout and Design
automation and its respective tools which will enrich and utilize my skills efficiently for the organization’s growth.

EDUCATION EXPERIENCE
KLE Tech University Design Automation Engineer
Hubli, Karnataka HCL Technologies (Sankalp Semiconductor), Hubli
B.E. ELECTRONICS AND From Sept 2021 – Present
COMMUNICATION
ENGINEERING VLSI Design Automation Projects
2017-2021 |CGPA: 9.01
Automation for Design Rule Deck
• Description: Developed more than 100+ Boundary DRC rules
Vidyaniketan PU for n3e technology.
Science college • Language used: Calibre SVRF
Hubli, Karnataka
(XII) Automation for Custom library
2016-2017| Marks: 93.5 % • Developed an automation for custom library quality checks.
• Language used: Python, Skill, Calibre DRV and Calibre SVRF
• Developed an automation to compare the golden vs custom
Dr.G.V.Joshi Rotary Eng cells based on the layer pattern.
• Language used: Python and Calibre TVF
Med High school
Hubli, Karnataka Automation for LIBGEN3
(X) • Developed an automation to for generating the Calibre and
2014-2015| Marks: 95.20 % CIM view for n3 technology.
• Language and Tools used: Python, skill, cadence and Calibre
tools
SKILLS
Automation for CIPGEN
Programming languages • Developed an automation to enable the open access
• Calibre SVRF verification (lvs compare for the given original .gds file and .cdl
• Python
file) for n3, n3e, n5, c16 and s14rf technologies.
• Cadence skill
• Language used: Python and Skill
• Calibre TCL
• Basics of C
Automation for Design packages
• Embedded C
DPSCOUT, DPCERTIFY and AMSL1QA
• Developed an automation on design packages which includes
verifications with quantitative and qualitative checks performed
Software/Platforms within few seconds and provides a complete overview of the
• Cadence Virtuoso current development status of the design package.
• Code blocks • Language used: Python and Skill
• Keil V4
Custom Layout Training for 180nm technology
ekLakshya Innovation Labs, Hubli
Non-technical From Sept 2021 – Feb 2022
• Good Communication skills
• Problem-Solving Skills • CMOS fabrication
• Keen Learner • Layout design for Standard Cell and digital circuit
• Self-Motivated • Schematic and Layout design of Arithmetic logic unit
• Layout design of Operational amplifier and Bandgap reference
• Layout design of PLL in UMC180
• DRC automation
Achievements
• Tookpart in KPIT SPARKLE for
an embedded project AUTO-
TRuVID (Automatic Traffic
Rules Violation Detector).
• Received Certification for the
contributing entitled “Ring
Oscillator with Improved
Design” in the 34𝑡ℎ
International Conference on
VLSID Design and 20𝑡ℎ
International Conference on
Embedded Systems.
Declaration
I hereby declare that the information furnished above is true to the best of my knowledge.
Place: Hubballi
Academic Projects
KLE Technological University, Hubli
From June 2017 - March 2021
AUTO-TRuVID (Automatic Traffic Rule Violation Detector)
• To implement a prototype that detects and identifies some of
the major traffic rules violated by people by using embedded
system with help of sensors.
• Language used: Embedded C
Design of 2 stage op-amp
• To Design a Buffer of vref (1.2V), with min gain (45db),
bandwidth of (7MHz), GM of min (-15db) and PM of min
(45db).
• Tool used: Cadence virtuoso
Improved Ring Oscillator
• To design an efficient ring oscillator of 1MHz frequency with
very less variations across PVT.
• Tool used: Cadence virtuoso
Pruthvi Benagi