University of Skikda Electrical engineering department Year 2022/2023 Sem 02

Level/Speciality: Master1 Instrumentation Duration: 1 h 30 min

Documents: Not allowed Date: 21st May 2023
Exam: Advanced digital electronics: VHDL-FPGA
Vdd
Exercise 01: (4 pts)
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Consider the following CMOS circuit:

1.1 Give the truth table of the output Y

according to inputs a and b. 𝑎 Y

1.2 What is the name of the function

performed by this CMOS circuit.
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Exercise 02: (8 pts) GND

Consider the following circuit defined by its timing diagram:

2.1 Give the truth table of this circuit.

2.2 Give the VHDL description of this circuit.
2.3 Add to this circuit a third input ‘reset’. The output
is ‘0’ when reset=1.
2.4 Write the entity/architecture of the question 2.3.

Exercise 03: (8 pts)

Let us consider the following circuit:

3.1 Give a VHDL description of the d-flip flop used in the circuit (synchronous clear).
3.2 Give a structural VHDL description allowing to implement the previous circuit in an FPGA
development board.
3.3 What is the name of the function performed by this circuit.

Dr. A. Ganouche Page 1 of 1 Good luck!