University Skikda Electrical engineering department Year 2022/2023 Sem 01

Level/Speciality: Master1 Telecommunications Systems Duration: 1 h 30 min

Documents: Not allowed Date: 16th Jan 2023
Exam: Programmable logic devices FPGA

Exercise 01: (4 pts)

Consider the following CMOS circuit:

Vdd

= PMOS =

B
Y
= NMOS =

GND

1.1 Give the truth table of the output Y according to inputs A and B.
1.2 What is the function performed by the above circuit.

Exercise 02: (8 pts)

Consider the following VHDL architecture of a T flip-flop:

architecture des of exo2_2023 is aaa<=not(aaa);

signal aaa:std_logic:='0'; end if;
begin end if;
process(clk) end process;
begin q<=aaa;
if clk'event and clk='1' then end;
if t='1' then

2.1 Complete the following timing diagram:

Dr. A. Ganouche Page 1 of 2 Good luck!

University Skikda Electrical engineering department Year 2022/2023 Sem 01

2.2 Give the truth table of the T flip-flop.

2.3 Give the VHDL code of the entity that corresponds to the previous architecture.
2.4 What is the role of the aaa signal?
2.5 Modify the program so that the flip-flop is synchronous with the two edges of the clk clock,
rising and falling.
2.6 Rewrite the process of the previous architecture, using selective assignment, at least once.

Exercise 03: (8 pts)

Let’s consider the following logic diagram of a given circuit:

3.1 Give the corresponding logic equation and truth table.

3.2 What is the famous name of this circuit.
3.3 Give a structural VHDL description allowing to implement the previous circuit in an
FPGA development board.

Dr. A. Ganouche Page 2 of 2 Good luck!