Abed aljawad numan

32015334044

IBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Xx IS
PORT( ----------------------------------->Clock & Reset:
Ck: IN std_logic;
Reset: IN std_logic;
----------------------------------->Inputs:
p: IN std_logic;
----------------------------------->Outputs:
r: OUT std_logic
-------------------------------------------
);
END Xx;
ARCHITECTURE behavioral OF Xx
IS -- (Behavioral Description)
TYPE states is ( A, B,C, D );
SIGNAL State, Next_State: states;
BEGIN
-- Next State Combinational Logic ----------------------------------
FSM: process( State, p )
begin
CASE State IS
when A =>
Next_State <= B;
when B => if (p = '1') then
Next_State <= C;
r<= '0';
else
Next_State <= A;
r<= '0';
end if;
when C => if (p = '1') then
Next_State <= D;
r<= '0';
else
Next_State <= A;
r<= '0';
end if;
when D => if (p = '1') then
Next_State <= A;
r<= '1';
else
Next_State <= A;
r<= '0';
end if;
END case;
end process;
-- State Register --------------------------------------------------
REG: process( Ck, Reset )
begin
if (Reset = '0') then
State <= A;
elsif rising_edge(Ck) then
State <= Next_State;
end if;
end process;
END behavioral ;