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RC 4558
RC 4558
RC4558
SLOS073G – MARCH 1976 – REVISED OCTOBER 2014
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
RC4558
SLOS073G – MARCH 1976 – REVISED OCTOBER 2014 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.2 Functional Block Diagram ......................................... 9
2 Applications ........................................................... 1 7.3 Feature Description................................................... 9
3 Description ............................................................. 1 7.4 Device Functional Modes.......................................... 9
4 Revision History..................................................... 2 8 Application and Implementation ........................ 10
8.1 Typical Application ................................................. 10
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 13
6.1 Absolute Maximum Ratings ..................................... 4 10 Layout................................................................... 14
6.2 Handling Ratings....................................................... 4 10.1 Layout Guidelines ................................................. 14
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 14
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 15
6.5 Electrical Characteristics........................................... 5 11.1 Trademarks ........................................................... 15
6.6 Operating Characteristics.......................................... 5 11.2 Electrostatic Discharge Caution ............................ 15
6.7 Typical Characteristics .............................................. 6 11.3 Glossary ................................................................ 15
7 Detailed Description .............................................. 9 12 Mechanical, Packaging, and Orderable
7.1 Overview ................................................................... 9 Information ........................................................... 15
4 Revision History
Changes from Revision F (September 2010) to Revision G Page
• Added Applications, Device Information table, Handling Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ..... 1
• Removed Ordering Information table. .................................................................................................................................... 1
1OUT 1 8 VCC+
1IN− 2 7 2OUT
1IN+ 3 6 2IN−
VCC− 4 5 2IN+
Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
1IN+ 3 I Noninverting input
1IN- 2 I Inverting Input
1OUT 1 O Output
2IN+ 5 I Noninverting input
2IN- 6 I Inverting Input
2OUT 7 O Output
VCC+ 8 — Positive Supply
VCC- 4 — Negative Supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC+ 18
Supply voltage (2) V
VCC– –18
VID Differential input voltage (3) ±30 V
VI Input voltage (any input) (2) (4) ±15 V
(5)
Duration of output short circuit to ground, one amplifier at a time Unlimited
TJ Operating virtual junction temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC–.
(3) Differential voltages are at IN+ with respect to IN–.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage, unless otherwise specified.
(2) Full range is 0°C to 70°C for RC4558 and –40°C to 85°C for RC4558I.
6 6
5 5
ICC – Supply Current – mA
3 3
2 2
1 1
0 0
0 2 4 6 8 10 12 14 16 18 20 -55 -35 -15 5 25 45 65 85 105 125
VCC – Supply Voltage – V TA – Temperature – °C
40 0 40 0
-20 -20
30 30
-40 -40
-60 -60
20 20
-80
Phase – deg
-80
Phase – deg
Gain Gain
Gain – dB
Gain – dB
10 -100 10 -100
-120 -120
Phase Phase
0 0
-140 -140
-160 -160
-10 -10
-180 -180
Figure 3. Gain and Phase vs Frequency Figure 4. Gain and Phase vs Frequency
(VCC = ±15 V, RL = 2 kΩ, CL = 22 pF) (VCC = ±15 V, RL = 10 kΩ, CL = 22 pF)
15 30
10 25
VOM – Output Voltage Swing – V
5 20
0 15
-5 10
-10
5
-15
0
6 8 10 12 14 16 18
1.E+00
1 1.E+01
10 1.E+02
100 1.E+03
1k 1.E+04
10k 1.E+05
100k 1.E+06
1M
VCC – Supply Voltage – V
f – Frequency – Hz
Figure 5. Output Voltage Swing vs Supply Voltage Figure 6. Output Voltage Swing vs Frequency
(RL = 2 kΩ, TA = 25°C) (VCC = ±15 V, RL = 2 kΩ, TA = 25°C)
32 15
30
14.75
28
14.5
26
14.25
24
22 14
20 13.75
18
13.5
16
13.25
14
12 13
100 1000 10000 -55 -35 -15 5 25 45 65 85 105 125
Figure 7. Output Voltage Swing vs Load Resistance Figure 8. Output Voltage Swing vs Temperature
(VCC = ±15 V, TA = 25°C) (VCC = ±15 V, RL = 10 kΩ)
-12 120
110
-12.25
100
–V OM – Output Voltage Swing – V
-12.5 90
G M – Open Loop Gain – dB
80
-12.75
70
-13 60
50
-13.25
40
-13.5 30
20
-13.75
10
-14 0
-55 -35 -15 5 25 45 65 85 105 125 100
1.E+02 1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06 10M
1.E+07
TA – Temperature – °C f – Frequency – Hz
Figure 9. Negative Output Voltage Swing vs Temperature Figure 10. Open Loop Gain vs Frequency
(VCC = ±15 V, RL = 10 kΩ) (VCC = ±15 V, RL = 2 kΩ, CL = 22 pF, TA = 25°C)
200 0.003
190
0.002
180
VIO – Input Offset Voltage – V
IIB – Input Bias Current – nA
170
0.001
160
150 0
140
-0.001
130
120
-0.002
110
100 -0.003
-55 -35 -15 5 25 45 65 85 105 125 -55 -35 -15 5 25 45 65 85 105 125
TA – Temperature – °C TA – Temperature – °C
Figure 11. Input Bias Current vs Temperature Figure 12. Input Offset Voltage vs Temperature
(VCC = ±15 V) (VCC = ±15 V)
14
12
Voltage––nV/rt(Hz)
nV/ÖHz
10
NoiseVoltage
8
Noise
6
– Input
Vn V–n Input
4
0
10
1.E+01 100
1.E+02 1.E+03
1k 10k
1.E+04 100k
1.E+05
f – Frequency – Hz
7 Detailed Description
7.1 Overview
The RC4558 device is a dual general-purpose operational amplifier, with each half electrically similar to the
μA741, except that offset null capability is not provided.
The high common-mode input voltage range and the absence of latch-up make this amplifier ideal for voltage-
follower applications. The device is short-circuit protected, and the internal frequency compensation ensures
stability without external components.
IN−
IN+
OUT
VCC−
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
R1 15 V
VOUT-
+
R3 +
VREF
R4
12 V
VDIFF
±
VOUT+
+
VIN
16 16
12 14
12
8
10
VOUT+ (V)
VDIFF (V)
4
8
0
6
±4
4
±8 2
±12 0
0 2 4 6 8 10 12 0 2 4 6 8 10 12
VIN (V) C003 VIN (V) C001
Figure 15. Differential Output Voltage Node vs Input Figure 16. Positive Output Voltage Node vs Input Voltage
Voltage
12
10
8
VOUTt (V)
0
0 2 4 6 8 10 12
VIN (V) C002
CAUTION
Supply voltages outside of the ±18-V range can permanently damage the device (see
the Absolute Maximum Ratings ).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.
10 Layout
GND
VIN IN1+ IN2í
RIN
VCCí IN2+
Only needed for Use low-ESR, ceramic
dual-supply bypass capacitor
operation
GND VS-
(or GND for single supply) Ground (GND) plane on another layer
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
www.ti.com 24-May-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
RC4558DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 (YRP, YRS, YRU) Samples
RC4558DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 RC4558 Samples
RC4558IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (YSP, YSS, YSU) Samples
RC4558IDGKRG4 LIFEBUY VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 (YSP, YSS, YSU)
RC4558IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 R4558I Samples
RC4558IDRG4 LIFEBUY SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 R4558I
RC4558IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 RC4558IP Samples
RC4558IPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 R4558I Samples
RC4558P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 RC4558P Samples
RC4558PSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 R4558 Samples
RC4558PSRG4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 R4558 Samples
RC4558PWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 R4558 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-May-2024
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 30-May-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-May-2024
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 30-May-2024
TUBE
T - Tube
height L - Tube length
W - Tube
width
Pack Materials-Page 3
PACKAGE OUTLINE
DGK0008A SCALE 4.000
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
C
5.05
TYP
A 4.75
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1
2X
3.1
1.95
2.9
NOTE 3
4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4
0.23
0.13
SEE DETAIL A
0.25
GAGE PLANE
1.1 MAX
0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20
TYPICAL
4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
8X (1.4) (R0.05) TYP
8X (0.45) 1 8
SYMM
6X (0.65)
5
4
SEE DETAILS
(4.4)
4214862/A 04/2023
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
SYMM
8X (0.45) 1 8
SYMM
6X (0.65)
5
4
(4.4)
4214862/A 04/2023
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
C
6.6 SEATING PLANE
TYP
6.2
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
3.1 2X
2.9
NOTE 3 1.95
4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.75 0.15
0 -8 0.05
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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