MIT Art Design & Technology University’s

MIT School of Engineering, Pune

S. Y. B. Tech. CSE
Subject: Computer Organization & Microprocessor Interfacing
Assignment No: III

Submission Date: 14/12/2020

Assignment Date: 03/12/2020

Q. 1 Identify the best cache replacement policy for Direct cache mapping. Justify your answer

Q. 2 List out various cache replacement algorithms & demonstrate their working with suitable
example
Q. 3 Solve for a byte addressable memory, where main memory is of size 128 KB, cache size is
16 KB and block size is 256 Bytes. Identify the number of tag bits required
Q. 4 Illustrate Pentium-IV cache organization with the help of neat diagram. Discuss the data
flow among different caches
Q. 5 Show how DMA is different and effective as Compared to programmed I/O & Interrupt
driven I/O.
Q. 6 Design an interface for 8087math coprocessor with 8086 microprocessor
Q. 7 How interrupts are handled by 8259 PIC? Demonstrate the working of 8259 PIC with
block diagram
Q. 8 Compare & Contrast Memory mapped I/O & Isolated I/O