Design and Test

• Producing a digital system begins with a

designer specifications in a high-level design
language
• Ends with manufacturing and shipping parts
to the customer.
• This process involves many simulations,
synthesis, and test phases that are described
here.
 RTL Design Process
• The designer first writes his or her design
specification in an RT level language such as
Verilog.
• Using standard HDL (Hardware Description
• Language) descriptions and testbenches in the
same HDL, this description will be simulated
and tested for design errors
 RTL Simulation
• Input of the RT level
simulator is taken from
the original problem
description
• The HDL model consists of
synthesizable module
interconnections in a top
level Verilog model.
• Detailed timing checks
and physical flaws are not
addressed at this level of
Simulation and only
checks functionality.
 Cont…
• For analyzing the behavior, the testbench can
inject design errors under unanticipated
circumstances.
• The testbench can be made to issue warnings
when and if it detects that the design’s behavior
contradicts the expected functionality.
• Verification and assertion-based verification
methods are useful in analyzing the design
• After a satisfactory simulation design meets the
design specifications, the next step, is RT level
synthesis
 RT Level Synthesis
• RT level synthesis takes the
behavioral description of a design
(myDesign) as input, and
produces a netlist of the design.
• The netlist, by postSynthesis
module, specifies
interconnection of low-level basic
logic components depending
upon the target library.
• The format for the netlist can be
the same HDL as the original
design.
• Before going to the next step,
this netlist must be tested.
• This simulation phase is referred
to as postsynthesis simulation
done with HDL simulation tool.
 Cont…
• It checks for delay issues, races, clock speed, and
errors caused by misinterpretation of the RT level
design.
• In general, the same testbench used for testing.
• Some times, new test vectors may be needed
where timing issues become important.
• For Confirmation, A testbench in the same HDL
can instantiate both descriptions and simulate
them simultaneously with the same test data.
• After completion of postsynthesis verification,
the next step is performing physical layout.
 Physical Layout
• The verified postsynthesis netlist of the design is
used by a layout and placement tool for
generating the design’s layout and routing of cells
• The output of this phase also needs to be tested
and verified for correctness
• The simulation here verifies wire lengths, wire
widths, and transistor sizes, and detects layout
and placement flaws.
• After a successful simulation, the layout will be
ready for manufacturing
 Chip Manufacturing
• The final step is manufacturing.
• Testing is done on the model of
the design (i.e., simulation),
testing is the last step is done on
the physical part.
• Testing the circuit under test
(CUT) against manufacturing
defects. Which may be broken
wires, shorts, open resistive
wires, transistor defects, and
other physical problems that
affect the functionality of a
manufactured part.
• Unsuccessful test results require
modifications in the design or
changes in the synthesis or
hardware generation process.
 Cont…
• As opposed to the other three forms of testing in
Fig. 1.1 that a software program (a simulator)
performs the testing of the model, in
manufacturing test, a physical device, which is a
hardware component or a test equipment,
performs the testing.
• The same test platform used in the three boxes
above the postmanufacturing box should be
translated to a test program that runs on a test
equipment for testing the finished part
 Postmanufacturing Test
• Postmanufacturing test has certain characteristics that
makes it conceptually different than the other three, and
thus needs special attention.
• Testing is referred to the exercise of checking a part or a
model to see if it behaves differently than its specification.
• What distinguishes between various testing are
 what is being tested,
 how is test data obtained,
 what it is being tested with,
 what procedure we use for testing it, and
 what we do with the test results.
 Device and Its Test Data
• Regardless of what it is that is being tested, it is treated
as a closed box that can only be controlled and
observed from the outside

• The key here is that once the part that is being tested is
configured for a certain set of inputs and outputs
(actual or virtual),
• no more access to the inside of the part, neither to
control, nor to observe.
 Cont…
• A test set is prepared ahead of time by the test-generation process.
• Test generation is done using a model of DUT

 Functional test generation, test vectors are made to examine various

functions of a DUT, uses the RT level or behavioral model of the DUT.
 Structural test generation, where test vectors are made to examine
interconnections within a DUT, uses the netlist model of the DUT.

• The expected response for a test set that can be saved for stored
response testing is prepared by simulating a working model of DUT
• The model from which the expected response of a circuit is
obtained is called good circuit model or golden model.