EDN Design Ideas 2001

design
Edited by Bill Travis and Anne Watson Swager

ideas
Preheat starter for electronic ballast
Arthur E Edang, Don Bosco Technical College, Mandaluyong City, Phillipines
lectronic ballasts for fluorescent age to force IC1B to pull down IC1A’s non- discharge through D1 and D2 to ensure
E lamps use various techniques to turn inverting pin to ground. With a ground-
on the bulbs. The design usually in- ed IC1A output, VO clamps low.
volves a compromise between turn-on The high-frequency switching strikes
precise timing.
voltage and lamp life because the two are the preheated lamp. In case the bulb fails Is this the best Design Idea in this
inversely related. One way to reach a rea- to start, the circuit turns off and then on issue? Vote at www.ednmag.com/edn
sonable compromise is to initially allow again. Residual charges on the capacitors mag/vote.asp.
a momentary inrush current to warm the
filaments, followed by a series of inter- 12V
rupted short circuits across the 12V
Figure 1
lamp that generate the required 10k
82k
high voltage to trigger the fluorescent. 10k
With a preheated filament, the necessary 100 pF
7.5k
1M
strike potential reduces to half.

10k 5
The trigger circuit in Figure 1 controls VCC _
2
the electronic switch across the bulb. At _ 100k 4 IC1C V0
3 +
10 IC 13 12V
start-up, IC1D’s output is low as C1 and C2 12V 1M 1A
charge toward VCC. IC1D’s low output +

11 12
pulls IC1C’s inverting input low, which 100k
causes VO to clamp high. A high level at TO
1M
VO closes the switch and forces current 1M HALF-BRIDGE
CIRCUIT
through the filaments. After approxi-
ELECTRONIC
mately 0.5 sec, IC1D’s output changes state SWITCH
and allows IC1C to accept the high-fre-
quency signal at its noninverting input.
IC1A is a square-wave oscillator, which
causes VO to be a high-frequency-pulse
0.5 SEC 1 SEC
series that lasts for approximately 1 sec.
At the end, C2 reaches a high enough volt- 12V
1M D1 12V
1M
Preheat starter for electronic 1.5 SEC
_ 6
ballast..............................................................113 1
IC1B C2 D2
330k
+
7 2.2 mF
Low-cost circuit programs 9 10k
+ 0.5 SEC
EEPROMs ......................................................114 1M 1M 14
IC1D
12V _ 8
Circuit yields ultralow-noise VGA..............116 C1
2.2 mF
1M
Sequential channel selector NOTES:
simplifies software ......................................120 IC1=LM339N.
DIODES=1N4606.
mC provides timer function ......................124
This trigger circuit generates a high-frequency-pulse series to strike a preheated lamp.
www.ednmag.com January 4, 2001 | edn 113

design
ideas
Low-cost circuit programs EEPROMs
Jarrod Eliason, Ramtron, Colorado Springs, CO
hen you migrate to 3.3V system 5-to-3.3V conversion better than previ- gardless of the supply level.
W supplies, you must usually replace

your old, reliable EEPROM pro-
grammer with a new, overly flexible and
ous logic families, such as the 74HC se-
ries. The 74HC family accommodates
3.3V operation, but the input-protection
The 74HCT family handles the 3.3-to-
5V conversion. This 5V CMOS logic fam-
ily uses input switching levels skewed to
expensive universal programmer. We diodes clamp the input voltage within a accommodate TTL-level inputs. The low
could not find a 3.3V programmer for diode drop of VDD (Figure 2a). So, ap- and high levels are 0.8 and 2.4V, respec-
less than $1000. For less than $100, the plying 5V to the input of a 74HC part tively, in comparison with the typical
circuit in Figure 1 extends the function- powered from 3.3V results in much un- CMOS levels of 1.5 and 3.5V. Because the
al life of any 5V EEPROM programmer. desired current. An external resistor inputs receive high levels of 3.3V at most,
You can apply the circuit to any bidirec- could limit this current, but this fix CMOS-optimized 74HC logic would not
tional 5 to 3.3V level-translating appli- would impact bus speed. The 74VHCT guarantee recognition of logic 1 inputs.
cation. The key to the circuit lies in and 74LVC families do not use a reverse- On the other hand, to a 74HCT powered
choosing the correct logic families. The biased diode to VDD (Figure 2b), so the from 5V, a 3.3V input level represents a
74VHC and 74LVC families handle the input voltage can safely rise to 5.5V, re- solid logic 1. We selected the tristatable
3.3V
2 3
V5 IN OUT V3
Figure 1 +
COM
+
0.1 mF 2.2 mF 0.1 mF 2.2 mF
5V 5V
DATA ADDRESS 5V V3
BUS BUS ADDRESS V3
BUS
13 0.1 mF
5V 0.1 mF
8 3V 5V
9 ADDRESS ADDRESS DATA OE3 3V
7 5V BUS 1
10 BUS BUS DATA
6 DATA
12 OEB1 OEB1 BUS
5 BUS 8
WEB3
4 OEB5 7
3 IC2 11
IC3 6 IC5
2 74VHC541 74VHC541
CEB5 5
1 8
1 OEB3 4
7
2 6 3
3 5 CEB3 2
1
4 OEB2
OEB2
19 V5
19
74HC04 74HC04 V3 V3
1 2 9 8 OE3
0.1 mF
OEB3 OE3
0.1 mF 0.1 mF OEB5
74HC04 3V
74HC04 DATA
3 4 11 10
1 1 BUS
OEB1 OEB1
13 12 13
5 6
8
74HC04 7 IC4 IC6
74HC04 74VHC541 74HCT541
6
3V
ADDRESS CEB3 5
BUS 0EB3 4
WEB3 3
2
OEB2 OEB2
3V 19 19
IC1 DATA
64-kBYTE OEB5
BUS
EEPROM 8
7
32-PIN PLCC 6
5
4
3
2
1
For less than $100, this circuit adapts a 5V EEPROM programmer for 3.3V operation.
114 edn | January 4, 2001 www.ednmag.com

design
ideas
buffer function for the EEPROM-pro- A 28-pin DIP socket, IC2, connects to
grammer level translation. The VDD
the 5V EEPROM programmer. The cir-
Figure 2
circuit in Figure 1 programs a cuit uses an additional adapter to inter-
3.3V, 64-kbit EEPROM, using a 5V pro- face to the 32-pin PLCC target device,
grammer. For the address and control IC1. The 74VHC and 74LVC logic parts
PAD PAD
pins, the output-enable pin of the are not readily available in DIP form, so
74VHC chips is constantly active. For the you can use SOIC-to-DIP adapters for
bidirectional data bus, the OEB5 and breadboarding. If the 74HCT541 is not
OE3 signals control the in/out selection. available, you can use the alternate-
When OEB5 is low and OE3 is high, a (a) (b) pinout 241 or 244.
read operation takes place, and the EE-
PROM has control of the data bus. When
OEB5 is high and OE3 is low, a write op- The 3.3V-powered 74HC-logic inputs are not Is this the best Design Idea in this
eration takes place, and the programmer amenable to 5V inputs (a); 74HVC and 74LVC issue? Vote at www.ednmag.com/edn
drives the data bus. inputs have no such problem (b). mag/vote.asp.
Circuit yields ultralow-noise VGA

Dale Ouimette, California Institute of Technology, Pasadena, CA
number of single-chip VGAs vari- problems. IC1 is a low-noise quad op exhibits approximately 3 nV/=Hz, re-
A able-gain amplifiers are available to-

day. Unfortunately, they all have
drawbacks, such as high noise, 55V lim-
amp, and IC2 is a quad SPDT CMOS
switch. The stages switch in successive
multiplication (gain) factors using a TTL
ferred to the input, for most gain settings.
The highest noise is 4.5 nV/=Hz at a
gain of 9 dB. Distributing the total gain
it, low input impedance, or nonlinear binary code. The values shown provide 0- across multiple stages increases the
gain/frequency characteristics. The cir- to 45-dB gain in 3-dB steps. For best low- overall bandwidth. The output stage
cuit in Figure 1 is a 16-step, ultralow- noise performance, the higher gain stages has a different configuration to yield
noise VGA that solves many of these precede the lower gain stages. The circuit a low-output-impedance output driver
Figure 1 15V
24 dB 0.1 mF
OPTIONAL
RANGE- 15V 0.1 mF IC2A IC2B IC2C
SHIFT ADG333 16 12 dB ADG333 6 dB ADG333ABR 3 dB
ATTENUATOR
4 SB VDD 7 SB 14 SB
SIGNAL 4 D 3 5 D 8 12 D 13 14 SIGNAL
R1 IN + SA + SA +
3 + 7 9 16 OUT
1 2 SA IC IC 10 12 IC1D
090 2 IC 6 _ 1B 11 _ 1C 15 _
_ 1A
R2 LT1125 10 11
1 LT1125CS LT1125CS
100 LT1125CS
13
0.1 mF
825 IC2D
GND VSS
115V 1k 1k ADG333ABR
6 5
17 SB
0.1 mF D 18
SA
19
1k
66.5 332 1k
2k
115V 20
BIT 3
BIT 2
BIT 1
BIT 0
This VGA offers ultralow noise, a wide dynamic range, and high bandwidth.

design
ideas
at all gain settings. log control. You can use R1
If you need to remotely TABLE 1—PERFORMANCE VERSUS GAIN and R2 in Figure 1 to shift
Noise
control the gain, you must down the overall gain range
Gain (referred to input) 3-dB bandwidth
concern yourself with ground Step (dB) V/V (nV/==Hz) (MHz) with little sacrifice of noise
loops that can compromise 0 0 1 3.1 10.5 characteristics. You can obvi-
the low-noise characteristics 1 3 1.4 3.8 7.7 ously alter the individual gain
of the circuit. One solution is 2 6 2 4.4 5.1 stages to yield other ranges
to place optoisolators in the 3 9 2.8 4.5 4.6 and step sizes, such as 0 to 30
four digital-control lines, so 4 12 4 3.6 2.7 dB in 2-dB steps. At the ex-
that no ground connection 5 15 5.6 3.6 2.7 pense of circuit simplicity,
exists between the two ends 6 18 7.9 3.7 2.6 you could replace the quad op
of the cable except through 7 21 11.2 3.7 2.6 amp with four ultra-low-
the power supply. The 8 24 15.8 3 0.88 noise op amps, such as the
method you use is an analog 9 27 22.4 3 0.89 LT1128 or AD797. This re-
differential-control voltage 10 30 31.6 3 0.94 placement lowers the noise to
using an ADC to generate the 11 33 44.7 3 0.96 approximately 1.4 nV/=Hz.
4 bits. Figure 2 shows a cir- 12 36 63.1 3 0.97 You could also increase the
cuit that performs this func- 13 39 89.1 3 0.97 number of stages, thereby
tion well. IC1 is a differential 14 42 125.9 3 1.04 providing a wider dynamic
receiver, and IC2 is an 8-bit 15 45 177.8 3 1.02 range, finer gain steps, or
ADC. In some applications, both. The benefits of this cir-
you could get away with using cuit over commercially avail-
only the ADC, because it already has a erates in a self-clocking mode and needs able single-chip VGAs include ultra-low
differential input. However, you must no other controls. noise, high bandwidth, 613V range, high
take care not to exceed the narrow com- R2 and C2 control the sampling fre- input impedance, ground-loop immuni-
mon-mode range of the ADC’s input. A quency, approximately 640 kHz for the ty, and user-defined dynamic range and
more robust solution is to place a differ- values shown. D1, R3, and C3 provide step size.
ential receiver in front of the ADC, as power-up initialization for the ADC’s
shown. R1 and C1 form a lowpass filter for clocking function. The control-voltage
the control voltage to the ADC. The 4 steps are 310 mV apart, providing ample Is this the best Design Idea in this
high-order bits from the ADC control the noise immunity. Table 1 shows the per- issue? Vote at www.ednmag.com/edn
CMOS switches. As shown, the ADC op- formance of the overall circuit with ana- mag/vote.asp.
15V VCC
Figure 2 0.1 mF
GND VCC IC2 + 10 mF

+CONTROL 7 ADC0804
3 AT 20V
+
8 S1ADICT S1ADICT 9 20
+VS R1 VREF/2 VCC
RG
0 TO 5V IC1 6 1k 6 11 BIT 3
CONTROL VOLTAGE REF VIN+ DB7
AD620 C1 7 12 BIT 2
VIN1 DB6
1
RG 1VS 5 1 mF
1CONTROL 2 8
A GND DB5
13 BIT 1
_ R2
4 0.1 mF 19 14 BIT 0
10k CLK R DB4
4 15
CLK IN DB3
1 16
115V C2 CS' DB2
140 pF 2 17
S1ADICT RD' DB1
3 18
WR' DB0
D1
5 10
VCC INTR' D GND
R3 + C
1M 3
4.7 mF
An ADC controls the gain-setting codes for the circuit in Figure 1.

design
ideas
Sequential channel selector simplifies software

Alex Knight, Cummins Engine Co, Columbus, IN
n efficient but powerful circuit Although the resulting circuit may 16. The oscillator frequency is approxi-
A is useful for a variety of applications

with limited I/O and for which you
want to use one input to sequentially se-
seem simple and standard, it is distinctly
robust. The delayed reset signals at IC2’s
Pin 1 and IC3’s Pin 2 return the counter
mately 21 Hz, but you can change R3 and
C1 to produce the desired frequency,
which is approximately 1/R3C1. You can
lect a different output channel (Figure 1). and flip-flop ICs to their initial state so also use a potentiometer in place of R3 to
When the software changes the state of that OUT1 is the first channel active at the make the frequency adjustable. Keep in
only one input, the circuit sequentially first count. The power-on and switch-ac- mind that the flip-flop clock-cycle peri-
selects one output channel at a time for tivated reset circuit includes R1, D3, and od should be much less than the expect-
test purposes. Because the test-applica- D4 to protect against ESD that could arc ed active and inactive periods of the IN
tion environment is potentially harsh, the over the switch contacts when someone signal but long enough to produce ade-
circuit must have relatively high noise first touches the switch. The IN signal in- quate debouncing of the input signal to
immunity and transient protection at the put circuit has similar transient protec- maintain good noise immunity. The cir-
inputs. You must also be able to reset the tion with R2, D1, and D2. A simple RC os- cuit serves a low-speed application, so the
circuit to resynchronize the hardware cillator generates the clock signal at IC2’s clock at IC2’s Pin 9 is 1.3 Hz.
with a test program after any interrup- Pin 9, and the second four-stage binary- The circuit filters and buffers the IN
tion in testing. ripple counter, IC3, divides this clock by signal before sending it to the flip-flop
Figure 1
5V 5V
IN 0.1 mF
10k
D1
1N4148 16 8
VCC GND
IC1B IC1C IC2
10k 74HC175
3 4 5 6 4 2
D0 Q0
5 7
D1 Q1
0.1 mF 6
D2 12
D2 Q1 5V 5V
1N4148 13 10 5V
D3 Q2
R3 9 0.1 mF 0.1 mF
470k CLK Q3
15 0.1 mF
RST
5V 16 8 9 10
14 7
0.1 mF
VCC GND VCC GND VCC GND
IC1A
IC4 IC5
14 IC3
1 2 74HC393 74HC237 UDN2981
15 1 18 OUT8
1 3 1 Y0 I1 01
7 CLKA Q1A A0 Y1 14 2 I2 17 OUT1
02
C1 4 2 13 3 16
Y2 I3 OUT2
0.1 mF 3 Q2A A1
12 4 03
CLKB 5 3 A Y3 I4 15 OUT3
Q3A 2 11 5 04
Y4 I5 14
8 10 6 05 OUT4
Q4B Y5 I6
Y6 9 7
I7 06 13 OUT5
6 7 8 12
5V CS1 Y7 07 OUT6
RSTA RSTB I8
11 OUT7
5V 08
2 12 CS2 LE
D3
1N4148 5 4
2.2M IC1D IC1E
9 8 11 10
0.1 mF
R1 D4
1k 1N4148
RESET
A robust circuit uses one input to sequentially select one output channel at a time.

design
ideas
input at IC2’s pin 4. The Schmitt invert- input of the decoder (IC4, pin 4) latches arate supply. IC5 has internal diodes on
er, IC1 with its built-in hysteresis and the the output channel that the state of the all of the outputs to clamp inductive
cascaded flip-flop circuit provide high A0-to-A2 address inputs select. Latching spikes.
immunity to noise, and the cascaded flip- the output channel ensures you that any The circuit includes a switch for gen-
flop ignores any glitches on the input sig- subsequent noise-induced counter-out- erating a reset signal, which you can use
nal that occur asynchronously to the flip- put state changes will not affect the out- in addition to or instead of an external re-
flop clock signal’s positive-going put-channel states. While CS1 is low, the set signal. The input can also be an ex-
transitions. The circuit uses the Q1 out- Y0-to-Y7 outputs from IC4 are also low. ternal analog signal or non-TTL, as long
put signal as the CLKA clock input to the This design maintains a similar off-time as you properly compensate for any dc
first four-stage binary ripple counter, IC3. for all of the output channels, as reflect- offset necessary to work at the switching
Negative-going transitions increment the ed in the input signal, although the cir- thresholds of the Schmitt inverter. You
counter as the timing diagram indicates cuit delays any change of state for each can cascade additional ripple-counter
at counts 1, 2, and 3 (Figure 2). The cir- of the outputs by approximately two cy- stages and add decoders and output driv-
cuit uses the Q2 output to select the ac- cles of the flip-flop clock period. ers to select from more output channels.
tive-high CS1 chip-select input of IC4’s IC5 can drive loads that sink as much
one-of-eight decoder, which allows plen- as 350 mA at room temperature, such as
ty of time for the ripple counter outputs relays, solenoids, dc motors, and lamps.
to stabilize, even at high flip-flop clock This eight-channel source-driver IC is
speeds. These outputs do not simultane- unnecessary if CMOS outputs suffice as Is this the best Design Idea in this
ously change states. With CS1 high, the the channel-select signals. The IC5 source issue? Vote at www.ednmag.com/edn
positive-going Q3 output signal at the LE voltage can climb to 35V if you add a sep- mag/vote.asp.
Figure 2
IC2, PIN 1
RST
IC2, PIN 9
CLK
D0
Q0
Q1
CS1
CLKA
LE
A0
A1
A2
Y0
Y1
Y2
Negative-going transitions increment the counter at counts 1, 2, and 3.

design
ideas
mC provides timer function
Tito Smailagich, ENIC, Belgrade, Yugoslavia
he circuit in Figure 1 is a mC- mainder of the desired time in seconds. timer interval into memory, press the
T based programmable timer with two

output channels. The first channel,
activated by pressing the red switch, S3,
The display decrements by 1 until it
reaches 0. The timebase in seconds de-
rives from the main oscillator of the mC,
green switch, and the mC writes the
value in its internal EEPROM. You
can download the software for the
has a red LED at its output. This channel which generates a real-time interrupt MC68HC11E1 mC from EDN’s Web site,
is active until it reaches its desired time- every 8 msec. The mC multiplies the 8 www.ednmag.com. Click on “Search
out point. The second output channel msec by 125, yielding a timebase of 1 sec. Databases” and then enter the Software
connects to a green LED and is active af- You program the desired time interval by Center to download the file for Design
ter a preselected time-out period. The pressing the yellow switch, S2; the display Idea #2629.
second channel remains active until the shows the programmed value. If you
next depression of the red switch.You can need to change the programmed value,
deactivate both channels at any time by pressing the red switch decrements the Is this the best Design Idea in this
pressing the green switch, S1. In normal value by 1 until it reaches 0, after which issue? Vote at www.ednmag.com/edn
mode, the display shows the current re- it starts with 99. If you need to put the mag/vote.asp.
XTAL VCC
27 pF 4.096 MHz 27 pF
31 10k
GREEN LED
Figure 1 30
D2
1k
8 29
VCC 10M OUT2 RED LED
7 28
1 OUT1 D1
1k
2 RSET 27
IN IC2 10k 17 42 7
MC34064 VCC
10k 19 DISPLAY 2 RIGHT
GND 41 6
1 mF HP-HDSP-H103
1 mF 10k 18 40 4
2 2
39
3 10k 10k IC1
MC68HC11E1 38 1
34 37 9
33 36 10
32 35 5
S1 S2 S3 10k
3 8
43 9
GREEN RED
44 10
45 7
YELLOW 11
6 DISPLAY 1 LEFT
46
12 HP-HDSP-H103
47 4
48 13 2
49 14 1
50 15 9
1k 52 10
VCC 16
51 5
J2 10k
1 mF 20
3 8
21 10k
22 10k
D3
1N4007 23 10k
24 10k
1 3
IN IC3 OUT VCC
7805 25 10k
10 mF 0.1 mF 3
GND 0.1 mF
2 10 mF 5
4 10k
VCC
6
VCC
J1
4321
An MC68HC11 mC provides flexible timing functions.

design
ideas
Open-loop power supply delivers as much as 1W
Christophe Basso, On Semiconductor, Toulouse, Cedex, France
or VCRs, TVs, and other equipment and allows operation over universal 2 • POUT
F that requires a standby mode, you mains. Because the circuit operates at
must supply power to a mP when constant output power, the following for-
other components are asleep to receive mula determines the necessary peak cur-
IP =
L P • FOSC
.
With an internal error amplifier that

and interpret any wake-up signal from rent:
the remote control or from the broad-
casting company. These types of
systems have rather low power Figure 1
consumption, and classical switch-mode 1N4007
power-supply ICs represent a clear
overkill for less-than-1W output levels.
Any active power-supply circuit also 1:0.08 1N5819
LP=2.7 mH 10V AT 90 mA
needs to be more cost- effective than the
standard structure using a metallic trans-
+
former. The circuit in Figure 1 reduces
470 mF/16V 12V/1.3W
the cost by eliminating the use of the op-
4.7 mF/400V 8
tocoupler. L1 + HV
2
IC1 directly drives an external 600V N
FB
IC1
MOSFET. The lack of an auxiliary wind- NCP1200P40
ing greatly simplifies the overall applica- 3 VCC 6
CS
tion circuitry; the controller’s integrated 4 5 MTD1N60E
dynamic self supply provides VCC. IC1 R1
GND DRV
works as a peak-current PWM controller, 18k
combining fixed-frequency operation at

100 nF
40, 60, or 100 kHz and the skip-cycle 6.8
RSENSE
method for low standby-power con-
sumption. IC1 regulates the peak current
NOTE:
THE TRANSFORMER IS AVAILABLE FROM ELDOR (ELDOR@ELDOR.IT, REF 2262.0058C)
AND FROM COILCRAFT (INFO@COILCRAFT.COM REF Y8844-A).
Open-loop power supply delivers IC1 regulates the peak current and allows this 1W supply to operate from universal mains.
as much as 1W ............................................143
Four-way remote control uses Figure 2
series transmission ......................................144 10.6
10.4
Analyze LED characteristics 10.2
with PSpice ....................................................150 OUTPUT 10
VOLTAGE 9.8
Programmable-gain amplifier (V) 9.6
is low-cost ......................................................152 9.4
9.2
PC hardware monitor reports 100 150 200 250 300
the weather ..................................................154 INPUT VOLTAGE (V AC)
The input-voltage rejection stays within 1V from 130 to 260V ac.

design
ideas
clips at 1V maximum, RSENSE is equal to circuit protection, which normally reacts from 130 to 260V-ac mains. This figure
1/IP(maximum). In this example, a 40- upon feedback-path loss. illustrates current mode’s inherent audio
kHz circuit and a 6.8V sense element de- Thanks to its avalanche capability, the susceptibility.
liver as much as 1W of continuous pow- MTD1N60E requires no clipping net-
er with LP52.8 mH. You can recompute work, which further eases the design. The
RSENSE for lower or higher output-power efficiency measured 64% (low line,
requirements. The 12V zener diode pre- POUT5866 mW) and 61% (high line, Is this the best Design Idea in this
vents the circuit from generating over- POUT51.08W). Figure 2 plots the input- issue? Vote at www.ednmag.com/edn
voltages. R1 deactivates the internal short- voltage rejection, which stays within 1V mag/vote.asp.
Four-way remote control uses series transmission

JM Terrade, Clermont-Ferrand, France
simultaneous four-
A way remote-control
system adheres to size,
cost, and reduced-complex-
EMITTER
DATA (4 BITS)
9-BIT
DATA PACKET
ity constraints and uses a

PARALLEL
series transmission to drive 433-MHz
TO SERIAL
EMISSION
parallel loads (Figure 1). ID CODE (5 BITS)
You can use this system as

long as the time constant of RECEIVER
the load is much larger than CLOCK
the total transmission time

for all data. With these con- 9-BIT DATA (4 BITS)
DATA PACKET 4
siderations, this design can D LATCH DATA (4 BITS)
drive any object with four SERIAL TO
PARALLEL
simultaneous controls as 433-MHz
RECEPTION
motors. COMPARISON CLOCK
The design uses a 9-bit
ID CODE (5 BITS)
data packet. The emitter
side of the design DATA CLOCKS AFTER
Figure 1 THREE IDENTICAL
converts 4 data bits TRANSMISSIONS
and a 5-bit ID code from LOCAL ID CODE
parallel to serial. The data

packet continuously trans- The emitter converts 4 data bits and 5 ID-code bits to serial data and continuously transmits the resulting data
mits, and the total informa- packet. The receiver compares the received ID code with the local code three times before clocking in new data.
tion arrives at the HF 433-
MHz emitter. The receiver side converts propulsion and direction. The transmis- keep the desired action. When released,
the 9-bit serial data to parallel data. Then, sion uses two 433-MHz, AM-radio mod- the switch returns to its null position.
the design compares the received ID code ules for the HF link. With no action on S1 and S2, the logic lev-
to the local code. The comparison result Power consumption is 10 mA during els on data inputs D6 to D9 of IC1 are low
clocks the 4 data bits for the D latch. This emission, so the emitter circuit can use a due to R3 to R6. When an action occurs on
configuration actually controls a small, 9V battery (Figure 2a). D1 protects the S1 or S2, the corresponding data input of
battery-powered boat with two-way, re- device against polarity inversion. S1 and IC1 is close to 5V. You can activate S1 and
mote-control switches. The switches are S2 are three-position, mom-off-mom S2 at same time. Voltage-divider pairs R1
mom-off-mom types, which give front- switches. Only the center, or null, posi- and R3 or R1 and R4 and R2 and R5 or R2
stop-rear and left-center-right com- tion is static. The user must push the and R6 produce acceptable levels for IC1
mands. The boat has two dc motors for switch in one direction and maintain it to inputs.

design
ideas
Diodes D2 to D5 permit C1 to charge el. Thus, 243 combinations (35) are pos- the 9-bit data packet to the HF emitter,
through R7. Then, Q1 conducts, and Q2 sible. However, three-state DIP switches IC2. The HF module uses amplitude
is on. D6 acts as a power-on indicator. are expensive, and 64 possibilities are modulation. The antenna is a 17-cm wire
The voltage drop across D6, R9, and zen- enough for many applications. If Pin 6 of that attaches directly to the pc board.
er-diode D7 results in a 5V supply for IC1 S3 provides a low level, A1 to A5 can be ei- When the power is on, transmission al-
and IC2. C1 continuously charges until S1 ther low levels or unconnected. If Pin 6 ways occurs. After a user releases S1 and
and S2 return to the null position. Then, of S3 provides a high level through R10, A1 S2, the emitter continues to transmit the
C1 discharges through R8, and Q1 switch- to A5 can be either high levels or uncon- null-position information until power
es off after approximately 8 to 10 sec nected. This arrangement gives 64 com- goes off, which takes approximately 8 sec.
(Figure 2b). binations. On the receiver side (Figure 3a), the
Inputs A1 to A5 of IC1 are three-state R11, R12, and C2 form the local oscilla- antenna is also a 17-cm wire attached di-
inputs: low, high, and unconnected lev- tor. The output of IC1 at Pin 15 provides rectly to the pc board. The incoming sig-
Q2
2N2907
Figure 2 10k
R9
10k ANTENNA
4.7k VCC
D6
LED
15 11
Q1 VCC
UN10KM
100 nF 1
+ R8 D7 +
C1 4
470k BZX55-5V1 10 mF 47k GND
10 mF 13
IC2
TX-433-SAW
R7
R10 100 nF 3
10k IN-VCC<8V
2
10k IN-VCC>8V
16 8
1 12 1 VCC GND
1 ON A1 ST2
2 11 2
2 A2
1N4148 3 10 3
3 A3 DOUT 15
4 9 4
4 A4
5 8 5
5 A5 11
6 7 IC1 RS
D2 D3 D4 D5 6
MC145026
1N4148 R11
S3 14 TE 100k
CTC 12
FRONT 1
R1 2 6 C2
D6 R12
3 S1 7 D 4.7 nF 47k
D1 4.7k REAR MS-500 7
13
9 RTC
1N4148 R2 LEFT 1 D8
9V 2 10
S2 D9
3
4.7k RIGHT
MS-500
+
100 nF R3 R4 R5 R6
2
10k 10k 10k 10k
0V
9V BATTERY NO
ACTION
S1: FRONT S1: FRONT NO
(a) S2: RIGHT S2: CENTER ACTION
VC1
5V
2.5V
TIME
VCC '8 SEC
5V
POWER IS ON. LED D6 IS ON.
ALL DATA BITS TRANSMIT CONTINUOUSLY.
D6 0 0 0 0 TIME
D7 1 0 1 0
D8 1 0 0 0 BITS A1 TO A5=ID CODE.
(b) D9 0 0 0 0
In the emitter circuit, two three-position switches, S1 and S2, determine the voltage on C1 (a) and the voltage levels of data bits D6 to D9 of IC1 (b).

design
ideas
nal arrives at the HF module, IC1, which the new transmission is valid. Three cor- when only one transmitted bit changes,
has a stable 5V power source. The 9-bit rect transmissions are necessary. There- the other bits keep their previous level.
data packet is available at the output, or fore, the design needs a stable RX_OK When the ID code is not valid or when
Pin 14, of the module. Just as for the signal, and, for this reason D1, R1, R2, and the HF link is lost, which implies that the
emitter, DIP switch S1 provides as many C1 create a time constant. The RX_OK distance between the emitter and the re-
as 64 possibilities for the ID code, and the signal goes low only when the transmis- ceiver is too long, D6 to D9 keep their pre-
setting must be the same combination as sion stops or when the ID code is invalid, vious levels. However, RX_OK goes low
the emitter. which can happen if the emitter has no after 70 msec and forces D6 to D9 to go
The 4 data bits are available at outputs supply and stops emitting or if another low.
D6 to D9 of IC2. When a valid transmis- transmitter is in the same area (Figure
sion arrives at the receiver, Pin 11 of IC2 3b).
goes high. But each time a user changes The internal D latch, IC2, clocks new Is this the best Design Idea in this
the position of the commands on the output levels only when the circuit re- issue? Vote at www.ednmag.com/edn
emitter, the Valid-T signal goes low until ceives a new data packet. In this way, mag/vote.asp.
VCC
VCC
Figure 3 100 nF
1 10 15 TEST
10k D'9
ANTENNA 16 8
VCC-HF VCC-BF VCC-OUT
13 1 12 1 VCC GND
TEST 1 ON A1
2 11 2 D'8
IC1 2 A2 D9 12
3 RF290-A5S 3 10 3
IN 14 3 A3 13
OUT 4 9 4 D8
4 A4
GND 5 5 D7 14
GND 8 D'7
5
2 7 11 6
A5 D 15
6
6 7
IC2
D1 RX_OK
MC145027 R1
VCC S1 9 1N4148
D-IN 11 1k D'6
VALID-T
1 3
V0 78LO5ACZ VI 6
R1
GND +
47 mF + 47k 10 C1 + R2
2 7 R2C2 10 mF 33k
100 nF
2
C1 100 nF
22 nF 180k
9V BATTERY
(a)
D6
TIME
D7 TO D9 9-BIT DATA PACKET
TIME
RECEIVED DATA KEEP EMISSION ALIVE

AT PIN 9 IC2 FOR '8 SEC
TIME
VALID-TRANS THREE IDENTICAL DATA

(PIN 11 IC2) PACKETS'45 mSEC
TIME
RX_OK '70 mSEC
'2.5V TIME
LOGIC LEVEL FOR

AND GATES
HIGH INPUT LEVEL: DATA IS ENABLED TIME
D'6
LOW LEVEL FORCE
D'6 TO D'9 LOW TIME
D'7 TO D'9
TIME
(b)
In the receiver (a), three correct transmissions must occur before Pin 11 of IC2 goes high (b).

design
ideas
Analyze LED characteristics with PSpice

Sam Mollet, GE Harris Harmon Railway Technology, Grain Valley, MO
ecent advances in LED technol- Carlo analysis, the forward
R ogy have lead to LEDs’ widespread characteristics of

use in outdoor-signal applications, each LED in the cir-
such as in traffic and railroad signals. A cuit vary randomly. Figure
Figure 1
RS
+
IFWD=ISz(eV /NzV 21).

D T
typical LED signal consists of an LED ar- 3’s example performs 20 +
ray and a power supply. When a low-volt- Monte Carlo sweeps at I
VD VFWD VD=NzVTzln FWD +1 .
IS
age power supply is either desirable or 1V/sec, with N set for a 2 I
VFWD=IFWDzRS+NzVTzln FWD +1 .
mandatory, series/parallel combinations 10% tolerance. IS
2
of LEDs become inevitable. However, an- The final example is the
alyzing and optimizing series/parallel analysis of a simple circuit
combinations of LEDs with varying for- (Figure 4a). The input This simple model and equations are the result of setting
ward characteristics can be complicated. consisted of a 60-mA PSpice’s diode-model parameters IFK and ISR to zero.
Using the parametric and Monte Carlo
capabilities of PSpice greatly simplifies
this task.
To model an LED in PSpice, use the
diode model. You can set the IFK and ISR
parameters in the diode model to zero;
Figure 1 shows the resultant PSpice diode
forward-current model and correspon-
ding equations. As the equations in the
figure show, you can express the forward
voltage across the diode model, or VFWD,
as the sum of the voltage across the se-
ries resistance and the voltage
Figure 2
across the intrinsic diode.
The dominant term in the VFWD equa-
tion of Figure 1, assuming RS is less than
10V, is the logarithmic term. Therefore, This simulation run varies N linearly from 2.07 to 2.53.
if you vary the model parameter N in
Monte Carlo or parametric analyses, then
the VFWD varies accordingly. A helpful
hint: When creating an LED model using
programs such as Parts (www.mi-
crosim.com), use curve-tracer plots or an
enlarged photocopy of the VI curve from
data books to extrapolate data points
along the VI curve.
Figure 2 shows an example for which
N varies linearly between 2.07 and 2.53,
or 2.3610%. The forward voltage at 20
mA varies from 1.59 to 1.94V, or
1.76569.9%. By editing the Figure 3
“N52.3299” statement in the LED mod-
el to “N52.3299 DEV 10%” assigns a
10% device tolerance to the LED model. Assigning a 10% tolerance to N causes the forward characteristics of each LED in the circuit to vary
Therefore, when you execute a Monte randomly during Monte Carlo analysis.

design
ideas
pulse, and the simulations determine the runs. The results for R50 reveal a large dard deviation of only 1 mA.
peak current through D1 for 0, 10, and standard deviation of 10 mA. The results
100V resistance values. The model state- for R510 reveals a smaller standard de- Is this the best Design Idea in this
ment assigned a 10% tolerance to N, and viation of about 5 mA (Figure 4b). The issue? Vote at www.ednmag.com/edn
the example executes 50 Monte Carlo results for R5100 reveals a small stan- mag/vote.asp.
Figure 4
LED
R1 R2 R3
{R} {R} {R}
2 D1 D4 D7
I1 LED LED LED
+ 60m RED RED RED
D2 D5 D8
LED LED LED
RED RED RED
(a) (b)
510V reveal a stan-

To analyze a simple circuit (a), simulations determine the peak current through D1 for three resistance values. The results for R5
dard deviation of approximately 5 mA (b).
Programmable-gain amplifier is low-cost

J Jayapandian, Indira Gandhi Centre for Atomic Research, Kalpakkam, India
umerous programmable- DAC in series with the op amp to atten-
N gain amplifiers are avail-

able, but a simple solution
provides the option of using 256
5V 8-BIT DATA
GND
uate the input signal and achieve the de-
sired variable-gain factor. You calculate
the current output, IOUT1, from the DAC
gain steps with an 8-bit DAC 8-BIT DAC as follows, where D0 through D7 are the
IREF AD 7524
and higher steps with higher bit VIN digital inputs to the DAC:
RIN
DACs (Figure 1). According to 1OUT2
RF IOUT1 =
VIN  D0 D1 D2 D3 D4 D5 D6 D7 
+ + + + + + +
 .
the inverting-amplifier configu- RFB R IN  2 4 8 16 32 64 128 256 
ration of an op amp, the 1OUT1 For example, if all of the bits are ones,
Figure 1 _
output voltage is LF356 VOUT
the 8-bit digital image is FF, and the cor-
VOUT5VIN(RF/RIN), where RF is + responding amplifier full-scale output is:
the feedback resistance, RIN is VIN  255 
VOUT = IOUT1 • R F =   • RF.
the input resistance, and VIN is R IN  256 
the input voltage of the amplifi- A DAC in series with an op amp attenuates the input sig- In an actual application, keep the val-
er circuit. Generally, by chang- nal to achieve the variable-gain factor. ue of RF fixed for the maximum gain. By
ing the feedback resistance, you varying the digital image pattern from 00
can get the desired gain. put-voltage signal. The shunt feedback to FF, you can get the variable amplifier
In this design, the 8-bit DAC in the in- resistance, RF, converts IOUT1 to a voltage. gain according to your requirements.
put stage acts as a programmable atten- Thus, the input signal, VIN, acts as a ref-
uator for the input signal and permits a erence input to the DAC. Instead of in- Is this the best Design Idea in this
maximum full-scale IOUT1 of 1 mA. The creasing the value of the feedback resis- issue? Vote at www.ednmag.com/edn
value of IOUT1 is proportional to the in- tor for higher gain, this circuit uses the mag/vote.asp.

design
ideas
PC hardware monitor reports the weather
Sean Gilmour, Analog Devices, Limerick Ireland
ou usually use PC hardware mon- of the measurement inputs, you can set channels use a two-wire scheme that sup-
Y itors to keep a close eye on power-

supply voltage levels, the speed of
system cooling fans, and even the tem-
limits that warn the user of changing
weather conditions. IC1 uses a switching-
current-measurement scheme, so you
plies switching current levels to the tran-
sistor. IC1 measures the difference in VBE
between these two currents and calculates
perature of the CPU. Until fairly recent- can mount the sensors hundreds of feet the temperature according to the follow-
ly, this level of system monitoring was re- from the IC and still maintain a high ing well-known relationship:
served for high-end servers running SNR.
mission-critical applications. However, IC1 connects to a parallel printer port DVBE5KT/q x ln(N),
now that low-cost hardware monitoring using a 74HC07 open-drain noninvert-
ASICs are available, advanced hardware ing buffer. Pin 2 of the parallel port is the where K is Boltzmann’s constant, q is the
monitoring has become a standard fea- serial clock. Pin 3 writes configuration charge of an electron, T is the absolute
ture in most new PCs. And hardware data into IC1, and Pin 13 reads data from temperature in Kelvin, and N is the ratio
monitors are now finding their way into IC1. of the two currents.
diverse applications, such as weather sta- The necessary software is simple, and You can also use the CPU temperature-
tions (Figure 1). the parallel-printer port is easily accessi- monitoring channels to measure changes
IC1 has two external temperature- ble using freeware drivers and DLLs that in resistance, making them useful for
measurement channels. One channel you can find on the Internet. You can bit- most resistive sensors, including photo
connects to a resistive humidity sensor, bang the SCL and SDATA lines using a diodes, photo resistors, gas sensors, and
and a second channel uses a 2N3906 programming language such as Visual resistive-humidity sensors.
transistor to sense the outdoor tempera- Basic or Visual C++.
ture. The internal temperature sensor The temperature-measurement chan-
measures the indoor temperature. One of nels use a thermal diode, such as that on Is this the best Design Idea in this
the tachometer inputs connects to the Intel’s Pentium processors (PII1), or a issue? Vote at www.ednmag.com/edn
output of a wind-speed meter. For each discrete npn or pnp transistor. These mag/vote.asp.
WIND SPEED
TEMPERATURE
HUMIDITY
FREQUENCY D+
Figure 1 OUTPUT RESISTIVE- STANDARD
HUMIDITY PNP D2
SENSOR TRANSISTOR
5V HUMIDITY-
13 CALIBRATION
PARALLEL-PRINTER PORT TRIM POT
(36-PIN CENTRONICS)
3 3
SDA
SERIAL
BUS
2 4
SCL
18
5
FAN1
74HC07
17
IC1
ADM1024
8
GNDD
10 mF 0.1 mF
+ 14
9
5V VCC
NTEST_IN/AOUT 13
VCC
10k
12
A PC hardware-monitor IC can also monitor weather-station characteristics.

design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all
published Design Ideas. An additional $100 Cash Award for the
winning design of each issue, determined by vote of readers.
Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine

275 Washington St, Newton, MA 02458
I hereby submit my Design Ideas entry. (Please print clearly)
Name
Title
Phone
E-mail Fax
Company
Address
Country ZIP
Design Idea Title
Entry blank must accompany all entries. (A separate entry

blank for each author must accompany every entry.)
Design entered must be submitted exclusively to EDN,
must not be patented, and must have no patent pending.
Design must be original with author(s), must not have
been previously published (limited-distribution house
organs excepted), and must have been constructed and
tested. Fully annotate all circuit diagrams. Please submit
text, software listings and all other computer-readable doc-
umentation on IBM PC disk or in plain ASCII by e-mail to
b.travis@cahners.com.
Exclusive publishing rights remain with Cahners
Business Information unless entry is returned to author, or
editor gives written permission for publication elsewhere.
The author must be willing to sign and return our publica-
tion agreement if the Design Idea is accepted for publica-
tion and must complete a W-9 tax form (W-8 for non-US
residents) before payment can be processed.
Signed
Date
Your vote determines this issue’s winner. Vote now at

www.ednmag.com/ednmag/vote.asp.

design
ideas
Open-loop power supply delivers as much as 1W
or VCRs, TVs, and other equipment and allows operation over universal 2 • POUT
F that requires a standby mode, you mains. Because the circuit operates at
must supply power to a mP when constant output power, the following for-
other components are asleep to receive mula determines the necessary peak cur-
IP =
L P • FOSC
.
With an internal error amplifier that

and interpret any wake-up signal from rent:
the remote control or from the broad-
casting company. These types of
systems have rather low power Figure 1
consumption, and classical switch-mode 1N4007
power-supply ICs represent a clear
overkill for less-than-1W output levels.
Any active power-supply circuit also 1:0.08 1N5819
LP=2.7 mH 10V AT 90 mA
needs to be more cost- effective than the
standard structure using a metallic trans-
+
former. The circuit in Figure 1 reduces
470 mF/16V 12V/1.3W
the cost by eliminating the use of the op-
4.7 mF/400V 8
tocoupler. L1 + HV
2
IC1 directly drives an external 600V N
FB
IC1
MOSFET. The lack of an auxiliary wind- NCP1200P40
ing greatly simplifies the overall applica- 3 VCC 6
CS
tion circuitry; the controller’s integrated 4 5 MTD1N60E
dynamic self supply provides VCC. IC1 R1
GND DRV
works as a peak-current PWM controller, 18k
combining fixed-frequency operation at

100 nF
40, 60, or 100 kHz and the skip-cycle 6.8
RSENSE
method for low standby-power con-
sumption. IC1 regulates the peak current
NOTE:
THE TRANSFORMER IS AVAILABLE FROM ELDOR (ELDOR@ELDOR.IT, REF 2262.0058C)
AND FROM COILCRAFT (INFO@COILCRAFT.COM REF Y8844-A).
Open-loop power supply delivers IC1 regulates the peak current and allows this 1W supply to operate from universal mains.
as much as 1W ............................................143
Four-way remote control uses Figure 2
series transmission ......................................144 10.6
10.4
Analyze LED characteristics 10.2
with PSpice ....................................................150 OUTPUT 10
VOLTAGE 9.8
Programmable-gain amplifier (V) 9.6
is low-cost ......................................................152 9.4
9.2
PC hardware monitor reports 100 150 200 250 300
the weather ..................................................154 INPUT VOLTAGE (V AC)
The input-voltage rejection stays within 1V from 130 to 260V ac.

design
ideas
clips at 1V maximum, RSENSE is equal to circuit protection, which normally reacts from 130 to 260V-ac mains. This figure
1/IP(maximum). In this example, a 40- upon feedback-path loss. illustrates current mode’s inherent audio
kHz circuit and a 6.8V sense element de- Thanks to its avalanche capability, the susceptibility.
liver as much as 1W of continuous pow- MTD1N60E requires no clipping net-
er with LP52.8 mH. You can recompute work, which further eases the design. The
RSENSE for lower or higher output-power efficiency measured 64% (low line,
requirements. The 12V zener diode pre- POUT5866 mW) and 61% (high line, Is this the best Design Idea in this
vents the circuit from generating over- POUT51.08W). Figure 2 plots the input- issue? Vote at www.ednmag.com/edn
voltages. R1 deactivates the internal short- voltage rejection, which stays within 1V mag/vote.asp.
Four-way remote control uses series transmission

simultaneous four-
A way remote-control
system adheres to size,
cost, and reduced-complex-
EMITTER
DATA (4 BITS)
9-BIT
DATA PACKET
ity constraints and uses a

PARALLEL
series transmission to drive 433-MHz
TO SERIAL
EMISSION
parallel loads (Figure 1). ID CODE (5 BITS)
You can use this system as

long as the time constant of RECEIVER
the load is much larger than CLOCK
the total transmission time

for all data. With these con- 9-BIT DATA (4 BITS)
DATA PACKET 4
siderations, this design can D LATCH DATA (4 BITS)
drive any object with four SERIAL TO
PARALLEL
simultaneous controls as 433-MHz
RECEPTION
motors. COMPARISON CLOCK
The design uses a 9-bit
ID CODE (5 BITS)
data packet. The emitter
side of the design DATA CLOCKS AFTER
Figure 1 THREE IDENTICAL
converts 4 data bits TRANSMISSIONS
and a 5-bit ID code from LOCAL ID CODE
parallel to serial. The data

packet continuously trans- The emitter converts 4 data bits and 5 ID-code bits to serial data and continuously transmits the resulting data
mits, and the total informa- packet. The receiver compares the received ID code with the local code three times before clocking in new data.
tion arrives at the HF 433-
MHz emitter. The receiver side converts propulsion and direction. The transmis- keep the desired action. When released,
the 9-bit serial data to parallel data. Then, sion uses two 433-MHz, AM-radio mod- the switch returns to its null position.
the design compares the received ID code ules for the HF link. With no action on S1 and S2, the logic lev-
to the local code. The comparison result Power consumption is 10 mA during els on data inputs D6 to D9 of IC1 are low
clocks the 4 data bits for the D latch. This emission, so the emitter circuit can use a due to R3 to R6. When an action occurs on
configuration actually controls a small, 9V battery (Figure 2a). D1 protects the S1 or S2, the corresponding data input of
battery-powered boat with two-way, re- device against polarity inversion. S1 and IC1 is close to 5V. You can activate S1 and
mote-control switches. The switches are S2 are three-position, mom-off-mom S2 at same time. Voltage-divider pairs R1
mom-off-mom types, which give front- switches. Only the center, or null, posi- and R3 or R1 and R4 and R2 and R5 or R2
stop-rear and left-center-right com- tion is static. The user must push the and R6 produce acceptable levels for IC1
mands. The boat has two dc motors for switch in one direction and maintain it to inputs.

design
ideas
Diodes D2 to D5 permit C1 to charge el. Thus, 243 combinations (35) are pos- the 9-bit data packet to the HF emitter,
through R7. Then, Q1 conducts, and Q2 sible. However, three-state DIP switches IC2. The HF module uses amplitude
is on. D6 acts as a power-on indicator. are expensive, and 64 possibilities are modulation. The antenna is a 17-cm wire
The voltage drop across D6, R9, and zen- enough for many applications. If Pin 6 of that attaches directly to the pc board.
er-diode D7 results in a 5V supply for IC1 S3 provides a low level, A1 to A5 can be ei- When the power is on, transmission al-
and IC2. C1 continuously charges until S1 ther low levels or unconnected. If Pin 6 ways occurs. After a user releases S1 and
and S2 return to the null position. Then, of S3 provides a high level through R10, A1 S2, the emitter continues to transmit the
C1 discharges through R8, and Q1 switch- to A5 can be either high levels or uncon- null-position information until power
es off after approximately 8 to 10 sec nected. This arrangement gives 64 com- goes off, which takes approximately 8 sec.
(Figure 2b). binations. On the receiver side (Figure 3a), the
Inputs A1 to A5 of IC1 are three-state R11, R12, and C2 form the local oscilla- antenna is also a 17-cm wire attached di-
inputs: low, high, and unconnected lev- tor. The output of IC1 at Pin 15 provides rectly to the pc board. The incoming sig-
Q2
2N2907
Figure 2 10k
R9
10k ANTENNA
4.7k VCC
D6
LED
15 11
Q1 VCC
UN10KM
100 nF 1
+ R8 D7 +
C1 4
470k BZX55-5V1 10 mF 47k GND
10 mF 13
IC2
TX-433-SAW
R7
R10 100 nF 3
10k IN-VCC<8V
2
10k IN-VCC>8V
16 8
1 12 1 VCC GND
1 ON A1 ST2
2 11 2
2 A2
1N4148 3 10 3
3 A3 DOUT 15
4 9 4
4 A4
5 8 5
5 A5 11
6 7 IC1 RS
D2 D3 D4 D5 6
MC145026
1N4148 R11
S3 14 TE 100k
CTC 12
FRONT 1
R1 2 6 C2
D6 R12
3 S1 7 D 4.7 nF 47k
D1 4.7k REAR MS-500 7
13
9 RTC
1N4148 R2 LEFT 1 D8
9V 2 10
S2 D9
3
4.7k RIGHT
MS-500
+
100 nF R3 R4 R5 R6
2
10k 10k 10k 10k
0V
9V BATTERY NO
ACTION
S1: FRONT S1: FRONT NO
(a) S2: RIGHT S2: CENTER ACTION
VC1
5V
2.5V
TIME
VCC '8 SEC
5V
POWER IS ON. LED D6 IS ON.
ALL DATA BITS TRANSMIT CONTINUOUSLY.
D6 0 0 0 0 TIME
D7 1 0 1 0
D8 1 0 0 0 BITS A1 TO A5=ID CODE.
(b) D9 0 0 0 0
In the emitter circuit, two three-position switches, S1 and S2, determine the voltage on C1 (a) and the voltage levels of data bits D6 to D9 of IC1 (b).

design
ideas
nal arrives at the HF module, IC1, which the new transmission is valid. Three cor- when only one transmitted bit changes,
has a stable 5V power source. The 9-bit rect transmissions are necessary. There- the other bits keep their previous level.
data packet is available at the output, or fore, the design needs a stable RX_OK When the ID code is not valid or when
Pin 14, of the module. Just as for the signal, and, for this reason D1, R1, R2, and the HF link is lost, which implies that the
emitter, DIP switch S1 provides as many C1 create a time constant. The RX_OK distance between the emitter and the re-
as 64 possibilities for the ID code, and the signal goes low only when the transmis- ceiver is too long, D6 to D9 keep their pre-
setting must be the same combination as sion stops or when the ID code is invalid, vious levels. However, RX_OK goes low
the emitter. which can happen if the emitter has no after 70 msec and forces D6 to D9 to go
The 4 data bits are available at outputs supply and stops emitting or if another low.
D6 to D9 of IC2. When a valid transmis- transmitter is in the same area (Figure
sion arrives at the receiver, Pin 11 of IC2 3b).
goes high. But each time a user changes The internal D latch, IC2, clocks new Is this the best Design Idea in this
the position of the commands on the output levels only when the circuit re- issue? Vote at www.ednmag.com/edn
emitter, the Valid-T signal goes low until ceives a new data packet. In this way, mag/vote.asp.
VCC
VCC
Figure 3 100 nF
1 10 15 TEST
10k D'9
ANTENNA 16 8
VCC-HF VCC-BF VCC-OUT
13 1 12 1 VCC GND
TEST 1 ON A1
2 11 2 D'8
IC1 2 A2 D9 12
3 RF290-A5S 3 10 3
IN 14 3 A3 13
OUT 4 9 4 D8
4 A4
GND 5 5 D7 14
GND 8 D'7
5
2 7 11 6
A5 D 15
6
6 7
IC2
D1 RX_OK
MC145027 R1
VCC S1 9 1N4148
D-IN 11 1k D'6
VALID-T
1 3
V0 78LO5ACZ VI 6
R1
GND +
47 mF + 47k 10 C1 + R2
2 7 R2C2 10 mF 33k
100 nF
2
C1 100 nF
22 nF 180k
9V BATTERY
(a)
D6
TIME
D7 TO D9 9-BIT DATA PACKET
TIME
RECEIVED DATA KEEP EMISSION ALIVE

AT PIN 9 IC2 FOR '8 SEC
TIME
VALID-TRANS THREE IDENTICAL DATA

(PIN 11 IC2) PACKETS'45 mSEC
TIME
RX_OK '70 mSEC
'2.5V TIME
LOGIC LEVEL FOR

AND GATES
HIGH INPUT LEVEL: DATA IS ENABLED TIME
D'6
LOW LEVEL FORCE
D'6 TO D'9 LOW TIME
D'7 TO D'9
TIME
(b)
In the receiver (a), three correct transmissions must occur before Pin 11 of IC2 goes high (b).

design
ideas
Method sets voltage in multiple-output converters
Robert Bell, On Semiconductor, Phoenix, AZ
hen you design a transformer for
W
MAIN TRANSFORMER DELTA TRANSFORMER
any power converter, you Figure 1 MBR2030CTL
face several compromises.
10T VOUT2
You must trade off core size against the
number of primary turns and flux den- T1 1T T2
sity. Another trade-off is the number of

turns and winding resistance versus the
MBR2030CTL
associated losses. After making these
VBUS
trade-offs, you usually arrive at a good VOUT1
compromise that involves the primary
1T 23T
and secondary turns. However, if the con-
verter has more than one output, you face
6T 5T
a new set of compromises. For high-
power, low-output-voltage converters, MTP20N20E
the number of secondary turns is often MURS120T3
very low. In a forward-converter topolo-
gy, it is common for a 3.3V transformer CONTROLLER
MC33023
to have one turn in its main secondary
winding. This one-turn configuration is
FEEDBACK
ideal for lowering winding resistance and
associated power losses. For this design,
the average output voltage is 3.3V per
turn. So, if you need another output from A delta transformer eliminates the problem of turns-ratio granularity.
the converter, that output is a multiple of
3.3V. For a multiple-output power con- ages is often not a whole number (a prob- delta transformer is parallel with the
verter, the ratio between the output volt- lem known as “turns granularity”). Re- VOUT1 winding, and the secondary of the
ferring to this example, if the main out- delta transformer is in series with the
put is 3.3V and the desired auxiliary VOUT2 winding. This connection has the
Method sets voltage in multiple-
output is 5V, two secondary turns yield effect of adding a portion of the main
output converters ........................................121
6.6V—a 32% error. A linear regulator output voltage, VOUT1, to the auxiliary
Circuit forms constant-current SCR..........122 could drop 6.6 to 5V but with the penal- output, VOUT2. (The turns ratio deter-
555 makes handy voltage-to-time ty of a power loss. Figure 1 shows an ap- mines the portion.) In the example
converter ........................................................124 proach to solving the granularity prob- above, suppose that the main trans-
lem if the regulation requirement is not former operates at a 50% duty cycle, and
Program predicts VSWR-mismatch
particularly tight (5 to 15%). assume that the rectifiers have 0.6V for-
RF uncertainties............................................124
Transformer T1 is a normal forward ward voltage drop. Then, the equation re-
PC monitors two-way RS-232 transformer. Each secondary winding has lating VOUT1 and the transformer second-
transmission..................................................126 one turn. The control loop regulates the ary voltage, VT1, during the on time is:
Passive filters fill the bill at main output, VOUT1, to 3.3V. The objec- 3.35(VT120.6)(0.5)2(0.6)(0.5). Thus,
audio frequencies ........................................128 tive is for the auxiliary output to be 5.5V. VT157.8V.
With only one secondary turn, that out- Now, you need to solve for the desired
Watchdog timer assumes
put will also be 3.3V. Consequently, you total VT (VT2) of the slave output, VOUT2:
varied roles....................................................130
need a simple way to increase the voltage. 55(VT220.6)(0.5)2(0.6)(0.5). Thus,
One microcontroller serves You can add another transformer, T2, VT2511.2V. VT2 is the sum of the main-
multiple external interrupts ......................132 dubbed a delta transformer, to the sec- transformer secondary voltage and the
ondaries (Figure 1). The primary of the delta-transformer secondary voltage. The
www.ednmag.com February 1, 2001 | edn 121
design
ideas
desired delta-transformer secondary resistive-voltage drop exists in the sec- use a small core gap. You can use this ap-
voltage is 11.227.853.4V. Because the ondary output. Therefore, the volt-time proach in all buck regulators to fine-tune
primary voltage of the delta transformer product of the main transformer’s sec- an auxiliary output.
is also 7.8V, the turns ratio of the delta ondary output is not exactly zero, which
transformer must be 7.8/3.452.3. In this is a required condition for the delta
example, you can use 10 and 23 turns for transformer’s primary to reset. So, you
the delta transformer. The main-trans- should make the primary winding of the Is this the best Design Idea in this
former secondary output delivers current delta transformer resistive to add a small issue? Vote at www.ednmag.com/edn
only during its on time, and an internal voltage drop in the forward direction or mag/vote.asp.
Circuit forms constant-current SCR

Robert Buono, Ringwood, NJ
typical SCR (silicon-controlled
A rectifier) requires a trigger

current, which causes the
SCR structure to latch on. Once the de-
Figure 1
1k Q3
1k
5V
vice latches, the current through the SCR 2N3906 LED

is solely a function of external compo- R1 1N4148
D2
nent values. The SCR has no inherent 1k
ability to limit the current flow once it TRIGGER R3 1k

latches on. Current continues to flow, as PULSE 1k + C1
5V 1N4148 1000 mF
long as the current exceeds a minimal val- 1 16V
Q1
ue known as the holding current. The cir- 0V D1 2N3904
cuit in Figure 1 is similar to an SCR, be- Q2 100
cause it also requires a trigger current to 2N3904
latch into its on state. However, once R2
CCOMP 30
latched, the circuit conducts a constant 10k 0.01 mF
current. The constant current continues
to flow, as long as the external circuitry
can provide it, and the minimum com-
pliance voltage of the SCR circuit is sat-
isfied. When these conditions are no Resembling an SCR, this circuit provides a constant current of controlled pulse width and amplitude
longer valid, the circuit latches off. The to a load.
circuit in Figure 1 provides a constant-
current pulse to drive an LED with cur- while in constant-current mode, Q2 also By choosing the proper values of R2 and
rent sourced from a capacitor. You trig- draws current through R3. Q2 thus main- C1, you can easily control pulse width and
ger the circuit with a narrow, tains Q3 in the on state (providing base amplitude.
negative-going pulse. The pulse, coupled current to Q1), even after the trigger pulse An apt application for this circuit is
through R1 and D2, turns Q3 on. Q3 pro- disappears. The circuit maintains the constant-current battery charging. Once
vides base drive to Q1. As Q1 turns on, constant-current mode, with Q1 drawing you trigger the circuit, it provides con-
current begins to flow through the LED a constant current through the LED, the stant current to charge a battery. When
and current-sense resistor R2. storage capacitor C1, and R2 until Q1 can the battery charges to a point where the
When 0.6V develops across R2, the cur- no longer sustain the constant current. charging current falls below the constant-
rent-limiting transistor, Q2, begins to This situation occurs when the voltage current level, the circuit latches off. Note
turn on and shunt base current from Q1, across C1 drops low enough to be unable that the circuit does not provide a con-
through diode D1. Q2 thus maintains the to maintain 0.6V across R2. Then, Q2 be- tinuous trickle charge, which could over-
current through R2 at a constant level gins to turn off, which allows Q3 to turn charge some batteries.
(~0.6V/R2) by controlling the base cur- off, thereby depriving Q1 of base current.
rent to Q1. At the same time, because the Q1 turns off, which results in a constant- Is this the best Design Idea in this
collector voltage of Q2 must be one diode current (flat-topped) pulse through the issue? Vote at www.ednmag.com/edn
drop lower than the base voltage of Q1 LED with sharply rising and falling edges. mag/vote.asp.
122 edn | February 1, 2001 www.ednmag.com
design
ideas
555 makes handy voltage-to-time converter
J Jayapandian, IGCAR, Tamil Nadu, India
he circuit in Figure 1 is a time constant of the circuit, with
T simple, low-cost volt-

age-to-time converter
using the ubiquitous 555 timer
Figure 1
VCC
C in farads and R in ohms. Dur-
ing one time constant, the voltage
across the capacitor changes by
chip. You can use the IC’s mono- 4 8 R
approximately 63% of VIN. The
stable multivibrator as a voltage- TRIGGER 2 7 VIN output timing of the monostable
to-time converter by connecting 6 multivibrator is tP51.1 RC. By
NE 555
the analog-voltage input to the C keeping RC constant with fixed R
charging resistor, R, instead of 3
and C values and varying the in-
connecting R to VCC. With this 5 put voltage, VIN, you obtain vari-
modification, the timer chip’s OUTPUT able output timing. The output
output-timing cycle, tP, is pro- 0.01 mF pulse width in this circuit is in-
portional to the input voltage, versely proportional to the input
VIN. When you apply an input tP voltage.
voltage, the voltage across capac-
itor C charges exponentially ac- Is this the best Design Idea in
cording to the formula VC= A voltage-controlled monostable multivibrator makes a handy this issue? Vote at www.ednmag.
VIN(12et/RC), where RC is the voltage-to-time converter. com/ednmag/vote.asp.
Program predicts VSWR-mismatch

RF uncertainties
Steve Hageman, Agilent Technologies, Santa Rosa, CA
ewlett-Packard (now Agi- the VSWR values, which lack phase
H lent Technologies) once of-

fered a useful little cardboard
slide rule for calculating the uncer-
information. So, one certainty
about a measurement is that it lies
between some range of values. In
tainty in RF measurements stem- reality, even the connectors and the
ming from VSWR (voltage-stand- transmission line in the measure-
ing-wave-ratio) mismatch. Unfor- ment path add uncertainty because
tunately, this handy device is no their true electrical length and,
longer available. A Visual Basic pro- hence, phase is unknown. So, the
gram accomplishes the same func- true power at the load may be high-
tion on a PC, however. You can er or lower than the measured val-
download the executable program Given the source and load VSWRs, ue. The conservative way to account
and its associated setup utilities on Figure 1 the VSWR Calc program quickly cal- for this error is to assume that the
a blind page at www.sonic.net/ culates RF measurement uncertainties. phase is unknown and assume the
~shageman/vswr.html. Mismatch worst case: The incident and re-
uncertainty is one of the most common ty stems from the fact that, at high fre- flected signals interact in the worst pos-
calculations an RF engineer makes when quencies, the length of a transmission sible way—in other words, at the peaks
determining the uncertainty of RF pow- line connecting a source and load may be and valleys. You express this scenario as
er measurements. The source and load sufficient to transform the impedance at VSWR5EMAX/EMIN, where EMAX and EMIN
VSWR interact along an unknown length one end of the line to another value at the are the maximum and minimum voltages
of line to produce some uncertainty in other end. along the line. VSWR is a common spec-
the power measurement. This uncertain- System specifications usually include ification in data sheets for RF devices,
design
ideas
such as amplifiers, sources, and power The uncertainty in the total measure- tion transfers the VSWRs and the calcu-
meters. VSWR relates to the absolute val- ment stemming from the source and load lated data to the Windows clipboard so
ue of the reflection coefficient g in the ex- VSWRs is Uncertainty(1)520log10 that documenting the calculations is easy
pression (11g1•g2) dB, and Uncertainty(2)5 in any Windows application. (The card-
20log10(12g1•g2) dB. board slide rule cannot perform this
11VSWR As a result, you have a range of either function.) Figure 1 shows the clipboard
γ= , plus or minus uncertainty. At small data of this example. The uncertainty in
1 + VSWR
VSWRs, the plus and minus converge to the example is 10.100 to 20.102 dB. You
and, in turn g relates to the return loss the same value. At higher VSWRs, the should know the measurement uncer-
in decibels in the expression plus and minus uncertainties diverge, so tainty, because it is relatively easy to ob-
RL5220log10g. Because the source and you need to calculate both. As an exam- tain totally uncertain measurements at
load each have a VSWR, the product of ple, consider a Hewlett-Packard ESG- high frequencies if the VSWRs are un-
the two gives the maximum VSWR: 3000 microwave source operating at 900 controlled or unknown. The VSWR Calc
VSWRMAX5VSWR1•VSWR2. The two MHz. Its VSWR is specified at 1.4 to 1. program is a Microsoft Visual Basic 32-
VSWRs produce a combined return loss, Then, assume that you measure the bit application that runs on Windows 95,
as follows: source’s output power with a Hewlett- 98, and NT 4.
Packard E4412A power sensor that has a
COMBINED R L = 120 • specified VSWR of 1.15 to 1. If you in-
 VSWR1 • VSWR211 put these figures into the VSWR Calc Is this the best Design Idea in this
LOG   dB.
 VSWR1 • VSWR2 + 1  program, you obtain the screen shown in issue? Vote at www.ednmag.com/edn
Figure 1. The “Copy to Clipboard” func- mag/vote.asp.
PC monitors two-way RS-232 transmission

Jerzy Chrzaszcz, Warsaw University of Technology, Poland
A TO B B TO A GND COM1
A TO B B TO A GND
he goal of monitoring trans-
T
1
mission in a data link RxD 6
1N4148
is obvious: You want Figure 1 2
7
to know the contents of the data, when 3
8
it was sent, and by whom. If one of the 4
communicating parties is a PC or an- 9
5
other user-programmable controller,
then you can modify parameter settings
1
or, at worst, change transmission rou- RxD 6
1
tines to generate log files or perform oth- 2 1N4148 RxD
6
2
er actions. This approach, however, may 7
7
3
be inconvenient or impossible to apply 8
3
8
in some cases. As an alternative ap- 4
4
9 RI
proach, you can use a PC with two seri- 5
9
5
al ports and a monitor program to ob- GND
GND
serve the link itself. The method in COM2
C0Mx
(a) (b)
Figure 1a needs no access or knowledge
of the communicating devices. A C pro- You can eavesdrop on RS-232 transmissions by using two COM ports (a); a simple modification (b)
gram opens two COM ports and installs adapts the method to PCs with only one COM port.
interrupt-service routines for IRQ4 and
IRQ3. Upon the reception of an inter- the program simplifies the time meas- along with the data and status bytes, in
rupt, the routine stores a byte in a com- urement, it preserves the original byte or- the circular buffer.
mon circular buffer with the COM iden- der and correctly reflects time relation- Unfortunately, not all PCs offer two
tifier and error flags. The main program ships as long as the main program keeps COM ports. This deficiency is a common
displays the contents of the buffer, indi- up with transmission speed. If you need drawback of notebook computers, which
cating time intervals in milliseconds be- greater precision, you can easily modify use a second UART controller for IrDA
tween consecutive transfers. Although the program to record time stamps, communication. But you can use even
design
ideas
these computers with another version of register is set. The interrupt-service rou- Databases” and then enter the Software
C to monitor the bidirectional link, pro- tine reads the register, clears the RITD Center to download the file for Design
vided that the transmission is not full- flag, and stores its value in a buffer. Thus, Idea #2661. The programs are simple and
duplex. A simple interface mixes both the interface is ready for another byte to accept 9600, 8, E, and 1 transmission pa-
data streams onto the receiver input (Fig- come from an arbitrary direction. The rameters. You can easily adapt the pro-
ure 1b). One channel connects to the RI main program can identify the data grams to other formats.
(ring indicator) input of the UART. source by checking respective bits. You
Whatever the byte value, the start bit can download the C listings and exe- Is this the best Design Idea in this
guarantees that the RITD (ring-indicator cutable files from EDN’s Web site, issue? Vote at www.ednmag.com/edn
trailing edge) bit in the modem-status www.ednmag.com. Click on “Search mag/vote.asp.
Passive filters fill the bill at audio frequencies

Richard Kurzrok, Queens Village, NY
ow-frequency filters, par- Acknowled gment
L ticularly at audio frequencies,

usually take the form of active filters.
These filters eliminate expensive induc-
Figure 1
L
1.32 mH
0.33 mF
L
1.32 mH
0.33 mF 0.33 mF 0.33 mF

I acknowledge Ed Wetherhold (An-
napolis, MD) for three decades’ worth of
significant work on low-frequency pas-
tors with windings of many turns. Both sive filters and related circuits.
analog and digital active filters are most
compatible with large-scale integration at References
the subsystem and system levels. Howev- A five-pole passive lowpass filter yields sharp 1. Wetherhold, Ed, “Audio Filters for
er, passive filters remain a viable option cutoff characteristics and low ripple. EN 55020 Testing,” Interference Engineers’
when you quickly need low-cost proto- Master, 1998.
types and test pieces (Reference 1). These ductor cores, fewer turns are required, and 2. DeMaw, MF, Ferromagnetic Core De-
filters use no external dc excitation and hand-winding is usually feasible. Howev- sign and Application Handbook, Chapter
require no complex pc boards. You can er, capacitors become large for lower fil- 3, Prentice-Hall, 1981.
easily wind some filter inductors using ter impedances. For the traditional 600V
manual techniques. Moreover, inductors impedance used at audio frequencies, in-
can handle greater power levels than ductors are larger by an order of magni-
small-signal active devices. You can con- tude. If you reduce the cutoff frequency Is this the best Design Idea in this
struct a simple lowpass filter with a 3-dB from 10 to 1 kHz, the inductor values also issue? Vote at www.ednmag.com/edn
cutoff frequency of 10 kHz; a source/load increase by an order of magnitude. mag/vote.asp.
impedance of 50V; five poles; and 0.02-
dB-ripple, Chebyshev response. Figure 1 TABLE 1—PARTS LIST FOR FIVE-POLE LOWPASS FILTER
shows the filter’s schematic; Table 1 pro- Function Value Realization Quantity
vides the parts list. Inductors 1.32 mH 28 turns No. 26 on Fair Rite toroid Two
No. 597700601-0.825-in. outer diameter
Table 2 shows the measured frequency
30.5253 30.25 in. thick
response with 50V source and load im-
Capacitors 0.33 mF Polypropylene with 2% tolerance Four
pedances. The extremely low passband-
Connectors BNC female Four-hole panel receptacle Two
insertion loss indicates that the inductors’
Enclosure Aluminum box Hammond 1590B/Bud CU-124 One
unloaded Q is greater than 100.You could
Board Cut by hand Vector board 169PP44C1 One
use smaller inductors, such as toroids with
Standoffs Male/female Amatom 9794-SS-0440 Six
0.5- or 0.625-in. diameters with accept-
able insertion losses (Reference 2). Note
that expensive Litz wire is unnecessary. TABLE 2—MEASURED FREQUENCY RESPONSE FOR LOWPASS FILTER
Lowpass filters need much lower inductor Frequency (kHz) Insertion loss (dB) Frequency (kHz) Insertion loss (dB)
unloaded Q values than do most bandpass 1 0.1 11 6.5
filters. At very low frequencies, both in- 3 0.1 13 15
ductors and capacitors can become large. 5 0.1 15 22.6
By using moderate filter-impedance lev- 7 0.15 20 36.5
els, such as 50 or 75V at kilohertz fre- 8 0.25 30 Greater than 50
quencies, inductor values can be lower 9 0.6 To 1 MHz Greater than 50
than 10 mH. With high-permeability in- 10 3.1

design
ideas
Watchdog timer assumes varied roles

Terry Millward, Maxim Integrated Products, Lambourn Hungerford, UK
he MAX6369-74 series uses a MX6373 to pulse
T of pin-selectable
watchdog timers
are designed to supervise mP
Figure 1
VCC
8 mA
R1
1k
WDO low for 170 msec every
5.2 sec. The load is a front-
panel power-on LED with a
activity and indicate when a 1-kV current-limiting resis-
WDI VCC
system is working improper- tor. By pulsing the LED
ly. During normal operation, GND WD0 rather than powering it con-
MAX6373
a mP should repeatedly tog- NC SET 2
tinuously, the average current
gle the WDI (watchdog in- decreases by a factor of 30 (88
put) before the selected SET 0 SET 1
mA versus 2.4 mA). The LED
watchdog-time-out period thus indicates that the equip-
elapses to indicate that the ment is on while minimizing
system is properly executing GND battery drain. By changing
code. If it fails to do so, the the Set pins to Set 050V, Set
supervisor IC asserts a A blinking LED allows a 30-to-1 average-current reduction in a power-on 15Set 25VCC, you can ex-
watchdog output WDO to indicator. tend the off time to 17 sec,
signal that a problem exists. thus reducing the average
The cited family of current to 32 mA. The circuit
Figure 2
watchdog supervisors in Figure 2 is similar to the
VCC
are available in SOT23-8 LOAD one in Figure 1 but uses a
packages and have selectable 8 mA MAX6371 to turn on a load
watchdog-time-out periods MAX6371 100k for 170 msec every 104 sec.
and delays of 1.7 msec to 104 WDI VCC The load can be a battery-
sec in seven steps. The ICs powered monitoring circuit
GND WD0
also have selectable output- that remains idle, saving
pulse widths of 1.7 or 170 NC SET 2 power and then wakes up to
msec, depending on part se- SET 0 SET 1 make a measurement. The
lection and the state of the: circuit in Figure 3 uses a
Set 0, Set 1, and Set 2 pins. MAX6373 with its Set inputs
You can use these devices for configured for timer dis-
GND
general-purpose timing abled. If you hold Set 1 low
functions, especially when This circuit wakes up every 104 sec to turn on a load for 170 msec. for longer than the watchdog
low current consumption is period (5.2 sec), then WDO
important. The ICs pulses low. You can use this
consume only 8 mA Figure 3 circuit in applications in
typical and 20 mA maximum VCC which a reset button is on a
over temperatures from a 2.5 front panel, for example. You
8 mA
to 5.5V supply. With WDI must deliberately depress the
MAX6373 100k 100k
connected to ground or VCC, button for at least 5.2 sec to
the internal timer cycles, WDI VCC trigger a reset. This feature
pulsing WDO low upon GND WD0 RESET can prevent an accidental re-
time-out. In addition to the set when someone inadver-
NC SET 2
lower current (20 versus 120 tently presses the button.
mA), the watchdog-timer IC SET 0 SET 1
RESET (PRESS FOR
takes less board space and 5.2 SEC TO RESET)
uses no timing resistors or Is this the best Design Idea
capacitors. The following cir- GND
in this issue? Vote at www.
cuits represent a few exam- edmag.com/ednmag/vote.
ples. You must press the reset button for at least 5.2 sec for the reset to take asp.
The circuit in Figure 1 effect.
design
ideas
One microcontroller serves

multiple external interrupts
Abel Raynus, Armatron International, Melrose, MA
n designing mC-based
I
5V
systems, you often
face a situation in Figure 1
which the mC has to respond
to an external event happen- R1 6 R2
100k 100k
ing at an uncertain moment S1 16 1
IRQ RESET
in time. One example is re-
ceiving an echo from an ob- S2 15 OSC1
C1
pA0 2 0.1 mF
ject in a pulse-range measur- CERAMIC
MC68HC705KJ1 RESONATOR
ing system. In these situa- S3 14 3 4 MHz
pA1 OSC2
tions, you would usually use
13 R3
an external interrupt. Unfor- pA2 pA4
11
tunately, low-end, small, in- 510
12
expensive mCs have only one pA3
pA5
10 R4 RED
LED
GREEN
LED
external-interrupt vector ad- 510
7
dress, so the mC can execute
only one interrupt-service
routine. What do you do if
the design objectives call for
the mC to react to several in- You can use an inexpensive mC to handle multiple external interrupts.
LISTING 1—MULTIPLE-INTERRUPT TEST ROUTINE

design
ideas
terrupts coming from different sources switches S1 to S3 (Figure 1). You can sim- mC program. The key to the method is to
and to process each of them in a differ- plify the interrupt-service routines to prepare the number-address of the in-
ent way? Figure 1 shows a design tech- operate with only two LEDs. The use of terrupt-service routine for the next ex-
nique that solves the problem. The the LEDs provides the opportunity to vi- pected interrupt in the special register
method is applicable to any mC, such as sualize and verify the interrupt process. Disp (dispatcher). In this case, the mC ex-
the 16-pin OTP MC68HC705KJ1 from After initialization, both LEDs turns off. ecutes every external interrupt with its
Motorola. This mC has two options for The system waits for the first interrupt own individual interrupt routine. The
handling external interrupts: via the IRQ from S1. As a result of the interrupt, the routine adds a delay of 200 msec for de-
pin triggered by a negative edge or via the green LED turns on. The system again bouncing the switches; you can eliminate
pins pA0 to pA3 triggered by a positive waits for the next interrupt from S2, and the delay if it is unnecessary for the in-
edge. You can choose these options as the red LED turns on. During the wait- terrupt signals. You can download List-
well as the capability to have edge or ing period, the mC can perform some ing 1 and associated assembly software
edge-and-level triggering by setting the function, which can differ for different from EDN’s Web site, www.ednmag.com.
proper bits in the MOR (mask-option projects. Service routines in real applica- Click on “Search Databases” and then en-
register). tions are much more complicated than ter the Software Center to download the
When you set pins pA0 to pA3 as ex- just lighting LEDs. But those details file for Design Idea #2650.
ternal-interrupt inputs, they connect in- are unimportant for illustrating this
side the mC as an OR gate. Hence, you method.
can trigger this mC from five external-in- The third external interrupt from S3
terrupt sources. If the number of sources switches off both LEDs, and the mC again
exceeds five, you can wire them through waits for an interrupt from S1. The limi-
an OR gate to any of the external-inter- tation of this method is that the sequence
rupt pins. To illustrate the method in the of incoming interrupts must be known, Is this the best Design Idea in this
simplest way, assume only three inter- but this constraint is unproblematic for issue? Vote at www.ednmag.com/edn
rupt sources, represented by pushbutton most applications. Listing 1 shows the mag/vote.asp.

design
ideas
Keep the heat down in power op amps
Vijay Damle, Digitronics, Pune, India
hen you include a power op 38V for a 7V p-p ac input. To control the clipping. Note that for fast-changing in-
W amp, such as PA05 from Apex Mi- negative-side SMPS, you must transfer put signals, the output may clip for a
crotechnology, in your design, it is information from SMPS1 to SMPS2. The short time until the power-supply volt-
desirable to minimize the supply-to-out- circuit in Figure 2, which generates cur- age rises. This phenomenon depends on
put differential to a minimum to reduce rent proportional to the input voltage, ef- the precision rectifier and the power sup-
power dissipation and to fully exploit the fects the transfer. Thus, SMPS2 generates plies’ response time.
amplifier’s output range. Our goal was to an equal-value but opposite-polarity
design a power amplifier to yield 70V p- voltage to that of SMPS1. If you need
p output at 10A with a fixed gain of 10 higher output current, you may need to
and a frequency of 30 Hz to 100 kHz. To increase the voltage headroom, depend- Is this the best Design Idea in this
obtain 635V swing entailed dc supplies ing on the power amplifier you choose. issue? Vote at www.ednmag.com/edn
of approximately 638V and two 65V Otherwise, you may experience output mag/vote.asp.
supplementary supplies. To derive the
full 10A at lower voltage, you PRECISION CONTROL
PROGRAMMABLE
ADDER
must reduce the supply voltage in Figure 1 RECTIFIER SMPS1 2
proportion to the output voltage to de- OFFSET V+ 5V
crease dissipation. In this case, the gain
is fixed at 10. So, you can control the dc PA05
voltage proportional to the input voltage 7V P-P MAXIMUM
VOUT
I/P
(Figure 1). SMPS1 and SMPS2 are iden- 30 Hz T0 100 kHz
tical voltage-programmed supplies (ex- V2 25V

cept for the 65V supplementary sup- GAIN=10
+
plies). The precision rectifier generates dc PROGRAMMABLE
output proportional to the ac-input am- SMPS2
CONTROL
plitude. To obtain approximately 66V
when no input signal is present, the cir- Power supplies track the input signal in bootstrap fashion, thus reducing power dissipation.
cuit adds offset voltage to the signal.
As the input increases, the
SMPS output increases from 6 to Figure 2 PNP (100V)
OUTPUT 15V
Keep the heat down +
2
in power op amps ......................................143 10k
+
Buck converter works efficiently SMPS1
6 TO 38V 10k
from phone line ..........................................144 40V=4 mA
215V SCALE
Sine reference is synchronous 2 +
with ac line ....................................................146 COMMON
Cascade bandpass filters 2
+PIGGYBACK SMPS2
for higher Q ..................................................148 (5V) CONTROL
26 TO 238V 1k
C program calculates checksums ............150
One-wire bus powers 40V=4V SCALE
water-level sensor........................................152 2PIGGYBACK
(25V)
Ideal transformers aid
in balanced-line analysis ..........................154
The switch-mode power supplies track each other with opposite-polarity outputs.
www.ednmag.com February 15, 2001 | edn 143

design
ideas
Buck converter works efficiently from phone line
Wayne Rewinkel, National Semiconductor, Santa Clara, CA
switching converter provides an 1.23V threshold controls the regulator’s ratings. C3 and C4 speed the comparator
A inexpensive way to generate 5V, 18

mA (48V, 5 mA maximum) directly
from a standard phone line (Figure 1).
output voltage according to the following
expression: VOUTt1.23V•(1RR3/R2). If
the divided output voltage is below the
action and thus reduce output ripple. R5
ensures that the 4041 receives sufficient
bias current, and R4 sets the maximum
The high input voltage and low available threshold, IC1 turns on, causing VOUT to bias current. L1 should have a value low-
current require a unique design approach ramp up until the voltage crosses the er than 100 mH and must have a satura-
to achieve high efficiency. The circuit uses threshold. Then Q1 pulls Pin 5 low, forc- tion rating exceeding 1A. Coilcraft’s
the LM2597HVM, which has a 60V rating IC1 into shutdown. IC1 stays in this DO3316683 inductor fills the bill nicely.
ing and power-saving features. Its VBIAS state until the output voltage again decays Smaller inductors degrade efficiency, be-
pin permits bootstrapping bias power to the comparator’s threshold and the cy- cause the 2597 goes into its pulse-cur-
whenever the output is higher than 4.4V. cle repeats. In this always-stable, discon- rent-limited protection mode. Larger val-
This feature reduces the bias current by tinuous-switching mode, the inductor ues also degrade efficiency by using
at least a factor of four to a typical cur- current is many times the load current, additional switching cycles. The circuit in
rent of 1 mA. Additionally, the IC has a so its stored energy at turn-off always Figure 1 provides satisfactory results with
shutdown/soft-start pin that, when forces a slight overshoot that has an effect input voltages of 10 to 60V. For an input
pulled low, shuts the regulator off (with similar to hysteresis. This overshoot is the of 48V, 5 mA, the available output cur-
10-mA maximum quiescent current). ripple voltage (ignoring capacitor ESR); rent measures 34 mA. The output regu-
When you release this pin, the IC starts you can estimate it from the energy translation is less than 2-mV output variation
switching with an increasing duty cycle. ferred to C2RC5 during a switching cycle. for inputs of 10 to 60V and load currents
These features combine with an external The following equation gives ripple: of 0 to 100 mA.
comparator and voltage reference to pro- VRIPPLEt=((VOUT•VOUT)1L1/(C21C5))).
vide the basis for a low-power switching R1 and C5 remove the large ESR-in-
regulator. duced spike from C2 caused by the 1A
The circuit uses the LM4041 ad- peak charging current. This lowpass fil- Is this the best Design Idea in this
justable-voltage reference with Q1 to ter is small and inexpensive, and it allows issue? Vote at www.ednmag.com/edn
form a small, low-power comparator. Its the use of capacitors with almost any ESR mag/vote.asp.
Figure 1
R1 VOUT
4.7 5V
VIN m 60V 7 3
VIN VBIAS
IC2
LM4041EIM R2
3-ADJ 3.9k
1 IC1
PGOOD
LM2597HVM
5
SS
C1 + C5
+
10 mF 2 C3
47mF
63V DELAY L1 R4 16V
10 nF
68 mH Q1 10k
>1A 4401
8
VSWITCH
C2 + +
220 mF C4
GND FB 16V 10 nF
6 4
D1
1A, 60V R3
R5 12k
10k
This inexpensive switching regulator derives its power directly from the phone line.

design
ideas
Sine reference is synchronous with ac line

P Seshanna, PhD, Assumption University, Bangkok, Thailand
any applications require a si-
M nusoidal reference voltage

synchronized to the ac line
voltage. You cannot derive such a refer-
Figure 2
ence voltage directly from the ac line be- (a)

cause the waveform of the ac line is dis-
torted because of nonlinear loads
connected to the line and because the
amplitude of the line signal varies. Hence,
you cannot use a simple step-down trans- (b)
former to derive the reference signal. The
circuit in Figure 1 develops a line-syn-
chronized reference signal whose phase
and amplitude you can adjust using po-
tentiometers P1, P2, and P3. The circuit (c)
steps down and converts the line voltage

to a square wave using the IC1A zero-
crossing detector. The integrator block,
IC1B, then integrates the square wave to
(d)
produce a triangular wave. The triangu-
lar wave passes through two narrow Distorted line voltage (a) produces a square wave (b). An integrator creates a triangular wave (c),
bandpass filters comprising IC2A and and bandpass filters produce a pure sine wave (d).
390k
Figure 1
L 3 0.47 mF
+ 1 22k 6
IC1A 2
220V 2
3V 2 IC1B
50 Hz 10k 5 7
+
N 10k 5k
P1
ZERO-CROSSING DETECTOR INTEGRATOR
0.1 mF
0.1 mF 100k 100k
253k
0.1 mF 253k
2 0.1 mF
2 1 16k 6 100k 100k
6 2
2 mF
16k IC
3 + 2A 2 2 2
IC2B 1
5 IC3A P3 IC3B OUTPUT
+ 7 5 + 7 3 +
5.6k
5.6k 1 mF 10k
P2
10k 1 mF
BANDPASS FILTERS PHASE-SHIFTER LEAD/LEG
An op-amp circuit uses only resistors and capacitors to generate a line-synchronized sine wave.

design
ideas
IC2B. The center frequency of the band- ence signal. You can adjust the amplitude wave has total harmonic distortion of
pass filters matches the 50-Hz line fre- of the output using potentiometer P1, 0.7%. Note that the circuit requires no
quency. The sine-wave output from the and you can adjust the phase with P2, P3, heavy, bulky inductors.
filters passes through two phase shifters or both. The circuit uses three low-pow-
to set the phase at either lead or lag. The er LM358 dual op amps. Figure 2 shows Is this the best Design Idea in this
allpass-filter configuration comprising the measured waveforms at different issue? Vote at www.ednmag.com/edn
IC3A and IC3B sets the phase of the refer- points in the circuit. The reference sine mag/vote.asp.
Cascade bandpass filters for higher Q

Trong Huynh and John Ambrose, Mixed Signal Integration Corp, Santa Clara, CA
witched-capacitor filters that an elliptic response if FSEL is low. When By inverting the clock between the two
S are preset for a given bandwidth

sometimes do not deliver the band-
width or Q an application requires. By in-
FSEL is high, you can select full-, third-,
or sixth-octave bandpass response. The
circuit in Figure 1 shows both ICs set for
filter ICs, you obtain a 10th-octave filter.
If you simply cascade the filters, without
the clock inversion, the signal has a de-
verting the clock between two switched- sixth-octave bandpass response. lay to the second filter equal to the clock
capacitor bandpass filters, such as the The clock-to-corner ratio of the period. The result is an increase in pass-
MSFS1 from Mixed Signal Integration MSFS1 is 50-to-1. With switched-capac- band ripple and no change in the Q of the
Corp, you can configure a high-Q filter itor filters, changing the clock frequency filter.
(Figure 1). The MSFS1 is a select- moves the center or corner frequency of
able, seventh-order, lowpass/bandpass, the response by the same amount. For ex-
switched-capacitor filter. Using the FSEL ample, if the input clock to the MSFS1 is
pin, you can select either a lowpass or a 1 MHz, the corner frequency is 20 kHz. Is this the best Design Idea in this
bandpass response. With the TYPE pin, Cutting the clock frequency to 500 kHz issue? Vote at www.ednmag.com/edn
you can select a Butterworth, a Bessel, or results in a corner frequency of 10 kHz. mag/vote.asp.
VCC
5V
100 nF
Figure 1
47k 47k
FSEL IN FILTER
INPUT
100 nF
FSEL IN OUT GND
IC2
OUT 100 nF MSFS1 VSS
FILTER GND TYPE
OUTPUT IC1
VDD
100 nF TYPE MSFS1
CLK
VSS
CLK
VDD
100 nF
74HC04N
IC1A
2 1
V1
+
1 MHz/5V
By inverting the clock to one switched-capacitor filter, you obtain a cascaded filter with enhanced Q.

design
ideas
C program calculates checksums

Ken Levine, Airshow Pacific Systems, Kirkland, WA
o ensure data integrity, it’s wise
T to frequently calculate file check-

sums. The C program in Listing 1
calculates the checksum of a file using a
LISTING 1—C PROGRAM FOR CALCULATING CRC
16-bit CRC (cyclic redundancy check).

The program assumes an 8-bit byte size.
The routine reads the file as binary and
processes one byte at a time. The CRC
formula the program uses is X161
X121X511, with a starting value of
hexadecimal FFFF. The program displays
the number of bytes processed. The file
calccrc.c starts by including the header
files needed. Next, the routine defines
and initializes the constants. (The pro-
gram does not use the C11 keyword
const; therefore, a C compiler can com-
pile the program.) Inside main(), the
program defines variables and issues the
initial starting value for the CRC. The
routine performs a check to verify that at
least two arguments passed to main(). If
only one argument passes, the program
terminates with a message that you need
to supply a file name.
The program reads and processes one
byte at a time until it reaches the end of
the file. Each time the program reads a
byte, the byte counter increments. At the
end of the file, the program displays the
CRC of the file and the number of bytes
read. The routine calculates the 16-bit
CRC, byte by byte, using the calcCRC16
function. This function passes the byte to
be processed and the current value of the
CRC and returns the new CRC value. The
program calculates the CRC for each bit
in the byte. The variable temp is assigned
the current CRC value right-shifted 15
times, XORed with the current byte val-
ue right-shifted seven times. This opera-
tion XORs the MSB of the CRC with the
MSB of the byte, so temp will have the
value zero or one. Note that this opera-
tion does not change the values of the
CRC or the byte. The CRC then left-shifts
one place. If temp is 0, nothing happens.
If temp is 1, the program XORs the CRC
with hexadecimal 1021 (the X121X511 (continued on pg 152)

design
ideas
term). Next, the byte left-shifts one place,
so the program can process the next bit. LISTING 1—C PROGRAM FOR CALCULATING CRC (continued)
This process repeats until the routine
processes all eight bits of the byte.
If you wish to use a different formula
to calculate the CRC, you need only
change the variable CRC16, assuming
that the formula still starts with the X16
term). If you wish to calculate a 32-bit
CRC, the variables INIT and CRC16 can-
not be of type int. You can set the vari-
ables SHIFT_CRC, SHIFT_BYTE, and
BYTE_SIZE to other values to accom-
modate various byte and CRC sizes. This
program is compiled using Borland
C11 3.0, Borland C114.5, and Mi-
crosoft Visual C11 1.0. You can down-
load Listing 1 from EDN’s Web site, Center to download the file for Design Is this the best Design Idea in this
www.ednmag.com. Click on “Search Idea #2674. issue? Vote at www.ednmag.com/edn
Databases” and then enter the Software mag/vote.asp.
One-wire bus powers water-level sensor

Dale Litwhiler, Lockheed Martin, Newtown, PA
ou can use the simple sensor cir- steal its power from the bus via the Schot- with a 50% duty cycle. The sensor pro-
Y cuit in Figure 1 to remotely monitor

the level of liquid water in a vessel
such as a swimming pool. The LMC555
tky diode, D1. Because the circuit is sens- vides a capacitance that varies with water
ing water that is part of the electrical cir- level.
cuit, you should use an ac-coupled signal Figure 2 shows one method of fabri-
sensor oscillator provides an output-sig- to avoid polarization of the water and
nal frequency that is a function of the wa- plating of the electrodes. One approach
ter level. This signal drives a DS2423 is to have the water in a circuit DS2423
Figure 2
pulse counter. A host PC or mC reads the branch that is in series with
output of the pulse counter via the Dal- some capacitance. In this sensor circuit, LMC555
las Semiconductor one-wire bus (Refer- the water is in the branch containing the PERFORATED
ence 1). The circuit uses approximately timing capacitance of a CMOS 555 timer, BOARD TWIST AND
150 mA of current, allowing the circuit to configured as a free-running oscillator C
SOLDER LEADS
1
DATA
Figure 1 + CK06-STYLE
ONE-WIRE D1 22 mF 3 0.1-mF
BUS 1N5817 VBAT CAPACITORS
2
DATA
GND
DS2423
6 A
IN GND
1
4 8
TO PROBE R VS
OUTER SHELL 7
6
(PIPE) DIS THR 0.1 mF
LMC555
3 2
OUT TRG
GND
RC 1
1M
C20 C1 C20
0.1 mF 0.1 mF FRONT VIEW SIDE VIEW

(PART OF PROBE)
A string of series-connected capacitors provides
A simple 555-type timer and a counter form the heart of a water-level sensor. an indication of water level.

design
ideas
cating the sensor. You epoxy-bond a se- Note that the frequency changes linearly the event of a catastrophic bus fault.
ries string of N radial-leaded ceramic ca- with water level. With these values of capacitance and
pacitors of equal value C underneath a pc This application uses 20 0.1-mF, resistance, the sensor’s output-frequency
board. Twist the leads of adjacent capac- CK06-style capacitors. The lead spacing range is approximately 7 to 142 Hz in
itors, solder them together, and trim of these capacitors is 0.2 in. These di- steps of approximately 7 Hz. In practice,
them to serve as electrodes to contact the mensions provide a measurement range you might read the counter at intervals
water. The outer shell of the sensor, a of 4 in. with a resolution of 0.2 in. This of several seconds to several minutes to
piece of 0.75-in. copper pipe, forms an- design uses 1 MV for the oscillator tim- obtain an averaging effect. This sensor
other electrode. If you place this assem- ing resistor, RC, because the timing re- has found application for two summers
bly vertically in a vessel, the capacitance sistance must be much larger than the in a residential swimming pool. Users
between the terminals of the sensor (the impedance of the water to minimize noticed no change in performance from
uppermost lead of C1 and the outer shell) timing error. (Measurements of several corrosion or plating of the electrodes.
increases in steps as the water rises and municipal and residential well-water
covers more of the capacitors. The water samples revealed impedance values of Reference
effectively short-circuits the capacitors to approximately 5 kV in the frequency of 1. Awtrey, Dan,“Transmitting data and
the outer-shell electrode. Because the ca- 5 Hz to 1 kHz with 0.5-in. probe spac- power over a one-wire bus,” Sensors, Feb-
pacitors are in series, the total capaci- ing.) Another reason for 1-MV oscilla- ruary 1997.
tance changes according to: CTOTAL= tor timing is that the DS2423 counter
C/(N2n), where n is the number of ca- has a maximum input frequency of ap-
pacitors with both leads covered by wa- proximately 2 kHz. Also, you must min-
ter. When you insert this expression in imize the power stolen from the bus. Fi- Is this the best Design Idea in this
the equation for the 555 oscillation fre- nally, you must maintain maximum issue? Vote at www.ednmag.com/edn
quency, you obtain fOSC5(N2n)/1.4RCC. isolation of the water from the bus in mag/vote.asp.
Ideal transformers aid in balanced-line analysis

Alan Victor, IBM Microelectronics, Research Triangle Park, NC
ransmission-line transformers
T combined with appropriate

resistor values are useful in hy-
brid applications over limited band-
Figure 1 VIN
N=1 N=1
VOUT
widths. One such device, the 1808 hybrid

combiner, is useful in CAD analysis for
verifying the performance of balanced T1 T2
and differential circuits. The completed VOUT /_11807
T3
transformer provides matched signal lev- RO
els, 1808 phase-shifted, and all ports at an
N=1:u O
4R
impedance Z0. You don’t need transmis- 50
sion-line transformers in the construc-
tion of this hybrid for analysis. Instead,
the circuit uses an ideal 1-to-1 trans- A simple transformer circuit aids in the analysis of differential and balanced circuits.
former. Combined with the appropriate
termination resistor and one additional to the two transformers you use, and with ing the arrangement in Figure 1. You can
transformer, an ideal differential-excita- R0 set at 25V, a 50V, three-port unit be- also turn the circuit around end-to-end
tion source is available. Extensive band- comes available. If you replace the termi- and then use it for combining the output
width, balanced and equal impedance at nation resistor, R0, with a transmission of the balanced circuit. Tests show that
all three ports, and infinite isolation pro- line and a variable resistor, then a 1808 the circuit yields a perfectly flat frequen-
vide an excellent circuit block to assist in phase-shifted variable impedance be- cy response from 1 to greater than 22
analyzing differential and balanced cir- comes available at the excitation ports. GHz and phase shifts of exactly 08 and
cuits. The circuit block is borrowed from You then have a tool for studying bal- 1808 (depending on the port).
power-amplifier hybrids where it is use- anced-line performance sensitivity to
ful for signal splitting and combining source-impedance variations. You can Is this the best Design Idea in this
(Figure 1). study high-speed, RF, and microwave us- issue? Vote at www.ednmag.com/edn
After you add a third transformer, T1, ing differential or balanced topologies us- mag/vote.asp.
design
ideas
Circuit senses high-side current
Bob Bell and Jim Hill, On Semiconductor, Phoenix, AZ
he accurate, high-side, current-
T
IS
sense circuit in Figure 1 does
Figure 1
not use a dedicated, isolated RS
supply voltage, as some schemes do. Only INPUT LOAD
the selected transistors limit the com- 0.025
mon-mode range. The circuit measures I1 I2

the voltage across a small current-sense R1 R2
I3 50 50
resistor, RS. The operation of the circuit
revolves around the high-side current
mirror comprising Q1 and Q2. All the cir- Q1A Q1B
cuit components have one overall func-
tion: to make the collector currents equal
in Q1 and Q2. The additional current mir-
ror using Q3 sets the values of the collec- VCC
tor currents. The collector current is
(VCC20.7)/(R51R6)Q100 mA. You can R6
49.9k
best calculate the gain of the circuit by Q2A Q2B
analyzing the loop formed by R1, RS, R2,
Q1B (emitter base), and Q1A (base emit-
ter). In Figure 1, the currents are IS, the VCC
high-side measurement current; I1 and I2,

Q3A Q3B
the mirror currents of Q1A and Q1B; and 7 + 3
I3, a branch current from the emitter of Q4
6 IC1
_ 2
Q1A. 10
C1 4
When you sum the currents around VO R3 R4 R5
the loop, (IS•RS) 1 (I2•R2)1VQ1B(e2b)2 RG 0.01 mF
49.9k 49.9k 49.9k
((I11I3)•R1)5 0. Because I15I2, R15R2,
0
Circuit senses high-side current................123
Adjustable filter provides NOTES: IC1 IS AN MC33202 RAIL-TO-RAIL OP AMP.
lowpass response ........................................124 Q1 AND Q2 ARE SC-88 MBT3906 DUAL PNPs.
Q3 COMPRISES MBT3904 SC-88 DUAL NPNs.
Monitor high-side current Q4 IS A 2N7002 SOT-23 FET.
without an external supply........................126

This circuit measures high-side currents without the need for auxiliary power supplies.
Noncontact device tests
power supplies..............................................128 and the emitter-base voltages are equal, imately 10V to several hundred volts,
Single chip detects I35IS•RS/R1. Looking at the remaining limited by the selected transistors.
optical interruptions ....................................130 circuitry, the op amp keeps the transis-
tors’ collector currents equal by control-
Programmable source powers
ling I3 through Q4. Therefore, the overall
dc micromotors ............................................132
transfer function is VOUT5IS•RS•RG/R1.
Optocoupler extends high-side For RG51 kV, the transfer function is Is this the best Design Idea in this
current sensor to 1 kV ................................134 VOUT50.5•IS. The circuit can operate over issue? Vote at www.ednmag.com/edn
a common-mode input range of approx- mag/vote.asp.
www.ednmag.com March 1, 2001 | edn 123
design
ideas
Adjustable filter provides lowpass response

ou can configure
Y simple lowpass filters

as pi sections with
nominal three-pole, 0.1-
TABLE 1—MEASURED AMPLITUDE RESPONSE OF ADJUSTABLE LOWPASS FILTER
Frequency
(MHz)
Box
insertion
loss (dB)
Filter 1
insertion
loss (dB)
Filter 2
insertion
loss (dB)
Filter 3
insertion
loss (dB)
Filter 4
insertion
loss (dB)
dB Chebyshev response 1 <0.1 0.1 <0.1 <0.1 <0.1
to provide a moderate 2 <0.1 0.3 0.1 0.1 0.1
amount of stopband 2.5 <0.1 0.6 0.1 0.1 0.1
selectivity. You can put 2.9 <0.1 1.7 0.1 0.1 0.1
four of these filters into 3.1 <0.1 2.5 0.15 0.1 0.1
one enclosure and then 3.3 <0.1 3.3 0.15 0.1 0.1
select discrete-filtering 4 <0.1 7.3 0.2 0.1 0.1
steps by using toggle 5 <0.1 13 0.45 0.2 0.1
switches. Manufacturers 6 <0.1 17.9 1.3 0.25 0.15
of commercially avail- 6.5 <0.1 20 2.1 0.25 0.2
able stepped attenuators 7 <0.1 21.8 3.1 0.25 0.2
and adjustable baseband 9 <0.1 28.2 8.3 0.4 0.2
equalizers commonly use 12 <0.1 33.4 15.3 1.3 0.25
this technique (Reference 14 <0.1 34.8 19.4 2.9 0.4
1). In an adjustable low- 17 <0.1 35.2 24.5 6.4 0.9
pass filter, each filter 20 <0.1 35.3 26.4 10.2 2.1
section uses commonly 23 <0.1 >35 28.8 14.5 4
available components 30 0.1 >35 31.7 19.2 9.9
(Figure 1). This example 50 0.2 >34 >34 23.5 20
uses filter-section cutoff 100 0.5 >28 >28 >24 >24
frequencies for standard
Figure 1
SECTION 1 SECTION 2 SECTION 3 SECTION 4
fC=3.083 MHz fC=6.586 MHz fC=14.491 MHz fC=21.310 MHz
S1 S2 S3 S4
L1 L2 L3 L4
4.7 mH 2.2 mH 1 mH 0.68 mH

C1 C2 C3 C4 C5 C6 C7 C8
1200 1200 560 560 270 270 180 180

pF pF pF pF pF pF pF pF
NOTE: ALL SWITCHES ARE DOUBLE-POLE, DOUBLE-THROW TOGGLE SWITCHES.
A switchable lowpass filter provides a choice of four distinct cutoff frequencies.
124 edn | March 1, 2001 www.ednmag.com

design
ideas
inductors and capacitors without the use solder lugs. The four filter sections ements. Stray series inductance, estimat-
need for any extra components in series have 50V characteristic impedance and ed at approximately 55 nH, arises from
or parallel. Fixed inductors are Coilcraft nominal 3-dB cutoff, from left to right in the 3.5-in. physical length of the enclo-
90 series axial-lead chokes with 610% Figure 1, of 3.083, 6.586, 14.491, and sure, plus 2 in. for the four switches.
tolerance. Fixed capacitors are poly- 21.310 MHz. Table 1 shows the measured
propylene units, available from any dis- amplitude response for the box alone and Reference
tributor, with 62% tolerance for the for the four individual filter sections. The 1. Kurzrok, Richard, “Adjustable-am-
1200-pF devices and 65% tolerance for low-cost, adjustable lowpass filter deliv- plitude equalizer provides small discrete
the other values. ers reasonable performance. As the fre- steps,” Electronic Design, May 31, 1999, pg
The adjustable lowpass filter is in a quency approaches 100 MHz, the trans- 76.
3.625-in.-long31.5-in.-wide31.0625- mission performance of the enclosure
in.-high Bud CU-123 die-cast aluminum deteriorates with all filter sections
box with input and output BNCs. Minia- switched to the off position. The inter-
ture toggle switches for the individual fil- connections between switched sections Is this the best Design Idea in this
ter sections are accessible at the enclo- use available bus wire without any pre- issue? Vote at www.ednmag.com/edn
sure’s exterior. Internal ground returns cautions to minimize parasitic circuit el- mag/vote.asp.
Monitor high-side current

without an external supply
Vijay Damle, Digitronics, Pune, India
ypical high-side cur- puts by more than 2.5V be-
T rent-sensing circuits re-

quire a dc source that is
2.5 to 13V greater
Figure 1 2.5 TO 13V
low the positive-supply
connection and tie the op
amp’s V1 pin to shunt V1
than the V1 high- SHUNT (Figure 2).
` 1
bus voltage (Figure 1). Gen- V` BUS
LOAD In the circuit, IC2 with
erating this supply is painful R10 and R11 generate a 15V
in many situations. For ex- output. The R3 and R6 pair
_
ample, in power supplies for VIN
and R5 and R8 pair form di-
TV transmitters, the main (LIMITED BY `
viders such that the op
SMPS (switch-mode power OP-AMP CURRENT- amp’s inverting and nonin-
SPECIFICATIONS) PROPORTIONAL
supply) output supplies the OUTPUT
verting inputs are approxi-
power amplifier, and a series mately 3V less than the V1
switching regulator steps supply of the op amp. You
down the main SMPS output can use R7 and R9 to trim
to drive the exciter. The sys- the offset to avoid the need
tem must remotely display Typical high-side current-sensing circuits require a dc source that is 2.5 to for potentiometers. Op
the currents of both of these 13V greater than the V1 high-bus voltage; generating this supply can be dif- amp IC1 and Q1 generate a
supply outputs, with 0 to ficult. current that is proportion-
50A corresponding to 0 to al to the shunt voltage. R12
5V referred to sense V2. Because of the put, though isolation is not required. generates a voltage that is proportional to
presence of a series switch, the V2 lines An alternative approach for this appli- the drop across shunt R4. R1 trims the
of both outputs are common. Thus, you cation takes advantage of low-offset op- gain.
cannot use shunts in the V2 line and amp characteristics to design a circuit If you use this circuit at less than 25V,
amplify. Shunts are necessary on the that works with a wide voltage range and then you can delete IC2, R10, and R11. You
positive bus of both the outputs. The needs no other supply. The V1 and in- should also ground IC1’s V2 pin by
main output supplies 30 to 45V at 30A, verting and noninverting terminals of the shorting R2, and you can replace R2 with
and the exciter supply outputs 22 to 26V OP07 op amp need a minimum of ap- a constant-current source to reduce the
at 10A. You need costly Hall-effect proximately 2 to 2.5V to function prop- power due to bus-voltage variation (Fig-
sensors to achieve the proportional out- erly. Thus, you can pull the op amp’s in- ure 3.)
design
ideas
Figure 2 Figure 3
SHUNT
0.002 R10
VIN BUS
LOAD 10k
25 TO 45V 82k
R4 R5
R3 200
200 _ IC2
IC1 TL431
Q1 R2= 2W NPN
OP07
` 2N2907 R11 DEVICE
10k 1N4007
R6 R8
R7 R9 22
820 820 1N4007
R2 50A=5V
330/5W R12
R1
5k At voltages less than 25V, you can replace R2
0V
with a constant-current source.
amplifier to reduce the output imped-

A modified current-monitoring circuit pulls the op-amp inputs below the positive supply voltage. ance, and the buffer can derive its sup-
ply across R2, which increases its operat-
This circuit was tested for 0 to 1558C, cuits have limitations due to op-amp ab- ing supply range by 15V or more. One
and it maintained proportional output solute-maximum voltage ratings. The limitation is that, in the case of a short
within 61% for a bus-voltage variation circuit acts as the minimum load that circuit, the current-proportional output
of 25 to 45V over this temperature range. SMPS outputs normally require, which drops to zero.
This approach has many advantages. eliminates or reduces high-wattage re-
An external supply is unnecessary. The sistance across the output. You can easi- Is this the best Design Idea in this
circuit is suitable for bus voltages of 5 to ly scale the circuit for different propor- issue? Vote at www.ednmag.com/edn
60V with component changes. Other cir- tional outputs. You can add a buffer mag/vote.asp.
Noncontact device tests power supplies

Alberto Ricci Bitti, Eptar, Imola, Italy
he probelike device in Figure 1 useful feature when testing boards that
T comes in handy as a quick go-

no-go test for step-down
power supplies. You can build it using a
Figure 1
operate without insulation from the
mains.
For optimum performance, use a very
very bright surface-mount LED and an bright-red LED. Other colors feature
inductor of the same type as in the pow- RED LED greater forward voltages, which reduce
er supply, which in this case is 100 mH. HIGH the sensitivity. You are not restricted to
100 mH EFFICIENCY
Placing this probe close to a working surface-mount LEDs, although this type
step-down power-supply coil lights the helps by keeping the probe small and
LED. The probe lights when the distance rugged.
from the step-down coil is as much as 1
cm, making the probe capable of testing
even plastic-encased or epoxy-filled
power supplies. Industrial engineers will Is this the best Design Idea in this
particularly appreciate the capability of An LED and an inductor make a simple probe issue? Vote at www.ednmag.com/edn
not touching the circuit, which is also a for testing power-on of the supply. mag/vote.asp.
design
ideas
Single chip detects optical interruptions

Frederick M Baumgartner, FM Broadcast Services, Parker, CO
etting up a light beam and detector IC in the circuit. The 567’s oscillator di- photo detector) also work to a degree.
S to count objects on a conveyer belt,

sense security intrusions, or drive a
tachometer is simple. However, the task
rectly drives an infrared LED on the op-
tical-transmitter end. When the pulsed
light returns to the IR phototransistor, a
Ambient light or another beam break-
er’s IR light doesn’t false-trigger the cir-
cuit unless significant near-frequency
is no longer trivial if you add ambient single-stage 2N2222 transistor amplifies light content exists. However, ambient
light or multiple beams, limit optical the resultant signal to drive Pin 3 of the light can swamp the detector, so you may
power, or extend the distance of the light LM567. Thus, the circuit essentially di- need to adjust the R2 bias for your appli-
beam more than a few inches.You can use rects the PLL to lock to itself, which cation. Of course, using a self-adjusting
optical lenses and filters and high-power makes Pin 8 go low. The values of R1 and module with IR filters can easily increase
optical sources on the light-path side to C1 provide operation of approximately 3 the range by two orders of magnitude.
improve performance. On the electronic kHz, and the filters set by C2 and C3 pro- One interesting variation of the circuit
side, servo-bias control of the detector vide a clean output from the 567. Oper- is to use two or more devices on the same
and electronic modulation and filtering ation from 2 to 5 kHz works best. Lower frequency, forming a ring. All devices
of the light beam can add considerable frequencies require more conditioning lock, and both ends detect a break in any
range. The circuit in Figure 1, which you and thus larger and more critical values beam or a modulation of the frequency
can use with these performance im- of C2 and C3, resulting in longer response of any device for communication.
provements, economically provides a times and possible jitter. Higher frequen-
minimal-parts-count circuit with negli- cies result in lower efficiencies for the
gible power requirements to achieve ap- cheap LED and phototransistor. Howev-
proximately a foot of useful range even er, tachometers may require higher fre- Is this the best Design Idea in this
under varying ambient-light conditions. quencies. IR components are unneces- issue? Vote at www.ednmag.com/edn
The venerable LM567 PLL is the only sary. Two same-color LEDs (one for the mag/vote.asp.
5V
Figure 1
C2
0.22 mF
1 8
C3
0.22 mF
2
R2 470k 10k LM567

2.2k 7
0.1 mF
3
6 330
IR
PHOTO
TRANSISTOR 0.1 mF R1 IR LED
TIL414 2N2222
10k
4 5
C1
0.047 mF
A light-beam-breaker detector uses just one IC and a few external components.

design
ideas
Programmable source powers dc micromotors
VK Dubey, JP Rao, and P Saxena, Centre for Advanced Technology, Indore, India
he circuit in Figure 1 is a simple,
T economic, compact, and

tricky way of using the LM723
as a programmable voltage source to
Figure 2
3000
2500
ENCODER 2000
drive dc micromotors. Because of the FREQUENCY
1500
(Hz)
mPs’ accurate positioning and control, 1000
these motors are useful in applications
500
such as optical mounts and flexible shaft
0
control, which take advantage of the 0 20 40 60 80 101 121 141 161 181 201 221 241
higher speed and fast movement of servo DAC CODE
controls compared with stepper motors.
These designs require a stable, program- The DAC-code versus encoder-frequency, or speed, curve is linear.
mable dc-voltage source.
The LM723 is a fixed linear regulator, n’t use the internal voltage reference of quency from the magnetic encoder in re-
but this application configures the regu- the LM723. The circuit also incorporates sponse to maximum speed is 2.8 kHz.
lator as a programmable voltage source. short-circuit current limiting and remote The circuit feeds back this signal to the
You can set the output to a value of 200 shutdown. Varying the output voltage mC to measure the speed. The linearity of
mV to 6V. The output, an emitter-fol- changes the speed of the motor that con- the voltage source is good over a voltage,
lower type, provides low output imped- nects across the output. temperature, and speed range (Figure 2).
ance. The circuit limits the maximum You adjust the minimum output volt- With only slight modifications in com-
output current to the load, or the motor, age of 200 mV by offsetting the DAC out- ponent values and ratings, you can use
at 75 mA. The output of an 8-bit DAC put with zero data, and successive DAC this same LM723 configuration in other
and a current/voltage converter provide input codes increase the voltage-source similar applications for higher output
a variable reference voltage. At the non- output to 6V. You can use a single-chip voltages.
inverting input of the LM723, you need mC for controlling the speed through the
to adjust the value of R1 so that the max- DAC, the direction, and the brake. The
imum reference voltage does not exceed no-load maximum speed is 15,100 rpm. Is this the best Design Idea in this
8.5V. Because the reference voltage comes By attaching a reduction gear-head with issue? Vote at www.ednmag.com/edn
from an external source, the circuit does- a ratio of 529-to-1, the maximum fre- mag/vote.asp.
15V
15V
Figure 1 200
V+ VCC BC547
V0
I/V CL
8-BIT CONVERTER 500
DAC AND OFFSET NI CS
1408 LM723 200 MOTOR
ADJUSTMENT
200
R1
2k INV
COM
5V
DATA
1N4007
2k
BRAKE CONTROL 2k RELAY
1000 pF
BC547 BC547
mC SPEED FEEDBACK 10k
FROM MOTOR ENCODER
DIRECTION CONTROL
NOTES:
RELAY=TWO-CHANGEOVER REED RELAY.
MOTOR=FAULHABER DC MICROMOTOR TYPE 1219-006 G, MICRO-ENCODER TYPE 30B.
Configuring an LM723 as a programmable voltage source provides a variable dc source for driving dc micromotors.

design
ideas
Optocoupler extends high-side current sensor to 1 kV

Roger Griswold, Maxim Integrated Products, Sunnyvale, CA
he task of sensing dc current at safety precautions when working with During operation, the load current
T high voltage is often problematic.

Most high-side current-sensing ICs
available off the shelf are good only to 30
high voltage.
The circuit has a floating section and
a grounded section, each requiring a lo-
passes through shunt R1 and produces a
small voltage. IC1 monitors this voltage
and outputs a proportional current of 10
or 40V. Combining an optocoupler with cal low-voltage supply. The floating sec- mA/V. This proportional output current
such an IC yields a sensing circuit in tion detects load current and drives the routes through R2, which produces a volt-
which the only limitation of the high-side high-voltage side of the optocoupler. The age proportional to the main load cur-
voltage is the optocoupler’s standoff volt- grounded section monitors the optocou- rent. The rest of the circuit generates a
age (Figure 1). pler’s low-voltage side and outputs a volt- copy of the voltage across R2 but on the
A precision, high-side current-sense age proportional to the high-side load low-voltage side of the optocoupler. IC2
amplifier, IC1, and a high-linearity analog current. IC3 has a feedback photodiode monitors the voltage across R2 and drives
optocoupler, IC3, extend the high-side on the high-voltage side that virtually the optocoupler’s LED via Q1. The LED
working voltage to 1000V dc. IC3 sup- eliminates the LED’s nonlinearity and generates light that impinges equally on
ports a continuous 1000V dc. Its UL rat- drift characteristics. In addition, IC3’s two the high- and low-side photodiodes. IC4
ing is 500V rms for 1 minute, and its tran- closely matched photodiodes ensure a monitors the low-side photodiode and
sient surge rating is 8000V dc for 10 linear transfer function across the isola- outputs a voltage proportional to the
seconds. You should follow all proper tion barrier. high-side load current. A graph shows the
ISHUNT, LOAD CURRENT

SHUNT R1
0.150
Figure 2
+ 8
9V DC 2 6 10 pF
1 1
1 4 R3
+ 7
100k
3
IC1 3 5 +
MAX4172 IC2 6
MAX4162
R2 2 _
3.32k
4
+
m1000V DC 3 4
1 Q1 HIGH-VOLTAGE
IC3 2N3906 LOAD
HCNR200
2 1 510
ISOLATION BARRIER
5 6 R4
100k
10 pF
+
3 7
+ 9V DC
IC4 6 1
MAX4162 +
2 _
OUTPUT
4
1
The ground-referenced output voltage, VOUT5ISHUNT (4.80V/A), is proportional to the high-side load current. As configured, the circuit measures load
currents to 1A.

design
ideas
output voltage as a function of The circuit output then
shunt current (Figure faithfully reproduces the
Figure 2
2). 5 voltage across R2. The
If R3 and R4 are equal, the MAX4162 op amp is a
overall transfer function is: good choice for this cir-
VOUT 4 cuit because of its input-
= 0.01 • R1 • R 2 . bias current of 1 pA, its
ISHUNT rail-to-rail input and out-
Three parameters let you 3 put swings, and its ability
modify the circuit to monitor OUTPUT to operate from one 9V
other maximum load currents VOLTAGE
(V) 2
battery. With R15150
and output a different voltage mV and R253.32 kV, the
range. The maximum IC1 out- output voltage for ISHUNT
put current is 1.5 mA, so the 1 51A is 4.80V using the
maximum allowed shunt volt- given transfer function.
age is 150 mV. Also, the maxi- Experimental results at
mum allowed photodiode 0 ISHUNT51.00A give VOUT5
0.0 0.2 0.4 0.6 0.8 1.0
current is 50 mA. Choose an R1 4.84V with an error less
value that produces 150 mV at SHUNT CURRENT (A)
than 1%.
the maximum load current
that the circuit monitors. The output voltage versus shunt current is linear.
Then, choose an R2 value that
produces the desired corresponding todiode at the maximum desired output
maximum output voltage at 1.5 mA. voltage, or Is this the best Design Idea in this
Match R3 and R4, and choose a value that VOUT _ MAX issue? Vote at www.ednmag.com/edn
allows less than 50 mA through the pho- R3≥ 16
. mag/vote.asp.
50 × 10

design
ideas
PWM circuit controls sensor’s AGC
Dongjie Cheng, Allegro Microsystems, Willow Grove, PA
ll electronic sensors have their
A limits on working distances

and environmental toler-
ances. Dynamic range defines a sensor’s
F i g u r e 1
100k
12V
3
+
V12
V+
maximum allowable variations in the sig- V12 IC1 1 1k
100k LM2902/
nal amplitude. ACG (automatic gain con- OUT
NS R2
trol) finds widespread use in systems to + V2 2
2 V2
12V
extend the dynamic range. Applications 2
100k 11
using photoelectric or ultrasonic tech- RECEIVER
niques involve both emission and detec- +
SIGNAL
FREQUENCY=1k 100k
tion energy. In many cases, the emission VOFF=5.9
V3
first establishes a background receiver VAMPL=5.8 2 V12
signal as a reference, and the receiver

monitors the signal and detects any 4 8 R1
RESET VCC 2.6k
changes against this reference. It is often 7
DISCHARGE
desirable to maintain the background TRIGGER 2 C1
TRIGGER
signal at a moderate level so that the sen- V1
6
THRESHOLD
sor works within its limits. A signal that +
TD=10n IC2 0.01 mF
is too weak cannot produce a significant 2
TF=10n 555
PW=0.099m CONTROL
SNR, and a signal that is too strong can PER=0.1m 3 CONTROL
5
OUTPUT
disable the sensor by saturation or pro- V1=0.1
GND 100 pF
TR=10n
duce overheating of the sensor. Design- V2=11.9 PWM EMISSION 1
ers use different techniques to achieve DRIVE
satisfactory signal handling. The simplest 10M
method might be adjusting emission
power or the receiver’s gain by manually
configuring jumpers or switches. An ex- A PWM circuit provides an AGC function to increase a sensor’s dynamic range.
ample of an AGC solution is to let a mP
constantly adjust emission to a suitable based technique for maintaining the ref- ing background signal. IC2A functions as
level. Figure 1 shows a simple PWM- erence signal at an ideal level. an inverter. Its output passes through the
The concept embodied in Figure 1’s lowpass filter R2/C2 to generate the Con-
technique is that, if the sensor sees a trol signal in Figure 2, fourth panel
PWM circuit controls sensor’s AGC..........125 strong background signal, the circuit down. IC2, a 555 timer, acts as a pulse-
slowly reduces the emission intensity at width modulator. Its output is a pulse
Two gates expand ASIC’s
the fundamental frequency by reducing train named PWM emission drive (Fig-
memory-decoding range ..........................128
the pulse width of the emission drive sig- ure 2, first panel). The frequency of the
Dual dc-motor-speed controllers nal. We verified the idea by using Or- PWM emission drive follows the 10-kHz
navigate robots ............................................130 CAD/Cadence PSpice modeling, fol- trigger signal, modeled with V1 and plot-
SDRAM interface slashes lowed by experimental verification. The ted in Figure 2 in the second panel down.
pin count........................................................132 voltage source, V3, generates a 1-kHz si- The modeled results in Figure 2 indicate
nusoidal signal named receiver signal. a negative correlation between the width
Minimize communication time
Figure 2 plots this signal for a half-cycle of PWM emission drive and the level of
between small mCs ....................................134
in the third panel down. The model sim- receiver signal. As the receiver signal de-
ulates the receiver’s filtered, slowly vary- clines, the control signal widens the puls-
www.ednmag.com March 29, 2001 | edn 125
design
ideas
10V
Figure 2
5V
0V
V (PWM EMISSION DRIVE)
10V
5V
SEL>>
0V
V (TRIGGER)
10V
5V
0V
V (RECEIVER SIGNAL)
10V
5V
0V
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65
V (CONTROL)
TIME (mSEC)
The PWM emission-drive signal gains width (top panel) in response to a declining receiver signal (third panel down).
12V
es of PWM emission drive to boost the
12V
4 8
R1 sensor’s emission power at the funda-
C1 10k
Figure 3 0.01 mF RESET VCC mental frequency.
7 0.1 mF 2.6k
DISCHARGE 4 8 The process maintains the width of the
555 RESET VCC
2 IC1A DISCHARGE
7 PWM signal with the width fluctuating
TRIGGER
6 555 around a stable point. This point de-
D1 THRESHOLD IC1B 0.01 mF
D1N4148
2
TRIGGER
pends on the signal strength. If a sensor
3 CONTROL 5 6
OUTPUT THRESHOLD works near its upper range limit, the sig-
470k GND
270 pF 1 3 CONTROL 5 CONTROL nal remains weak despite the increased
OUTPUT
TRIGGER GND
1M pulse width, so the stable point shifts to-
0.1 mF
1 ward the maximum pulse width. In this
PWM EMISSION DRIVE
12V
Design Idea, the sensor is sensitive to the
10-kHz fundamental frequency because
1V 11V 12V
10k 12V 100k of a bandpass filter. Therefore, a 50%
3
1 D2 3 8 + 4
V+ PWM duty cycle yields the maximum
IR LED + V+ IC2A
1
100k LM2902/ OUT signal amplitude. On the other hand, if
2 TLC272/ OUT
101/TI 2
2
NS
V2 a sensor operates near its lower range
100 2 11
2 V2 limit, the pulse width converges to a very
D3
PHOTO-
4
100k 100k
narrow width for a medium background
DIODE
12k signal. The time constant R1C1 in Figure
Q1
FMMT3904 RECEIVER SIGNAL
1 also affects the location of the stable
330 pF C10
0.1 mF
point. A longer time constant pushes the
2200 pF
TO CONTROL
CIRCUIT
PWM stable point to a higher duty cycle
5.5V 11V
and vice versa. In this case, the R1C1 time
5 8
+ V+ LLSD103A/CYL constant is half the trigger period (0.05
IC3B 7 0.01 mF
TLC272/ OUT msec). You usually need to perform a test
101/TI
10k
6
2
V2 1M to determine R1, C1, or both. The test en-
4 1M
0.01 mF sures that 50% is the maximum duty
1M
This circuit proves the validity of the PSpice
model for the PWM AGC circuit.

design
ideas
cycle from the modulator. The Trigger plifier first amplifies the 10-kHz pho- emission drive, the sensor constantly
signal must be a narrow, negative pulse tocurrent from the IR photodiode. The tries to reverse any trend of the back-
train. signal then goes through a second-stage ground signal. In varying the distance be-
Figure 3 shows a hardware setup to test amplifier and then undergoes filtering tween the IR LED and the photodiode, an
the PSpice model, using an infrared sen- and peak detection to generate the qua- oscilloscope showed signal behavior as
sor. IC1A and IC1B are 555 timers (the dual si-dc receiver signal. IC2A then inverts the predicted by the model.
TLC556 or LM556). IC1A is a free-run- signal to provide the PWM control. The
ning oscillator that supplies the 10-kHz PWM emission drive drives the IR LED
Trigger pulses for the IC1B PWM circuit. in such a way that the IR photodiode re-
IC1B drives the IR LED and Q1. The 11, ceives medium-radiation intensities. Be- Is this the best Design Idea in this
1, and 5.5V voltages come from filtered cause the receiver’s signal amplitude is issue? Vote at www.ednmag.com/edn
voltage sources. A transimpedance am- proportional to the pulse width of PWM mag/vote.asp.
Two gates expand ASIC’s memory-decoding range

Vinh Hoang, Ericsson Inc, Brea, CA
any electronic circuits imple-
M ment chip-select lines on

an ASIC. From the begin- Figure 1
ning of the design cycle, the chip selects, 00000000
EXISTING MEMORY MAP
00000000
NEW MEMORY MAP
CS0 to CS4, have defined bases on the CS0 FOR PROM 64 MBYTES CS0 FOR PROM 64 MBYTES
memory map (Figure 1). Adding func- 03FFFFFF 03FFFFFF

04000000 04000000
tions to the product requires increasing CS1 FOR DRAM 64 MBYTES CS1 FOR DRAM 64 MBYTES
the DRAM space. Now, you must re- 07FFFFFF 07FFFFFF
08000000 08000000
design the ASIC so the chip select, CS1,
RESERVED 64 MBYTES CS1 FOR DRAM 64 MBYTES
can accommodate the new memory
0BFFFFFF 0BFFFFFF
space of 04000000 to 0BFFFFFF. 0C000000
CS2 TO CS4 CS2 TO CS4
0C000000
The circuit in Figure 2 uses two exter- FOR OTHER FOR OTHER
nal exclusive-OR gates to expand mem- FFFFFFFF DEVICES FFFFFFFF DEVICES
ory-address-decoding space for the CS1

signal from the initial range of 04000000 (a) (b)
to 07FFFFFF to 04000000 to 0BFFFFFF.

When address line A27 is low, exclusive- As you modify a product, you may have to expand the product’s memory space (a) to accommodate
OR gates IC1A and IC1B allow A27 and A26 more DRAM (b).
signals to pass through unchanged. In
this case, the ASIC decodes the address to the existing memory map. However, cesses the address range 08000000 to
range 04000000 to 07FFFFFF, according when address line A27 is high, which ac- 0BFFFFFF, both IC1A and IC1B act as in-
verters. Thus, the circuit inverts lines A26
and A27, so that the ASIC now sees the
ASIC (EXISTING) address range 04000000 to 07FFFFFF in-
74LCX86 CS0 stead of 08000000 to 0BFFFFFF. The
Figure 2 A31 TO A 28 A31 TO A 28
function of the exclusive-OR gates is to
A27 1 CS1
3 map the CS1 selected address range of
2 IC1A A27
CS2
08000000 to 0BFFFFFF to 04000000 to
CS3 07FFFFFF.
4 CS4
IC1B 6 A26
A26
5 A25 A25
A24 A24
Is this the best Design Idea in this

issue? Vote at www.ednmag.com/edn
Two exclusive-OR gates expand the memory-address-decoding space for CS1. mag/vote.asp.

design
ideas
Dual dc-motor-speed controllers navigate robots
Shyam Sunder Tiwari, Robotics Software Pvt Ltd, Gwalior, India
obile robots need simple and
M lightweight dc-motor
speed-control hardware
that can work with low-power batteries.
Figure 1
3 TO 12V 3 TO 12V
Flip-flop type navigation systems allow

only one motor to operate at a time while 1 1
the other motor remains off. Navigation 1000 mF
1000 mF A LEFT-HAND A RIGHT-HAND
direction changes alternatively even DC MOTOR (3 TO 12V) DC MOTOR (3 TO 12V)
when the robot has to navigate through a 2 2
straight path. Line-tracker robots are of
this type.
Zigzag motion lets the robot look at 2N3055 2N3055
the track toward its left and right such LPT PORT D4
1
LPT PORT D0
1
33, W 33, W
that it can correct its path if necessary. 2 Q1 ON HEAT SINK 2 Q2 ON HEAT SINK
You can drive both motors if this type of GROUND ON LPT

motion is undesirable. The circuit in Fig-
ure 1 has two independent motor-speed-
control channels: one for a righthand-
side motor and the other for a left-
hand-side motor. Power to each motor is Independent control channels drive righthand and lefthand dc motors.
pulse-width-modulated using a Basic
computer program (Listing 1). The pow- at the port pin turns on the motor pow- know the position of the robot. The cir-
er-driver circuit uses npn power transis- er, and level zero turns off the motor cuit works for small dc motors operating
tors, Q1 and Q2. These transistors have power. If both D0 and D4 are set to one, from a power source in the range of 3 to
high-power-kicking ability that the ro- then both motors operate together. Re- 12V.
botics require. The PC’s parallel port diverse control does not occur. Thus, only
rectly controls the base of these transis- one motor needs to operate to turn the
tors. LPT port data bit D0 operates a robot backward until rotation is com- Is this the best Design Idea in this
righthand-side motor, and data bit D4 plete.You can add feedback sensors to the issue? Vote at www.ednmag.com/edn
operates a lefthand-side motor. Level one hardware. These sensors are necessary to mag/vote.asp.
LISTING 1—MOTOR-SPEED CONTROL

design
ideas
SDRAM interface slashes pin count
Tim Hellman, M&M Consulting, Concord, MA
any designs need deep buffering
M but don’t require ultra-

high-memory bandwidth.
Examples include image and audio pro-
Figure 1
VCC
cessing, as well as some deep-FIFO ap- RAS CKE

plications. These designs often use a sin- CAS CS
gle 38 SDRAM device that connects to SDRAM
WE (SUCH AS MICRON
an FPGA or ASIC. This approach solves
DQM MT48LC8M8A2)
the buffering problem but also burns a lot PLD/ASIC
BANK[1:0]
of valuable pins, which can be as many
ADDR[11:8]
as 27 for a single SDRAM device. The de-
ADDR[7:0]
sign in Figure 1 takes advantage of the
burst counter inside the SDRAM to re- DQ[7:0]
CLOCK
duce this pin count to 18 by multiplexing
the lower eight address lines with the
data. The efficiency loss is low; the design
requires only one extra clock during the
write burst. Figure 1 uses an 8Mx8, 125- To reduce the interface-pin count to 18, you can take advantage of the burst counter inside the
MHz SDRAM, but this technique works SDRAM by multiplexing the lower address and data lines.
with any SDRAM.
The read- and write-cycle timing dia- sume a 50-MHz system clock, a read la- the cycle (when the row and column ad-
grams reveal the secret (Figure 2). The tency of 2, and a full-page burst. During dresses are presented), so there’s no prob-
figure shows a burst of 4, but any pow- the read cycle (Figure 2a), the data bus lem with using the data bus to carry ad-
er-of-2 burst works. These diagrams as- is inactive during the initial portion of dress data. A precharge command ends
the burst and prepares the RAM for the
next access.
Figure 2 For the write cycle, however, some
READ CYCLE
COMMAND PRE- trickery is necessary (Figure 2b). Nor-
ACTIVE READ NOP NOP
(RAS, CAS, WE) CHARGE mally, the first byte of write data is pre-
SD_BANK sented to the SDRAM with the Write
BANK (ROW 13:12)
command, along with the starting col-
SD_ADDR [11:8]
COLUMN ADDRESS
umn address for that burst. By asserting
the DQM (data-mask) signal, the
SD_DATA
DATA 0 DATA 1 DATA 2 DATA 3 SDRAM ignores the data lines during this
phase, thus allowing them to be used for
ROW COLUMN
SD_DQM ADDRESS ADDRESS the column address.
Note that the DQM signal does not
(a)
WRITE CYCLE prevent the internal column address from
PRE- incrementing, however. Thus, the write-
COMMAND ACTIVE WRITE NOP CHARGE NOP
(RAS, CAS, WE) column address presented with the Write
SD_BANK BANK (ROW 13:12)
command must be one less than the de-
sired burst starting address. For FIFO de-
SD_ADDR_HI COLUMN ADDRESS signs, this requirement is trivial because
you can initialize the write-address col-
SD_DATA DATA 0 DATA 1 DATA 2 DATA 3 During the read cycle (a), the data bus is inac-
ROW COLUMN tive during the initial portion of the cycle so the
ADDRESS ADDRESS
data bus can carry address data. During the
SD_DQM
write cycle (b), asserting the DQM command
causes the SDRAM to ignore the data line dur-
DQM HERE PREVENTS ADDRESS
(b) FROM BEING WRITTEN AS DATA. ing this phase, which allows the data lines to
carry the column address.

design
ideas
umn counter to 21 rather than 0. The this design. This controller uses a simple You can extend this idea to 316
column-address counter in the SDRAM eight-state finite-state machine to gener- SDRAMs and to multiplex a few more of
wraps around at the end of the column, ate the SDRAM control signals and uses the address lines while getting a boost in
so this approach works even at the be- a pair of row/column counters to keep memory bandwidth. If you do extend the
ginning of a column. track of the FIFO put/get pointers. The idea, be careful with SDRAM line A10 be-
You can download a simplified version special initialization and incrementing of cause this line has special meaning dur-
of a FIFO controller that uses this tech- the write row and column pointers sat- ing some SDRAM commands. You can
nique, described in the Verilog language, isfies the requirement that the write col- also use this technique with double-data-
from EDN’s web site, www.ednmag.com. umn start off one behind the desired rate SDRAMs.
Click on “Search Databases” and then en- write address. The code occupies 35% of
ter the Software Center to download the a small Xilinx SpartanXL-S10 device, and
file for Design Idea #2659. The listing runs at 50 MHz. For the sake of exam-
omits some of the details, such as ple, all of the outputs are combinatorial, Is this the best Design Idea in this
SDRAM refresh/init cycles, and FIFO but a true high-speed design should use issue? Vote at www.ednmag.com/edn
flags, to highlight the portions relevant to registered I/O. mag/vote.asp.
Minimize communication time between small mCs

Abel Raynus, Armatron International Inc, Melrose, MA
hen designing a multicontroller
W system, it is convenient to
organize the communica-
tion between mCs via one wire line. Un-
Figure 1
TRANSMITTER
START LOG0 LOG1
RECEIVER
fortunately, low-end mCs have no serial- LSB MSB
MC68HC705KJ1
interface capabilities like their more
expensive counterparts. Low-end mCs
have no SCI (serial-communication-in-
pA0 pA0
terface, SPI (serial-peripheral interface),
or SIOP (simple serial-I/O port). Thus,
a designer needs to use software tools to
THE 8-BIT WORD "11110001"
create a serial interface (Reference 1).
One approach, which uses the external
interrupt for message receiving, results in
message duration of 13.5 to 21.5 msec.
For many applications, this time is unim-
portant. However, some applications may
require you to minimize the message The data word from the transmitting mC connects to Pin pA0 of the receiving mC, which you pro-
time as much as possible, especially when gram as an external-interrupt input.
both the timer and external interrupts are
in use. The mC cannot simultaneously ex- You cannot minimize the message time gram as an external-interrupt input.
ecute these interrupt requests, and the ex- by just changing some number in the When an external interrupt occurs, the
ternal interrupt has a priority. Hence, a program. You must instead use a time- mC can process this interrupt only when
message and, therefore, the external-in- measurement concept that leads to mod- the current instruction execution is com-
terrupt-service routine that are too long ification of the whole program (Figure plete. This waiting time is always unpre-
can affect the program-process timing re- 1). The data word from one mC to an- dictable and can range from zero to the
lated to timer interrupt. other comes to Pin pA0, which you pro- time of the longest instruction in the pro-

design
ideas
gram (Figure 2). So, this time differs for
each user program. Nevertheless,
if a program has no exotic in- Figure 2
structions, such as SWI (software inter- MAXIMUM DETECTED PULSE WIDTH
rupt) and MUL (multiplication), then MINIMUM DETECTED PULSE WIDTH

the longest instruction can execute in six EXTERNAL-
INTERRUPT MEASURED PULSE WIDTH
cycles, which takes 3 msec for an oscilla- PULSE
tion frequency of 4 MHz (Reference 2).
EXTERNAL-
Saving the contents of the CPU registers INTERRUPT
on the stack and loading the program PROCESS
counter with an external-interrupt vec-

tor address take nine more cycles.
Only at this point can the interrupt- TIME
service routine begin the pulse-width 3 4.5 6
23.5 mSEC
measurement. (You can download the EXTERNAL- mSEC mSEC mSEC
INTERRUPT 9.5 mSEC
message receiver and transmitter pro- PULSE ARRIVES 19 CYCLES
END OF EXTERNAL-INTERRUPT-
grams EDN’s Web site, www. SERVICE-ROUTINE EXECUTION
EXTERNAL-INTERRUPT
ednmag.com. Click on “Search Databas- PROCESS BEGINS
es” and then enter the Software Center
to download the file for Design Idea EXTERNAL-INTERRUPT-
END-OF-SERVICE-ROUTINE PART INVOLVED
SERVICE-ROUTINE EXECUTION
#2682.) After executing three instruc- BEGINS IN THE PULSE-WIDTH MEASUREMENT
tions (lines 36 to 38 of the message-re-
ceiver program), this process completes
in 12 cycles, or 6 msec. Hence, the width
of an external interrupt pulse cannot be The mC can service an external interrupt only when it finishes executing the current instruction,
less than 10.5 msec. and the waiting time can range from zero to the time of the longest instruction in the program.
From another side, it is more conven-
ient for the transmitter part of the pro- culated and put into register pW is one pause between pulses (lines 48 to 52 of
gram to use only one subroutine, called timer count (clk). So the widths of the message-receiver program). With all
Pulse, to generate all the pulses with dif- LOG0, START, and LOG1 pulses are 4, 9, the above chosen values, the longest mes-
ferent widths by changing the number of and 14 clk, respectively. Remember that sage, $ffHEX. lasts 0.84 msec.
the loop repetitions (X) only. The loop the moment of beginning and external The design in Figure 1 uses a one-
duration is 5 msec (lines 43 to 46 of the interrupt processing could be at any time time-programmable Motorola MC68-
message-receiver program), so the gen- in the range of 3 msec, or 2 clk, which HC705JK1 (Motorola mC, but this idea
erated pulse is equal to 5X12.5 msec. You causes the same variations in the meas- is applicable to any mC. You would need
can choose the pulse-width values ac- ured pulse width. To overcome this prob- to recalculate the timed values according
cording to your project objectives. In this lem, you select the proper pulse width to the mC’s technical data.
case, for LOG0 X52, width512.5 msec; within a fork, which should greater than
for START X54, width522.5 msec; and or equal to 2 clk. In this case, the fork is References
for LOG1 X56, width532.5 msec. How- equal to 4 clk. Finally, you use the fol- 1. Raynus, Abel, “Single wire connects
ever, as you can see from Figure 2, the lowing pulse selection logic: 3 clk, microcontrollers,” EDN, Oct 22, 1998, pg
pulses that the receiver measures are LOG0,7 clk, 8 clk,START,12 clk, and 102.
shorter by 4.5 msec than transmitted 13 clk,LOG1,17 clk. 2. MC68HC705KJ1/DTechnical Data,
pulses. So, the measured pulses have The minimal interval between the two Revision 1.0, Motorola.
widths of 8, 18, and 28 msec. The mC’s in- consecutive external-interrupt pulses
ternal free-running timer/counter is the should be more than the number of in-
clock. You can at any time read the value terrupt-service-routine cycles plus 19 cy-
of the first eight stages of this counter cles (Reference 2). The service routine’s
from the (TCR) time-counter register. longest path occurs when the program is
One time count is equal to four machine processing the widest incoming pulse
cycles, or 2 msec. Note that the pulse- (LOG1), which takes 47 cycles. Thus, the
width measurement must be complete interval between pulses should be more
before the TCR overflow that happens than 47119566 cycles, or 33 msec. Is this the best Design Idea in this
every 23256, or 512 msec. In the pro- Choosing the number of time-loop rep- issue? Vote at www.ednmag.com/edn
gram, the unit of pulse-width value cal- etitions of X510 results in a 52.5-msec mag/vote.asp.

design
ideas
Single FET controls LED array
Len Sherman, Maxim Integrated Products, Sunnyvale, CA
hite-LED backlights are gain-
W
Li-ION L1
ing acceptance because they offer CELL
2.7 TO 10 mH, D1
higher reliability and simpler drive 5.5V 1A MBR0530L
circuitry than backlights based on CCFL C1 FDN337N
(cold-cathode-fluorescent- 10 mF Q1
Figure 1 C2
lamp) and EL (electrolumines- 10 10 mF KEYPAD
1 V EXT LEDs
cent) technology. As a result, white-LED CC
backlights are increasingly common in 9

CS
PDAs (personal digital assistants), cell NDS7002A
Q2
phones, digital cameras, and other MAX1698
portable devices. A design in which the 3 8
REF PGND
display requires backlighting for extend- BACKLIGHT
BRIGHTNESS
ed periods needs an efficient circuit that LEDs
drives the LEDs with a controlled current R1 4 7
500k ADJ AGND
and eliminates the wasted power associ-
ated with current-limiting resistors. Fig-
6
ure 1 shows a switch-mode boost design FB
ON
that regulates current instead of voltage. 2 SHDN OFF
OFF BACKLIGHT
Because all the LEDs are connected in se- R3 ON OFF
C R
ries, they all receive the same current 15 4 2
100k
10 nF
without the need for ballasting resistors.
Identical currents help achieve uniform
intensity. And, because the output cur- When this circuit turns off the backlight LEDs, the keypad LEDs remain on with no change in inten-
rent is low (20 mA in this case), the out- sity.
put-filter capacitance, C2, can be smaller
than for a load consisting of parallel- The circuit’s 90% conversion efficien- their current. The remaining LEDs (for
connected LEDs. cy offers a distinct power-saving advan- the keypad, for example) remain on, and
tage over resistor-limited and linearly their intensity remains constant because
regulated designs. It might appear that a IC1 regulates their current, by sensing the
Single FET controls LED array ..................131 series-LED connection is unsuitable for voltage across R2 (300 mV at full bright-
Circuit protects battery applications in which some (but not all) ness). When the circuit turns the LEDs on
from overdischarge ....................................132 LEDs must be off. A cell phone, for ex- and off, the R2-C4 network at the gate of
Two diodes change
ample, sometimes needs that capability Q1 slows the load changes sufficiently to
demagnetization-signal polarity..............134
for occasions when the display is off but prevent transients in the LED drive cur-
the keypad remains lit. Or, a PDA might rent. Other features include adjustable
Simple scheme keeps need to play a sound file while maintain- intensity via the ADJ pin and full shut-
current drain constant ................................138 ing illumination in the buttons but not down via the SHDN pin.
RS-232/485 converter the display. In the circuit of Figure 1,
has automatic flow control........................140 switching off individual LEDs or groups
of LEDs is not a problem, even with se-
Circuit provides accurate
ries drive. Applying a logic-high level to Is this the best Design Idea in this
RTD measurements ....................................142
the gate of a simple MOSFET switch, Q2, issue? Vote at www.ednmag.com/edn
turns off a subset of LEDs by shunting mag/vote.asp.
www.ednmag.com April 12, 2001 | edn 131
design
ideas
Circuit protects battery from overdischarge

Martin Wuzik, Implex AG Hearing Technology, Ismaning, Germany
ll electronic circuits powered
A by a battery discharge the

battery. In some applica-
tions, it is undesirable to overdischarge
Figure 1
VBAT
Q1
LP0701 VSYS
MAIN CIRCUIT
the battery, because it could irreversibly

reduce the battery’s capacity and the
10M
number of discharge/charge cycles. The 10M
circuit in Figure 1 protects a single IC1
R3111Q131C-TR
NiMH (nickel-metal-hydride) cell by dis- Q2 Q3 +
2 V 1 10 mF
connecting the load from the battery. Fig- DD OUT
ure 2 shows the output voltage, VSYS, ver- TN2501 TN2501
GND
sus the input voltage,VBAT. For this NiMH
4
battery, the switching points are 1.1 and
1.3V. If the battery discharges and VBAT
drops below 1.1V, Q1 switches off ,and IC2
the node Main Circuit disconnects from R3111Q111A-TR
2 1
the battery. In that case, the battery’s only VDD OUT
load is the pair of voltage detectors IC1
1.35V
and IC2 from Ricoh (www.ricoh- GND
NiMH
usa.com). The load current of one detec- BATTERY 4
tor is typically 800 nA, so the battery

drain is 1.6 mA. The user must now
charge the battery. Once the battery
charges and the voltage reaches 1.3V, the A simple circuit prevents excessive discharge of NiMH cells.
load reconnects to the battery and re-
mains connected as long as VBAT stays 1.8
above 1.1V. 1.6

DOWN
IC1 is a voltage detector with
Figure 2 1.4
a 1.3V setpoint and a push-pull
output. IC2 has a 1.1V setpoint. An im- 1.2
portant difference between the two de- 1
VSYS
tectors is that IC2 has an open-drain out- UP
put. If the battery voltage drops but 0.8
remains within the 1.1 to 1.3V range, 0.6

IC1’s output is low, and Q2 switches off.
0.4
Q3 switches on because IC2’s output is
still in the high-impedance state. If VBAT 0.2
drops below 1.1V, IC2’s output switches 0
low, Q3 turns off, and, as a result, Q1 also 0 0.5 1 1.5 2
switches off. As soon as VBAT drops be- VBAT
low 1.1V, the load disconnects from the The load disconnects from the battery when the voltage drops below 1.1V and reconnects when the
battery. The load reconnects to the bat- battery charges above 1.3V.
tery only when the battery charges to a
voltage higher than 1.3V. At voltages of are low-threshold MOSFETs from Su- higher voltages of Li-ion batteries by se-
1.1 to 1.3V, IC2 cannot switch on Q3 be- pertex (www.supertex.com). The circuit lecting the voltage detectors.
cause the IC’s output is an open-drain uses no trimming resistors. You can se-
type and VSYS is low. IC1’s output must as- lect IC1 and IC2 off the shelf with 100- Is this the best Design Idea in this
sume a high state to switch on Q2 and to mV steps and 2% switching-point accu- issue? Vote at www.ednmag.com/edn
finally switch on Q1 on. The transistors racy. You can adapt the circuit for the mag/vote.asp.
132 edn | April 12, 2001 www.ednmag.com

design
ideas
Two diodes change demagnetization-signal polarity
ower-supply designers usually in CCM forces the diode to brutally stop and starts to ring at a high frequency be-
P like flyback converters to operate in

DCM (discontinuous-conduction
mode) rather than in CCM (continuous-
conducting. Also in DCM, valley switch-
ing ensures minimum switching losses
that COSS and all the parasitic capaci-
cause of the leakage-inductance presence.
During this time, the primary current
transfers to the secondary, and a reflect-
conduction mode). In DCM, the flyback tances bring. ed level of N3(VOUT1VF) appears on the
converter is a first-order system at low In valley switching, or QR (quasireso- MOSFET drain, where N is the second-
frequencies, which eases the feedback- nant) operation, the curve of the drain- ary-to-primary turns ratio, VOUT is the
loop compensation. You can use a low- source voltage, VDS, of a typical flyback output voltage, and VF is the secondary-
cost secondary rectifier, thanks to soft converter, shows that when the power diode forward drop. As soon as the pri-
blocking conditions. In DCM, IP goes to switch closes, you observe a low level due mary current has fallen to zero in DCM
zero, and the diode stops conducting, to the RDS(ON)3IP product (Figure 1a). operation, the transformer core is fully
whereas the power-switch turn-on event At the switch opening, VDS rises quickly demagnetized (Figure 1b). The drain
Figure 1
(a) (b)
A typical drain-source waveform of a flyback converter shows high-frequency ringing (a). In DCM operation, the primary current ramps up and down
to zero (b).
Figure 2 VOUT 20.0

VAUX
10.0
0
210.0
GND
VIN 220.0
20.0
10.0
0
210.0
220.0
(a) (b)
An auxiliary winding (a) lets you observe the flux image in the transformer’s core for both flyback and forward operation (b).

design
ideas
HV VOUT HV VOUT
Figure 3
NP NP
1N4148 DAUX
56 NS NS
VAUX VAUX
RVALLEY NA RVALLEY NAUX

10 mF
GND
221N4148 221N4148
VDEM VDEM
(a) (b)
A simple component arrangement allows forward-mode detection with a flyback-like PWM controller (a) or flyback-mode detection with a forward-
like controller (b).
branch starts to ring but at a lower fre-

700
quency than in Figure 1a because the pri-
mary inductance, LP, is now in-
Figure 4
volved. 500
This natural oscillation exhibits the
following frequency value, where CLUMP
represents all of the circuit’s parasitic ca- 300
pacitances, such as COSS and the stray ca-
pacitance from the transformer.
1 100
FRING = .
2 π L P • C LUMP
100
As with any sinusoidal signal, there are
peaks and valleys. When you restart the
532 mSEC 536 mSEC 540 mSEC 544 mSEC 548 mSEC
switch in the valley, all the parasitic ca-
pacitance values are at their lowest pos- When you properly adjust the time constant using RVALLEY, the switch restarts in the middle of the
sible levels. Also, the capacitive losses, valley.
which are equal to 1/23CLUMP3
VDS23FSW, are small because the MOS- in flyback operation, as the power wind- When the battery you charge is close to
FET is no longer the seat of turn-on loss- ing, or in forward operation. The ob- 0V, the auxiliary windings are also near-
es, which removes the usual turn-on par- served signals look the same but have dif- ly 0V because both windings are coupled
asitics. That is the secret of QR operation. ferent polarity (Figure 2b). Note that in flyback mode. By operating in forward
You can easily observe the core flux both signals center about ground. The mode, whatever happens on the second-
through an auxiliary winding (Figure problem lies in the fact that most PWM ary side is invisible, and the voltage is al-
2a). Thanks to the coupling between the controllers accept only the flyback polar- ways there to supply the controller. How-
windings, the auxiliary section delivers a ity. Typical examples include the MC- ever, the demagnetization signal now has
voltage image of the core’s flux through 33364 and MC44608 (www.onsemi. the wrong polarity, and the controller
the following formula: com). In battery-charger applications, doesn’t restart at the core’s reset event.
dφ you usually wire the auxiliary winding— Figure 3a shows a way around this
VAUX = N • . the one that self-supplies the controller problem. You still wire the winding for
dt
and gives the demagnetization signal— forward operation, but you add two ex-
Now, you can wire the winding either in forward mode. The reason is simple: tra diodes in series with the winding. At

design
ideas
the switch closing, you apply N3VHV, iliary winding in flyback mode (Figure MC33364. A small offset from the inter-
where N is the ratio between the auxil- 3b). The problem and the cure are simi- nal reference to the demagnetization pin
iary winding, NA, and the primary wind- lar. brought by a 150-kV resistor and a typ-
ing, NP. You clamp VDEM to 20.6V, and When you properly select RVALLEY, this ical RVALLEY of 10 kV have provided good
the current circulates through RVALLEY. At resistance naturally combines with sense- circuit operation.
the switch opening, the voltage reverses pin internal capacitance to add switch
and becomes positive but clamped to delay right in the middle of the wave
0.6V on VDEM. When this level collapses, (Figure 4).
the PWM controller reactivates the pow- Some controllers exhibit different de-
er switch. magnetization threshold levels. The
You can implement this same type of MC33364 starts at around 1V, and the
circuit for PWM controllers that need a MC44608 toggles at 65 mV. Because of Is this the best Design Idea in this
forward demagnetization signal but for the diodes, you clamp VDEM between issue? Vote at www.ednmag.com/edn
which you would like to operate the aux- 6600 mV, which could not trigger the mag/vote.asp.
Simple scheme keeps current drain constant

Peter Güttler, APS Software Engineering GmbH, Cologne, Germany
t is sometimes advantageous to
I keep the overall current con-

sumption of an electronic de-
vice constant. A large, seven-segment dis-
Figure 1
ISUP I3
play, for example, draws nearly zero R1
12 TO IN OUT
current when no segment is on to hun- 24V
50 IC2
dreds of milliamps when fully lit. This 7805
heavily varying current can cause EMI ILOAD
GND
problems when a device receives its pow-
1 mF
er through long cables from a remote C3
I1
power supply. The low-parts-count cir-
+ C2 + R2
cuit in Figure 1 keeps current consump- C1 C4 I2 I4
10 mF
10 mF 0.1 mF
tion constant. IC2 is an ordinary three- GND
terminal regulator that supplies 5V to the IC1
load, R2. IC2 draws a total current 7905
I35ILOAD+I4. (I4 is approximately 8 mA, IN OUT
the quiescent current of IC2). The nega-
tive three-terminal voltage regulator, IC1,
maintains 5V across R1. The current
through R1 is I2RI3. So, I255V/R1SI3, and
total supply current ISUPtI1R5V/R1. I1 is This circuit maintains a constant supply current of approximately 102 mA.
approximately 2 mA, the quiescent cur-
rent of IC1. If the load draws more cur- mA. C1 and C4 are input-filter capacitors, ence voltage.) If your application cannot
rent, IC1 reduces I2 and vice versa. C2 improves ripple rejection, and C3 pro- tolerate the 5V drop across R1, try using
This regulation works well as long as vides stability. Note that R1 dissipates an LM337 with a 1.25V reference voltage
I3 is smaller than 5V/R1. If the load draws (5V)2/R1 and must have an adequate for IC1.
more current, IC1 stops regulating and power rating. IC1 and IC2 may require
the voltage drop across R1 rises above 5V. heat-sinking. The minimum supply volt- Is this the best Design Idea in this
This example sets R1 at 50V, setting the age for this circuit is 12V. (The minimum issue? Vote at www.ednmag.com/edn
supply current, ISUP, to approximately 102 input voltage for IC257V1IC1’s refer- mag/vote.asp.

design
ideas
RS-232/485 converter has automatic flow control
John Howard, Kw Aware, Ventura, CA
S-485 communications can pro-
R vide longer range and better

noise immunity than RS-
232, as well as multidrop capability. Be-
Figure 1 VCC
0.1 mF 1
C1+
IC1
MAX232
VCC 16
VCC
cause it does not have separate transmit 2

V+ 0.1 mF
and receive lines, RS-485 requires flow 0.1 mF
GND 15
3
control. RS-232/485 converters often use C12 T1OUT 14
4
one of the RS-232 handshaking lines to C2+ R1IN 13
0.1 mF
control direction, but several communi- 5 C
22 R1OUT 12
RS-232
cations-software packages do not sup- DB-9 CONNECTOR 6 V2 T1IN 11 IC2
MAX483 VCC
port flow control. The circuit in Figure 2 7 T 10
Rx 2OUT T2IN
1 is an RS-232/485 converter that uses the 3 8
1 8
Tx R2OUT 9 RO
transmitted signal itself to control the R2IN VCC
5 2 7
flow. The circuit uses MAX232 and GND RE A
3 6 R2
MAX483 interface circuits, IC1 and IC2 0.1 mF DE B
120 RS-485
GND 5
from Maxim Integrated Products (www. 4
DI
VCC
maxim-ic.com) to convert between the
ICs’ respective signal levels and logic lev- TRIGGER
LINE 100k IC3 VCC
els. Because both ICs invert the signal, the LM555
circuit preserves the original sense of the
1
signal. The MAX483 is normally in the GND VCC 8 R1
receiving mode. When transmission be- VCC
2
TR DISCH
7
gins, the signal triggers IC3, the LM555 3
OUT THRESH
6
timer, which in turn toggles IC2’s DE and 4
RST 5
RE lines, putting the chip into the trans- CTL C1
mitting mode. 0.1 mF
10k Q1
Q1, the 2N3906, fully discharges C1 2N3906
each time the trigger line goes low,
restarting the timing cycle. The values of
R1 and C1 determine how long IC3 main-
tains the transmitting mode after trans-
mission ends. This interval should be Automatic flow control makes RS-232/485 conversion easy.
long enough such that the converter
doesn’t switch directions while sending so long that the converter misses received is in farads. The flow control responds
characters containing long sequences of characters. The interval T in seconds is within a few microseconds after trans-
zeros. On the other hand, it shouldn’t be T51/R1C1, where R1 is in ohms, and C1 mission commences, so the converter
does not miss any bits at low
TRANSMITTED DATA
(LOGIC SIDE OF INTERFACE CHIPS) and medium data rates. The
application for this circuit
operates at 14,400 bps. Fig-
TIMED DELAY AFTER
DELAY IN TOGGLING TRANSMISSION ENDS ure 2 shows the timing of the
Figure 2 FLOW CONTROL (SET BY C1 AND R1) serial and flow-control lines.
(SEVERAL MICROSECONDS)
FLOW-CONTROL LINE The entire circuit can fit into
(LOW=RECEIVE, HIGH=TRANSMIT) a DB-25 (or even a DB-9)
back shell.
RECEIVED DATA
(LOGIC SIDE OF INTERFACE CHIPS)
Is this the best Design Idea
in this issue? Vote at
www.ednmag .com/edn
R1 and C1 determine how long the transmitting mode lasts. mag/vote.asp.

design
ideas
Circuit provides accurate RTD measurements
Tito Smailagich, ENIC, Belgrade, Yugoslavia
he circuit in Figure 1 is an efficient TABLE 1—RESISTANCE VERSUS TEMPERATURE FOR PT100 RTD ELEMENT
T measuring circuit for PT100 RTD el-

ements. IC1 provides an accurate
2.5V output and, together with P1 and R1,
8C
120
119
V
92.16
92.55
8C
6
7
V
102.34
102.73
8C
32
33
V
112.45
112.83
8C
58
59
V
122.47
122.86
8C
84
85
V
132.42
132.8
also provides a stable 1-mA current to the 118 92.95 8 103.12 34 113.22 60 123.24 86 133.18
RTD element. The output of IC2 is 117 93.34 9 103.51 35 113.61 61 123.63 87 133.57
20.1V. P2 provides a zero adjustment (at 116 93.73 10 103.9 36 114 62 124.01 88 133.95
08C) for IC3, an amplifier with a gain of 115 94.12 11 104.29 37 114.38 63 124.39 89 134.33
25. P3 provides a gain adjustment. If, for 114 94.52 12 104.68 38 114.77 64 124.78 90 134.71
example, you replace the RTD element by 113 94.91 13 105.07 39 115.15 65 125.16 91 135.09
a fixed resistance of 124.78V (the RTD’s 112 95.3 14 105.46 40 115.54 66 125.54 92 135.47
resistance in Table 1 at 648C), you would 111 95.69 15 105.85 41 115.93 67 125.93 93 135.85
trim P3 to obtain 0.64V output. Tolerance 110 96.09 16 106.24 42 116.31 68 126.31 94 136.23
values for Class A and B elements are 19 96.48 17 106.63 43 116.7 69 126.69 95 136.61
60.35 and 60.88C, respectively. You can 18 96.87 18 107.02 44 117.08 70 127.08 96 136.99
use the standard values from Table 1 or, 17 97.26 19 107.4 45 117.47 71 127.46 97 137.37
if you need more accuracy, you can cali- 16 97.65 20 107.79 46 117.86 72 127.84 98 137.75
brate the PT100 element in a controlled- 15 98.04 21 108.18 47 118.24 73 128.22 99 138.13
temperature environment. 14 98.44 22 108.57 48 118.63 74 128.61 100 138.51
13 98.83 23 108.96 49 119.01 75 128.99 101 138.88
12 99.22 24 109.35 50 119.4 76 129.37 102 139.26
11 99.61 25 109.73 51 119.78 77 129.75 103 139.64
0 100 26 110.12 52 120.17 78 130.13 104 140.02
1 100.39 27 110.51 53 120.55 79 130.52 105 140.4
Is this the best Design Idea in this 2 100.78 28 110.9 54 120.94 80 130.9 106 140.78
issue? Vote at www.ednmag.com/edn 3 101.17 29 111.29 55 121.32 81 131.28 107 141.16
mag/vote.asp. 4 101.56 30 111.67 56 121.71 82 131.66 108 141.54
5 101.95 31 112.06 57 122.09 83 132.04 109 141.91
110 142.29
RTD 649k
Figure 1 GAIN ADJUST
PT100
5V P1
5V
VCC
VCC
5V
7
VCC 3
1-mA ADJUST 7 +
3 6
+ 27k OUTPUT
6 2
2 2.5V 500 R1 2 1 IC3
IC1 OUT 1 IC2 4 LTC1050
1 IN MC1403 P1 2.21k LTC1050
4
GND VEE
0.1 mF 0.1 mF VEE 15V
15V
3
10.2k
ZERO ADJUST
P2 0.1V 27k
1k
274
This circuit provides accurate temperature measurements using a PT100 RTD element.

design
ideas
Delay line aids in one-shot simulations
Christophe Basso, On Semiconductor, Toulouse, France
any designers use small pulse small pulse generator. The operating 2 shows the signals associated with the
M generators to delay signals, open

timing windows, drive sam-
ple/hold circuits, and other functions.
principle of the circuit lies in applying
two “1” levels to the AND-gate input be-
fore the delay line switches high. Figure
circuit in Figure 1. Listing 1 shows
netlists for Intusoft’s IsSpice4 and Ca-
dence’s PSpice.
Though the hardware implementation of
these generators does not pose any prob-
lems, the lack of dedicated circuitry
sometimes puzzles the Spice simulation INPUT SIGNAL
of the system. A common approach to
this problem is to implement a time con-
stant involving a resistor, a capacitor, and
a comparator. Unfortunately, each time DELAY-LINE OUTPUT
you need a time constant, you must re-
calculate the resistor value, the capacitor
value, or both. Despite the fact that inline
equations can do this job for you, delay INVERTER OUTPUT
lines can often offer a smarter solution.
Figure 1 shows the implementation of a
ONE-SHOT OUTPUT
X5
X6
UTD X8 AND2
TD41m INV
Out
In utd
2 3
21 mSEC 25 mSEC 29 mSEC 33 mSEC 37 mSEC
A one-shot multivibra- This plot shows timing details for Figure 1’s Spice model.
Figure 1 tor (shown with Spice Figure 2
nomenclature) makes a simple short-pulse gen-
X1 X3
erator. A1 SMALLPULSE X2 SMALLPULSE
PWMGEN VPULSE DELAY=70 nSEC INV DELAY=20 nSEC SMP
PWM
1 2 3
SMALLPULSE SMALLPULSE
VTRIGGER
Delay line aids
in one-shot simulations..............................129
X4
Sine-wave generator outputs MUL X5
PSW1
precise periods ............................................132 A
K*A*B VSAMPLED
V1 6 4
High-voltage current-feedback B
` 5 CSH RDR
amplifier is speedy ......................................136 SINE + 10 pF 1M
MODULATION
AC-power monitor SMP
uses remote sensing ..................................138
This PWM application is a sample/hold circuit in Spice-simulation nomen-
Figure 3 clature.
www.ednmag.com April 26, 2001 | edn 129

design
ideas
Figure 3 shows a typical application
circuit for the one-shot multivibrators.
You can use IsSpice4 or PSpice to simu-
late this sample/hold circuit. Figure 4
shows the waveforms associated with the 70 nSEC
circuit in Figure 3. A PWM signal (top

waveform) generates a kind of arbitrary
staircase signal. The multiplier, X4, sinu- S/H TRIGGER
soidally modulates the PWM signal. The
circuit cascades two small pulse genera-
tors (SMALLPULSE). One creates a de-
lay signal to sample at a given time (X1,
70 nsec); the other calibrates the width
MODULATED SIGNAL
(X3, 20 nsec) of the sampling signal (sec-
ond waveform). The third waveform in
Figure 4 shows the sinusoidally modu-
lated signal; the fourth waveform is the
sampled signal. You can download the Is-
Spice4 and PSpice listings for three one-
S/H OUTPUT
shot types from EDN’s Web site, www.
ednmag.com. Click on “Search Databas-
es” and then enter the Software Center to
download the file for Design Idea #2680. 100 nSEC 300 nSEC 500 nSEC 700 nSEC 900 nSEC

Figure 4
issue? Vote at www.ednmag.com/edn These timing signals illustrate the operation of Figure 3’s circuit.
mag/vote.asp.
LISTING 1—NETLIST FOR MONOSTABLE SHORT-PULSE GENERATOR

design
ideas
Sine-wave generator outputs precise periods

ectangular pulse generators, cise number of periods. The signal
R even at high frequencies,

are easy to design. How-
ever, the design becomes more diffi-
F i g u r e 1
END
COUNT
ENABLE SIGNAL
GENERATOR
SIGNAL
OUTPUT
has to start and stop exactly at 0V.
The scheme in Figure 1 can produce
one to 15 periods of a 20-MHz sinu-
cult if you need a signal that contains TRIGGER TRIGGER
INPUT DOWN INPUT SYNC
a precise number of periods with a si- COUNTER COMPARATOR A signal generator, down counter, and
nusoidal shape. Although it is easy to comparator can produce an output signal
produce a good sine wave, the diffi- N
that contains a precise number of sine-
culty is producing a signal with a pre- (NUMBER OF PULSES) wave periods.
5V
14
Figure 2 VDD 2
1 100 nF
A B
13 100 nF 3.3k
C 1 nF 10 nF 47k
IC4A VSS 1 5V
5V S
7 1 10 3 4 SIGNAL
100 nF 25V OUT
4 REF IIN A0 A1 19
3 OUT
A B 5 COSC
7 R2 5 5V
R3 C1
2 3
+ 6 10
G C
22 pF V`
17
1k IC4B 6 IC1 100 nF
2 GND
2 MAX038 9
LF356N 8 7 GND1
4 A B 9 DADJ
20 100 nF
6 C 8 V1
3.74k FADJ
IC4C
25V PDO PDI SYNC DGND DV` GND2 GND3 GND4 25V
12 13 14 15 16 2 11 18
100 nF 11 A B
100 nF 10
12 C 100 nF
100
IC4D
15V
5V
Q1 R1 10
E VP0106 10
8
IC3C 9
100 nF
C2 5V
13
11
10 nF
IC3D 12 F
100 nF
5V
330 4
6
5 IC3B
25V
100 nF
100 nF 7
2
1 3
A VCC IC3A 1 C D
5V
A 2 12 4 16
TRIGGER IC5A
B CTEN
IN 10 nF 74LS123 MIN-MAX
14 13 B 11 100 nF
C
15 Q LOAD IC2
1k R/C 74AC191 14
V+ 3 CLK
CLR
D0 D1 D2 D3 UP-DN
8 3 2 6 7 8 5 5V
S1
8 ON 1 470
1
7 2 470
2
6 3 470
3
5 4 470
4
IC1 contains the generator and comparator. The sync signal at point F drives the counter, IC2. The setting of S1 determines the end of count and thus
the number of periods, N, at the output.

design
ideas
soidal wave. The scheme has two main
characteristics: The positive edge
of a 5V signal triggers the input, Figure 3
and the output is one to 15 periods of a
20-MHz signal, adjustable to within
610%.
Initially, the trigger input is inactive,
the generator is disabled, and the count-
er is loaded with the number N. When
the trigger input becomes active, the
counter waits, and the end-count output
enables the generator. A sine wave ap-
pears at the output. At the end of each
period of the sine wave, the comparator
produces a sync signal that drives the
counter’s clock input. When N periods of
the output wave have occurred, the end-
count signal disables the generator.
In the actual circuit, a MAX038, IC1,
is the generator (Figure 2). This IC con-
tains the sine-wave generator and the
comparator. The sync signal is available
at Pin 14. The counter has to be fast
enough to stop the generator before the
next output period starts. The 74AC191,
IC2, is a 4-bit up/down counter with pre-
set inputs. NAND gates IC3A and IC3B dis-
able the counter after the end-count goes
active. A one-shot circuit, IC5A, ensures A timing diagram that corresponds to three periods shows the precise sine-wave output at S.
that the input trigger pulse is long
enough to allow 15 pulses. A MOS TABLE 1—WAVEFORM-SHAPE SETTINGS resistance. The switches ap-
switch, IC4, short-circuits the oscillator A0 A1 Waveform
ply the voltage at G to Pin
capacitor, C1, to stop IC1’s generator. If X 1 Sine
5 of IC1, which stops the in-
the circuit simply grounds C1 to stop the 0 0 Square
ternal oscillator. The levels
generator, the output voltage is not zero. 1 0 Triangle
at the signal output and at
To obtain a zero output voltage, the cir- the sync output, F, depend
cuit connects input Pin 5 of IC1 to a neg- on the voltage at Pin 5. The
ative 0.5V-dc voltage generator compris- continuously loading the number N that voltage at F needs to be 5V, and the volt-
ing an LF356N and associated com- you program using S1. The level at D is age at Signal Out needs to be as close to
ponents. high, and the counter can’t run. The volt- 0V as possible. You need to carefully ad-
Because the signal at Pin 5 of IC1 goes age at C is low. The circuit connects just R3 to match these conditions. The
positive and negative, IC4’s switch re- NAND gates IC3C and IC3D in parallel to output voltage is just over 0V when G is
quires a 65V supply. The level for the provide more current to drive Q1 faster close to 20.5V.
command signal also has to swing posi- during switching. C2 is also necessary to When the trigger input goes high, one-
tive and negative. MOS transistor Q1 pro- drive Q1 faster. These NAND gates invert shot IC5A starts running. The voltage at B
vides the level-shifting from 0 to 5V log- the level at D, and Q1 is on, driven with also goes high for 10 msec. This delay
ic levels to 65V, or 4016, logic levels. 0V through R1. Thus, a 5V level is pres- must be longer than 16 periods of the
NAND gates IC3C and IC3D allow a fast ent at E, and the IC4 switches are on. Po- output signal. The voltage at D now goes
drive for Q1. tentiometer R3 controls the voltage at G; low and enables the counter. As before,
The circuit’s operation consists of the LF356N acts as a voltage follower. The IC3C and IC3D invert the level at D, and the
three timing periods: load N with trig- 10V resistor, R2, prevents oscillations 5V drive turns off Q1. A 25V level is
ger input inactive, down-count with trig- during switching. C1 and the MAX038 present at E, and IC4 switches are off. The
ger input high, and disabled (Figure 3). input represent the charge impedance. internal oscillator of IC1 is now running,
When the trigger input is inactive, one- The four switches of IC4 connect in par- and a signal is present at the output, S.
shot IC5A is inactive. The level at Point B allel to present a lower resistance of Each time the output signal is positive,
in the circuit is low, and counter IC2 is 200V/4, or approximately 50V, of total the sync output at F is also positive. At the

design
ideas
end of each period, a positive-going edge Q1. A 5V level is present at E, and IC4 cuit for one to 15 pulses. The circuit can
appears at F. Each positive edge at F switches are on. The internal oscillator of produce other signal shapes, depending
makes counter IC2 count down by one. IC1 stops, and the output signal at F re- on how you connect A0 and A1 of IC1
When the circuit has produced N pe- turns to zero. Before returning to the (Table 1). You can also replace S1 with a
riods at S, the voltage at C goes high, original state, the signal at B should re- mC to produce any pattern of pulses.
which indicates end of count. The volt- turn to zero, which happens after the end
age at D goes high and disables the of the delay that one-shot IC5A produces. Is this the best Design Idea in this
counter. IC3C and IC3D invert the voltage All is now ready for another train of issue? Vote at www.ednmag.com/edn
at D, and the resulting 0V drive turns on pulses. Using S1, you can program the cir- mag/vote.asp.
High-voltage current-feedback amplifier is speedy

Joseph Ting, Institute of Atomic and Molecular Sciences of the Academia Sinica, Taipei, Taiwan
he circuit in Figure 1 powers a mi-
T croparticle and nanoparticle

ion trap through a 1-to-5-
turns-ratio, high-voltage transformer. It
Figure 1
R2
150 D4 C1
230V
0.01 mF
1 kV
also works successfully as a driver for a R1 20V 0.1 mF
D1 R3 1W
560 Q4
piezo-tube scanner and in a near-field LED 100
2N2907 +
47 mF
scanning optical microscope. The circuit 400V
is robust and works with supplies rang-
ing from 650 to 6230V. The measured Q1
R4
30 2.4
parameters at 6230V supply voltage are 2N2907 1 1W
IC2
gain of 26-dB from dc to 23-dB point at 2 EL 6
33
1W
7 MHz; output swing of 6200V, rise and 100k
2003CN
Q2
4 MTP
fall times of 70 nsec for an output step of 0.01 mF MTP
2N50E
2P50E
350V, slew rate of 4100V/msec, and sup-
D3
ply current of 56 mA. 1N914
The red LEDs, D1 and D2, in Figure 1 C3955 Q3 10 VOUT
15V A1381 R5
provide a 1.8V drop; the LEDs are more 1W 100k
VIN 1W 6.2V
rugged than precision IC voltage refer- 1k IC1 1
2 EL 6
ences. The current supply for IC1 comes 2003CN
R8 R6 R7
from R1 and the source comprising D1, R2, 1k 4 2.4k 2.4k
240
R3, and Q1. R3’s trimmed value is such 1W 1W
Q7
that Q2’s quiescent current is approxi- 15V A1381
10
Q6
mately 15 mA. You can determine this 1W
C3955
current by measuring the voltage drop 100k MTP
1N914
across R4. The same adjustment also con- 0.1 mF 1W 2P50E
trols the output-voltage offset. IC2 is a MTP

2N50E
unity-gain, high-current driver for Q2. D3 100k IC3
1
prevents IC2’s input from going more 2 EL 6

1W
2003CN
negative than its negative supply. Q3, D4, 33
2.4
2N2222 4
C1, and R5 provide the negative bias for 30
IC2. Q4 is an output-current limiting 0.01 mF
switch. Q4 starts to turn on at IOUT5290 D2
1 kV
100 2N2222
mA. You can replace the bipolar transis- LED
560 20V 0.1 mF
tors C3955 (npn, Q2 and Q6) and A138 150 1W
(pnp, Q3 and Q7) by equivalents as long +
as they have the following minimum 47 mF

specs: VCEOM250V; ICM100 mA, and 2230V 400V
fTM100 MHz.
You should mount all the power tran- This high-voltage, current-feedback amplifier slews at 4100V/m msec.

design
ideas
sistors in individual finned heat R7 may result in excessive dissi-
sinks with an overhead 3-in. fan pation. Do not change the val-
for cooling. The pc-board layout ue of R8, because it is optimized
is not critical and needs no for speed. Be cautious when
ground plane. However, you measuring and using this cir-
must use single-point ground- cuit, because it harbors lethal
ing to minimize ringing. For the voltages. The National Science
component values shown, the 50V/DIV Council of Taiwan sponsored
circuit is very stable and needs this project.
no compensation capacitors.
Figure 2 shows a large-signal re-
sponse for a 69V, 1-MHz
square-wave input. This circuit
has a fixed gain of 20. For high-
er gains, you can increase 100 nSEC/DIV
the values of R6 and R7. Figure 2
For lower values, it is better to Is this the best Design Idea in
insert an attenuator at the input, The circuit has a clean square-wave response with minimal over- this issue? Vote at www.edn
because smaller values of R6 and shoot and no ringing. mag.com/ednmag/vote.asp.
AC-power monitor uses remote sensing

Sanjay R Chendvankar, Tata Institute of Fundamental Research, Colaba, Mumbai, India
he detection circuit in the Design
T Idea “Circuit monitors ac-power

loss” (EDN, Nov 24, 1999, pg 172) re-
quires a physical connection with the
ANTENNA
9
IC1D 10
PIEZO-
BUZZER
S1
mains to sense the power loss. The circuit
9V
in Figure 1 senses the power loss through D1
the radiated power-line signal. The bat- 3 IC1A
1 2
5 IC 4
1N914
7 IC1C 6 11 12
IC1E +
tery-operated circuit has a quiescent-cur- 4049
8
1B
9V
1 BATTERY
rent drain of approximately 2 mA. The R1
antenna, which is either a telescopic an- 2.2M C1
0.1 mF
1W
tenna or simply an approximately 2-ft- 8
14
IC1F
15
long wire, intercepts the radiated
power-line signal. The CMOS in- Figure 1
verters, IC1A and IC1B, amplify this weak
signal and convert it into a digital signal. A low level at the outputs of IC1D, IC1E, and IC1F activates the piezo-buzzer and warns of ac-line
D1 and C1 generate a steady dc voltage at failure.
the input of IC1C. D1 prevents discharge
of C1 through the output of IC1B when low; hence, the levels of IC1D, IC1E, and deactivates the buzzer. You can turn S1 on
the square wave at this output periodi- IC1F are high, and the buzzer is off. When after ac power resumes.
cally goes to a low level. Inverters IC1D, the ac power fails, the output of IC1B goes
IC1E, and IC1F connected in parallel en- low; C1 discharges through R1; and IC1D,
hance the current-sink capacity for sink- IC1E, and IC1F go low. This level activates Is this the best Design Idea in this
ing the piezo-buzzer current. When the the piezo-buzzer and warns of ac-line issue? Vote at www.ednmag.com/edn
ac mains is present, the output of IC1C is failure. Switching off the battery power mag/vote.asp.

design
ideas
Circuit detects first event
Kelly Flaherty, National Semiconductor, San Mateo, CA
he circuit in Figure 1 is a “first- dual comparator is a good fit for this ap- can cascade two first-event detectors to
T event” indicator, like a game show’s plication, because it draws only 7-mA obtain more channels.
“who’s first to answer” detector. It in- quiescent current, and it has rail-to-rail
dicates which of the two momentary inputs and outputs. The comparator’s Is this the best Design Idea in this
switches, S1 or S2, closes first by latching sourcing capability allows it to easily issue? Vote at www.ednmag.com/edn
the corresponding channel, ICA or ICB, to drive an LED. Figure 2 shows how you mag/vote.asp.
a high state. As either of the outputs
VBAT
latches high and lights its respective LED, 1 +
R3A
it locks out the other channel and pre-
vents it from triggering. The other mo- 9V 500k
mentary switch, S3, resets either of the BATTERY SET 1
R2A
3 8
+
latched outputs to its initial low (LED- S1 90k
ICA 1 LATCH 1
R1A 10k LMC6762
off) state. At the initial condition, the R4A
2 _ 1/2
VBAT 1k
positive input of each comparator is ap- 1M
R5B
proximately at 0V, because both outputs D1A 100k

RESET LED 1
are low. The negative inputs are at 1 AND 2 914
VBAT/11, as set by voltage divider R4 S3 914
and R5. In this initial condition, as- Figure 1
D1B R5A
sume that S1 is momentarily closed. The R4B
5 6 _ 100k
positive input of ICA becomes /6(VBAT), as VBAT
ICB
1M 5 LATCH 2
set by voltage divider R2A and R3A. Be- R2B LMC6762
SET 2 5 1/2
cause 5/6(VBAT) is greater than VBAT/11, S2
+ 4 1k
90k
the output of ICA goes high, and the pos- R1B 10k
R3B
itive input of ICA latches its threshold to LED 2
approximately VBAT/6. 500k
Correspondingly, the negative input of GND

ICB latches to approximately VBAT, thus
preventing S2 from triggering ICB’s out- Which button did you push first? This circuit reveals the answer.
put high. S3 resets (turns off) either of the VBAT VBAT
active outputs by pulling the inverting in-
SET 1
puts one diode drop below VBAT. Both LATCH 1
S1 RESET 1 AND 2
channels are then in their initial condi- LATCH 2
tion and ready to go again. The LMC6762 SET 2
S2
RESET LED 1
Circuit detects first event ..............................89 1, 2, 3,
AND 4
High-speed pulse generator LED 2
S5
has programmable levels ............................90 VBAT
Low-battery indicator
SET 3
has high efficiency ........................................92 LATCH 3
S3 RESET
LCD-bias supply provides 3 AND 4 LATCH 4
precise tracking ..............................................94 SET 4
S4
Rolling-code generator uses flash mC ......94 LED 3
SEPIC generates 5V at 100 mA ..................98

Figure 2 LED 4
Look-up table helps bit flipping..................98
With the addition of six diodes, you can cascade two first-event detectors.
www.ednmag.com May 3, 2001 | edn 89

design
ideas
High-speed pulse generator has

programmable levels
John Guy, Maxim Integrated Products, Sunnyvale, CA
illiputian dimensions pole, double-throw) switch
L associated with the sub-

micron geometries of
most digital and many ana-
can create pulses whose high
and low levels are program-
mable.
log processes result in much A feature of analog
faster circuit operation. As switches that hinders their
ICs speed up, the rise and fall use as pulse generators is the
times of most pulse and intrinsic built-in delay—the
function generators, which break-before-make time—
are typically 5 nsec, become that guarantees that an
inadequate for measuring SPDT switch does not short
time intervals lower than 20 the two switched terminals
nsec. You can overcome this together during a transi-
limitation with analog com- tion. Unfortunately, this de-
parators or advanced CMOS lay and the switches’ finite
logic gates, which create turn-on time also extends
faster digital edges. Their rise the rise and fall times. You
and fall times are fast can avoid this effect by
enough, but the signal adding a dynamic pullup
levels include ground Figure 2 and a dynamic pulldown to
and VCC only. the circuit (Figure 1). A suf-
Designers have applied The input (lower) and output (upper) traces illustrate fast output transitions ficiently low pullup and
the submicron processes and settable output levels. pulldown impedance can
that high-speed digital cir- drastically improve the cor-
cuits use to analog switches as well, so the switches also produce fast rise and fall responding rise and fall times.
turn-on and turn-off times for these times. What’s more, an SPDT (single- The input clock signal, F1, controls an
5V
74VHC04 IC2
f2 1 MAXIM
IC3A IC3B IC3C IC3D IN1 MAX4644 6
OUTPUT
5V 2 SIGNAL
V+ 5
0.1 mF
3
GND 4
0.1 mF
INPUT R1
SIGNAL IC1 47
Figure 1 f1 1 MAXIM
IN1 MAX4644 6
5V 2 V+
5
3
GND 4
0.1 mF
V_HIGH
V_LOW
0.1 mF 0.1 mF
Analog switches provide dynamic pull-up and pull-down at the output of this pulse generator to ensure fast rise and fall times.
90 edn | May 3, 2001 www.ednmag.com

design
ideas
SPDT analog switch, IC1, which the cir- cause the series resistor, R1, is large with You can set V_LOW and V_HIGH to any
cuit configures as the pullup/pulldown respect to the MAX4644’s on-resistance, level within the supply range for IC1 and
driver. The input clock signal also drives or 47V versus 2.5V typical, the immedi- IC2. The circuit’s quiescent current is es-
a high-speed CMOS inverter, IC3, to create effect on output voltage is minimal. sentially zero, with brief peaks only dur-
ate a delayed clock signal, F2. The delayed However, when F1 propagates through ing the output transitions. Rise and fall
clock drives an SPDT analog switch, IC2, the inverter string, the falling edge of F2 times at the output are approximately 4
which the circuit configures as the out- causes IC2 to transition from V_LOW to nsec, and the output impedance is 2.5V.
put driver. V_HIGH. The presence of a low-imped-
Consider the steady-state condition in ance pullup, R1, provides drive for the sig-
which F1 is low and F2 is high. IC1’s nal transition, and the closing of IC2
COM pin and IC2’s COM pin connect to quickly follows. Is this the best Design Idea in this
V_LOW, and a rising edge on F1 causes The input signal is 5V logic, and the issue? Vote at www.ednmag.com/edn
IC1 to pull the output signal high. Be- output swings from 1V to 2V (Figure 2). mag/vote.asp.
Low-battery indicator has high efficiency

Joe Neubauer, Maxim Integrated Products, Sunnyvale, CA
he usual method for implement-
T ing the low-battery warning featured

in most battery-operated equipment
is to illuminate an LED. However, the
FROM CONVERTER OUTPUT
R1 R2
IC1
MAX9030
LED exacerbates the low-battery condi-
tion. You can greatly reduce the LED’s NECESSARY ONLY IF 6
LBO IS UNAVAILABLE 1
power consumption by operating it at a + 4
3
low frequency and a low duty cycle. An FROM LBO
2N3906
R3 2
existing LBO (low-battery output) like 2 5 SHDN
that found in dc/dc converters offers a
convenient way to light the LED (Figure
1). IC1 is a small, inexpensive compara-
FROM LBO R4
tor with shutdown capability, housed in
a six-pin SC70 package. It remains
in shutdown condition while the Figure 1
R5 50
1N4148 LED
battery is at normal operating levels but
asserts LBO when the battery voltage
falls below a preset threshold. Active-
high LBO is usable as shown, but an ac-
tive-low warning, LBO, requires the op-
tional circuitry shown. IC1 turns on, Operating the low-battery LED at low duty cycle saves power and extends battery life.
causing the LED to flash according to the
following analysis: First, you want to keep choff ’s current laws to find the compara- ding to this performance are: C150.1 mF,
the duty cycle low: DC5tON/(tON1tOFF). tor’s high and low trip levels: R15R25R351 MV, R453.6 MV, and
You derive the on-time from the equation V TRIPHI 5V OUT [R 3 (R 1 1R 2 )]/[R 3 (R 1 1 R5591 kV.
for time-varying voltage across a charg- R2)1R1R2], and VTRIPLO5VOUT[R3R2]/
ing capacitor: V(t)5V(12e1t/RC), so [R3(R11R2)1R1R2]. Assuming a 2.5%
tON52R5Cln(TRIPHI12VTRIPHI/VOUT). You duty cycle and assuming that the LBO
then derive the off-time from the equa- trips the comparator on when the battery
tion for time-varying voltage across a dis- voltage equals 3V, the resulting trip lev- Is this the best Design Idea in this
charging capacitor: V(t)5Ve1t/RC, so els are 1V for low and 2V for high. The issue? Vote at www.ednmag.com/edn
tOFF52R4Cln(VTRIPLO/VOUT). Use Kir- standard component values correspon- mag/vote.asp.

design
ideas
LCD-bias supply provides precise tracking
David Kim, Linear Technology Corp, Milpitas, CA
mall monochrome LCD systems switching frequency and a 36V internal ing requirement, you should use a preci-
S often require split (dual)-bias sup-

plies with precise voltage tracking to
prevent plating of the LCD. The circuit in
switch results in small, low-profile circuit.
LCD bias requires high voltage at low
current. A charge pump consisting of C2,
sion-resistor network, such as the 664 se-
ries from BI Technologies (www.bitech-
nologies.com), for R1 and R3. The unique
Figure 1 provides 618 to 620V ad- C4, D2, and D3 generates the negative out- input stage of the LT1636 allows you to
justable LCD bias voltages with 1% track- put voltage. Some benefits of this circuit generate the VCC of the inverting op amp
ing accuracy. The circuit operates from a topology include zero output power dur- from the rectified switching waveform
single 4.2 to 2.5V Li-ion cell for portable ing shutdown and low output ripple. (using D1 and C1) of the LT1611 switch-
monochrome LCD applications. The cir- The LT1636 rail-to-rail op amp gener- ing regulator. You adjust both LCD-bias
cuit comprises two blocks: a negative- ates the positive LCD-bias output. The supplies by varying the 2-kV poten-
bias supply using the LT1611 inverting large capacitive-load capability, low qui- tiometer at the feedback node of the
switching regulator and a positive-bias escent current, and high-impedance in- LT1611 regulator.
supply using the LT1636 rail-to-rail op put stage make the LT1636 suitable in this
amp. The LT1611 converts the Li-ion bat- application. The LT1636 inverts the LT- Is this the best Design Idea in this
tery input voltage to a negative output 1611’s output to provide the positive issue? Vote at www.ednmag.com/edn
voltage. The combination of 1.4-MHz LCD-bias voltage. To meet the 1% track- mag/vote.asp.
POSITIVE BIAS SUPPLY
D1
Figure 1
C1
MBR0540 1 3.3 mF, 35V
SPRAGUE
NEGATIVE BIAS SUPPLY 592D335X9035D2
D2 OUTPUT
INPUT
SUMIDA CLQ61B-4R7 C2 MMBD914LT1 2 7 218 TO ;20V
4.2 TO 2.5V R2
AT 300 mA
6
R1 LT1636
4.7 mH 0.1 mF 15 100k 3
D3 4
5 1 MMBD914LT1
VIN SW
4
SHDN LT1611 NFB
3
GND
1 C3 2 1 C4 R3
C5 3.3 mF, 35V
33 mF, 10V 100k
SPRAGUE SPRAGUE
592D335X9035D2 1000 pF 592D335X9035D2
R4 2k
R5
13.3k LCD BIAS ADJUST 196k OUTPUT

218 TO ;220V
AT 300 mA
This LCD-bias supply provides better than 1% tracking of the positive and negative outputs.
Rolling-code generator uses flash mC

Wallace Ly, National Semiconductor Corp, Santa Clara, CA
any security-alarm systems re- dom numbers to prevent unwanted visi- implement such a generator, you would
M quire the use of a random number.

A computer program uses this ran-
dom number to create a sequence of ran-
tors from gaining entry into a protected
facility. You can use a “rolling-code gen-
erator” to produce random numbers. To
typically need a microcontroller with ex-
ternal memory. Instead, you can use Na-
tional Semiconductor’s COP8SBR flash
design
ideas
mC with “virtual-EEPROM” technology.
TERMINATOR
This technology allows you to use a sec-
READ FROM
tion of flash memory as if it were EEP- THE FLASH
ROM. Because this mC is a true-flash de- [1FFF].
IS LFSR RANDOM-
vice, the maximum number of erase/ [DATA]=
NO
NUMBER
write cycles is typically 100,000 cycles. SEED 00? GENERATOR
The flow chart in Figure 1 and the C code
in Listing 1 show the adaptation of a
textbook LFSR (linear-finite shift regis- YES
FEED THE
ter) to the COP8 flash mC. RANDOM-NUMBER
GENERATOR
An initial “seed” first drives the TO THE PROGRAM
input. The seed then traverses F i g u r e 1
several exclusive-OR stages. The routine
then saves the result to a virtual-EE- This random-number generator uses the virtual-E2 feature of the COP8 mC.
PROM location. This approach allows an
embedded-system designer to easily cre- mag.com. Click on “Search Databases,” Is this the best Design Idea in this
ate a highly secure system without in- then enter the Software Center to down- issue? Vote at www.ednmag.com/edn
curring the cost of an external non- load the file for Design Idea #2704. You mag/vote.asp.
volatile memory, such as a dedicated can find additional information about
serial EEPROM. You can download List- the COP8SBR and its virtual-E2 feature
ing 1 from EDN’s Web site, www.edn- at www.national.com/cop8.
LISTING 1—SOURCE CODE FOR A VIRTUAL-EEPROM BASED RANDOM-NUMBER GENERATOR

design
ideas
SEPIC generates 5V at 100 mA
Dongyan Zhou, Linear Technology Corp, Milpitas, CA
ome applications require an in-
S put voltage higher than the break-

down voltage of the IC supply pin.
In boost converters and SEPICs (single-
VIN
4 TO 28V
47k
L1
47 mH
C2
0.22 mF
D1
L2
47 mH C3
VOUT
5V,
100 mA
ended primary-inductance con- Q2 15 mF
Figure 1 2N7002
verters), you can separate the VIN
pin of the IC from the input inductor 5
Q1 1
and use a simple zener regulator to gen- 2N3904 VIN SW
erate the supply voltage for the IC. Fig- IC1 100k, 1%
4 SHDN 3
ure 1 shows a SEPIC that takes a 4 to 28V C1 LT1613 FB
input and generates 5V at 100 mA. 1 mF
NO GND
In this application, Q1 and Q2 gener- CONNECT
2 32.4k, 1%
ate the supply voltage for IC1 because the
supply voltage exceeds IC1’s maximum
input voltage. The circuit uses Q1 in NOTES: C1 IS TAIYO YUDEN LMK212BJ105MG.
place of a zener diode to save cost. The C2 IS TAIYO YUDEN UMK316BJ224ML.
emitter-to-base breakdown voltage gives C3 IS AVX TAJA156M010R.
L1AND L2 ARE MURATA LQH3C470K34.
a stable 6V reference. The follower, Q2, D1 IS MOTOROLA MBR0540T3.
provides the supply voltage for the IC.
This circuit demonstrates an inexpensive Q1 stands in for a zener diode in this SEPIC with a wide input-voltage range.
way to extend the input range of the IC.
This SEPIC can step up or step down hibiting any possible load current in Is this the best Design Idea in this
the input voltage. Because the flying ca- shutdown mode, which is important for issue? Vote at www.ednmag.com/edn
pacitor, C2, breaks the input-to-output dc portable applications and which prevents mag/vote.asp.
path, the output disconnects from the in- the input voltage from appearing at the
put when you shut down the device, in- output.
Look-up table helps bit flipping

Brad Bierschenk, High End Systems, Austin, TX
n certain instances in embedded ample, you can use the 16-bit DPTR
I software, a programmer needs to flip

the order of the bits in a byte so that
B7 to B0 become B0 to B7. Bit flipping is
LISTING 1—BIT-FLIPPING CODE SEGMENT (data pointer) plus an 8-bit offset in ac-
cumulator (A) to load the accumulator
with a byte value.
useful, for example, when a synchronous This approach is dynamically more ef-
serial port does not allow programmatic ficient than rotating a byte location
selection of bit order, such as MSB first or through carry bits, but it is not the most
LSB first, for its shift register. You need a statically efficient approach because the
software method to translate data if the look-up table requires 256 bytes of ROM.
processor sends data to a receiving device (00000000b), the second byte is offset 1 You can download the inversion table
that expects a certain bit order, but the se- (10000000b), the third byte is offset 2 from EDN’s Web site, www.ednmag.com.
rial port can provide only the other bit (01000000b), and so on. The program Click on “Search Databases” and then en-
order. needs only to load the value to be trans- ter the Software Center to download the
One solution is to provide a look-up lated into a register that you can use as an file for Design Idea #2621.
table in ROM in which the value of each offset, index the look-up table, and load
byte in the table is its offset into the table the corresponding value from the Is this the best Design Idea in this
but with a reversed bit order. In other index1offset location (Listing 1). Using issue? Vote at www.ednmag.com/edn
words, the first byte is offset 0 the Philips 83C51 architecture as an ex- mag/vote.asp.

design
ideas
mC eliminates offboard EEPROM
with “virtual-EEPROM” routines
Wallace Ly, National Semiconductor Corp, Santa Clara, CA
OP8flash mCs let you allocate
C some of their internal flash

memory as a nonvolatile
storage space. This line of flash mCs ac-
Figure 1 THE BOOT ROM
CONTAINS FLASH-MODIFICATION
SUBROUTINES.
THE PROGRAM CAN SELF-START
IN-SYSTEM PROGRAMMING
BY JUMPING INTO THE BOOT-ROM
PARTITION.
complishes this task by accessing some
memory functions built into the boot
ROM. In addition to some of these VIRTUAL-EEPROM FLASH
memory functions, the COP8flash mC ROUTINES
JSRB PROGRAM DATA BYTE 128
MEMORY RAM
can initiate and control in-system pro- COP8FLASH
BOOT ROM PC
gramming under software. You can use BYTE 1
“virtual EEPROM,” although not truly
EEPROM, to mimic the behavior of the
storage space of an offboard EEPROM.
Note that the flash inside the COP8flash This example of a 128-byte virtual EEPROM shows how you can mimic the behavior of the storage
mC is not just renamed E2. This fact has space of an offboard EEPROM.
significant implications because the
flash mC is rated for 100,000 erase/ EEPROM, then they may execute a
write cycles and 100-year data reten- “flush” to dump the contents of the
tion. modified RAM into the flash mC. MODIFY THE RAM
CONTENTS
Figure 1 depicts how you can allocate A system designer may bring up the
a 128-byte virtual EEPROM. Although issue that the “dumping” of the RAM
users may not write over the same byte into the flash mC may take too long.
twice, they may modify RAM contents. However, the opposite is true if you take DOES
Additionally, you can “shadow” the flash the following into consideration: A typ- WRITE_COUNTER=0?
mC with RAM. If users want to perma- ical write to the flash mC takes a
nently save the contents of the virtual few microseconds, and a page Figure 2
YES
erase takes 8 msec, independently of the
mC system clock. So, the dumping FLUSH THE MODIFIED
NO
process may take less than 10 msec. RAM CONTENTS
mC eliminates offboard EEPROM However, a designer is hard-pressed to
INTO THE FLASH
with “virtual-EEPROM” routines ..............123 find an offboard serial EEPROM that
Medical timer warns has less than 100 msec of access time.
NEXT PROCESS
when pills are due ......................................124 Figure 2 shows how to visualize the
Temperature monitor and
sample virtual-EEPROM code. As you
fan controller reduce fan noise ................128
shadow the flash mC, you write bytes to
the RAM, and a WRITE_COUNTER When the WRITE_COUNTER equals 0, the rou-
Circuit forms random decrements. When the WRITE_ tine flushes the contents of the RAM.
bit-sequencer generator ............................132 COUNTER equals 0, the routine flush-
es the contents of the RAM. The flash A system designer can set the WRITE_
mC then saves the contents of the RAM. COUNTER to 0 to immediately copy
www.ednmag.com May 10, 2001 | edn 123

design
ideas
the contents of the RAM into the flash Databases” and then enter the Software Is this the best Design Idea in this
mC. You can download the Virtual Center to download the file for Design issue? Vote at www.ednmag.com/edn
EEPROM C code from EDN’s Web site, Idea #2688. mag/vote.asp.
www.ednmag.com. Click on “Search
Medical timer warns when pills are due

ome people need to take medica-
S tion at precise, regular intervals.

When you’re in a hospital, a medical
staff is present to ensure that you take
TABLE 1—TIMING DETAILS FOR CIRCUIT IN FIGURE 1
Positive edge
IC2
Period Positive edge
IC3
Period
your medication on time. But when Q1 0.858 msec 1.17 msec 3.51 sec 7.03 sec
you’re taking medication at home, you Q2 1.717 msec 3.43 msec 7.03 sec 14.06 sec
must frequently look at the clock—a clear Q3 3.433 msec 6.866 msec 14.06 sec 28.12 sec
annoyance. When my wife was pregnant, Q4 6.866 msec 13.73 msec 28.12 sec 56.25 sec
she needed to take medication every two Q5 13.73 msec 27.5 msec 56.25 sec 112.5 sec
hours from 8 am to 10 pm. To help her Q6 27.46 msec 55 msec 112.5 sec 225 sec
time the two-hour intervals, I built the Q7 54.93 msec 110 msec 225 sec 7.5 minutes
battery-powered circuit in Figure 1. The Q8 109.86 msec 220 msec 7.5 minutes 15 minutes
circuit derives its power from a 9V PP3 Q9 219.7 msec 439 msec 15 minutes 30 minutes
battery. All the ICs are CMOS-based; the Q10 439 msec 878 msec 30 minutes One hour
low power consumption of the circuit al- Q11 879 msec 1.758 sec 1 hour Two hour
lows one-week autonomy. When you Q12 1.758 sec 3.51 sec 2 hour Four hour
VCC
9 VCC
Q1
16 VDD 16 VDD Q2 7
IC1 IC2 VCC 10 Q3 6 10k
P1 Q4 5 1k
8 VSS 8 VSS Q5 3 Q5
START BUTTON Q6 2
9V PP3 IC3 Q7 4 2N2907
Q8 13
BATTERY 220 nF Q9 12
BP1 + BZ1
Q10 14
11 Q11 15 1 BUZZER
RES 1
Q12
Figure 1 Q4
10k CD4040
VCC 2N7000
VCC
R1 680
1N4148 D2
LD1
22k 4 C
8 IC1 9
Q1 Q2
12k V R MCI4555 Q2 7 A 1N4148
7 3 10 6 1k D1
DIS Q P1 Q3Q4 5 Q1
P1 6 THR GND 1 Q5 3
2 2N7000 1k
10k Q6 1N4148
TR CV IC2 Q7 4 Q3
2 5 Q8 13 1k B
Q9 12 2N7000
P2 Q10 14
11 15 2N7000
1k RES Q11 1N4148
Q12 1
22 nF 10 nF
CD4040
The buzzer in this circuit sounds at precise two-hour intervals.

design
ideas
press the start button, BP1, a two- Figure 2
hour delay commences. During
this delay, LED LD1 flashes to indicate the Q9-IC1-T4439 mSEC.
220 mSEC
delay is in progress and the battery volt- TIME
age is satisfactory. After the two-hour de-
lay elapses, the buzzer, BZ1, emits short Q10-IC1-T4878 mSEC. 439 mSEC
beeps for one minute If you don’t press TIME

the start button again, LD1 stays lit con-
Q11-IC1-T41.758 SEC. 878 mSEC
tinuously to indicate that the delay has
elapsed. Pressing the start button initiates TIME
a new two-hour delay cycle. Q12-IC1-T43.51 SEC. 1.758 SEC
IC1, a 555 timer, operates as an astable

TIME
multivibrator and produces a rectangu-
POINT A (Q10 AND Q11)
lar waveform at its output. The period
TIME
should be equal to 858.3 msec. P1 and P2
POINT B (Q9 AND Q12).
permit gross and fine adjustments of the
period. For the two-hour delay, P1 yields TIME
a 620-minute adjustment; P2 produces a LED LD1 (A AND B) 220 mSEC

ON
62-minute adjustment. For a precise ad-
TIME
justment, observe the Q7 output of IC2
and trim to obtain a period of 110 msec. 3.5 SEC
IC2 is a 212 divider whose Q12 output has
a 3.51-second period. This output con- These waveforms show what elapses in the circuit of Figure 1 during the two-hour time-out.
nects to IC3’s clock input. IC3 then
yields a 14,400-second period, or
Figure 3
four hours. The circuit detects the
positive edge of Q12, which occurs after Q10-IC1-T4878 mSEC.
439 mSEC
two hours. Changing the connection to
IC3 to another output or trimming P1 TIME
and P2 allows you to set different delays. Q11-IC1-T41.758 mSEC. 878 mSEC
Table 1 shows the timing details for the
various outputs of IC2 and IC3. TIME
Figure 2 shows timing details for the 1.758 SEC
POINT A (Q10 AND Q11) 439 mSEC
first two hours after asserting start for the
circuit in Figure 1. Q12 of IC3 is at a low TIME
level, and transistor Q1 is off. Thus, D1and Q12-IC2-T44 HR.

2 HR.
D2 cannot conduct. To light LD1, Q2 and TIME
Q3 must be on, which is the case when Q9 56 SEC
Q5-IC2-T4112 SEC.
to Q12 of IC2 are at a high level. This
high-level condition occurs for 220 msec TIME
every 3.5 seconds. This time period 439 mSEC

1.758 SEC
might seem short, but R1’s low value and BUZZER ON
the choice of a high-luminosity LED TIME
makes LD1’s flashing clearly visible. Fig-
ure 3 shows timing details after the two
LED LD1
hour time-out delay. Q12 of IC3 assumes FLASH CONTINUOUSLY ON
a high level, and Q1 grounds Point C. As TIME
a result, D1 conducts, and LD1 stays con-

tinuously on, indicating that the delay
has terminated. D2 conducts when Q4 The buzzer sounds, and the LED stays on after the two-hour time-out.
and Q5 are on, and the buzzer sounds.
These transistors turn on when Q5 of IC3 total duration of 56 seconds. This time Is this the best Design Idea in this
is at a low level and Q10 and Q12 of IC2 period might seem short, but it is long issue? Vote at www.ednmag.com/edn
are at a high level. These conditions oc- enough to create an audible beep. The mag/vote.asp.
cur for 439 msec every 1.8 seconds, for a start button restarts the cycle.

design
ideas
Temperature monitor and fan controller

reduce fan noise
David Hanrahan, Analog Devices Inc, Limerick, Ireland
he scheme in Figure 1 reduces sys-
T
FAN 1
tem acoustic noise by run-

ning system fans at their op- Figure 1
timum speeds for a given temperature. CONTROL SPEED
IC1 combines 618C-accurate temper-
OPTIONAL
ature measurement of three tempera- ZONE B
2N3904
D1+
IC1
SDA SDA
16-CHARACTER3
PIC16C84
tures with automatic fan-speed control D12 ADM1030/ 4-LINE LCD
ADM1031* SCL SCL
of two channels. A two-wire serial in- (ZONE A)
terface allows you to oversee critical ZONE C
2N3904
*D2+
temperature and fan-speed data. NPN *D22

transistors, such as the 2N3904, can SHIELDED CONTROL SPEED
measure temperatures in remote loca- TWISTED-
PAIR CABLE
tions. The microcontroller interface al-
lows you to connect an LCD to display
FAN 2
all monitored parameters.
You program IC1’s automatic-fan- A scheme with multiple temperature-measurement and fan-control channels can run system fans at
speed-control function using TMIN and the optimum speeds for a given temperature.
TRANGE (Figure 2). TMIN is the
SPIN UP FOR 2 SEC
temperature at which the fan au- Figure 2 MAXIMUM
tomatically turns on and runs at
minimum speed. TRANGE is the temper-
ature-to-fan speed-control slope, with
options of 5, 10, 20, 40, and 808C. FAN SPEED
Choosing one of the TRANGE options al- TRANGE
lows you to define how the fan reacts to
temperature variation. MINIMUM
An example of programming IC1 fol-
lows. Setting Configuration Register 1
(Reg 0x00) to 0x99 starts the device in
automatic-fan-speed-control mode, TMIN TMAX=TMIN+TRANGE.
with the FANFAULT function enabled. TEMPERATURE
A setting of Remote Temp 1 TMIN/TRANGE
(Reg 0x25)50x63 sets TMIN for fan 1 to The values of TMIN and TRANGE set the parameters of the automatic-fan-speed control loop.
488C and TRANGE to 408C. The Fan reach-
es full speed at 888C. A setting of Remote bility over which temperature channel outputs illuminate whenever an over-
Temp 2 TMIN/TRANGE (Reg 0x26) 5 0x62 controls each fan.You can also decide that temperature condition occurs or a fan
results in a TMIN for Fan 1 of 488C and a the maximum speed calculated for all fails. The THERM output is a fail-safe
TRANGE of 208C. The fan reaches full speed temperature channels controls the fans. output that goes low if a preprogrammed
at 688C. Figure 4 shows the circuit diagram for overtemperature THERM limit is ex-
The fan runs at low speed until the sys- the temperature-monitor/fan-control ceeded. In the event of an overtempera-
tem requires a higher level of cooling. The circuit. The PIC16C84 writes the config- ture condition, both fans automatically
fan speed responds automatically to tem- uration settings to IC1 and optionally run at full speed. If some external device
perature variation, reducing acoustic drives an LCD. The mC bit-bangs pins 2 pulls the THERM pin low, the fans also
noise (Figure 3). You can program addi- and 3 to provide serial clock and data for run at full speed. The FANFAULT pin sig-
tional features, such as fan spin-up time IC1. The mC reads and displays all tem- nals catastrophic fan failure. If one fan
and minimum fan speed. The automat- peratures and fan speeds. The LEDs that fails, the second fan automatically spins
ic-fan-speed-control mode allows flexi- connect to the THERM and FANFAULT at full speed to compensate for the loss

design
ideas
of airflow. Should the failing fan recover
or be replaced, both fans auto-
Figure 3 37
matically return to their normal
operating speeds. 35
You can extend this idea for multiple
fans with redundant cooling using two ICs
33
to monitor six temperature zones (Figure
5). This scheme cross-connects the
dB 31
THERM and FANFAULT signals. The
same pin drives fans A1 and A2, which will
run at the same speed. Likewise, fans B1 29
and B2 connect in parallel to a common

FET. Fans C and D are redundant coolers 27
that the system uses only if it gets exces-

sively hot or a fan fails. If either fan A1 or 25
40 45 50 55 60 65 70 75 80
A2 fails, fans B1 and B2 automatically run
TEMPERATURE (8C)
at full speed. The FANFAULT output of
IC1 asserts low, pulling THERM of IC2 low, Automatic-fan-speed control reduces acoustic noise.
5V V+
5 OR 12V
COOLING
FAN
TACHOMETER 5V 5V 5V
PIC16C84
10k IC1 2.2k 2.2k
1 PA2 PA1 18
NDT3055L 1 PWM_OUT1 SCL 16 2 PA3 PA0
17
NM0S 16
2 TACH/A1N1 SDA 15 3 PA4 OSC1
4 MHz
3V
3 PWM_OUT2 INT 14 4 MCLR OSC2 15 6 5 4
4 13 5V
TACH/A1N2 ADD 5 GND VCC 14 33 pF RW RS
5V V+ 33 pF
5 GND D2+ 12 6 PB0/INT PB7 13 14 D7
5V 12 13 D6
10k 6 V D21 11 7 PB1 PB6
CC
7 10 8 PB2 11 12 D5
5V THERM D1+ PB5
9 OPTIONAL
8 FANFAULT D11 9 PB3 10 11 D4
TACHOMETER PB4 16-
10 CHARACTER3
5 OR 12V 10k ADM1030 D3 4-LINE LCD
FAN (ADM1031) 9
D2
NDT3055L
8
NMOS D1
7
D0
VCC GND
2N3904 3 2 1
TEMPERATURE ZONE C
5V
Figure 4 5V 5V
470
FANFAILURE
2N3904
5V TEMPERATURE ZONE B
470
OVERTEMPERATURE
The mC bit-bangs pins 2 and 3 to provide serial clock and data for IC1 and reads temperatures and fan speeds.

design
ideas
which causes redundant fans C and D to to run at full speed. Fans C and D also au- Is this the best Design Idea in this
run at full speed. If either fan B1 or B2 fails, tomatically run at full speed. If the faulty issue? Vote at www.ednmag.com/edn
fans A1 and A2 automatically run at full fan is replaced, all fans return to their nor- mag/vote.asp.
speed. The FANFAULT output of IC2 pulls mal operating speeds. FANFAULT signals
THERM of IC1 low, causing fans A1 and A2 alert the system to fan failure.
FAN B1 FAN B2 FAN C

FAN A1 FAN A2
FAN FAN
FAN
SPEED SPEED
SPEED
TEMPERATURE TEMPERATURE
ZONE 3 ZONE 4
IC1 IC2
ADM1031 ADM1031
FAN D
FAN FANFAULT FANFAULT
SPEED
THERM THERM
FANFAULT A
Figure 5
FANFAULT B
TEMPERATURE TEMPERATURE TEMPERATURE TEMPERATURE

ZONE 1 ZONE 2 ZONE 5 ZONE 6
Using two ICs provides for monitoring six temperature zones.
Circuit forms random-bit-sequence generator

Przemyslaw Krehlik and Lukasz Sliwczynski,
University of Mining and Metallurgy, Krakow, Poland
random-bit-sequence generator ing random noise to form the outgoing a jitter in the generated bit sequence
A is basic equipment for prototyping

and testing any data-transmission
system. You use such a generator when
data stream. The circuit uses the
ECLinPS logic family (Reference 1). The
MC10EL16 liner receiver converts the
(Reference 2). The second MC10EL31
flip-flop eliminates the jitter problem.
We tested the generator with clock fre-
measuring BER (bit-error rate) and pat- incoming noise to a digital signal. Next, quencies to 1 GHz and observed no
tern-dependent effects in a transmission a rising clock edge of the first anomalies in the output eye pattern or
system. Such effects can include baseline MC10EL31 flip-flop samples this ran- frequency spectrum. Note that the
wander, pattern-dependent data jitter, dom signal. Ideally, this flip-flop should ECLinPS devices are ultrafast ICs, so you
and recovered-clock jitter. Most se- provide a random bit sequence. need to exercise special care in your pc-
quence generators yield a PRBS Unfortunately, when the data at the board design. You should terminate the
(pseudorandom bit sequence) from a flip-flop’s input changes simultaneous- generator’s inputs and outputs with
shift register with appropriate feedback. ly with the clock’s rising edge, the flip- 50V, keep all connections short, and de-
Thus, the sequence has limited length, flop may fall into a metastable state. couple all ICs with local capacitors. You
and the generator continuously repeats Thus, the resulting output state is inde- can use a circuit from Reference 3 for a
the same pattern. The generator in Fig- terminate, and a significantly extended noise source. The voltage of the noise
ure 1 overcomes these limitations by us- propagation delay may result, producing source should be 100 mV to 1V rms, and

design
ideas
its frequency spectrum should be at least 2. Metastability and the ECLinPS Is this the best Design Idea in this
equal to the clock frequency. Family, Motorola Application Note issue? Vote at www.ednmag.com/edn
AN1504. mag/vote.asp.
References 3. Sliwczynski, Lukasw, “Zener diode
1. High Performance ECL Data, Mo- and MMICs produce true broadband
torola, 1995. noise,” EDN, Oct 14, 1999, pg 158.
Figure 1
MC10EL16 MC10EL31 MC10EL31
1 mF 47 1 mF
NOISE A B
GENERATOR D Q D Q OUT
51
390
CLK Q CLK Q OUT
47 1 mF
VBB
390 390
51 10 nF
CLOCK
INPUT
10 nF
This generator produces truly random bit sequences at frequencies to 1 GHz.

design
ideas
Highpass filters use modified equal-element design
sing a modified equal-element de-
U sign for a lumped-circuit

lowpass filter has several ad-
vantages over the well-known equal-ele-
Figure 1
C1=1 OR 2 C2=1 C3=1 C4=1 C5=1 OR 2
ment design (references 1 and 2). The

modified design exhibits superior pass-
VIN L1=1 L2=1 L3=1 L4=1 VOUT
band performance with only modest
degradation of stopband selectivity.
Moreover, the modified design is simple
and easy to manufacture. You can extend
the modified equal-element design to Doubling the values of the outside capacitors in an equal-element filter improves passband per-
highpass LC filters. Both equal-element formance.
and modified equal-element filters use
the normalized highpass prototype (Fig- TABLE 1—MEASURED RESPONSE FOR 3.56-MHZ MODIFIED HIGHPASS FILTER
ure 1). For the equal-element filter, the Frequency (MHz) Insertion loss (dB) Frequency (MHz) Insertion loss (dB)
normalized value of the outside capaci- 2.9 39 6 0.4
tors C1 and C5 is 1; for the modified 2.95 34 6.5 0.25
equal-element filter, it’s 2. The design ref- 3.1 29.8 7 0.2
erence frequency, at normalized frequen- 3.3 19.8 8 0.2
cy x51.0, is not the 3-dB cutoff frequen- 3.5 9.8 10 0.1
cy for the filters in Figure 1. The 3-dB 3.6 4.5 15 0.15
cutoff frequency occurs close to x51.9. 3.7 1.2 20 0.1
In contrast, in Butterworth and Cheby- 3.8 1 25 0.15
shev filters, x can equal 1.0 at the 3-dB 3.9 1.7 30 0.2
cutoff frequencies. You use this different 4 2 40 0.2
normalization method to calculate the 4.2 1.7 50 0.25
values of the circuit elements. 4.5 0.8 60 0.35
We designed, assembled, and tested 5 0.25 80 0.2
two nine-pole, modified equal-element 5.5 0.4 100 0.4
filters. The filters used vector boards in
die-cast aluminum boxes with BNCs. All
TABLE 2—MEASURED RESPONSE FOR 11.17-MHz MODIFIED HIGHPASS FILTER
Frequency (MHz) Insertion loss (dB) Frequency (MHz) Insertion loss (dB)
9 37.8 13 1.4
Highpass filters use 9.5 30 13.5 0.85
modified equal-element design ..............103 10 22 14 0.4
Position detectors provide 10.5 15 14.5 0.25
motor-control logic......................................104 11 7 15 0.25
11.2 2.8 17.5 0.4
Bipolar transistor boosts
11.4 1 19 0.45
switcher’s current by 12 times ..................106
11.6 0.8 20 0.4
Negative resistor cancels 11.8 1.2 25 0.3
op-amp load ................................................108 12 1.5 30 0.2
Op amps make JFET circuits 12.2 1.8 40 0.2
repeatable ....................................................108 12.4 2 50 0.2
12.6 1.8 60 to 100 Less than 0.6
12.8 1.6
www.ednmag.com May 2 4, 2001 | edn 103

design
ideas
capacitors were 65% polypropylene quency of 21.22 MHz. Assuming a ratio ter to obtain a bandpass filter of high
units. We selected the filter design fre- of 1.902-to-1, this figure corresponds to bandwidth. This technique provides an
quencies based on available capacitor a cutoff frequency of 11.168 MHz. After alternative to using image parameters
values. The first filter had a reference fre- denormalizing the filter to actual circuit (Reference 3).
quency of 6.773 MHz. Assuming a ratio values (as in Reference 1), we determined
of 1.902-to-1, this figure corresponds to all inductor values, L1 through L4, to be References
a cutoff frequency of 3.561 MHz. After 0.375 mH. The interior filter capacitors, 1. Kurzrok, Richard, “Equal-element
denormalizing the filter to actual circuit C2, C3, and C4, are equal to 150 pF. The filter improves passband performance,”
values (as in Reference 1), we determined filter’s input and output capacitors, C1 EDN, March 15, 2001, pg 123.
all inductor values, L1 through L4, to be and C5, are then equal to 300 pF. To ob- 2. Taub, JJ, “Design of Minimum Loss
1.175 mH. The interior filter capacitors, tain this value, we connected two stan- Bandpass Filters,” Microwave Journal,
C2, C3, and C4, are equal to 470 pF. The dard 150-pF capacitors in parallel. All the November 1963, pg 67.
filter’s input and output capacitors, C1 inductors used 10 turns of number 26 3. Kurzrok, Richard, “Wideband filter
and C5, are then equal to 940 pF. To ob- magnet wire wound on Micro Metals uses image parameters,” EDN, Oct 26,
tain this value, we connected standard T25-6 toroids. Table 2 shows the meas- 2000, pg 174.
820- and 120-pF capacitors in parallel. ured amplitude response. Assuming in-
All the inductors used 15 turns of num- ductor unloaded Q of approximately
ber 26 magnet wire wound on Micro 100, the measured data shows good cor-
Metals T37-2 toroids. Table 1 shows the relation with calculated values. You can Is this the best Design Idea in this
measured amplitude response. cascade the modified equal-element issue? Vote at www.ednmag.com/edn
The second filter had a reference fre- highpass filter with a similar lowpass fil- mag/vote.asp.
Position detectors provide motor-control logic

Steve Pomeroy and Russell Hedges, Elgar Corp, San Diego, CA
n the circuit of Figure 1, assume
I that a brush-type dc motor

must drive a load back and
forth between two endpoints on a lead
Figure 1
R2
15
C2
0.1 mF
screw. Optical sensors determine end of

travel, and an SPDT switch selects to Q1
R1 10k Q431
which end to send the load. The sensors + C1 2.4k
themselves supply all the necessary di- 470 mF
35V S1
rectional logic, and a triac powers the
1.2k
motor with the necessary polarity of half- 13V RMS 1/2W M1
wave pulses from the 13.5V-ac input.
Starting with the load parked at the south
IC2
end, when you set switch S1 to north, the IC1
H21B1
H21B1
ac input connects to the LED in the
north-side sensor, IC1, through current-
limiting resistor R1 and reverse-polarity- D1 D2 D3
1N4002 1N4148 1N4148
protection diode D2. The phototransistor
output from IC1 then supplies firing puls-
es to the gate of triac Q1 during the north-
bound half-cycle, and the load proceeds The optocouplers provide both position-control logic and triac gate drive to the motor.
toward that detector.
Similarly, IC2 drives the motor during gate drives comes from the ac input and imately 2A.You can easily scale the design
the other half-cycle to push the load the half-wave rectifier comprising D1 and for larger or smaller motors.
south, and stops when it reaches the C1. You might need snubber R2 and C2 if
south endpoint. This scheme works even the motor’s inductance causes spurious Is this the best Design Idea in this
when you change the direction switch firings of Q1 during undesired half-cy- issue? Vote at www.ednmag.com/edn
while the load is in motion. Power for the cles. The motor’s stall current is approx- mag/vote.asp.
design
ideas
Bipolar transistor boosts

switcher’s current by 12 times
Wayne Rewinkel, National Semiconductor Corp, Santa Clara, CA
he circuit in Figure 1 uses a mini-
T mal number of external parts

to raise the maximum output
current of a 0.5A buck switching-regula-
Figure 1
VIN
7
R1
0.22
Q1
D44H8
L1
47 mH
tor IC to more than 6A. The circuit ac- 0.04V
VIN R2
commodates input voltages of 15 to 60V 4.7
COILCRAFT
5 8 DMT2-47
and delivers output voltages of 3.3, 5, or OFF VSWITCH
12V, depending on your choice of IC. Fig-
LM2594HVN
ure 2 provides a graph of conversion ef-
C1 + 3.3, 5, OR 12V
ficiency for the three standard output 680 mF VERSION 4
FB VOUT
voltages, plotted over a range of input 63V
voltages extending to 60V. The circuit is GND + C 2
1, 2, 3 6 D1 1000 mF
useful in applications requiring higher MBR660 25V
input voltage, higher current, or both
than is available from standard ICs. The
LM2594HVN is a buck regulator that
switches an internal 0.5A device at 150
kHz. This current suffices to feed the base Less expensive than a “brick” converter, this circuit accommodates high input voltages and output
of Q1 and the bias resistor, R2. The func- currents.
tion of R2 is to quickly turn off Q1, a fast
npn switch with a beta greater than 10 at
90
6A. The purpose of R1 may not be 2A
Figure 2
obvious without some knowledge 6A
12V
of the internal workings of the 2594. Its
85
value is such to produce sufficient volt-
age drop at peak current so Q1 begins to
saturate. The saturation causes Q1’s beta
EFFICIENCY (%) 80 2A
to drop, and, as the transistor’s base cur-
rent rises to more than 0.5A, the 2594 6A
drops into its pulse-by-pulse limited-pro-
tection mode, followed by a reduction in 75
5V
clock frequency if the overload is severe. 2A
This design example uses through-
6A
hole components, because low-ESR ca- 70
3.3V
pacitors and inductors in through-hole
form are inexpensive and easy to find.
Worst-case line and load conditions 10 20 30 40 50 60
cause Q1 and D1 to dissipate 3W each, so VIN
you must choose a heat-sink size to keep The circuit of Figure 1 delivers good efficiency for 15 to 60V inputs.
the temperature rise within acceptable
limits. A heat-sink rating of 6 to 78C/W at high VIN and more than 5W at low VIN. down. If you don’t need the IC’s on/off
can accommodate both devices for op- You should locate R1 away from the reg- feature, then you should also solder Pin 5
eration to 858C ambient temperature. ulator IC to minimize heating. The DIP to the ground plane.
The capacitors are low-ESR types from version of the 2594 dissipates as much as
Nichicon’s PL series (www.nichicon-us. 0.5W at high VIN; you should solder leads Is this the best Design Idea in this
com). R2 dissipates less than 0.25W, but, 1, 2, 3, and 6 to a ground-plane area issue? Vote at www.ednmag.com/edn
at full load current, R1 can dissipate 1W greater than 2 in.2 to avoid thermal shut- mag/vote.asp.

design
ideas
Negative resistor cancels op-amp load
Elliott Simons, Maxim Integrated Products, Sunnyvale, CA
ccurate op amps have high open- Figure 2 presents a practical applica- curate buffer’s load resistance. If these
A loop gain, low offset voltage and cur- tion of the concept. The first op amp is an
rent, low voltage and current noise, accurate, unity-gain buffer, and the sec-
and low distortion. However, they often ond op amp is a high-current, high-
magnitudes match perfectly, the buffer
sees an open circuit at its output. The
buffer drives the positive input of the sec-
lack the ability to provide high output bandwidth, gain-of-2 driver. Because ond amplifier, and the second amplifier,
currents while maintaining all the other R15R2 in this negative-resistance stage, via its negative-resistance input, drives
high-accuracy specifications. In other its input resistance is 2RNF52200V, the load. Gain error, output-current lim-
words, high-accuracy op amps have a which matches the magnitude of the ac- its, and resistor mismatches limit the
problem driving low-impedance loads. minimum resistance the circuit can drive,
One solution to the problem is to but driving a 200V load is easy. That load
“cancel” the load. If your resistive Figure 1 R2 is an order of magnitude lower than the
load is RV and you connect it in parallel load the unassisted accurate amplifier can
with a negative resistor of 2RV, the re- R1 handle without suffering degradation of
sistance of the parallel combination is in- 2 performance. Note that the second op
finite. The circuit of Figure 1 can gener- VOUT amp’s gain error, offset voltage, and off-
ate negative resistance at its input: + set current do not affect the first op amp’s
RIN52RNF(R1/R2). You derive this value RIN accuracy. The step response of this circuit
as follows: N is well-behaved and exhibits no ringing.
VOUT5VIN(11R2/R1); IIN IIN RNF The negative-resistance approach
IIN5(VIN2VOUT)/RNF52(VIN/RNF)(R2/ works equally well with dual-supply op
R1); and This circuit exhibits negative resistance at its amps, because the negative-resistance
RIN5VIN/IIN52RNF(R1/R2). input. portion can both source and sink current.
10V
If the driver op amp does not have built-
R2 in gain-setting resistors, you can set its
Figure 2 noninverting gain closer to unity, there-
500
R1 by allowing both op amps to share a pow-
2
500
er supply. This approach limits the out-
put swing of the accurate op amp, but
5V +
that restriction may be acceptable in a
2 given application. To ensure full band-
width for the accurate op amp, the driv-
VIN + 200 er op amp should have much higher
200
LOAD RNF bandwidth.
MAX4250 VOUT MAX4014
ACCURATE GAIN-OF-2 DRIVER Is this the best Design Idea in this
OP AMP
Connecting a negative resistance in parallel with the load enables a precision op amp to drive 200V. mag/vote.asp.
Op amps make JFET circuits repeatable

Glen Brisebois, Linear Technology Corp, Milpitas, CA
ecause they use practically no bias ance. JFETs are also fast devices, with gar- simple resistor-based bias network, the
B current (a useful feature in itself),

JFETs also have practically no cur-
rent noise. This feature means that you
den-variety types specified in the hun-
dreds of megahertz. On the flip side,
JFETs are difficult to exploit in a manu-
same part number can give results that
differ by several volts from device to de-
vice. One way to use JFETs in a repeatable
can use JFETs in very-high-resistance cir- facturing environment because they have and manufacturable manner is to use the
cuits and obtain good noise perform- widely varying dc specifications. With a topology that Figure 1 shows. The pur-
design
ideas
VS+
D VS+
G N-CHANNEL R1
IN JFET
S
OUT
3 pF
2N5486
PHOTODIODE
INFINEON V S+
+ 2
SFH213FA 2 7
1M 49.9
2 LT1806 VOUT
VS2 3
+
100 pF 4
VS2
R1 VS+ 50
10M VS2
Figure 1 Figure 2 3 + 7
10k
6
LT1097 2N3904
2
2 4
The op amp biases the JFET at IDSS, with VGS
VS2 0.1 mF 2.4k
NOTE:
50V. 33k ADJUST PARASITIC CAPACITANCE
AT R1 FOR DESIRED RESPONSE
CHARACTERISTICS.
2200 pF
VS=65V.
pose of the op amp is to bias the JFET at VS2 V S2
VGS50V and, therefore, at ID5IDSS. It
meets this goal by increasing the current
in the bipolar transistor until VGS50V
and ID5IDSS. This fast, high-gain photodiode amplifier uses Figure 1’s scheme to bias the JFET.
In this condition, the JFET operates at
its highest gain (gm) and lowest voltage- TABLE 1—RESULTS FOR VARIOUS RF WITH 1.2V OUTPUT STEP
noise condition. The JFET operates as a
RF 10 to 90% rise time (nsec) 3-dB bandwidth (MHz)
follower with zero offset. The only re-
100 kVV 64 6.8
quirement for the op amp is that it have
200 kVV 94 4.6
ultralow bias current. A variety of op-
499 kVV 154 3
amp types satisfy this criterion, includ-
1 MV V 263 1.8
ing JFET-input op amps, such as the
LT1462; superbeta-input op
amps, such as the LT1097; and than approximately 10 kV.
micropower op amps, such as Table 1 shows the rise time
the LT1494. Figure 2 shows an and bandwidth achieved for
implementation of the topology several transimpedance gains
of Figure 1, using an inexpen- (as set by RF). To obtain op-
sive, fast 2N5486 JFET. This de- timum speed characteristics,
vice specifies IDSS at 8 to 20 mA you make “parasitic-capaci-
at room temperature. The tance adjustments” (the ca-
LT1097 maintains the gate- pacitor with broken lines in
source voltage at 0V by adjust- Figure 2) by adjusting the
ing the JFET’s drain current. The proximity of RF’s leads to its
source of the JFET connects to body. Figure 3 shows the
the inverting input of the 325- time-domain pulse response
MHz, low-noise LT1806 op with RF51 MV. Connecting
amp. RF closes the loop back to two 499-kV resistors in series
the JFET’s gate. In this applica- improves the response.
tion, the circuit serves as a tran- The circuit of Figure 2 exhibits clean pulse
simpedance amplifier for a fast Figure 3
response with little overshoot or ringing.
photodiode.
Selecting a high value, 10 MV for R1 to attenuate the noise and shape the noise
maintains low noise gain, but you could bandwidth of the slow loop. Measure-
reasonably reduce it to a few times larg- ments show the output-noise spectral Is this the best Design Idea in this
er than RF. The values of the other resis- density is 9 nV/=Hz with RF 50V, so re- issue? Vote at www.ednmag.com/edn
tors and capacitors in the LT1097 loop sistor noise dominates with RF greater mag/vote.asp.

design
ideas
Neat idea nets $1500
in EDN ’s yearly Design Ideas contest
EDN is pleased to announce this year’s $1500 grand-prize ular as low-offset switches in R/2R ladder networks in D/A
winner for Design Ideas: Art Hogrefe of State College, PA, a converters in the 1960s and 1970s. In his eminently useful
consultant who specializes in communications and analog- Design Idea, Hogrefe takes the application a step further and
circuit design. He takes the honor for “Inverted bipolar tran- thoroughly characterizes the bipolar transistor’s attributes
sistor doubles as a signal clamp,” which was published in as a low-offset clamp and rectifier. Check it out for your-
EDN’s Nov 9, 2000, issue. In case you missed it the first time self.
around, you can read all about it below. And be sure to send us your own Design Idea. EDN pub-
In Hogrefe’s innovative idea, he uses a bipolar transistor lishes about 150 Design Ideas per year, and each one is au-
in an inverted configuration as a rectifier, or clamp, with low tomatically entered into a best-of-issue and year-end com-
forward voltage. He offers a meticulously thorough com- petition. You can find guidelines at www.ednmag.com/
parison of the characteristics of the transistor versus those ednmag/write_di.htm along with a coupon to email sub-
of a germanium diode. The idea of using bipolar transis- missions or use the coupon on pg 152 to submit your ideas
tors in an inverted mode is not new: these devices were pop- by mail.
Inverted bipolar transistor

doubles as a signal clamp
Art Hogrefe, Puma Instrumentation, State College, PA
number of circuits, such as level
A detectors and AM demodula-

tors, benefit from a rectifier
with a low offset voltage. Silicon diodes
Figure 1 VBIAS 2
0
have an offset of approximately 0.6V and R1
do not work well in low-level circuitry. A VEBR
22
Schottky diode is a bit better with an off-
set of approximately 0.4V. A few germa- EMITTER
CURRENT 24
nium diodes are still available, but they (mA)
do not tolerate the temperature range of
NOTES: 26
silicon. Also, you can’t include a germa- INVERTED BETA IS LESS THAN 1;
nium diode in an IC. A superior config- FOWARD BETA IS GREATER THAN 100.
MAXIMUM EMITTER VOLTAGE IS 28
uration uses a bipolar transistor for these LESS THAN VEBR+0.6.
applications. USE IB TO SET INVERTED
EMITTER CURRENT. 210
Figure 1 shows the bipolar-inverted- POSITIVE EMITTER VOLTAGE CAUSES 24 22 0 2 4 6 8
clamp circuit and a typical transfer func- INVERTED OPERATION. EMITTER VOLTAGE (V)
NEGATIVE EMITTER VOLTAGE
tion. The collector connects to ground or CAUSES FORWARD-OPERATION, NOTE:
any other desired reference voltage. A HIGH-CURRENT, LOW-IMPEDANCE TRANSFER FUNCTION FOR 2N3904
CLAMP ACTION. WITH 40-mA BASE DRIVE.
fixed current drives the base. In the ab-
sence of any external drive, the emitter (a) (b)
voltage is near zero. Driving the emitter

with an external voltage produces the The bipolar inverted clamp (a) has an excellent rectification characteristic (b) because of the
transfer function in Figure 1. 2N3904’s large forward-beta-to-reverse-beta ratio.
www.ednmag.com June 7, 2001 | edn 149

design
ideas
The circuit achieves this excellent rec-
tification characteristic by using a
Figure 2
transistor with a large forward-
beta-to-reverse-beta ratio. Many of these 10
transistors are still available. The 2N3904
provides excellent characteristics at a low
cost. The reverse beta of the 2N3904 is 1
FORWARD-
only 0.25, so that for positive voltage on TRANSISTOR
the emitter, and, with 40 mA of base drive, EMITTER CURRENT
the emitter, current is around 10 mA. This (mA) 0.1
current is sufficient in most level-detector

applications for which the ac input am-
0.01
plitude changes slowly.
The emitter current at even small neg-
ative voltages is much greater than in the 0.001
inverted region because the forward beta 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VOLTS
of the 2N3904 is greater than 100. Im- NOTES:
pedance is low up to the beta-limited for- =2N3904 INVERTED-CLAMP EMITTER CURRENT.
ward current, at which point the imped- =1N34 GERMANIUM-DIODE FORWARD CURRENT.
ance increases to approximately the value

of R1/beta. Figure 2 shows the forward- A logarithmic scale of the 2N3904’s forward-transistor emitter current and the forward current of
transistor emitter current of the 2N3904 the 1N34 show the impressive response of the 2N3904 at small voltages.
and the forward current of the 1N34
germanium point-contact diode. The 1.4
logarithmic current scale shows
Figure 3 DC OUTPUT VERSUS CARRIER LEVEL
the impressive response of the 1.2
2N3904 at small voltages. 2N3904
Figure 3 shows the output as a level de-
tector for the two clamps. The transistor 1.0
circuit that produced these results is sim- 1N34
ilar to the demodulator in Figure 4 ex- 0.8
OUTPUT
cept the base drive is 40 mA. For the (VDC)
1N34, the anode connects to ground, and
0.6
the cathode connects to the input capac-
itor in place of the transistor’s emitter.
Figure 3 shows that the two configura- 0.4
tions have similar responses to input lev-
els and that the 2N3904 has a bit less off- 0.2
set, as you would expect from Figure 2.
The output can drive a signal level me-
0
ter or following electronics as part of an 0 0.5 1 1.5 2 2.5 3
automatic-level-control or automatic- INPUT (VAC PK-PK)
gain-control loop.
NOTES:
The transfer function in Figure 1 also FOR 2N3904, VDC=0.5VAC20.08, AND IBASE=41 mA.
shows a sudden increase in inverted cur- FOR 1N34, VDC=0.5VAC20.11.
rent at approximately 7.6V, which occurs
at the reverse breakdown voltage for the When operating as demodulators, the two configurations have similar input-level responses.
emitter-to-base junction. Because you
know in this case that the base is near production, such as for test equipment, a base drive current of 300 mA. This cur-
0.6V, the breakdown voltage for the test- it is practical to select individual transis- rent is necessary to track the RF-modu-
ed part is near 7V. Production circuits tors to slightly increase the dynamic lation envelope and depends on the size
would have an input limit of 6.6V p-p be- range. A 6V p-p input dynamic range is of the input capacitor, modulation fre-
cause of the minimum specified break- sufficient in many applications. quency, and maximum signal amplitude.
down voltage of 6V. Note that, for a small The RF demodulator in Figure 4 has The reverse current, which is IBASE times
150 edn | June 7, 2001 www.ednmag.com

design
ideas
the reverse beta, must be large enough to to prevent distortion in the output wave- emitter node and the lower trace at the
discharge the input capacitor at the high- form. Figure 5 shows the running de- output.
est modulation frequency and amplitude modulator with the upper trace at the
Figure 4
6.6V
1-MHz CARRIER
WITH 100% AMPLITUDE
MODULATION AT 5 kHz 20k
120k
OUTPUT
1 nF
1 nF
2N3904
NOTES:
BASE-DRIVE CURRENT IS 300 mA, EMITTER REVERSE CURRENT
IS APPROXIMATELY 75 mA.
2N3904 FORWARD BETA IS GREATER THAN 100;
REVERSE BETA IS APPROXIMATELY 0.25.
EMITTER-BASE REVERSE-BREAKDOWN VOLTAGE IS GREATER THAN 6V.
AC-DRIVE VOLTAGE IS LESS THAN 6.6V P-P.
A scope photo shows the running demodulator;

Using the inverted clamp as an AM demodulator requires a base current Figure 5 the upper trace is the emitter node, and the
of 300 mA to track the RF-modulation envelope. lower trace is the output.
Design Idea Entry Blank

Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for the win-
ning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design, selected among
biweekly winners by vote of editors. Find the entry blank at http://www.ednmag.com/ednmag/di_entry.htm to email submissions.
To: Design Ideas Editor, EDN Magazine

275 Washington St, Newton, MA 02458 Entry blank must accompany all entries. (A separate entry
I hereby submit my Design Ideas entry. (Please print clearly) blank for each author must accompany every entry.) Design entered
must be submitted exclusively to EDN, must not be patented, and
Name must have no patent pending. Design must be original with
author(s), must not have been previously published (limited-distribu-
Title tion house organs excepted), and must have been constructed and
Phone tested. Fully annotate all circuit diagrams. Please submit text, soft-
ware listings, and all other computer-readable documentation on a
E-mail Fax PC disk by mail or by e-mail to b.travis@cahners.com.
Company Exclusive publishing rights remain with Cahners Business
Information unless entry is returned to author, or editor gives written
permission for publication elsewhere. The author must be willing to
sign and return our publication agreement if the Design Idea is
Address accepted for publication and must complete a W-9 tax form (W-8 for
non-US residents) before payment can be processed.
Country Zip
Design Idea Title Signed
Date

design
ideas
Stepdown converter uses

a ceramic output capacitor
Karl R Volk, Maxim Integrated Products, Sunnyvale, CA
any stepdown (buck) dc/dc-con-
M verter ICs incorporate a

voltage-mode-control al-
gorithm. As a result, for stable operation
Figure 1
INPUT
2.7 TO 5.5V IN LX
L1, 10 mH
RL, 0.2 OUTPUT
1.8 OR 1.5V
in continuous-conduction mode, the ap- AT 250 mA
2.2 mF
plication circuit’s output capacitor is nor- COUT
mally a high-ESR tantalum type for two IC1 R1 4.7 mF
MAX1734 5k X5R
reasons. The portion of output ripple due
to ESR provides the current-mode signal
that’s necessary for cycle-to-cycle stabil- OUT
ON SHDN
ity. In the frequency domain, this capac- OFF CFF
itor also provides a zero that cancels a GND
10 nF
620%
pole in the buck converter’s second-order
LC filter, thereby shifting operation back
to the stable region by reducing the rip- A stepdown dc/dc converter, which normally requires a tantalum output capacitor, can operate
ple’s phase shift to less than 908. with a ceramic output capacitor by deriving feedback from the LX pin via the R1/CFF filter.
The circuit in Figure 1, however, allows
the use of an inexpensive ceramic output
capacitor. To remove the effects of CERAMIC COUT TANTALUM COUT
phase lag in the feedback loop, the Figure 2
circuit derives feedback from the LX pin,
via the first-order RC filter comprising R1
and CFF instead of the output. Connect- 50 mV/DIV
VOUT
ing the tail of CFF to the output node in- AC-COUPLED
stead of to ground, as you would for a
normal filter, provides a fast “feedfor-
ward” load-transient response. 200 mA
A ceramic-capacitor circuit offers sev- ILOAD
eral benefits over a standard application 20 mA
circuit. First, ceramic capacitors are more
reliable than tantalum capacitors. Sec-
5 mSEC/DIV 5 mSEC/DIV
ond, ceramic capacitors are more readily (a) (b)
available than tantalum types. Third, ce-
ramic capacitors cause output ripple of Load-transient response waveforms show that using a ceramic output capacitor produces lower
less than 5 mV p-p versus more than 20 output ripple and less overshoot (a) than the standard application circuit with a tantalum output
mV p-p (Figure 2). For this circuit, the capacitor (b).
load-transient overshoot is also lower: meet this requirement, calculate the val-
Stepdown converter uses less than 50 mV p-p versus more than 100 ue of R1:
a ceramic output capacitor ......................154 mV p-p.
Single printer-port pin acts IC1, a stepdown dc/dc converter with  20 mV   L1   ILOADMAX 
an internal synchronous rectifier that R1 ≅    .
as an encoder output ................................156  2 × VOUT   TMIN   2 × IOUTSENSE 
supplies a fixed 1.8 or 1.5V output at 250
VFC makes simple
mA from an input range of 2.7 to 5.5V,
capacitance meter ......................................158
needs 20 mV p-p or more at its output Per the data sheet for the MAX1734,
pin for stable operation under load. To VOUT is 1.5 or 1.8V, L1 is 10 mH, TMIN is 0.4

design
ideas
msec, ILOADMAX is 250 mA, and IOUTSENSE is transients, the inductor series resistance than 200 mV, the peak-to-peak load-
4 mA. The result is R154.3 kV for VOUT5 should be as follows: transient voltage increases, but the dc-
1.8V, and R155.2 kV for VOUT51.5V. You L1 load regulation decreases.
can therefore round R1 to 5 kV. RL ≅ . Finally, choose COUT large enough for
R1 × C FF
Next you calculate the feedforward ca- stability:
pacitor value: Note that this expression is the typi-
 ∆IL 
cal, not the maximum, inductor resist- COUT ≥ 2 ×   × TMIN ,
 20 mV 
 2 × VOUT   TMIN  ance. In this case, the value of RL should
C FF ≤   . be approximately 200 mV, which allows
 20 mV   R1 
you to use a small inductor and causes an where DIL is approximately 100 mA when
approximate efficiency drop of only 3% the MAX1734 operates with a 10-mH in-
If R155 kV and VOUT51.5V, then at maximum loads and much less at ductor. In this case, COUT should be
CFFm12 nF. Select CFF510 nF. Choosing lighter loads. Because the inductor time greater than 4 mF.
a much smaller value causes excessive constant, L1/RL, matches the feedback
load-transient overshoot, and choosing a time constant, R13CFF, the short-term Is this the best Design Idea in this
larger value causes instability under load-transient response equals the dc issue? Vote at www.ednmag.com/edn
loaded conditions. For optimized load load regulation (Figure 2). If RL is less mag/vote.asp.
Single printer-port pin acts as an encoder output

Haobin Dong, Huazhong University of Science and Technology, China
ncoders and decoders are com-
E mon elements in alarm, re-

mote-control, and measure-
ment systems. However, most of these
Figure 1 TE
ENCODER
1 WORD
DOUT
devices require many I/O lines when un- TRANSMITTED
4 WORDS 4 WORDS
der microprocessor or PC control. For CONTINUOUSLY
example, the HT-12E encoder has eight
address pins, four data pins, and one At power-up, the HT-12E encoder begins a 4-word transmission cycle.
transmit-enable-control pin. As an alter-
native, you can simulate the HT-
12E using a single pin of a PC’s Figure 2
printer port as the encoder output. Soft- ONE-THIRD-BIT
ware determines the functions of the en- SYNC PERIOD
DATA-CODE
coder. 12-BIT PILOT PERIOD ADDRESS-CODE PERIOD PERIOD
The HT-12E is a CMOS IC. This en-
coder serially transmits data as defined One complete transmission period includes a pilot period, a bit-sync period, an address-code peri-
by the state of the A0 to A7 and D0 to D3 od, and a data-code period.
input pints. On power-up, the DOUT pin
is low. The HT-12E begins a 4-word the status of the 12 bits of address and pler and the decoder, IC1. The encoder
transmission cycle on receipt of a trans- data in the order of A0 to A8 and D0 to D3 output comes from printer Port Pin 2 of
mission enable, or TE, signal, which is (Figure 2). the DB25 connector. The data port is at
active low. The cycle repeats as long as The IC encodes each logic high or low address 0x378h of the PC’s LPT. R1 lim-
the TE signal is low. When TE goes high, into pulses (Figure 3). The encoder rep- its drive current from the PC’s printer
the encoder completes its final 4-word resents a logic low as a long pulse (011) port. IC2’s Schmitt trigger shapes the op-
transmission cycle and then stops (Fig- and a logic high as a short pulse (001). tocoupler’s output. The D0 pin of IC1
ure 1). Every logic bit takes three OSC periods. connects to R2 and an LED.
You can preset the status of each ad- The information sequentially transmits According to Figure 2 and Figure 3,
dress or data pin independently to logic via the DOUT pin. one complete transmission period con-
high or low. If the TE signal is low, the en- Figure 4 shows the test circuit for a vir- sists of 73 OSC periods. The pilot peri-
coder scans and sequentially transmits tual encoder that includes an optocou- od, which is 12 bits, is all logic low (0, 36
design
ideas
OSC periods) followed by a one-third-
bit sync period (one OSC). After FOSC
Figure 3
those periods follows 8 bits of
"ONE"
address and 4 bits of data, all of which
need 36 OSC periods. Every bit of ad-
"ZERO"
dress or data is either a “001” encoded ADDRESS/
pulse for a logic high or a “011” for all DATA BIT
other cases. A time interval exists be- A short pulse of “001” represents a logic high, or a “one,” and a long pulse of “011” represents a
tween two pulses, and a software loop logic low, or a “zero.”
controls the interval. Also, the interval
5V
must be in accordance with the OSC pe- 6N136
riods of the decoder. R1

8
Software listings consist of implemen- 300
2 4.7k
IC2
74HC14
2
tation routines in Turbo C, the 6 1 2 TO OTHER
main code for determining the Figure 4 3 HT-12D
5
delay time, and a test-program site. You 25 5V
R2
100k
can download the listings from EDN’s PRINTER-
470
18
Web site, www.ednmag.com. Click on PORT 16 15 14 10
DB25 VCC OSC1 OSC2 DIN D0
“Search Databases” and then enter the CONNECTOR
IC1
Software Center to download the file for HT-12D
Design Idea #2713. The delay time,T_de- A0 A1 A2 A3 A4 A5 A6 A7 GND

1 2 3 4 5 6 7 8 9
lay, is a global variable in the codes. The
variables T_min, T_max, and T_step are ADDRESS=0300
properly predefined based on the PC. Af-

ter you compile and execute the delay- A test circuit includes an optocoupler and a decoder IC.
time program, the T_delay value is read
when the LED starts to flash. The value you will observe that the LED continues Is this the best Design Idea in this
for the current design and the PC is 1000. to flash until you hit any key to stop the issue? Vote at www.ednmag.com/edn
Compile and run the test program, and code. mag/vote.asp.
VFC makes simple capacitance meter

K Suresh, Indira Gandhi Centre for Atomic Research, Kalpakkam, India
hen you develop the prototype
W
R3
of a circuit using capacitors 20k
Figure 1 330
or when you replace an VS=5V 9 10
old, defective capacitor with a new one, 13
14 ● FREQUENCY COUNTER
0.01 mF VIN ● DMM WITH FREQUENCY-
you often need to know the value of the 2
1
FOUT= .
10(R1+R2)•CX MEASUREMENT FEATURE
capacitor you use or replace. At times, the A
11
IC1 8 ● PC's PARALLEL PORT
CX
values printed on the capacitors are no AD537
12 VOLTAGE/
longer readable. Also, the wide tolerance A' FREQUENCY 4 CX=(1024/FOUT)FARADS
VIN CONVERTER R1
band of the capacitors can leave you mak- 5
3 820
ing a wild guess about the capacitor val- VREF
0.1%
ue. In these situations, you normally go V EXT 7

1V R2
looking for an LCR bridge of a DMM 500
with a capacitance-measurement facility.

Not all DMMs have this feature, and find-
ing the capacitance value from an LCR A simple VFC uses its internal reference to produce a serial pulse train whose frequency is inverse-
bridge is a cumbersome process. ly proportional to unknown capacitance CX. Options for measuring the VFC’s output include: using a
An alternative is a simple, low-cost frequency counter, using a DMM with a frequency-measurement feature, and hooking the output to
VFC (voltage/frequency converter) with a PC parallel port through simple counters and buffers.
a few inexpensive components (Figure
1). This circuit can measure capacitance VIN where VIN is in volts, R1 and R2 are in
FOUT = Hz,
values of nanofarads to tens of micro- 10(R1 + R 2 ) × C ohms, and C is in farads. For IC1, with an
farads. The output transfer function is input range of 0 to 10V, the output of the
design
ideas
VFC is a serial pulse train in the frequency range of 0 to 150
kHz with a nonlinearity error of less than 0.05%.
In normal operation of the VFC, you provide a VIN of 0 to
10V and choose R1 and R2 such that you get VIN/(R11R2), a cur-
rent range of 0 to 1 mA to obtain a good linearity between VIN
and FOUT. However, in this design, there is no external input to
the VFC. Instead, the design exploits an internal reference volt-
age, VREF, by simply connecting the VREF output to the VIN in-
put. To avoid the possibility of loading the reference source,
you can also apply VREF to VIN through a buffer. Also, you can
use an external voltage input from a constant voltage source,
such as a battery, and connect it, as the dotted lines in the fig-
ure indicate.
To measure an unknown capacitance value, you connect the
capacitor between terminals A and A’ very close to the VFC.
With VIN5VREF51.00V and R11R2 trimmed to 1 kV, the re-
sulting output of the VFC is a serial pulse train whose frequency
varies inversely with the value of the unknown capacitance CX
as follows:
1014
CX = FARADS.
FOUT
You use the R3 and R2 trims to obtain calibrations at the high-

er and lower ends of the capacitance range, respectively. Thus,
after due calibration, a 1-Hz output of the VFC indicates the
unknown capacitance as 100 mF, and the maximum output of
the VFC, 150 kHz, indicates that the capacitance is approxi-
mately 0.6 nF. If you want to increase the measurable capaci-
tance range, you use a VFC with a wider output-frequency
range, such as 0 to 1 MHz. In this case, you must take care of
the parasitic capacitances.
You can measure the output of Figure 1’s circuit in a num-
ber of ways. One simple and direct approach is to use a simple
frequency counter or a low-cost DMM with a frequency-meas-
uring feature. Thus, the simple VFC becomes a handy capaci-
tance interface for your DMM to enable you to measure the ca-
pacitance. Alternatively, you can also use a programmable
counter, such as the Intel 8254, which is available in most PC
add-on cards. One more approach is to attach a simple 16-bit
counter, such as the CD4040 and CD4520, to your printer port
using the necessary buffering and control (Reference 1). In the
last two cases, you can exploit a special BIOS interrupt, INT1Ch
of your PC, without affecting its normal service routine to pro-
vide a measuring window of 1 second. During the measuring
window, the serial output of the VFC drives a counter. A the
end of the measuring window, the counter contents transfer
to the PC, and you manipulate the data to display the unknown
capacitance value directly on the PC’s screen.
Reference
1. “Use your printer port as a high-current ammeter,” EDN,
July 6, 2000, pg 144.
Is this the best Design Idea in this issue? Vote at www.

ednmag.com/ednmag/vote.asp.

design
ideas
Differential amp drives high-speed ADC
Chau Tran, Analog Devices Inc, Wilmington, MA
he schematic in Figure 1 is the dis-
T crete-element version of an A/D-

converter drive circuit. The circuit
converts a single-ended input to a dif-
VIN
+
62
78 467
+
AD9631
2
15
AIN
ferential output. The ADC’s reference 350

1000
voltage determines the common-mode
range of the differential outputs. The + VREF
circuit contains two AD9631 750 1/2 0.1 0.1
Figure 1 2 OP279 mF mF
amplifiers—one connected in 1/2 2
OP279 AD6640
noninverting mode, and the other con- +
nected in inverting mode. The OP279 0.1 mF
425
amplifiers buffer and scale the ADC’s 467 350
reference voltage to set the common-
350
mode range of the two outputs. The cir- 2
15
cuit in Figure 1 requires many resistors. AD9631 AIN
The two 15V resistors help prevent os- +
cillation arising from the capacitive in- 127
puts of the ADC. The circuit has sever-
al disadvantages, such as poor gain
accuracy, high distortion, and limited This ADC driver uses many resistors and is prone to errors.
speed. The circuit in Figure 2 is an im-
proved ADC driver.
The circuit consists of one AD8132 am- RF
plifier and four resistors. You can

set the gain of the system by ad- Figure 2
AD8132
VOM
justing the ratio of RF to RG. The input ac-
commodates both single-ended and dif- S 5 AIN
R1
2.5k 1k
VOCM
RG 2
Differential amp drives VIN 8 + R2
high-speed ADC ..........................................107 2.5k 1k
RG AD6640
+
1 2
Circuit provides flexible VREF
gain ranges ..................................................108
High-resolution volume-unit meter
S 4 AIN
simplifies CD recording ..............................110
VOP
Small, portable altimeter VCM
2
operates from a single cell ........................112
Circuit breaker monitors RF
leakage current ............................................116
An integrated amplifier provides improved accuracy and higher speed.
www.ednmag.com June 21, 2001 | edn 107

design
ideas
ferential signals. The circuit in Figure 2 Figure 4 shows the gain error and the low vides level-shifting to the reference volt-
is a low-distortion, high-speed (300- distortion in the circuit of Figure 2. The age of the ADC.
MHz-bandwidth) driver.You can also use waveform at the node VOCM indicates the
it to drive precision delta-sigma ADCs. output-balance error. The topology of Is this the best Design Idea in this
Figure 3 shows the performance at 10 Figure 2’s circuit also improves the com- issue? Vote at www.ednmag.com/edn
MHz and unity gain (RF5RG5499V). mon-mode rejection ratio, because it pro- mag/vote.asp.
VIN
500 mV p-p VIN
10 MHz 500 mV p-p
10 MHz
VOP VOCM
10 mV/DIV
VOM
At 10 MHz and unity gain, the out-of-phase The output-balance error in Figure 2’s circuit
Figure 3 outputs have low distortion. Figure 4 is lower than 1 mV with a 500-mV, 10-MHz
input signal.
Circuit provides flexible gain ranges

Luo BenCheng, Chinese Academy of Sciences, Beijing, China
ertain designs need a program- the gain from 1 to 1000. IC2, a CD4051, You can compute the weighting resistors,
C mable-gain amplifier with a wide is a programmable, low-voltage 1-of-8 R0 to R7, for a given input-output signal
gain range and high accuracy and analog multiplexer, which connects to range as follows: VOUT5VIN(112RK/-
common-mode rejection. Usually, it’s eight weighting resistors, R0 to R7, to in- (RX1RON)), where RON is the on resist-
wise to exploit a programmable-gain increase the gain range of the circuit. The ance of the CD4051, typically 125V. RK is
strumentation amplifier, such as an overall gain of the circuit depends on the the 50-kV internal feedback resistor of
AD625. Unfortunately, the gain range of value of the selected weighting resistor. the AD623, and RX is one of the selected
such standard parts is weighting resistors. IC3, a
VCC
fixed at certain values, lim- Z4
C
CD4052, is a 2-of-8 program-
Z3
iting their flexibility. Fig- CHANNEL
Z
B IC2
8
7
4
VSS mable-difference-input IC.
SELECT 2 CD4051 +
ure 1 shows a multichan- A IC1 6 VOUT
You can control the port-se-
AD623
nel, eight-level-program- VSS R0 R1 R2 R3 R4 R5 R6 R7 1 2 5 lect pins, Z0 and Z1, of IC3 and
3
mable-difference-amp- 2 Z2 to Z4 of IC2 with a mC, such
lifier circuit. IC1, an Z1
A 13
as an AT89C51 or an 80C196.
Z0
AD623, operates from a B
IC3
CD4052 3 With the aid of some software,
single supply. This ampli- the circuit can provide self-ad-
V2 V+ VSS
fier is a low-power, low- VSS justing gain.
INPUT DIFFERENCE SIGNAL
cost instrumenta-
Figure 1
tion amplifier that Is this the best Design Idea in
offers good accuracy. A You choose the weighting resistors to obtain the optimum gain ranges for this issue? Vote at www.edn
single external resistor sets your application. mag.com/ednmag/vote.asp.

design
ideas
High-resolution volume-unit meter
simplifies CD recording
Chester Simpson, National Semiconductor, Santa Clara, CA
igitally recorded music on CDs acteristic: The average volume levels of the on a single CD. This variation can be a
D offers superior quality to that record-

ed on vinyl records or tape, but most
prerecorded CDs have an annoying char-
recorded signal can vary by as much as 14
dB from disk to disk. Significant variances,
such as 4 dB, can occur from track to track
problem when recording your own CDs
because you can end up with large varia-
tions in loudness between songs.
Figure 1
NOTES:
1. ALL CAPACITORS ARE CERAMIC.
2. R5 IS A 100-kV AUDIO-TAPER 3
CD RECORDING RECEIVER/ POTENTIOMETER; R1 IS A 10-kV LINEAR
DECK AMPLIFIER POTENTIOMETER; AND ALL IC2
OTHER RESISTORS ARE 1/8W, 5%. LM3914
2
LINE OUT CD INPUT 10
6 3.6 dB
L +
L R R
1k 2 11
3 dB
+
L R3 7 1.25V
R
VOLUME- 1k REFERENCE 1k
UNIT 2 12
METER 2.3 dB
+
JACKS
1k
0.01 mF 0.01 mF 2 13
R4 1.6 dB
+
430
51k 51k ON POWER 1k
0.1 mF ON 8 2 14
0.9 dB
+
+
2k 1k
8 2 15 D1
3 0 dB
+ 9V +
IC1A 1 ALKALINE
LM358 1k
2
2 3.3V 2
4 16
20.9 dB
+
R5 1k
2 17
100k 9 22 dB
N/C BAR/DOT +
AUDIO
GAIN ADJUST SELECT
1k
2 18
CW 23.2 dB
+
1k
2 1
24.6 dB
+
1k
5 RISE-TIME R2 4
+ 1N914 ADJUST 820
IC1B
6 7
2
200k 20k CW
2
C1
1 mF 5
R1 +
1N914
10k 560k
LINEAR
200k 2
A high-resolution, average- (not peak-) reading volume-unit meter produces an accurate reading of loudness.

design
ideas
CD digital-recording decks typically Another feature of IC2 is that the re- depends on R1’s setting. This bandwidth
have peak-reading-only volume-level sistors connected to Pin 7 externally pro- selects the range of sound that most re-
meters. This feature is adequate to pre- gram the LED current. The resistor val- flects perceived loudness based on the
vent clipping but does a poor job of ues in Figure 1 result in an LED current ear’s frequency response. Lower bass sig-
reading the average volume, or loud- of approximately 8 mA. To conserve nals typically have large signal levels in
ness, level. If you set the recording lev- power, the circuit leaves the bar/dot-se- absolute magnitude, but the ear hears
els just below the peak clip level, average lect pin, Pin 9, open to select “dot” mode. these signals less due to the Fletcher-
volume variances of 6 to 8 dB can result IC2 has some built-in overlap, so that at Munson effect. If they register on the me-
due to varying levels of dynamic-range least three LEDs are on at any time dur- ter display, the bass-frequency signals
compression in recording the original ing typical operation of the meter, which would indicate higher loudness than you
material. eliminates flicker and makes the meter actually hear.
A high-resolution, average- (not peak-) easier to view. The ear also perceives very-high-fre-
reading volume-unit meter produces an You use this volume-unit meter with quency sounds less loudly than absolute
accurate reading of loudness (Figure 1). the peak-reading meter in the recording magnitude would suggest, although the
The meter connects to the line outputs deck. You should initially set up the effect is not as pronounced as the low-
from the recording deck to monitor sig- recording levels by finding the loudest frequency roll-off. So, to get an accurate
nal level. IC1A sums the left and right portion of the music and adjusting the approximation of loudness, the meter
channels and adjusts gain. This adjust- record level of the deck to approximate- measures the middle range where the ear
ment allows you to calibrate the 0-dB ly 4 to 5 dB below the peak clip level the is most sensitive.
LED, D1, to the signal level of your CD meter shows on the CD deck. The CD- The battery current was measured and
recorder. deck makers advise against any clipping found to be 22 mA while operating,
IC1B is a precision rectifier, which sends because it causes distortion. Backing off which means the expected battery life of
the positive portion of the signal to the by 4 to 5 dB from the clip level allows a 9V alkaline battery should be at least 20
input of IC2, an LM3914 dot/bar-display some headroom in case later-recorded hours. Because the meter sets only record
IC. R1, R2, and C1 filter the signal to the tracks have higher dynamic range (the levels, you can switch it off during
input of IC2 to provide an averaging ef- ratio of peak signal level to average signal recording to conserve the battery.
fect. R1 adjusts the rise time of the sig- level). You should then set the gain-ad- The circuit connections to the external
nal, which increases or decreases the me- just potentiometer, R5, so that the 0-dB stereo system are in the line coming from
ter’s ability to track a fast rising signal. LED lights on the loudest sound. Adjust the line outputs of the CD-recording
Increasing R1 slows rise time, making the subsequent track-record levels to this deck and going to the input of the re-
meter more average-reading than peak- same level, based on the average loud- ceiver/amp. The meter effectively con-
reading. ness, to ensure that the deck’s recording nects in parallel with the input of the re-
IC2 contains all the necessary circuit- meter does not exceed the clip level. ceiver/amp. For this reason the volume-
ry to drive a 10-LED string as well as an Adjust R1, the rise-time adjust, so that unit meter’s input impedance is very high
internal reference. R3 and R4 bias up the the meter will respond to average level to prevent loading the line output.
bottom of the resistor string to 0.4V changes but miss fast peaks. This control
above the ground pin, which effectively is user-adjustable, and the optimum set-
reduces the total decibel range of the me- ting depends on the music type. Is this the best Design Idea in this
ter and increases the resolution and ac- The meter’s bandwidth is approxi- issue? Vote at www.ednmag.com/edn
curacy of each LED step. mately 250 Hz to 2 kHz; the upper limit mag/vote.asp.
Small, portable altimeter

operates from a single cell
Todd Owen, Linear Technology Corp, Milpitas, CA
ome sports enthusiasts want to and compensating for nonlinearities in sure transducer. The circuit takes advan-
S know altitude changes from an ini-

tial elevation. A small, lightweight,
portable altimeter is easy to design using
air-pressure changes with respect to alti-
tude produces a reasonably accurate al-
timeter.
tage of the inverse relationship between
air pressure and altitude. The aim of this
circuit is to be small, lightweight, and
modern micromachined pressure trans- Figure 1 shows a small, handheld al- portable. Accuracy is not paramount; er-
ducers. Inverting barometric pressure timeter based on a micromachined pres- rors as high as 3%, such as a 300-ft error
design
ideas
at 10,000-ft altitude, are acceptable. The ciated components then inverts the out- a DeHavilland DHC-6 Twin Otter for an
speed of the circuit is also not critical: Ex- put of the instrumentation to provide a ascent to 13,000 ft, followed by free de-
treme changes in altitude in milliseconds voltage that is inversely proportional to scent—limited by the engineer’s parasitic
may prove fatal to whoever is attempting air pressure. D4 and R1 introduce the drag—to 3000 ft. Subsequent deploy-
to read the output. nonlinear gain, and the final output is di- ment of an aerodynamic decelerator
The heart of the altimeter is an NPC- rectly proportional to altitude. (Precision Aerodynamics Icarus Omega
1220-015-A-3L pressure transducer. This R2 performs gain calibration in the sig- 190) prevented engineer injury or circuit
5-kV bridge provides 0 to 50 mV of out- nal-conditioning circuitry. This poten- damage. Aircraft rental for testing is avail-
put voltage for a 0- to 15-psi pressure tiometer calibrates out any normal variable at many local airports. Extensive in-
range. To power the transducer and sig- ations in part tolerances and sets the struction in free descent and the use of
nal-conditioning circuitry, a micropow- altimeter for a 100-mV change in output aerodynamic decelerators are highly rec-
er dc/dc converter, IC1, generates 5V from for every 1000 ft of altitude. The circuit ommended before undertaking testing of
a single AA battery, and a charge pump has some initial offset, as well as an off- this nature. Contact USPA at 1-703-836-
generates a 25V supply. set that is determined by barometric- 3495 for further information.
The output of the transducer drives an pressure variations. You can use R3 to R5
instrumentation amplifier, IC2, which to null this offset, giving a 0 to 1V out- Is this the best Design Idea in this
provides an initial gain of 21. A nonlin- put for 0 to 10,000 ft of altitude. issue? Vote at www.ednmag.com/edn
ear gain stage comprising IC3B and asso- Altimeter testing was performed using mag/vote.asp.
25V
D1
10 mF D2 10 mF
Figure 1
+ +
L1
10 mH D3
5V
6 36k
220 pF IN 5
IC1 SW
3 1M
LT1307
V125
SHDN 10 mF
1.5V
AA CELL 1 2
VCC FB
GND
4 LT100421.2
100k 324k
1000 pF
5V
LUCAS NOVASENSOR
8 NPC-1220-015A-3L
V125 3 + R1
IC3B 1 4 D4
5V 56.2k 169k
LT1490
2 1 1 1 2 R2
7 1N5711
4 1 10k
1 IC2
38.3k 6
2.43k LT1167 1IC
G421 3A
15V ` 5 LT1490
243k 5
` 3 8 4 V125 `
3 V125
1
15V TO 4 2 -
R3 DIGIT DVM
549k 59k
1k 2
R4
50k
6
RSET R5 0 TO 2V4
14.3k 0 TO 20,000 FT
NOTES:
5
D1 TO D3: MOTOROLA MBR0520L.
L1: COILCRAFT D01608-103.
To produce a reasonably accurate altimeter, conditioning circuitry inverts the barometric pressure of a micromachined pressure transducer and com-
pensates for nonlinearities in air-pressure changes with respect to altitude.

design
ideas
Circuit breaker monitors leakage current
Sharath Kumar, Gemplus R&D Centre, Dubai, United Arab Emirates
he residual-current circuit break- ever, if this voltage exceeds tolerable lim- output goes high. This output controls
T er in Figure 1 continuously monitors its, the circuit immediately deactivates Q1. When Q1 turns on, Q2 turns off,
the supply lines for any leakage cur- the relay, thereby disconnecting the faulty which deactivates the relay.
rent and immediately disconnects the load. Any further or repeated attempts to Two trim potentiometers facilitate
supply if necessary. Load-supply wires, restart the device with the faulty load re- tripping at user-preset levels. R2 controls
both live and neutral, pass through the sult in repeated tripping of the relay. You the coarse setting, and R1 provides for fin-
magnetic core of the CR4311-5 trans- have to manually disconnect the faulty er adjustments. Typically, the muscles in
ducer (www.crmagnetics.com), which load and restart the device. the human body can tolerate current up
monitors the supply current. Under nor- The circuit configures IC1B as a preci- to 20 mA. Hence, R1 and R2 must have
mal circumstances, because the current sion, fast-acting voltage comparator. IC1A settings that cause the relay to trip at leak-
flowing in both conductors is equal and provides a stable 6V reference to IC1B. age currents of greater than 15 mA that
opposite, no flux is generated in the When the voltage on the noninverting in- the transducer senses from the load-
transducer core. However, under faulty put of IC1B rises above the preset refer- mains supply wires. R3 allows control
conditions, the current in the live wire ex- ence voltage on its inverting input, the over the hysteresis. D1 to D3 provide pro-
ceeds the current in the neutral tection. C1 and C2 are decoupling
wire, which catalyzes the produc- and charge-pump capacitors, re-
tion of flux in the core. spectively.
Figure 2 TRANSDUCER
This transducer core has a CR4311-5 A 12V, 0.5A mains power-sup-
secondary winding that generates ply unit is sufficient to effectively
a voltage based on the produced run the circuit. The relay contacts
AC MAINS TO
flux. The generated voltage ranges SUPPLY SECONDARY LOAD must have a rating suitable for the
from 0 to 10V and is directly pro- load. Figure 2 shows the wiring
portional to the sensed ac cur- layout for attaching the circuit to
rents. an ac-mains circuit. All compo-
A high-speed comparator, IC1B, RESIDUAL-CURRENT nents are standard industrial
CIRCUIT BREAKER
detects this generated voltage and RELAY grades and are commonly avail-
12V DPDT
compares it with a set reference. If able.
the detected voltage is within a
tolerable range, the relay remains The residual-current circuit breaker uses a transducer to moni- Is this the best Design Idea in
active, and the load remains con- tor the supply current and a relay to disconnect the mains from this issue? Vote at www.edn
nected to the mains supply. How- the load. mag.com/ednmag/vote.asp.
VCC
12V
RELAY
Figure 1 12V DPDT
C1 C2 NC
+
0.1 mF 100 mF D1
2.2k 25V DC
D2 1N4148
NO TO LOAD
1N4148 100 pF
4.7k
TRANSDUCER IC1A 1M
CR4311-5 10M AC MAINS
68k 5 LM319A 2.2k
SUPPLY
+ D3
12 Q2
3.9V 1N4148 9
4 + BC107
2 R1 7 10k Q1
5k IC1B
220k 10 BC148
SECONDARY 2
R2 220k 22k
10k
100k 270k R3
2.2k
IC1B is a precision, fast-acting comparator and controls whether the relay is active based on a preset reference-voltage level.

design
ideas
Circuit yields accurate absolute values
Marco Pisani, Istituto di Metrologia G Colonnetti, Turin, Italy
he circuit in Figure 1 delivers the
T absolute value of the input

signal with an accuracy better
than 10 ppm of the full-scale range. The
Figure 1
VIN +
_
IC1
circuit has low zero-crossing error. You

R
can use it as an asynchronous demodu-
D D
lator, as a source for logarithmic ampli- R 1 2 2R
fiers, or simply as a demonstration of the

_
wonders of feedback. The circuit uses two
R IC2 VOUT=VIN
op amps; five identical resistors, R; one R
+
double-value resistor, 2R; and four ther-
D3 D4
mally matched diodes. When the input,
VIN, is positive, IC1’s output is 2VIN1VD3
(the voltage drop across D3). D2 is re- This full-wave rectifier circuit yields the accurate absolute value of the input signal.
verse-biased, thus IC2 behaves as a volt-
age follower, yielding VOUT5
R(VIC12VD4)/2R. Because the same
amount of current (VIN/R) flows in D3
and D4, assuming their characteristics are
the same, VD35VD4, and VOUT5VIN.
When VIN is negative, IC1’s output is
2VIN2VD1. D4 is reverse-biased, and IC2
is an inverting amplifier, yielding
VOUT5R(VIC11VD2)/2R. Again, the cur-
rent flowing in D1 and D2 is VIN/R, and
VOUT52VIN. For good performance,
● The six resistors must match close-
ly to guarantee symmetrical gain.
● The diode pairs, D1-D2 and D3-D4,
must have tight thermal coupling to
minimize errors at low input
voltages. (It’s best if the pairs Figure 2
are on the same chip.)
Even with a 40-mV p-p signal, the circuit in Figure 1 yields an accurate absolute value.
Circuit yields accurate absolute ● The op amps must have low offset. amps’ offset and tweaking the resistors,
values..............................................................125 In a practical configuration, you can the residual error is within 100 mV p-p
ADC enables temperature-compensated configure D1 through D4 using base-col- over the 13V p-p operating range. Figure
weigh-scale measurements ......................126 lector junctions of a monolithic transis- 2 shows the behavior of the circuit with
tor array, such as an MPQ6700. The re- a 40-mV p-p input signal (bottom trace).
Single cell lights any LED ..........................128
sistors are 10- and 20-kV, 1% metal-film
Lowpass filter uses only two values ........130 units. You can use optional 100V trim-
Quickly discharge power-supply mers in series with the resistors in the cir-
capacitors ......................................................132 cuit to trim for optimum performance. Is this the best Design Idea in this
The op amps are OP27 devices, with their issue? Vote at www.ednmag.com/edn
offset trimmed. After adjusting the op mag/vote.asp.
www.ednmag.com July 5, 2001 | edn 125
design
ideas
ADC enables temperature-compensated
weigh-scale measurements
Albert O’Grady, Analog Devices, Limerick, Ireland
ou can provide temperature com-
Y pensation in weigh-scale applica-

tions by simultaneously measuring
both the temperature of the bridge and
EXCITATION VOLTAGE55V
IN`
OUT`
20k
AVDD DVDD
the primary output of the bridge trans- OUT1 AIN1

AIN2 XTAL 1
ducer. Traditionally, an integrated mul-
tiplexer connects multiple input variables IN1 REFIN (`)
32 kHz
to a single sigma-delta ADC. Each time 12k
REFIN (1) XTAL 2
the multiplexer switches the input, the
ADC must flush the digital filter of all
RL1
data pertaining to the previous channel. IOUT 1
Before the new data becomes valid, the RL 2
200 mA
AIN 5
system must account for the settling time
and latency, reducing the maximum THERMISTOR AD7719
1K7A1 RDY
RL3
throughput rate. For example, with an AIN 6 SCLK
ADC containing a second-order sigma- RL4
DIN CONTROLLER
delta modulator and a third-order digital REFIN 2
filter, the output-settling time for a step DOUT
RREF 10k
input is three times the period of P1 CS
the data rate. Switching from the F i g u r e 1
DGND
primary to the secondary channel can re- AGND
PWRGND
duce the primary channel’s throughput
by a factor of six when you need to mon-
itor primary and secondary variables to-
gether. In many cases, you can monitor Two independent ADCs eliminate the throughput limitations of multiplexed measuring systems.
the secondary variable only intermit-
tently and thus minimize the reduction use the bridge-excitation voltage to pro- and 60-Hz rejection by programming the
in throughput. Figure 1 shows a solution vide the reference to the ADC. A resistive AD7719 for an output data rate of 19.8
to the throughput problem that uses the divider, however, allows you to use the Hz. With a gain of 128, the ADC achieves
two independent channels of an AD7719 full dynamic range of the input. This im- 13-bit resolution at this data rate.You can
dual sigma-delta ADC. plementation is fully ratiometric, so vari- increase the resolution by reducing the
The ADCs convert in parallel, so you ations in the excitation voltage do not in- update rate or by providing additional
can simultaneously measure both the troduce errors in the system. digital filtering in the controller.
bridge output and the bridge tempera- The resistor values of 20 and 12 kV in The secondary channel of the AD7719
ture. The output data from both meas- Figure 1 yield a 1.875V reference voltage monitors the bridge temperature with
urements is available in parallel, thereby for the AD7719, with a 5V excitation volt- the aid of a thermistor. An on-chip cur-
removing the latency associated with age. The main-channel (programmable) rent source excites the thermistor and
multiplexed data-acquisition systems. gain is 128, resulting in a full-scale input generates the reference voltage for the
The main channel monitors the bridge span of the ADC equal to the full output AD7719. As a result, excitation signals do
transducer, and the secondary channel span of the transducer. A low-side switch not affect performance, and the config-
monitors the bridge temperature. The disables the transducer to save power in uration is fully ratiometric. The circuit
bridge transducer develops a differential standby mode. The AD7719 features fac- uses a four-wire force/sense configura-
output voltage between the Out(1) and tory calibration, and its signal chain uses tion to reduce the effects of lead resist-
Out(2) terminals. A bridge sensitivity of a chopping scheme to reduce gain and ance. Lead resistance of the drive wires
3 mV/V produces a full-scale output of offset drifts, eliminating the need for field shifts the common-mode voltage but
15 mV when a 5V excitation source pow- calibration. A key requirement in weigh- does not degrade the performance of the
ers the bridge. The ADC’s reference volt- scale applications is the ability to reject circuit. Lead resistance of the sense wires
age can assume any value between and line-frequency components (50 and 60 is immaterial because of the high imped-
including the supply voltages, so you can Hz). You can achieve simultaneous 50- ance of the AD7719’s analog inputs. The
126 edn | July 5, 2001 www.ednmag.com
design
ideas
reference-setting resistor, RREF, must have operating range of the circuit. The max- operating range is 226 to 1708C.
a low temperature coefficient. The imum voltage on the auxiliary input
AD7719 achieves 16-bit resolution in the is REFIN 2 or 2V. With a Betatherm Is this the best Design Idea in this
secondary channel, using a 19.8-Hz up- 1K7A1 thermistor (www.betatherm. issue? Vote at www.ednmag.com/edn
date rate. The thermistor determines the com) and 200-mA excitation current, the mag/vote.asp.
Single cell lights any LED

Al Dutcher, Al Labs, West Deptford, NJ
he circuit in Figure 1 allows supply voltage, the higher the
T you to light any type

of LED from a single
cell whose voltage ranges from 1 to
Figure 1
D1
1N4148 R3 L1 D2
clipping level, and the result is
correspondingly less feedback.
Q1 inverts this clipping level to
1.5V. This range accommodates al- R4 68 330 mH BLUE reduce the turn-on bias to Q2 at
680 2
kaline, carbon-zinc, NiCd, or 4 higher cell voltages. We chose
NiMH single cells. The circuit’s R5 R2
2N3904s, but any small-signal
S1
principal application is in LED- 680 330 npn works. Q2 runs at high cur-
3 Q2
1
based flashlights, such as a red LED 2N3904 rent at the end of the charging
+
in an astronomer’s flashlight, which Q1 ramp. Internal resistance causes
2N3904 1.2V
doesn’t interfere with night vision. R1 its base-voltage requirement to
1.5k
White LEDs make handy general- rise. The R2-R1 divider at Q1’s
purpose flashlights. You can use the base raises the collector voltage
circuit in Figure 1 with LEDs rang- to match that requirement and
ing from infrared (1.2V) to blue or A simple circuit provides drive from a single cell to an LED of thus controls Q2’s final current.
white (3.5V). The circuit is tolerant any type or color. The LED’s drive current is a
of the varying LED voltage re- triangular pulse of approxi-
quirements and delivers relatively con- tors maintain current flow, they are es- mately 120 mA peak, for an average of
stant power. It provides compensation sentially current sources as long as their approximately 30 mA to a red LED and
for varying battery voltage. The circuit is stored energy lasts. An inductor assumes 15 mA to a white one. These levels give a
an open-loop, discontinuous, flyback any voltage necessary to maintain its con- reasonable brightness to a flashlight
boost converter. Q2 is the main switch, stant-current flow. This property allows without unduly stressing the LED. The
which charges L1 with the energy to de- the circuit in Figure 1 to comply with the supply current for the circuit is approxi-
liver to the LED. When Q2 turns off, it al- LED’s voltage requirement. mately 40 mA. A 1600-mAhr NiMH AA
lows L1 to dump the stored energy into Constant-voltage devices, such as cell lasts approximately four hours. L1
the LED during flyback. LEDs, are happiest when they receive must be able to handle the peak current
Q1, an inverting amplifier, drives Q2, an their drive from current sources. The without saturating. The total cost of the
inverting switch. R4, R5, and R2 provide LED in Figure 1 receives pulses at a rap- circuit in Figure 1 is less than that of a
feedback around the circuit. Two inver- id rate. The inductor size is relatively white LED. You can use higher current
sions around the loop equal noninver- unimportant, because it determines only devices and larger cells to run multiple
sion, so regeneration (positive feedback) the oscillation frequency. If, in the un- LEDs. In this case, you can connect the
exists. If you replace L1 with a resistor, the likely case the inductor value is too large, LEDs in series. If you connect them in
circuit would form a classic bistable flip- the LED flashes too slowly, resulting in a parallel, the LEDs need swamping (bal-
flop. L1 blocks dc feedback and allows it perceivable flicker. If the inductor value last) resistors. You can also rectify and fil-
only at ac. Thus, the circuit is astable, is too small, switching losses predomi- ter the circuit’s output to provide a con-
meaning it oscillates. Q2’s on-time is a nate, and efficiency suffers. The value in venient, albeit uncontrolled, dc supply
function of the time it takes L1’s current Figure 1 produces oscillation in the 50- for other uses.
to ramp up to the point at which Q2 can kHz neighborhood, a reasonable com-
no longer stay in saturation. At this point, promise. D1 provides compensation for
the circuit flips to the off state for the du- varying cell voltage. By the voltage-divi- Is this the best Design Idea in this
ration of the energy dump into the LED, sion action at Node 4, D1 provides a vari- issue? Vote at www.ednmag.com/edn
and the process repeats. Because induc- able-clipping operation. The higher the mag/vote.asp.

design
ideas
Lowpass filter uses only two values
Richard M Kurzrok, Queens Village, NY
n recent years, image- capacitors of two different
I parameter design of LC fil-

ters has received new con-
sideration (references 1 and
TABLE 1—AMPLITUDE RESPONSE FOR FILTER IN FIGURE 2
Frequency
(MHz)
1
Insertion loss
(dB)
0.1
Frequency
(MHz)
4
Insertion loss
(dB)
5.2
values. Figure 2 shows the
schematic of an equivalent
composite lowpass filter.
2). The composite lowpass This filter uses judicious
1.5 0.1 4.1 12.7
filter uses interior constant-k combinations of compo-
2 0.15 4.2 20.8
full sections terminated by nents in series, parallel, and
2.5 0.1 4.3 31.2
m-derived half-sections. For series-parallel. The filter uses
2.9 0.2 4.4 Greater than 40
best passband response, you eight inductors and 14 ca-
3.2 0.25 5 Greater than 40
usually select m to equal 0.6. pacitors of only one value
However, m=0.5 can still give each.
useful filter performance Table 1 gives test results for
while reducing the number of the lowpass filter of Figure 2.
component values. A low We constructed the filter on
number of component values Vector board in a die-cast alu-
is advantageous for low-cost minum enclosure with BNC
manufacturing. The design technique is 1 shows a schematic of the composite input and output connectors. The 3-dB
also applicable to highpass and wide- lowpass filter. The filter uses four in- cutoff design frequency is 3.88 MHz with
band filters (references 3 and 4). Figure ductors of two different values and five source and load impedances of 50V. All
capacitors are polypropylene units of
L1=0.5 L3=2 L5=2 L7=0.5 820 pF65%. All inductors are 2.05 mH
and made of 20 turns of number 26
AWG magnet wire on Micro Metals T37-
C1=1.5 C7=1.5
Figure 1 2 toroids. The toroidal inductors, with
unloaded Q exceeding 100, provide low
C2=1.5 C4=2 C6=1.5 passband-insertion loss. Surface-mount
inductors with unloaded Q of 10 to 20
yield higher passband losses, which are
acceptable in many applications.
References
1. Kurzrok, Richard M, “Low cost low-
A composite lowpass filter uses four component values.
pass filter design using image parame-
L7A
ters,” Applied Microwave & Wireless, Feb-
L1A
ruary 1999, pg 72, and correction May
L1B L3A L3B L5A L5B L7B 1999, pg 12.
2. Kurzrok , Richard M, “Update the
C1A C1B C7A C7B design of image-parameter filters,” Mi-
crowaves & RF, May 2000, pg 119.
3. Kurzrok, Richard M, “Filter design
C1C C7C uses image parameters,” EDN, May 25,
2000, pg 111.
C2B C6B 4. Kurzrok, Richard M,“Wideband fil-
Figure 2 C3A C3B
C2A C6A ter uses image parameters,” EDN, Oct 26,
C2C C6C
2000, pg 174.
NOTE:
ALL NORMALIZED INDUCTORS AND CAPACITORS EQUAL 1.
By judicious connection of components, this filter uses only one value each for the inductors and issue? Vote at www.ednmag.com/edn
capacitors. mag/vote.asp.

design
ideas
Quickly discharge power-supply capacitors

Stephen Woodward, University of North Carolina, Chapel Hill, NC
perennial challenge contacts of the DPDT
A in power-supply
design is the safe
and speedy discharge, or
Figure 1 S 1
1:1 on/off power switch create
a filter-capacitor-discharge
path that exists only when
“dump,” at turn-off of the NC you need it: when the sup-
large amount of energy stored CVS2 ~ ply is turned off. When the
NC = 50J
in the postrectification filter 120V AC 2 switch moves to the off po-
capacitors. This energy, CV2/2, sition, it establishes a dis-
can usually reach tens of charge path through resis-
joules. If you let the capacitors + 4400 mF 1k tors R1 and R2 and the
RB 25W V=150V
self-discharge, dangerous 200V power transformer’s pri-
voltages can persist on un- mary winding. The result is
loaded electrolytic filter ca- an almost arbitrarily rapid
pacitors for hours or even dump of the stored energy,
days. These charged capaci- while the circuit suffers ze-
tors can pose a significant haz- A bleeder resistor ensures safety but wastes much power. ro power-on energy waste.
ard to service personnel or Use the following four cri-
even to the equipment itself. teria to optimally select R1,
The standard and ob- R2, and S1:
Figure 2
vious solution to this S1 1:1
TURN-OFF
DISCHARGE PATH
● The peak discharge
problem is the traditional current, V/(R1 1R2),
R1
“bleeder” resistor, RB (Figure should not exceed S1’s
1). The trouble with the RB fix contact rating.
is that power continuously ● The pulse-handling
and wastefully “bleeds” 120V AC
R2
capability of R1 and
through RB, not only when it’s R2 should be adequate
desirable during a capacitor to handle the CV2/2
dump, but also constantly + 4400 mF
thermal impulse. A
V=150V
when the power supply is on. 200V 3W rating for R1 and
C
The resulting energy hemor- R2 is adequate for this
rhage is sometimes far from 50J example.
negligible. ● The discharge time
Figure 1 offers an illustra- constant, (R11R2)C,
tion of the problem, taken Otherwise unused switch contacts can dump energy while not wasting power. should be short
from the power supply of a enough to ensure
pulse generator. The CV2/2 energy stored penalty in a low-duty-cycle pulse-gener- quick disposal of the stored energy.
at the nominal 150V operating voltage is ator application. This waste dominates all ● S1 must have a break-before-make
150234400 mF/2, or approximately 50J. energy consumption and heat produc- architecture that ensures breaking
Suppose you choose the RB fix for this tion in what is otherwise a low-average- both connections to the ac mains
supply and opt to achieve 90% discharge power circuit. This scenario is an un- before making either discharge con-
of the 4400-mF capacitor within 10 sec af- avoidable drawback of bleeder resistors. nection, and vice versa. Otherwise,
ter turning off the supply. You then have Whenever you apply the 10%-in-10-sec a hazardous ground-fault condition
to select RB to provide a constant RC time safety criterion, the downside is the in- may occur at on/off transitions.
no longer than 10/ln(10), or 4.3 sec. RB, evitable dissipation of almost half the
therefore, equals 4.3 sec/4400 mF, or ap- CV2/2 energy during each second the cir-
proximately 1 kV. The resulting contin- cuit is under power.
uous power dissipated in RB is 1502/1 kV, Figure 2 shows a much more selective Is this the best Design Idea in this
or approximately 23W. This figure repre- and thrifty fix for the energy-dump prob- issue? Vote at www.ednmag.com/edn
sents an undesirable power-dissipation lem. The otherwise-unused off-throw mag/vote.asp.

design
ideas
Watchdog timer allows entry to test mode
Greg Sutterlin and Larry Barnes, Maxim Integrated Products, Sunnyvale, CA, and
Craig Gestler, Mining Safety Appliances Co, Mars, PA
anuals for microprocessor-based
M devices often include in-

structions for entering a
“secret mode” in which you can test or re-
Figure 1 VCORE
S1
3.3V
set the device. These instructions typi- TO mC

4 3.3V
cally ask you to depress and hold one or VCC3
two switches for a minimum time inter-
val. You can adopt several measures to 3.3V
6
VCC
5 S2
IC1 1M
avoid accidentally triggering the test MAX6360 5
TO mC
mode: Depress two keys, hold both 1
WDI
TO mC 1k
keys simultaneously and continuously RST
through the minimum interval, and 2

MR
3
GND
make the interval two to five seconds
long. You can implement such designs
with a handful of resistors, capacitors,
and diodes and a comparator or two.
Such circuitry may remain useless or lack You can activate IC1 only by depressing S1 and S2 simultaneously for at least 2.9 sec.
customer appreciation, but it raises cost
and complexity while lowering system re- ure 1 monitors two voltages, provides a WDI, which remains floating because the
liability. A better alternative is to imple- power-on reset, and includes a watchdog 1-MV resistor limits the current to less
ment the function with minimal addi- timer. If you don’t need the watchdog than 5 mA. The transistor turns on and
tional components (Figure 1). function elsewhere in the system, it can forces WDI to the active-high level only
Microprocessor-based devices usually help to implement the switch-delay cir- when you depress S1 as well. If you de-
include a voltage supervisor that moni- cuitry. Fortunately, the watchdog timer press the switches in reverse order, WDI
tors the VCC level and, in some cases, the self-resets when the WDI (watchdog in- switches high only when you close S2. You
core voltage. When either voltage drops put) Pin 5 is floating, an indication that must close both switches to activate the
below its threshold, the supervisor issues the circuit is disabled. Thus, you can im- watchdog timer. After the timer activates,
a reset to the microprocessor. IC1 in Fig- plement the switch-delay circuitry by en- IC1 imposes a 2.9-sec delay before assert-
abling and disabling the watchdog timer. ing a reset (Pin 1). If you release either
Simply provide an interface between or both switches during this 2.9-sec peri-
WDI and the switches that enable the test od, the timer resets. Thus, for the mini-
Watchdog timer allows
mode. The nominal time-out period for mal cost of an npn transistor and three
entry to test mode..........................................87
IC1’s watchdog timer is 2.9 sec. resistors, the supervisor IC can monitor
Transistors offer thermal protection WDI must float when both switches two voltages, provide a power-on-reset
for controller....................................................88 are open and when you depress only one. signal, and implement a dual-switch de-
Variable load tests voltage sources ..........90 When you depress both, WDI must as- lay function. To monitor one voltage, you
sume either the active-high or the active- can replace IC1 with a MAX823.
Linear supply uses switch-
low state as specified in the data sheet.
mode regulation ............................................90
Note that WDI can remain floating while
Sonarlike method detects sinking 5 mA. The npn transistor isolates
fluid level ..........................................................94 WDI from the switches’ pulldown resis- Is this the best Design Idea in this
tors. When S2 closes, current flows issue? Vote at www.ednmag.com/edn
through the base of the transistor to mag/vote.asp.
www.ednmag.com July 19, 2001 | edn 87
design
ideas
Transistors offer thermal protection for controller
hen a switch-mode power-sup-
W
5V
1N5819 600 mA
ply controller, such as On Semi- +
47 mF +
conductor’s NCP1200, op- 350V 1 HV 8 470 mF
erates at a high ambient temper- F i g u r e 1 NCP1200
10V
2 7
FB
ature, you should protect the entire pow- 3 6 MTD1N60E
er supply against lethal thermal runaway. CS VCC
4
The NCP1200 operates directly from the GND DIV
5
EMI
power mains without an auxiliary wind- FILTER MOC8103
ing; therefore, the die in the IC dissipates
+
power (Figure 1). Unfortunately, the in- UNIVERSAL 10 mF
ternal temperature-shutdown circuitry INPUT
3V
cannot perform its protection function
because the die is not at ambient tem-
perature but at a temperature that’s high- A controller IC implements a low parts-count offline power supply.
er than ambient by a few tens of degrees.
To overcome this problem, you BC547’s base, and the thyristor
can implement a thermistor-based Figure 2 1 8
latches, thereby permanently
design, but this solution compromises 2 7 stopping the NCP1200’s puls-
the system’s cost. Fortunately, you can use 3 NCP1200 6 es. Once you remove the sup-
10k
standard bipolar transistors to imple- BC557 4
ply from the power mains, the
5
ment a low-cost thermal-shutdown cir- thyristor resets. The 0.1-mF ca-
cuit. Figure 2 shows how to build a clas- pacitor prevents spurious
sic thyristor circuit using two inexpensive BC547 316k noise from triggering the
bipolar transistors: a BC557B pnp and a + thyristor.
10k + 22 mF
BC547B npn. The idea is to use the neg- 0.1 mF We conducted tests on the
ative-temperature coefficient of the sili- thyristor-based temperature-
con ;22 mV/8C) to fire the thyristor. protection scheme using BC-
In the inactive state, both the upper Two bipolar transistors configure a thyristor-based tempera- 547B and BC557B transistors.
and the lower transistors in Figure 2 are ture-shutdown circuit. The “B”extension is important
in the off state because of the presence of because it corresponds to a
the 10-kV resistors. The thyristor struc- low a certain level, the IC internally narrow hFE range of 200 to 450. This de-
ture connects between the feedback pin, blanks the cycles, and the power transis- sign uses transistors in TO-92 packages,
FB, and ground. One feature of the tor turns off. If the thyristor permanent- mounted close to each other. If only one
NCP1200 is to skip unwanted switching ly pulls the FB pin to ground, the transistor heats up, thermal results vary.
cycles when the power demand dimin- NCP1200 no longer delivers pulses. Once Therefore, you should mount these two
ishes. The IC performs this function in- latched, the thyristor prevents any restart, components close to each other on the pc-
ternally by constantly monitoring the FB until you disconnect the power supply board-component side so that they will
pin. When the voltage on this pin falls be- from the power mains. The 316-kV re- operate at approximately the same junc-
sistor combines with the 10-kV resistor tion temperatures. From 20 bipolar-tran-
TABLE 1—TEMPERATURE to form a voltage divider from the VCC sistor combinations, you can obtain the
SHUTDOWN VERSUS VBE rail. This rail, on average, varies from lot results shown in Table 1. You can see that
VBE VBE TLATCH-OFF to lot from 10.3 to 10.6V, for a total DV the latch-off threshold temperature varies
(mV, npn) (mV, pnp) (88C) of 300 mV. This variation translates to by only approximately 58C for all combi-
665 654 110 to 115 less than 10 mV at the transistor’s base. nations of transistors (Reference 1).
666 656 110 to 115 When the temperature rises, the BC547’s
667 656 110 to 115 turn-on VBE diminishes until it reaches Reference
666 657 110 to 115 the divider voltage on its base. (This volt- 1. “Bipolars provide safe latch-off
670 659 110 to 115 age is approximately 320 mV, but you can against opto failures,” EDN, Dec 7, 2000,
664 653 115 alter it to accommodate other tempera- pg 190.
666 652 115 ture levels.) At this point, the BC547 con-
667 655 110 to 115 ducts current, and the BC557’s base volt- Is this the best Design Idea in this
667 657 110 age starts toward ground. The BC557’s issue? Vote at www.ednmag.com/edn
669 653 110 collector current further biases the mag/vote.asp.
design
ideas
Variable load tests voltage sources
Michele Frantisek, Brno, Czech Republic
he circuit in Figure ure 1 consists of an op amp,
T
12V
0.1 mF
1 serves as a IC2, driving transistors Q1
variable, cur- Figure 1 and Q2. IC2 compares the ref-
VCC 12V
rent-sink load for testing Q1 erence voltage at Point A
A 10k 2N3440
voltage sources. You use DBO VOUT +
1k
with the voltage across resis-
IC2
digital commands to set VSEN
OP77
tor R. IC2’s output voltage
the load current of the DB3 2 controls Q1 and Q2 such that
VSEL DEVICE
DATA DB4
device under test over a INPUTS
IC1
212V
UNDER the voltage across R equals
AD558 Q2 TEST
wide range, independent- DB7
10k
TIPL762 the reference voltage at point
ly of the device under CE A. The voltage across R is
1
test’s output voltage. The CS
R 10W proportional to the current
GND GND
circuit comprises an AD- 1% from the device under test
558 DAC, IC1, which pro- and is independent of the
vides a reference voltage output voltage of the device
at Point A. Practically any A simple circuit allows digital control of current, independent of voltage. under test. The value of R in
type of DAC converter Figure 1 is 1V; thus, the cir-
works well in this appli- TABLE 1—DAC OUTPUT VOLTAGE VERSUS INPUT CODE cuit provides a sink current of
cation. The AD558 is a Digital input of IC1 1A when the voltage at point
single-supply type with Binary Hexadecimal Voltage at Point A (V) A is 1V. With the values
an internal reference; 0000 0000 00 0 shown in Figure 1, you can
these features simplify 0000 0001 01 0.01 control currents of 0 to 2.55A
the design. IC1 generates 0000 1111 0F 0.15 over a device under test volt-
an output voltage of 0 to 0001 0000 10 0.16 age range of 5 to 250V. Be sure
2.55V (Table 1). The 1000 0000 80 1.28 to limit the power dissipation
control inputs CE and 1111 1111 FF 2.55 in Q2 to 120W.
CS in IC1 allow you to
control the DAC from a microprocessor to obtain direct access to the DAC’s data Is this the best Design Idea in this
bus. If your application does not involve inputs. issue? Vote at www.ednmag.com/edn
a data bus, connect CE and CS to ground The second part of the circuit in Fig- mag/vote.asp.
Linear supply uses switch-mode regulation

David Magliocco, CDPI, Scientrier, France
ou can use simple circuits to pates appreciable power when the
Y implement small, regulated

plug-in power supplies. In Fig-
ure 1, a basic and versatile 5V sup-
FUSE LINK
AC IN
TRANSFORMER
D1 D2
1N4100 1N4100
mains voltage is high. Figure 2
shows that Q1 must handle nearly
0.75W at nominal input voltage
ply uses a zener diode and an emit- and output current. A TO-92
ter-follower transistor. You must D4 R1 small-signal transistor, such as a
D3 1N4100 150
calculate and design the trans- Q1 BC337, is adequate for 300 mA,
1N4100 BD135
former such that Q1 is close C2 +
but a medium-power device, such
Figure 1
to saturation at low mains 2200 mF/ 5V as a BD135, is a better choice. To
16V
voltages and nominal output cur- D5 R6 + C2 cut costs, this design uses no heat
5.6V 1k 1 mF/
rent. Additionally, you must choose 10V
R1 to ensure proper bias for the 0V
This simple plug-in power supply is
zener diode. The transistor dissi- effective but has no current limiting.

design
ideas
2
sink. Inasmuch as the circuitry is inside
a nonventilated plug-in plastic Figure 2 1.75
case, the junction temperature of
1.5
the BD135 attains temperatures greater
AT 230V INPUT WITH SWITCH-MODE CURRENT LIMITING
than 1008C. 1.25
AT 230V INPUT WITH LINEAR CURRENT LIMITING
Assuming that you need current lim- POWER
(W) 1
iting, if you use a linear current-limiting
circuit, Q1 needs to dissipate nearly 2.5W 0.75
in the case of a short-circuited output.

0.5
The probable result is the melting of the
plastic case and the failure of Q1. To avoid 0.25 CURRENT-LIMITING
SWITCH MODE ZONE
that disaster, you can use switch-mode 0
current limiting. Figure 3 shows the cir- 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350
cuit of Figure 1 with some additional IOUT (mA)
components, and Figure 2 shows the

benefits of the limiting. Q1 and Q2 act as Without switch-mode current limiting, the circuit of Figure 1 can crash and burn.
one emitter follower, but with lower base
current. A small-signal Schottky diode, FUSE
LINK
BAT85, which receives its bias from R3 TRANSFORMER
1N4001
and R2, provides an approximate 0.25V

W2
reference voltage for comparator IC1A’s 100 mF/ +
AC IN 25V
noninverting input. The inverting input W1
reads the voltage drop created by the out-
put current across R3. As long as the out- 1N4001 1N4001 Q2
1k BD136
put current remains less than 300 mA, 2.2k
the output of the comparator is in 10k
a high-impedance state (open- Figure 3 1N4001 1N4001
Q1
BC337 L1
collector), and the circuit works like a lin- 300 mH
+
ear regulator. 2200 mF/ 5V
16V R1 R2
If the output current reaches 300 mA, 1k 1k +
10 mF/
D1 1k
the comparator’s output switches low 1N5818
10V
8
and thus turns off Q1 and Q2. The current IC1B 5.6V 1 2
2
0V
through L1 decreases exponentially and LM393
5 IC1A
+
3 1k
+ LM393 4 R 3
flows through Schottky diode D1. As the 7 D2
BAT85 0.82
2 6
emitter of Q1 is then at approximately
0.5V, the bias current in D2 decreases.
The voltage drop across D2 drops by ap- The addition of a few components protects Figure 1’s circuit against overcurrent conditions.
proximately 10%. As a consequence, the
output current decreases until it reaches
270 mA. Then, the comparator switches 5.5
back to a high-impedance state, 5 LINEAR ZONE
turning on Q1 and Q2 and again Figure 4
4.5
biasing D2 with R1 and R2. The current 4
in L1 increases exponentially until it 3.5
again reaches 300 mA. L1 is a 300-mH in- 3
ductor using a powdered-iron core. Fig- VOUT
(V) 2.5
ure 4 illustrates the current-limiting ac- CURRENT-LIMITING
2
tion of the switch-mode circuitry. SWITCH-MODE ZONE
1.5
1
0.5
0
0 25 50 75 100 125 150 175 200 225 250 275 300 325 350
Is this the best Design Idea in this IOUT (mA)
mag/vote.asp. Switch-mode current limiting restricts current in Figure 3’s circuit to about 320 mA.

design
ideas
Sonarlike method detects fluid level
Robert LeBoeuf and Eric Masse, National Semiconductor, Salem, NH
igure 1 illustrates a simple, cost-
F effective method of measur-

ing the height of fluid in a
column by using ultrasonic waves. Two
Figure 1
POWER FOR RECEIVER
AMPLIFIER
PIEZOELECTRIC
RECEIVER
PIEZOELECTRIC TRANSMITTER
FUNNEL TUBE
ULTRASONIC TRANSMITTED WAVE
piezoelectric transducers generate and COAX CABLE
listen to the ultrasonic acoustical wave. SCREW-

First, the transmitter piezo element re- ADJUSTABLE CHIRP
FITTING
ceives stimulation from a square wave 8
COP8
that lasts three or four cycles. This tech- LM111 mC
OUTPUT
nique produces the most efficient trans- ECHO
COMPARATOR DATA
L PULSE
fer of electrical energy to acoustical en- ECHO 8
ergy. The acoustical wave produced at the EXTERNAL OFFSET
transmitter funnels down into the wave- h REFLECTED WAVE
WAVEGUIDE TUBE
guide tube. The wave then concentrates FLUID
at the tip of the funnel tube and dispers- VESSEL
es into the waveguide tube. Part of the
wave, or “crosstalk,” travels up toward the A fluid-level measurement system uses ultrasonic sonar principles.
receiver. The other part travels down to-
ward the fluid. The receiver detects and
ignores the crosstalk component of the
wave. Part of the crosstalk wave is ab-
sorbed in the reflection from the receiv-
er, and the remaining energy propagates
down toward the fluid. The receiver then
listens to the wave that echoes off the sur-
face of the fluid. The first of these waves
that strikes the receiver is the component
that has propagated toward the fluid.
This component is the primary echo. The
crosstalk wave arrives shortly thereafter
with a reduction in amplitude; this wave
constitutes the secondary echo.
The COP8 mC measures the time it
takes to propagate a wave from an arbi-
trary point on the surface of the
fluid to the receiver. You can Figure 2
choose any arbitrary point; the mC can
offset, or compensate for, the point with To make a measurement, the receiver must ignore the crosstalk wave and concentrate on the
the aid of external data. The mechanical primary echo.
system in Figure 1 has two major advan-
tages. The first advantage is a cost savings
in using two separate piezo elements.
Piezo elements for only receivers and
only transmitters are less expensive in the
ensemble than a piezo element designed
for both. The other advantage is the
crude “mechanical diode” that the funnel
tube forms. A high-intensity wave prop-
agates from the tunnel, but the receiver
recaptures only a small fraction of
Figure 3
it. Figure 2 shows a typical wave-
shape using Panasonic (www.panasonic.
com) EFRTSB40KS and EFRRSB40KS
piezo elements. Upon application of the Some adjustments in the system produce a more distinct primary echo.

design
ideas
chirp wave, the receiver imme-
diately detects the crosstalk TRANSMITTER POD
wave. After an interval, 2 J3

Figure 4 P3
the receiver detects the PIEZO
primary echo, followed closely 1

by the secondary echo. 4 3 2
Reducing the amplitude of
the crosstalk wave is conven-
RECEIVER POD
ient (Figure 2) This reduction 5V
allows shorter waveguide
500k
tubes, increasing the versatility 10 mF 7
of the design. One simple way
2 V+ IC2
of reducing crosstalk is to ad- 2 CLC425
3 6
+ 2
just the receiver’s distance from OUT J1
P1
the funnel tip, thus moving the 2 X1 +
receiver to an antinode. An- V2

4
other possible adjustment is to 1 PIEZO 4 3 2
1k 1k
reduce the length of the chirp. 10 mF
5V JP1 JP2
Figure 3 shows the acoustical 25V POWER CABLE
1 1
waves after making the cited
2 2
adjustments. In the circuit of 3 3
Figure 4, the COP8, IC1, puls-
25V
es I/O port G5 at the piezo el-
ement’s resonant frequency of 5V JP4 JP3
approximately 40.3 kHz. This 5V 1 1
signal switches Q1 and ener- 2 2
gizes the series-LC tank circuit, R1
3 3
which has the same resonant 7

10 3
1k 25V
frequency as the piezo element. 9 IC3 2 J2 P2
LM111W 2.2k 2.2k
This tank circuit boosts the 2.5k 2
100 pF
6 5 + 0.001 mF
voltage across the piezo ele- 1
0.001 mF
ment from 5 to 25V p-p. The R2
1 mF 4 3 2
25V 1k
receiver then detects and dis-
5V
cards the crosstalk wave. After
L1 CLOSE TO L1
a short interval, the crosstalk M2N7000 Q 47 mH
1
vanishes, and the COP8 begins 1 mF 220 mF
listening to the output of the

comparator and begins count- 5k 0.1 mF
0.1 mF
ing program cycles and, thus, 0.1 mF
J4
P4
time.
25V 0.05 mF
When the echo reaches the
piezo receiver X1, IC2 amplifies 5V
the echo 1000 times. The am- 4 3 2
4
plified signal then routes to the 1 VCC 5
G6/5 LO/CMPOUT CLK
LM111 comparator, IC3. The 16 6
G5 L1/CMPIN2 STROBE
first echo component to reach 15
7
G3/TIO L2/CMPIN+ DATA
the amplitude of the threshold L3
8
set by R1 and R2 trips IC3 to a IC 1 9
10 MHz 3 COP823CJ/SO L4
logic one, and the COP8 stops CLK 10
L5
Y2 11
counting. Figure 5 illustrates 10 pF L6
2 12
this process. The COP8 starts G7/CKO L7/MODOUT
14
listening at the rising edge of 10 pF GND RST RESET
the trace labeled “COP8 Timed 13
Interval,” just after the cross-
talk becomes silent. When the BASEBOARD
echo’s amplitude crosses the
comparator’s trip voltage, the The ultrasonic fluid-level measurement system uses standard, readily available components.

design
ideas
comparator’s output switches high,
and the COP8 stops timing. Armed
with this timing data, converting
the figures to a distance is trivial.
One constraint is that the leading
edge of the echo must occur after
the disappearance of the crosstalk.
This constraint demands an offset
distance or an origin that meets the
constraint. Assuming the con-
straint is satisfied, the distance is
d5VAIR(t/2). The velocity of sound
in air at room tempera-
ture is 345m/sec, or 0.345 Figure 5
mm/msec. Solving for distance,
d50.172t mm, with t in microsec- The COP8 doesn’t start listening until its timed interval arrives after the disappearance of the
onds. crosstalk wave.
If you apply this distance to the
waveform in Figure 5, the distance from internal pullup, and then an interrupt oc- When the decimal-digit register reaches
the origin to the fluid’s surface is 0.172 curs on a negative edge. At some prede- nine, the next decimal register incre-
mm/msec3(6750 msec24750 msec)- termined time, the crosstalk is finished, ments, and so on. This operation pro-
5344 mm, or 13.54 in. The COP8 mC and the timer starts and counts down un- duces three registers with a decimal-
controls the fluid-level detector. Its first til the interrupt occurs. When the nega- equivalent number.
function in producing the waveform is to tive edge arrives on the port pin, the re- The COP8 can then send the data to
“chirp” the piezo transmitter. The mC sults of the timer transfer to the upper the display panel. You set the flags in the
uses its 16-bit programmable timer to and lower R1B. It remains on the port pin control register for microwire/plus seri-
perform this step. The timer’s clock speed to convert the number in the R1B regis- al I/O. This setting configures ports G4
is the same as that of an instruction cy- ters. Because the timer counts down, you and G5 as data out and clock, respective-
cle, which is one-tenth of the oscillator need to subtract the number from the ly. You configure ports G0 and G1 as out-
speed (10 MHz). You set the appropriate starting point to determine the actual put enable and strobe, respectively. You
timer control for PWM. This process time. The difference in fluid level deter- then use a look-up table to send the cor-
produces a square wave of 40 kHz with mines whether you need a prescaler. Be- rect data to the display driver. The data
50% duty cycle. This figure represents the cause the speed of the timer is 1 msec, any loads into the serial-I/O register. The
resonant frequency of the piezo elements value greater than 1 msec shows up as an busy flag in the PSW register initiates the
(Figure 5). You should minimize the over-range condition on the display. This data transfer. The transfer continues at
crosstalk because it is unusable for the example with a 2-ft change in fluid level clock speed until all 8 bits complete the
measurement. The system should gener- uses a prescaler with a factor of four, transfer. The process occurs for all three
ate only three or four pulses to perform meaning that the resolution decreases by digits, starting with the least significant
this step. More pulses create longer a factor of four. digit. You can download the assembly
crosstalk and problems if the piezo re- Once you determine the prescaler, you code for the COP8 from EDN’s Web site,
ceiver receives the crosstalk and primary need to convert the data in the two 8-bit www.ednmag.com. Click on “Search
echo at the same time. The timer in the registers to a three-digit decimal equiva- Databases,” then enter the software cen-
mC starts and then experiences a short lent for the three seven-segment LED dis- ter to download the file for Design Idea
delay. During this delay, port G3 gener- plays. The conversion process is similar #2718. You can find additional informa-
ates the square wave. The short delay lim- to counting. You set up three 8-bit regis- tion about the COP8 at www.national.
its the amount of pulses to the piezo ters and increment them each time the com/cop8.
transmitter. two 8-bit registers decrement. Consider
While the waveform from the trans- the lower 8 bits of the hexadecimal num-
mitter propagates down the tube, a de- ber. Each time the lower 8-bit register
lay ensures that the COP8 does not trig- reaches zero, the upper register decre-
ger during the crosstalk. The mC’s timer ments, and the lower bit begins at 0xFFh
characteristic then goes into input-cap- again. This process repeats until the
ture mode. Because the LM111 has a hexadecimal registers equal zero. Each Is this the best Design Idea in this
common-emitter transistor output, the time a hexadecimal number decrements, issue? Vote at www.ednmag.com/edn
programming of port G2 uses the weak a decimal-digit register increments. mag/vote.asp.

design
ideas
Centronics port generates narrow pulse widths
Darvinder Oberoi, CEDTI, Jammu, India
P1
ariable-pulse-width signals are
V
1
VCC 5V
useful in control circuitry for 14
Figure 1 2
positioning and holding pur- 15
poses in robotics and power electronics. 3 R2
J1
+
Frequently, the need arises for pulses with 16 1k
1
4 DESIRED PULSE
width less than 1 msec. Delays less than 17
2
3
1 msec are usually not available in most 5
R1
2
programming languages, so generating 18 Q1

SL100
6 10k
such pulses can be a problem. To gener- CENTRONICS 19
ate a fractional-millisecond delay you can PORT 7
20
use a PC’s 8254 16-bit timer (Counter 2), 8
which normally controls the PC’s speak- 21
er. The desired pulse is available at the 9
22
PC’s Centronics port (Figure 1) through 10
a buffer stage, which protects the port 23
from overload damage. Counter 2 oper- 11
24
ates at a clock frequency of 1.193181 12
MHz. To generate a pulse width less than 25
13
1 msec, you operate Counter 2 in mode
2 as a rate generator. You do this by set-
ting the control-word value to 0B4h and You can use the Centronics port on your PC to generate narrow pulse widths.
by writing this data to the control-regis-
ter port, address 43h. Initially, Counter 2 LISTING 1—TURBO C11 LISTING FOR PULSE GENERATION
contains FFFFh at address 042h. Bit 0 of (Continued on next page)
port 61h is at logic 1 to enable the count-
er, and bit 0 of the printer port (in this
case, 0378h, printer_port) is at logic 0.
Listing 1 contains the software necessary
for controlling the pulse-generation
process.
Setting bit 0 of port 61h enables
Counter 2. The counter decrements by
Centronics port generates

narrow pulse widths ......................................97
Preprocessor for rotary encoder
uses PAL ........................................................100
Inverters form three-phase VCO ..............102
Power inverter is bidirectional ..................104
Design Ideas Entry Blank ..........................106
www.ednmag.com August 2, 2001 | edn 97

design
ideas
LISTING 1—TURBO C11 LISTING
one every 0.8380958 msec. Before the FOR PULSE GENERATION (Continued)
generation of the pulse, it’s necessary to
compute Counter 2’s required count (re-
quired_count) to generate a pulse of de-
sired duration (desired_time). When the
counter is enabled, a “while” loop reads
back the counter’s count through port
42h in two read cycles. This count (count-
er_data) data helps to compute the
counts that have elapsed (count_
elapsed), and, once the required count
arrives, the software exits this read loop.
The software disables the counter by set-
ting bit 0 of port 61h to logic 0. The pulse
goes low for the desired time (for exam-
ple, 10 msec Off_Time). This cycle of
pulse generation with a desired width re-
peats until you press the “Q” or “q” key.
The software performs all its calculations
during the pulse’s off (low) time.
The software in Listing 1 uses Turbo
C11, Version 3. You can download List-
ing 1 from the Web version of this arti-
cle at www.ednmag.com. Using this soft-
ware, you can increase or reduce the
pulse width (desired_time) in variable
time steps (for example, 50 msec per
Time_Step) by using the numeric key-
pad’s keys 6 and 4, respectively. By press-
ing Key 5, you can fix the pulse’s duration
at a nominal value (for example, 500
msec Neutral_Time). Key 8 fixes the
pulse’s duration at the maximum desired
pulse width (for example, 750 msec
Max_Time). Key 2 fixes the pulse’s min-
imum desired width (for example, 250
msec Min_Time). The hardware we used
for testing the software is a P-II system
running at 400 MHz, with 32 Mbytes of
RAM, operating in MS-DOS mode.

mag/vote.asp.
98 edn | August 2, 2001 www.ednmag.com

design
ideas
Preprocessor for rotary encoder uses PAL
David Rathgeber, Alles Corp, Toronto, ON, Canada
otary encoders usu- the negative-going direction
R ally provide quadra-

ture pulses that indi-
cate both the amount of
LISTING 1—PAL SOFTWARE FOR ENCODER
PREPROCESSOR
outputs, and two other outputs
serve as D registers. A single
chip can thus condition two
rotation and the direction encoders with inputs and out-
(Figure 1). A microcon- puts left over for miscellaneous
troller can calculate the ro- encoding tasks. The design
tation direction and keep works as follows: The two ex-
track of angular movement. tra outputs serve as D-type
Many microcontrollers’ in- registers, with an encoder in-
terrupt inputs, such as those put as the data and the strobe
on the Zilog Z86C90, can serving as the clock. When an
detect only a falling edge. input (A or B in Figure 2)
Some with programmable changes, the corresponding de-
edge detection, such as the layed output (ADEL or BDEL)
Zilog Z86E30, can function changes on the next strobe.
with either rising or falling Therefore, the delayed outputs
edges but not both. Howev- mirror the inputs, with the de-
er, for maximum resolu- lay depending on the strobe’s
tion, it is desirable to look at frequency. An examination of
each rising and falling edge. the diagram in Figure 2 reveals
In these cases, you need four unique patterns that relate
four inputs to read the en- to forward encoder rotation
coder. Further, when you and four that relate to reverse
read the two inputs, you can rotation. Listing 1 shows the
assess the direction of rota- PAL software, in Synario for-
tion only by referring to the previous This design uses an AMD PALCE- mat. You can download the PAL software
read operation. The microcontroller thus 16V8Z that requires minimal supply cur- from the Web version of this article at
must keep track of the previous state of rent and costs less than $1. In addition to www.ednmag.com.
each input. You can use a simple PAL or the two encoder inputs, the scheme re-
other programmable-logic chip to pre- quires a strobe, which occurs much more
condition the encoder outputs to pro- frequently than the encoder edges. This
duce a single falling-edge output for each design uses the DS pin on the microcon- Is this the best Design Idea in this
rising and falling edge for each rotation troller, but you could probably use the issue? Vote at www.ednmag.com/edn
direction. crystal clock as well. Two PAL outputs are mag/vote.asp.
A
Figure 1 Figure 2
ADEL
ENCODER
OUTPUT A B
ENCODER
OUTPUT B BDEL
FORWARD ROTATION REVERSE ROTATION
FORWARD REVERSE
INTERRUPT INTERRUPT
To determine the direction of rotation, it’s necessary to detect both
rising and falling edges of the encoder outputs. A PAL produces unique patterns for forward and reverse rotation.

design
ideas
Inverters form three-phase VCO

Al Dutcher, AL Labs, West Deptford, NJ
ou sometimes need an inexpensive
Y VCO that can produce even-

ly spaced three-phase out-
puts over a wide frequency range. You
Figure 1
VDD
VDD
could use tracking all-phase filters with U04 U04 U04

2408 1208
only one oscillator, but this technique is 07
50k
difficult to implement and offers limited 2N3906
1N4148 1N4148 1N4148
range. Other methods, such as using a 680 680
DSP, are feasible, but they’re complex and
1N4148 1N4148 1N4148 ACTIVE CURRENT MODE
expensive. The inspiration for the VCO OR RESISTIVE CONTROL
in Figure 1 came from Texas Instru-
ments’ application notes of years ago, de- 100 nF 100 nF 100 nF
5V
tailing the use of unbuffered U-type in-
verters for use in ring oscillators. The
application note’s circuit consists of only
the inverters. The circuit generates rela-
tively squarish waveforms. Any ring os- A ring-type oscillator generates 3-phase outputs over a wide frequency range.
cillator’s operation depends on the fact
that an odd number of
inversions exists around
the loop. Any odd 400
Figure 2
number of inverters
would work. The feedback is
200
inverting, or negative. The
feedback creates an initial
bias equilibrium at the tran- VOLTAGE (mV) 0
sition voltage for the gates.
Loop gain greater than
unity is a necessary condi- 2200
tion for oscillation. Un-
buffered inverters typically 2400
have a gain of 15 or there- 3.5 4.1 4.7 5.3 5.9 6.5
abouts at dc and approxi- TIME (mSEC)
mately 7 with capacitive
loads. Three inverters thus The circuit in Figure 1 generates 12088-spaced, 600-mV p-p outputs.
have a total gain of more
than 340, which is plenty for oscillation. With no added capacitors, the circuit of ond, they allow the gates to operate as
At high frequencies, the inverters exhib- Figure 1 can operate at frequencies as current diverters, alternately charging
it a lagging phase shift arising from prop- high as tens of megahertz using and discharging the capacitors. The rate
agation delay. Enough lagging shift added 74ACU04 gates. Added capacitors can at which the capacitors discharge de-
to the inversions ultimately turns the to- drop the frequency to usable levels. The pends on the common supply current to
tal inversion into noninversion. The cir- frequency equates to IDD/3C. For lower the inverters. This rate and, hence, the os-
cuit of Figure 1 starts out with the 1808 frequency applications, 74HCU04 gates cillation frequency is proportional to the
inversion and adds 608 of lag for 2408 per are suitable, because they’re less sensitive operating current. The range of frequen-
stage. Three stages of 2408 works out to to layout considerations. cies over which the circuit can operate is
7208 total. This figure represents two The diodes in Figure 1 perform two more than 1000-to-1 (supply current
complete trips around the phase circle for tasks. First, they limit the excursions of from 10 mA to 10 mA). Note that at the
noninversion. Noninversion implies re- the gates to 600 mV p-p, so that the gates low-current, low-frequency end of the
generation, which begets oscillation. always operate in their linear region. Sec- range, the circuit cannot supply much

design
ideas
signal current and might need buffering. put so that the amplifier delays track at
Figure 2 shows the three-phase 1207 higher frequencies. In principle, you can
Figure 3
waveforms. The concept doesn’t 907
extract any set of phase angles by the ju-
work well with normal ac- or HC- 07 dicious adjustment of component am-
DIFFERENCE
buffered gates, because they have far too plitudes in the external circuits. The cir-
much gain and would drive the nodes cuit’s main drawback is that it does not
into square waves. The ACU and HCU 2407 have a high-Q resonator attached, so
types are somewhat obscure, but they phase noise could be a problem. When
nonetheless have multiple sources. Don’t Vector subtraction of two outputs produces a you incorporate the circuit into a rela-
forget to ground the inputs of the re- 908 quadrature signal. tively tight PLL circuit, the performance
maining three gates of these hex devices. improves considerably. The capabilities
Floating inputs are verboten with all connect a differential amplifier to the 120 of this oscillator allow it to lock over a
CMOS devices. and 2408 outputs. It rejects the common- wide range of frequencies.
The circuit generates three equally mode, 1808 components. The difference
spaced outputs. Because it generates sub- between these two outputs is at 908, and
stantially sinusoidal outputs, you can eas- it tracks well over the range of the oscil- Is this the best Design Idea in this
ily obtain quadrature-spaced outputs by lator. You can use the same type of dif- issue? Vote at www.ednmag.com/edn
trigonometric means (Figure 3). You can ferential amplifier to amplify the 08 out- mag/vote.asp.
Power inverter is bidirectional

Tom Napier, North Wales, PA
f you want to swap charge in either
I direction between unevenly

loaded positive and negative
battery buses, you need an inverting dc
Figure 1
POSITIVE
INPUT/OUTPUT
47k
RATIO ADJUST
NEGATIVE
OUTPUT/INPUT
transformer. One implementation is the 50k
symmetrical flyback converter shown in

Figure 1. The circuit can generate a neg- 10k T1
ative output from a positive supply or a
positive output from a negative supply.
8
When the circuit starts up, the substrate VCC
diode of the output FET bootstraps the DISC RST 4
+ 555
output voltage to the point where syn- (CMOS) 6.8 mF
6.8 mF
chronous switching takes over. When the 6 THRES OUT 3
+
gate-switching signal is symmetrical, the

output voltage is approximately 295% of 2 TRIG CON
the input voltage, and the efficiency is GND
1
greater than 80%. You can obtain voltage 1000 pF IRF520 IRF9530
step-up or step-down by adjusting the
switching ratio.
When I used the circuit between two
4V lead-acid batteries, a comparator ad-
justed the switch ratio to drive charge in An inverter circuit swaps charges between opposite-polarity batteries.
the desired direction. The circuit auto-
matically replaces charge drained from can add gates to the drive circuit to turn age. My prototype supplies approxi-
one battery to the other. In a short-bat- off both FETs whenever the battery volt- mately 100 mA.
tery-life application, the 2.5-mA standby ages balance. The minimum input volt-
current from each battery may be negli- age is a function of the gate thresholds Is this the best Design Idea in this
gible. Using lower-gate-capacitance, of the FETs. The 69V rating of the issue? Vote at www.ednmag.com/edn
FETs can reduce losses. Alternatively, you CMOS 555 timer sets the maximum volt- mag/vote.asp.
design
ideas
Convert periodic waveforms to square waves
Ron Mancini, Texas Instruments, Bushnell, FL
onverting periodic waveforms 5V
C to square waves is an integral

part of extracting a clock sig-
nal from data, creating waveform gener-
Figure 1
INPUT
SIGNAL
CIN
R1
1M
+
5V
5V
R3
2k
TTL
OUTPUT
R4
CINT
ators, and making timing-pulse genera- 0.1 mF R2 1 0.1 mF
2 TLC393 TTL 2M
tors. Any square-wave-conversion circuit 1M GATE
2
is more valuable when the square wave’s
duty cycle is variable and controllable. 5V
2
Figure 1 shows a circuit that has these at- TLV2470
1M +
tributes and can drive several TTL-com- R5
patible loads. CIN couples the input signal ADDITIONAL TTL
GATES IF REQUIRED
onto a dc level set by R1 and R2 (the level
is VCC/2 when R15R2). Thus, the period-
ic signal at the noninverting comparator You can obtain a square wave with 2 to 98% duty cycle with this simple circuit.
input rises above and falls below VCC/2.
The parallel value of R1 and R2 (RP) and fall times. The longer rise and fall times put comparator. If the voltage on the pos-
CIN form a highpass filter with a 23-dB give the circuit more control range. itive-integrator input is VCC/2, the output
frequency of 1/(2pRPCIN). Increasing RP When the input signals are symmetri- square wave must be symmetrical for its
or CIN lowers the cutoff frequency for cal, setting the dc level at VCC/2 produces average value to be VCC/2. Adjusting R5 to
low-frequency applications. If high-fre- the maximum pulse-width control and its center point yields a 50%-duty-cycle
quency noise riding on the signal causes duty-cycle range. Asymmetrical input square wave. Adjusting R5 close to ground
problems, add a capacitor in parallel with signals require a different dc level, be- yields a square wave that is low for most
R2; this addition eliminates the high-fre- cause the time durations of the positive of the period, and adjusting R5 close to
quency noise by creating a low-frequen- and negative portions (with respect to VCC yields a square wave that is high for
cy filter. If the input signal is a square VCC/2) of the coupled signal are not most of the period. The integrator pole is
wave, the added capacitor integrates the equal. RP’s value must be low to prevent at fP51/(2pR4CINT). With the values
square wave, thus increasing its rise and input-bias current from developing an shown in Figure 1, the 0-dB crossover
appreciable offset voltage. The compara- frequency is 0.8 Hz. The gain of the inte-
tor in this design is a CMOS TLC393 ver- grator circuit is unity at 0.8 Hz, and the
Convert periodic waveforms sion of the industry-standard LM393. gain rolls off at 20 dB per decade, so the
to square waves ..........................................105 The comparator weighs the dc-refer- comparator’s small-signal gain is not
enced input signal against a reference high enough to cause oscillation. The se-
Circuit improves on first-event
voltage from the integrator output. The lection of the integrator pole is a trade-
detection ........................................................106
comparator’s output waveform is a off between stability and control-re-
LED doubles as emitter and square wave. The comparator drives a sponse time. The circuit in Figure 1 does
detector ..........................................................108 gate (or several gates if you need more not oscillate or multiple-switch under
Watchdog circuit uses ac triggering ........112 output drive) through R3. R3 must have any conditions. It produces a square wave
a low value to quickly charge the gate in- that’s adjustable from 2 to 98% duty
Use power line for baud-rate put during the low-to-high transition. cycle, and it responds to 20-mV input
generation......................................................112 The current the comparator can sink lim- signals.
Inline equations offer hysteresis its R3’s lower value.
switch in PSpice ............................................114 The TLV2470 integrator integrates and
inverts the output square wave and feeds Is this the best Design Idea in this
it back as the reference voltage for the in- issue? Vote at www.ednmag.com.
design
ideas
Circuit improves on first-event detection

Lawrence Arendt, Oak Bluff, MN, Canada
he circuits in figures 1 and 2 ex- simple scalability. You can easily add any flops having reset and clear pins: either
T hibit certain advantages over the cir-

cuit shown in the Design Idea in
EDN, “Circuit detects first event,” May 3,
number of additional player-event-de-
tection channels to an event-detection
configuration. All that’s needed is that
74F74s for regulated 5V supplies or, with
minor circuit changes, 4013s for unreg-
ulated 9V-battery supplies. For a 74F74
2001, pg 89. The n-player first-event-de- you connect the additional circuits to a implementation, the D input of flip-flop
tection circuit offers several improve- common five-wire bus consisting of VCC, FF0 connects to logic 1. The Q output of
ments: ground, the Reset, the SwitchBus signal, this flip-flop drives the SwitchBus signal.
● It has fewer passive components. It and the CaptureInhibit signal. Thus, the The Q outputs of FF! through FFn have
needs only n diodes instead of (n21n)/2 wiring complexity is independent of n; in a diode-OR connection to the Cap-
for three or more players. And, exclud- other words, it is O(1). Expanding the tureInhibit signal, which clocks the clock
ing the LEDs’ current-limiting resistors, number of players for the original event- input of FF0. All the Set inputs for FF1
the circuit needs only n11 resistors in- detection circuit requires additional through FFn are connected through re-
stead of 5n. diode-connected reset signals from each sistors to logic 1. Upon power-up or after
● The circuit uses less expensive ICs. channel to all other channels, resulting in you press the reset button, all the flip-
The 74F74 or 4013 costs only 25% of the a wiring complexity that scales as flops’ Q outputs are at logic 0 because of
price of a LMC6762 (DigiKey catalog). (n222n), or O(n2). a pulse on the flip-flops’ Reset inputs. The
● The circuit offers inexpensive and ● The improved circuit uses D flip- reset forces the SwitchBus signal to logic
5V
4 VCC
9V 9V 6
VCC SWITCHBUS 5 Q PR 5V VCC VCC 1
2 S
74F74 D VCC Q 5 9V
FF0 CAPTUREINHIBIT 4013 D VCC
6 3
Q CLK SWITCHBUS 2 FF0 3 CAPTUREINHIBIT
10k CL Q CLK
10k 0.1 mF R
RESET 1 10k
10k RESET 4
5V 10k
PLAYER 1 VCC
10 PLAYER 1
12 D1 10k 8
0.1 mF DPR 9 9 D1
Q D S 13
74F74 Q
1N914 4013
11 FF1 R1 1N914
CLK 8 5V RESET 11 FF1 R1
CL Q VCC CIRCUIT CLK
Q
12 9V
470 R VCC
RESET 13 LED1 1k
10 LED1
CIRCUIT
10k 5V
VCC 10k
PLAYER 2 4 Figure 2 PLAYER 2
2 D2 6
D PR 5 5 D2
Q D S 1
74F74 Q
1N914 4013
Figure 1 3
CLK
FF2
6
R2
5V 3 FF2
1N914
R2
CL Q VCC
CLK
CLK 2 9V
470 R Q
1 LED2 1k VCC
4 LED2
10k 5V 10k
VCC
PLAYER N 4
DN PLAYER N 6
2 PR 5 DN
D 5 S 1
74F74 Q D
3 FFN 1N914 4013 Q
6 RN FFN 1N914
CLK 5V 3 RN
CL Q CLK 2 9V
VCC Q
470 LEDN R VCC
1 1k
4 LEDN
This first-event-detection circuit uses standard 74F74 flip-flops with a

5V supply. You can use 4013 flip-flops in a 9V-battery-powered system.

design
ideas
0. When you press player-event switch m, flop connections are the same as for the (SwitchBus) to logic 0. Because Switch-
the logic-0 SwitchBus signal connects to 74F74 circuit. Upon power-up, or after Bus is now at logic 0, and applying a log-
the Set of the mth flip-flop, forcing QM to you press the reset button, all the flip- ic 0 to the Set input of a 4013 has no ef-
logic 1. QM now clocks FF0, forcing its Q flops’ Q outputs are at logic 0, because of fect, any further switch closures by player
output (SwitchBus) to logic 1. Because a pulse on the flip-flops’ Reset inputs. m or any other player now have no effect.
SwitchBus is now at logic 1, and applying The Reset signal forces the SwitchBus sig-
logic 1 to the Set input of a 74F74 has no nal to logic 1. When you press player-
effect, any further switch closures by event switch m, the logic-1 SwitchBus
player m or any other player now have no signal connects to the Set input of the
effect. mth flip-flop, forcing QM to logic 1. QM Is this the best Design Idea in this
For a 4013 implementation, the flip- now clocks FF0, forcing its Q output issue? Vote at www.ednmag.com.
LED doubles as emitter and detector

Kyle Holland, LI-COR Inc, Lincoln, NE
very junction diode exhibits 1
E some degree of photo-

sensitivity when it re-
ceives light comprising an appropri-
Figure 1 0.9
0.8
ate range of wavelengths. The spectral
response of a junction diode depends 0.7
RESPONSIVITY
EMISSION
on a variety of factors, including ma-
terial chemistry, junction depth, and 0.6
packaging. The packaging of most
devices aims to inhibit sensitivity to RELATIVE 0.5
RESPONSE
radiant flux to maintain the intended
function of the device. However, 0.4
some devices’ packaging and con-
0.3
struction techniques allow conven-
ient exposure to light. The most
0.2
common light-sensitive devices, pho-
todiodes and phototransistors, sense 0.1
and measure light from a variety of
sources. Other light-sensitive diodes, 0
which don’t usually come to mind for 700 750 800 850 900 950 1000 1050 1100
light-sensing applications, are LEDs. WAVELENGTH (nm)
LEDs, packaged to emit radiant flux,
can serve as narrowband photode- Enough overlap exists between the responsivity and emission curves to make a LED useful for both
tectors. The devices lend themselves transmission and reception.
to applications in which they serve as
spectrally selective photodetectors or to
applications in which they act as
transducers. References 1 through Figure 2
SYSTEM 1 SYSTEM 2
4 provide further information on opto-
electronic devices. Tx
OPTICAL OPTICAL
Tx
Rx Rx
An LED’s sensitivity to light and par- Tx/Rx
TRANSCEIVER TRANSCEIVER
Tx/Rx
ticularly to its emission wavelength de-
pends primarily on the device’s bulk ma-
terial absorption and junction depth. For
LEDs that have low bulk absorption, This half-duplex application uses a LED for both transmission and reception.
design
ideas
photosensitivity at or near
peak wavelength is low, and, 5V
VCC
as a result, the creation of Tx
hole-electron pairs is low.
5V R7
GaAs-based emitters with IC2
emission wavelengths of 940 C3 + C2
270k R8
R3 C1 100k
nm have relatively good sen- 3.3M 0.1 mF 10 mF 10 pF R9
sitivity at or near their peak R1
Tx/Rx
470 D1 (GENERAL-
emission wavelength, thanks Q1
3 8 1N4148 PURPOSE
1k + + 5
to high bulk absorption. Fig- 1
+
R10 I/O PIN)
IC1A V 7 Rx
ure 1 shows the relative re- R2 IC1B
1k
2 6
sponsivity and emis- 100 2 2 2
Figure 3 4
sion spectra for an R4 GND
R6
Infineon (www.infineon. LED 10k
10k
com) SFH409 LED. This in- R5
470
frared GaAs LED has peak
emission at 940 nm with a
half-peak bandwidth of 50
nm. In detection mode, it One dual op amp and a handful of components turn a LED into a dual-purpose device.
peaks at 920 nm with a half-
peak bandwidth of 55 nm. As Figure 1 acting as a shunt current-to-voltage con- blocks any transition occurring on the Rx
shows, the wavelength of peak respon- verter and a high-speed, noninverting line from activating the UART’s receiver.
sivity is shorter than the peak-emission voltage amplifier (IC1A). Resistor R3 pro- When switching between transmitting
wavelength, and a fair amount of overlap vides a slight bias of a few millivolts to and receiving modes, the software should
exists between the two curves. Thanks to R4 to keep IC1A in its linear region. The include a time delay to allow for pream-
this overlap, the LED is useful as a trans- op amp in this design is the high-speed plifier recovery. The preamplifier-recov-
ducer. Figure 2 shows a half-duplex ap- dual OPA2350 from Texas Instruments’ ery delay is typically less than 10 to 20
plication that exploits the LED. Burr-Brown division (www.ti.com). The msec. Note that for 8051-class microcon-
Here, the LED links two embedded device has rail-to-rail inputs and outputs trollers with depletion-mode pullup re-
systems via a fiber-optic cable or a short- and a gain-bandwidth product of 38 sistors on their I/O pins, you should re-
distance, line-of-sight coupling path. Fig- MHz, and it can operate from a single 2.7 place D1 with a pnp transistor and an
ure 3 shows the transceiver circuit used to 5V supply. The transconductance gain associated base resistor.
in Figure 2’s application. The circuit can of the preamplifier is a function of the
send half-duplex data between two em- values of R4, R5, and R6. In the circuit of References
bedded systems at rates as high as 250 Figure 3, the resistor values produce a 1. “The Radiometry of Light Emitting
kbps. The circuit comprises the LED transconductance gain of approximate- Diodes,” Technical Guide, Labsphere Inc,
driver, the preamplifier, and the output ly 220,000. The output comparator, IC1B, North Sutton, NH.
comparator. The LED driver drives the converts the preamplifier’s output signals 2. “GE/RCA Optoelectronic Devices,”
LED during data transmission and un- to logic-level voltages. You set the input GE/RCA Corp, 1987.
hooks the Tx pin from the LED during threshold of the comparator by adjusting 3. Gage, S, D Evans, M Hodapp, and H
data reception. The Tx pin connects to resistor R8. By properly adjusting the Sorensen, Optoelectronics Applications
transistor Q1 via base resistor R1. When threshold, you can obtain good pulse Manual, McGraw-Hill, 1977.
the Tx pin is in the idle state (logic 1), the symmetry for a variety of input-power 4. Sze, S, Semiconductor Devices—
quiescent current of the LED driver is conditions. The combination of R9 and Physics and Technology, Wiley, 1985.
zero, because Q1 is off. Activating the Tx C1 provides ac hysteresis and additional
pin (logic 0) causes Q1 to turn on. Resis- overdrive for improved comparator
tor R2 sets the LED’s output-power level. switching. Moreover, R9 limits the
You should set the power level to com- switching current on input Pin 5 of IC1B
pensate for transmission losses through for logic one-to-zero transitions.
the communication medium and to During data transmission, the trans-
minimize pulse-distortion phenomena mitter circuitry drives the preamplifier
in the communication link. R2 should be and comparator. To prevent locally trans-
50 to 220V when the circuit operates mitted data from causing UART overrun
from a 5V supply. errors, the Tx/Rx line should be at a log- Is this the best Design Idea in this
The preamplifier consists of resistor R4 ic-1 level. The combination of R10 and D1 issue? Vote at www.ednmag.com.

design
ideas
Watchdog circuit uses ac triggering
Shyam Tiwari, Sensors Technology Private Ltd, Gwalior, India
dc-triggered reset of a that a reset signal from a
A watchdog circuit is prone to

failure. If the watchdog
program hangs up, then the
Figure 1 Q1
2N2222
1k
74C14
watchdog circuit to a mi-
croprocessor is equivalent
to a power-on reset, but it is
reset signal becomes activated con- LOW ACTIVE not. The warm-boot and
WATCHDOG 1k RESET
tinuously, and the microprocessor + cold-boot programs in em-
RESET C1 OUTPUT
has no way to escape the situation. FROM THE 1 mF 10 mF bedded microprocessors
MICROPROCESSOR
We found that a simple solution significantly differ. Warm-
uses an ac trigger to reset the boot watchdog signals are
watchdog circuit (Figure 1). We This watchdog circuit uses ac triggering to avoid watchdog-signal prone to hang-up. The cir-
used an RC oscillator consisting of hang-up problems. cuit in Figure 1 can activate the
a 74C14 gate to generate active-low microprocessor even if the
reset signals to the microprocessor at ap- to a low level. If the watchdog trigger re- watchdog signal hangs up.
proximately 10-msec intervals. High-lev- mains in a high state for a longer period
el pulses at the base of the transistor than you want, the oscillator generates an Is this the best Design Idea in this
switch Q1 reset the charging capacitor C1 active-low reset pulse. You may believe issue? Vote at www.ednmag.com.
Use power line for baud-rate generation

Joseph Julicher, Microchip Technology Inc, Chandler, AZ
ne cost-saving measure asso-
O ciated with 8-bit embedded mi- TABLE 1—SAMPLE NUMBERS FOR BAUD-RATE GENERATION
crocontrollers is to use a resis- FOSC
tor-capacitor oscillator. These RC
4
Reference Timer 1 Timer 1 Calculated Desired
60 16 4166.667 4,000,000 9600 1 25

Actual
9615.38
Percent
(MHz) frequency prescale counts frequency baud rate BRGH SPBRG baud rate of error
0.16
oscillators are inexpensive, but the
4.4 60 16 4583.333 4,400,000 9600 1 28 9482.75 21.22
trade-off is low stability with tem-
3.6 60 16 3750 3,600,000 9600 1 22 9782.6 1.90
perature and voltage. In many appli-
cations, the low cost of an RC oscil-
lator is alluring, but the application can power this PIC microcontroller from INTRC value is 4 MHz, and the power-
requires a stable clock source for baud- a separate circuit that includes voltage line frequency is 60 Hz. Set BRGH for a
rate generation or event timing. In these regulation (see Tech Brief 008 at baud clock 16 times the baud rate, and set
cases, you can find a low-frequency, sta- www.microchip.com concerning a trans- Timer 1 prescale to 16. The desired baud
ble clock source and use it to calibrate a formerless power supply). The power line rate is 9600.
baud-rate generator or event timer. One supplies a solid 50- or 60-Hz reference The formula we use is ((Timr1 val-
source of a low-frequency, stable clock is frequency. You can use the 16-bit Timer ue3prescaler3reference frequency3
the line voltage. This voltage is a good 1 to time the internal oscillator. As the in- baud multiplier))215SPBRG value. We
source 50- or 60-Hz frequency that you ternal RC time constant drifts, the timer used a spreadsheet to run some sample
can easily interface to the microcon- count changes, and you can use the val- numbers, and the results are in Table 1.
troller’s 16-bit timer. By counting CPU ue to determine new values for the baud- To use the technique with a PIC micro-
cycles for a half cycle of the external rate generator. If you adjust the baud-rate controller, simplify the math to
clock, you can determine the frequency generator appropriately, you can main- (Timr1/160)215SPBRG. You will find
of the microcontroller’s internal RC os- tain the baud rate to 62% of the desired that 9600/(16360)5160. This simplifi-
cillator and calibrate the baud rate. value. The incremental cost may be less cation causes a slight error; the rounded
The PIC16F627 flash microcontroller than the cost of a crystal or ceramic res- off value of SPBRG becomes 27 instead
can benefit from this technique. This de- onator. You can also use this technique to of 28. The error at 4.4 MHz becomes
vice has an internal 4-MHz RC oscillator. periodically learn the value of the inter- 2.3% instead of 21.22%.
You can create a simple capacitor-cou- nal RC oscillator to calibrate time cap-
pled circuit to allow the microcontroller tures of external events. The following is Is this the best Design Idea in this
to see the pulses from the power line. You an example of the technique: The base issue? Vote at www.ednmag.com.
design
ideas
Inline equations offer hysteresis switch in PSpice

mooth-transition switches are teresis. Figure 1a shows how to wire this events. Figure 2 shows how you can de-
S convenient devices in many Spice-

based simulators. Their action can
greatly ease the convergence process. Un-
component in a simple comparator ar-
chitecture. Figure 1b shows the resulting
VOUT versus VIN curve. In Cadence’s
rive the new device with adjustable hys-
teresis.
Listing 1 is the complete PSpice netlist
fortunately, these devices lack inherent (www.cadence.com) PSpice, the S1 prim- for the switch. The inputs V(plus) and
hysteresis, a helpful feature used to build itive switch implements a soft transition V(minus) route the switch-control signal
UVLO (undervoltage-lockout) systems, between RON and ROFF, but VON and VOFF to the Bctrl behavioral element. (A b el-
oscillators, and other systems. Intusoft’s are simply the final levels that reflect the ement in IsSpice4 becomes a “value” E
(www.intusoft.com) IsSpice4 not only specifications for RON and ROFF. To incor- source in PSpice.) When the switch is
provides users with smooth-transition porate some hysteresis, you just need to open (Bctrl delivers logic 0), the reference
devices, but also adds the Berkeley Spice add some analog-behavioral-model node (node ref) becomes armed at the
primitive switch featuring adjustable hys- sources to help tailor our switching highest toggling point (7V in Figure 2’s
13 VOUT
VIN +
Figure 1 VT THRESHOLD=5
9 VIN
VH HYSTERESIS=2
1 S1 2
+ +
VOUT (V) 5
V2 VOUT VCC
3 10
R1
10k
1
23
1 3 5 7 9
(a) (b)
VIN (V)
This switch circuit (a) toggles at 7V and resets at 3V, yielding 4V hysteresis (b).
Bctrl
Voltage
V(plus)-V(minus)>V(ref) ? 1:0
Rconv1
10Meg NodePlus
plus Figure 3 Rt R1
8 + 100k 1k
+
Rconv3 S1 Vc VOUT
10Meg 3 2
_
+ X1 1
3 + Vcc
+ SWHYSTE
Rconv2 NodeMinus Ct Vt45V 15
Figure 2 10Meg
Bref 100 pF Vh42V
minus Voltage
ref
+
Rconv4
10Meg
_
V(8,9) > 0.8 ? 3V : 7V
Some analog-behavioral-model sources and a primitive S switch yield a

switch with adjustable hysteresis. These results clearly show the 4V hysteresis in Figure 2’s subcircuit.

design
ideas
example). When the input voltage in-
creases, it crosses the ref level, and Bctrl
switches high. Switch S1 closes and au-
thorizes the current to flow in its termi-
nals through RON. At this time, the Bref
source has detected that S1 is closed and
now modifies its reference node to the
second level (3V in the example). When
the input voltage drops, it crosses the 7V
level, but no action takes place, because
ref has changed to 3V. When the input
voltage finally crosses 3V, S1 opens and
applies ROFF between its terminals. Figure
TIME (mSEC)
3 shows the PSpice simulation results,
confirming the 4V hysteresis. Figure 4 A switch with hysteresis and a few passive elements produce an RC
shows how to build a simple RC test os- Figure 4
oscillator.
cillator, using the PSpice-derived hys-
teresis. You can download the PSpice LISTING 1—PSPICE NETLIST FOR SWITCH WITH HYSTERESIS
netlist from the Web version of this arti-
cle at www.ednmag.com.

issue? Vote at www.ednmag.com.

design
ideas
Video emitter uses battery power
he block diagram in Figure 1
T shows how to make a cable-

free, direct-video system. The
system allows users to walk from booth
Figure 1
12V BATTERY
POWER SUPPLY
ANTENNA
to booth at an exhibition to interview VIDEO SIGNAL

people and to display the interviews in IMAGE VIDEOCAMERA VIDEO
AUDIO SIGNAL EMITTER
real time on three screens at key loca- SCENE
tions. You can use the small and simple SOUND
system each time you need to capture im- MICROPHONE UHF CHANNEL 22
AUDIO SIGNAL
age and sound on the run. Figure 2 (pg
96) shows a detailed schematic diagram VIDEO PROJECTOR
VIDEO RECORDER
of the video system. The system provides ANTENNA
VIDEO PC INPUT
no stereo audio but rather mixes togeth-
er right and left sources. IC2A acts as an TV RECEIVER IMAGE/SOUND VIEWERS
inverter/adder. At Point C, the ac signal
represents the sum of the left and right
channels: VC52R1(VA/R21VB/R3). With
the same value for the three resistors, A wireless, battery-powered video system uses UHF Channel 22 to transmit signals to video
VC5(VA1 VB). C8 and C9 block any dc receivers.
voltage at points A and B. IC2A works
from a single 12V supply but needs a con- supply, but when the output voltage is camera is on. When the videocamera is
tinuous bias voltage to provide a positive close to 0V, it needs some help to avoid off or disconnected, the supply current
and negative swing around 6V. R4 and R5 signal distortion. Pulldown resistors R6 decreases to only a few milliamperes.
create a 6V bias source for both IC2A and and R7 minimize the distortion. IC5 and C4 through C7 provide a 5V
IC2B. IC2B acts as an inverting voltage am- IC4 is a video-emitter IC from Aurel supply to IC4. IC1 and C1 through C3 pro-
plifier with a gain of P1/R8. With the val- (www.aurel.it) that works in the UHF vide a stable 12V supply to IC3 and the
ues shown, you can adjust the gain as band at 479.5 MHz (UHF Channel 22). LM358. You can connect a 12V battery
high as 4.7. You can adjust P1 for audio Its output power is 2 mW to a 75V an- directly to J1. IC3’s data sheet specifies a
gain as high as 13 dB. C10 blocks the 6V tenna, A2. Typical supply current is 90 supply level of 11.4 to 12.6V, but tests
dc at Point D, so only the ac audio volt- mA. The signal from the videocamera show that the IC works properly if the
age is present at the audio input of IC 4. connects directly to IC4’s input. If you supply is higher than 11V. The total 200-
The LM358N works well from a single need more power, you can add IC3, also mA current consumption yields approx-
from Aurel. This IC works in the same imately three-hour battery life with 12
frequency band as IC4 and boosts power AA cells. If you use a switching power
Video emitter uses battery power ..............95 to 19 dBm in the 75V antenna. Both IC3 supply, you would obtain longer battery
and IC4 are available in small, single-in- life, but you need to take filtering meas-
Circuit avoids metastability..........................96 line packages. A Switching Level signal ures to avoid interference with the video
Microphone uses “phantom power” ......100 from Pin 8 of the SCART video connec- path. If an ac outlet is available, you could
tor is present when the videocamera is use an 18V, 300-mA wall adapter to re-
Measure humidity and
on. The current consumption of IC3 and place the battery.
temperature on one TTL line....................102
IC4 is 90 (5V) and 100 mA (12V), re-
Low-cost anemometer fights dust ..........102 spectively. To reduce power consump- Is this the best Design Idea in this
tion, a dual-contact relay, K1, connects issue? Vote at www.ednmag.com/edn
IC3 and IC4 to the supplies only when the mag/vote.asp.

design
ideas
WALL ADAPTER
IC1 IC5
15 TO 18V 300 mA BATTERY INPUT 5V
78M12 12V 78MO5
1N4003 1k
15 TO 18V 12V 1 AHR
BORNE2 IN OUT IN OUT
+ C2 BORNE2 C5 C6
D1 GND C3 GND C7
2 100 nF 2 100 nF 100 nF D2
+ C1
100 nF + C4 + 10 mF
1 RED LED
1 100 mF 100 mF
J1
5V
Figure 2 A2 12V
75V ANTENNA
A1
75V ANTENNA
IC4
MAV-UHF 479
100 nF 1
11 VCC
8 ANT 15
VCC 3 ANT
7 100 nF 7
GND 10 10 GND
GND-OUT
13 IC3
4 6
VIDEO-IN RF-IN MCA 479
VIDEO GND 3 2
VIDEO-GND 12V EN
2
AUDIO-IN
1
12V AUDIO-GND
21 20 VIDEO IN
K1
19 REL-G5V2
18 D3
17 1N4003 SOUND GND
16
15
14 2N7000 SOUND OUT
13
12 1k
11 2
10 R1 C
9 3 P1 1
8 SWITCHING LEVEL A C8 47k CH
7 47k
4.7 mF R2
IC2A R6
IC2B
6 SOUND IN LEFT 2 10k 4.7 mF
5 1 1 61 D
+ 3 + 7 +
4 SOUND GND 47k
C9 5 +
3
4.7 mF R3 LM358N R7 C10
2 SOUND IN LEFT 2k LM358N
1 2k
+
47k
SCART B
R4 VCC/2=6V
VIDEOCAMERA IN 12V
8 V+ 10k +
R5 2.2 mF
IC2P 10k
4 V1
In this video transmitter, 12 AA cells provide approximately three hours of operation.
Circuit avoids metastability

Jonathan Eckrich, Adaptivation, Sioux Falls, SD
onsider a computer system while some bits are chang-
C that has a host proces-

sor connected to a re-
mote-I/O subsystem (Figure 1).
Figure 1
REMOTE
HOST DATA
HOST CLOCK
REMOTE CLOCK
HOST
SYSTEM
ing. The result is that some
data may be corrupt, or,
worse, the input registers
The host clock treats the I/O sys- SYSTEM may go into a metastable
tem, which is located far from the LOGIC REMOTE DATA state. The circuit in Figure 2
main hardware, as a slave. Because prevents clocking bad or
of the transmitters, receivers, re- changing data. It does so us-
mote-system logic, and cable At or near 360 or 1808 phase difference between the two clocks, this ing only general-purpose,
length, the data the host receives has remote-I/O system is subject to metastability. “jellybean” logic. The key is
a dramatic latency. This latency can to remote-clock back to
be larger than the clock period. If the problem with such latency is that receiv- host. This action allows XOR gate IC1A to
length of the cable is indeterminate, then ing registers in the host system might compare the phase difference between
the latency is also indeterminate. The clock in the data from the remote system the host clock and the delayed clock.
design
ideas
When the two clocks are nearly in clock. If the host were to clock in the data too low, the resulting ripple can cause the
phase, the duty cycle of IC1A’s output is on the rising edge of its clock, metasta- output of the comparator to be unstable.
close to 0%. When the two clocks are bility would become a concern. You can You could use a comparator with hys-
close to 1808 out of phase, the duty cycle simply clock in the data on the falling teresis to reject the ripple. Some instabil-
approaches 100%. Whatever the duty cy- edge of the host clock, but this solution ity of the comparator’s output is accept-
cle is, it is constant during normal oper- yields the same problem if you choose a able, because you can safely use either the
ation. The only way it can change is for new cable with a different length. rising or the falling edge for most laten-
the cable length between the two systems Without any analytical effort on the cies. You need stability only when the
to change. R1 and C1 form a lowpass fil- designer’s part, the circuit in Figure 2 au- clock is near 360 and 1808 out of phase,
ter. Set R3 equal to R4 so that the reference tomatically selects which clock edge to so you have little to lose by using a large
voltage is at midpoint. IC2 and IC1B then use. Note that comparator IC2 can be a R1C1 time constant to present a dc volt-
select whether to clock register IC3 on the low-speed part, because it operates at dc age to the comparator’s input.
rising or falling edge of the host clock. IC4 only. Note also that if the two clocks are
ensures that the data changes consistent- 3606908 out of phase, the circuit uses the
ly with the rest of the host system. Figure falling edge of the clock. If they are Is this the best Design Idea in this
3 shows a (delayed) remote clock that is 1806908 out of phase, the circuit uses the issue? Vote at www.ednmag.com/edn
nearly 3608 out of phase with the host rising edge. If the R1C1 time constant is mag/vote.asp.
DATA
8D 8Q 8D 8Q
7D 7Q 7D 7Q
Figure 2 6D 6Q 6D 6Q
5D 5Q 5D 5Q
SYNCHRONIZED
4D
IC3 4Q 4D IC4 4Q
VCC DATA
3D 3Q 3D 3Q
2D 2Q 2D 2Q
R3 1Q
HOST CLOCK R1 1D 1Q 1D
IC1A 1 IC1B CLK CLK
REMOTE CLOCK IC2
+ OC OC
C1 +
R4
This circuit automatically chooses between the rising and the falling edge on the host clock for clocking in data.
HOST CLOCK
Figure 3 DATA OUT

FROM HOST
CLOCK
FROM REMOTE
DATA IN
DATA IN 0 DATA IN 1 DATA IN 2 DATA IN 3
FROM REMOTE
XOR:A OUTPUT
DATA IN CLOCKED IN
ON RISING EDGE POTENTIAL METASTABLE STATE
OF HOST CLOCK
DATA IN CLOCKED IN
ON FALLING EDGE DATA IN 0 DATA IN 1 DATA IN 2
OF HOST CLOCK
Clocking data on the wrong edge can result in metastability; the circuit in Figure 2 selects the right edge.

design
ideas
Microphone uses “phantom power”
Bruce Trump, Texas Instruments, Tucson, AZ
he electret microphone capsule is tom-power source. The amplifier outputs The receiving-end amplifier, IC3, is a
T similar to those commonly used in

telephones, cassette recorders, and
computers. The element functions as a
use ac coupling, C2 and C3, to the micro-
phone’s output terminals to block the dc
phantom-power voltage on the audio
low-noise instrumentation amplifier
with three internal op amps. Its configu-
ration and laser-trimmed resistors pro-
capacitor with a fixed trapped charge. lines. Differential-output voltage capabil- vide excellent CMR (common-mode-re-
Sound pressure moves a diaphragm, pro- ity is limited to approximately 2V p-p be- jection) properties. The high CMR rejects
ducing variations in the capacitance. This cause of the limited power supply avail- noise and power-line hum that appear
action produces an ac-output voltage able to drive the op-amp output currents. equally in both signal lines. Low noise (1
with an extremely high source imped- This level is adequate, because it corre- nV/=Hz), though unnecessary for high-
ance. A FET inside the capsule uses an ex- sponds to an extraordinary sound level output microphones such as those de-
ternal-resistor drain load (Figure 1). R1 beyond the linear range of the capsule. scribed here, is necessary in professional-
and R2 provide an appropriate load im- Phantom-powered microphones de- audio equipment to accommodate the
pedance and voltage from the 10V sup- rive power for their active circuitry from use of low-output ribbon and dynamic
ply. The basic performance of this simple the receiving-end circuit through the microphones. These microphone types
capsule is excellent, but it requires further same leads that transmit the audio signal. are strictly passive electromechanical
signal processing to conform to profes- The 48V phantom-power supply couples generators and do not require a power
sional phantom-powered-microphone through two 6.8-kV resistors, R10 and R11, source. Phantom power earns its name
standards. to both signal lines. This coupling allows from the fact that these microphone
The output of a phantom-powered mi- the microphone’s low output impedance types “float” at 48V without harm. The
crophone is a low-impedance differential to drive a differential ac signal on the rel- electret capsules are available in various
signal. IC1 is a simple voltage buffer that atively “soft” impedance of the phantom sizes and physical configurations. They
provides low-impedance drive for one supply voltage. In the microphone, pow- include both omnidirectional and direc-
output. IC2 is a unity-gain inverter that er comes from the signal lines through re- tional (cardioid) types. Directional cap-
derives its drive from the output of IC1. sistors R8 and R9. Zener diode D1 regu- sules have a vent in the rear; you must
Bias for the noninverting input of IC2 lates the voltage. These resistors also mount them with free access to both the
comes from a heavily filtered output of provide a soft impedance on the balanced front and the back to obtain proper char-
IC1. We selected the dual op-amp IC1/IC2 line, allowing the outputs of IC1 and IC2 acteristics.
for its low noise and low distortion prop- to inject their differential ac-output sig-
erties. R6 and R7 provide immunity from nal. You can locate the microphone hun-
long-line capacitance, RF interference, dreds of feet from the receiving-end Is this the best Design Idea in this
and transients that occur when you “hot- phantom power and amplifier and still issue? Vote at www.ednmag.com/edn
plug” the microphone into a live phan- obtain excellent performance. mag/vote.asp.
MICROPHONE PHANTOM RECEIVING-END

POWER AMPLIFIER
D1 48V
33 mF +
10V 1 mF
R8 R9 +
15V
1.5k 1.5k
Figure 1 R1 _ C2 R6 6.8k 6.8k
3.3k IC1
+ R10 R11
OPA2227*
+ 33 mF 47 + +
R2
10 mF IC3
6.2k RG
2 2 INA163*
10 mF
1k 1k _
PANASONIC 3 3 +
1 1
WM-034CY*
_ 3.3k 3.3k
C3 R7
IC2
10k +
OPA2227*
+ 33 mF 47 _15V
+
10 mF
*AVAILABLE FROM
DIGI-KEY
This microphone system derives its power from the receiving-end circuitry through the leads that carry the audio signal.

design
ideas
Measure humidity and temperature on one TTL line
Shyam Tiwari, Sensors Technology Pvt Ltd, Gwalior, India
y combining the responses of an
B Analog Devices (www.analog.com)

AD590 temperature sensor and a
Humirel (www.humirel.com) HS1101
5
2 13
HUMIDITY
humidity sensor, you can generate a sin- OUTPUT

TEMPERATURE
gle TTL-level signal containing 4
Figure 1
information from both sensors
10 5V
(Figure 1). This design uses a 74HC123 9 TO 12V IC1
monostable multivibrator, IC1, to form a +
74HC123 16, 11, 3
IC2 OR
free-running oscillator. The AD590 cur- 74HCT123
AD590
rent source (1 mA/K), IC2, and a fixed 1- 1
7 R1
nF capacitor, C1, control the timing of the C1
1M
first monostable multivibrator in the 1 nF 15
6
74HC123. Another monostable multivi-
brator uses a fixed 1-MV resistor along HS1101
1, 8, 9 14
with the capacitive output of the HS1101
(172 pF at 0% relative humidity and 222
pF at 100% relative humidity) for its tim-
ing. Combining the two monostable
multivibrators creates a free-running os- A monostable-multivibrator IC provides temperature and humidity information in one TTL signal.
cillator that produces a single-line signal
from both sensors. The high- and low- increased pulse width with rises in hu- toisolator in the output path if you need,
level pulse widths carry the information midity levels. The circuit in Figure 1 rep- say, 1500V isolation.
related to the sensor signals. The AD590 resents a simple method of transmitting
circuit displays pulse-width reduction signals from analog sensors by digital
with rising temperature, because of its in- rather than analog means. The technique Is this the best Design Idea in this
creased output current with higher tem- eliminates noise in signal transmission issue? Vote at www.ednmag.com/edn
peratures. The HS1101 circuit displays over long distances. You could add an op- mag/vote.asp.
Low-cost anemometer fights dust

Jim Christensen, Maxim Integrated Products, Sunnyvale, CA
s higher levels of power dissipa- that is worse than the original problem.
A tion underscore the need for cool-

ing, more and more fans are finding
their way into small electronic enclo-
TABLE 1—FAN VOLTAGE
VERSUS COOLING TIME
Fan voltage Cooling time
Trying to sense a clogged filter by sens-
ing the fan’s rotation with tachometer
signals is useless, because fan rotation is
sures. The dust that fans pull into these (V) (sec) not directly related to airflow.You can de-
enclosures can, however, cause major 12 30 tect poor filter maintenance by deter-
problems for high-reliability systems. By 8 47 mining the actual airflow with a “hot-
coating heat sinks and electrically 6 60 wire” anemometer, but most electronic
charged components, the dust acts as a 0 (no fan) 84 anemometers are costly and bulky. As an
blanket that raises the effective thermal alternative, you can create an SMBus/I2C
impedance between the components and air intake. If you fail to replace the filter anemometer using an I/O expander, a
the air. A simple way to combat this prob- on a regular basis, however, it can become few inexpensive switches, and a low-cost
lem is to place a disposable filter on the clogged and act as an air dam, a condition remote-temperature sensor (Figure 1).
design
ideas
Use the SMBus I/O expander, IC4, to the temperature drops; you can deter- times as long as 30 minutes do not sig-
turn off MOSFETs Q1 and Q2 and to turn mine it by noting the time required for nificantly alter the times. The circuit
on the analog switches IC2 and IC3. Mea- the transistor to return to within 18 of its draws approximately 200 mA when Q3 is
sure the ambient air temperature with no original temperature. The temperature heating. If this power dissipation poses
preheating of Q3. Then, to apply current sensor injects a small current into the a problem, you can lower the measure-
for heating Q3, turn off IC2 and IC3 and base junction, so careful layout is impor- ment frequency to hourly or even daily
turn on Q1 and Q2. Allow an approximate tant to keep noise off the DXP and DXN cycles, because changes in airflow occur
five-minute “soak” to reach temperature lines. slowly over time. You can also schedule
equilibrium. (The exact heating time If you mount the remote transistor in the measurements during times of low
necessary for equilibrium depends on the an air channel, the use of twisted-pair system activity, when overall power use is
setup; you must determine it by experi- wire allows distances to 12 ft. Table 1 low.
ment.) At equilibrium, remove power shows fan voltage (airflow) versus cool-
from Q3 by turning off Q1 and Q2, and ing time for a sensor placed approxi-
turn on analog switches IC2 and IC3 to mately 12 in. away from a fan running at Is this the best Design Idea in this
make temperature measurements. Air- full speed (12V), medium speed (8V), issue? Vote at www.ednmag.com/edn
flow directly relates to the rate at which low speed (6V), and zero speed. Soak mag/vote.asp.
3.3V
220
Figure 1
100k Q1
0.1 mF
6 FDN336P
SMBDATA 9 VCC 100k
SMBCLK 8 IC2
MAX4626 10 Q3
5 2W
7 2N3904
5 2 1
10 IC1 DXP TWISTED PAIR
MAX1618 4
2 2200 pF
ADD1 IC3
MAX4626 5
1
ADD0 4 1
DXN
3 4 AIRFLOW
100k Q2
FDN335N
3.3V
1 xF34ALL SWITCHES OFF.
xF24MEASURING SWITCHES ON.
xF54POWER FETs ON.
8
2
I/O1
9
3
10 IC4 I/O2
MAX1661
4
7 I/O3
3.3V
6
ADD
This anemometer measures airflow by heating Q3 and then noting the time for Q3 to return to its original temperature.

design
ideas
Circuit gang-programs EEPROMs over I2C bus
Denisa Stefan, Catalyst Semiconductor, Sunnyvale, CA
ou use the fully controlled circuit VCC
Y in Figure 1 to parallel-pro-
gram two-wire serial EE-
PROMs via the I2C bus. Gang program-
Figure 1
SCL
CAT24WC16
mers must address all memory devices 2
I C BUS 2
I C BUFFER
SDA SCL A2
during a write operation. To verify the (82B715) 1
0 A1
4 MAX352
memory contents, however, the system SDA A0
must address only one memory at a time
during read operations. Therefore, the CAT24WC16
system in Figure 1 addresses the memo-
SCL A2
ry devices either in parallel or one at a 16-BIT I/O
1 A1
(PCF8575)
time. Information transfer between de- SDA A0
vices connected to the I2C bus system re- SCL P01
P02
quires a SDA (serial-data) and SCL (se- SDA
rial-clock) signals. A device connected to P07
the bus can operate as a transmitter or a A0 P10
receiver. A master device initiates a data A1
CAT24WC16
transfer on the bus, generates clock sig- SCL A2
A2 P17
nals, and terminates the transfer. The 15 A1
SDA
master addresses a slave device. To con- A0
2
nect devices on an I C multimaster bus,
the SDA and SCL lines must be bidirec-
tional and must connect to a positive An I2C expander and analog switches provide gang programming and serial read access for multiple
supply voltage through pullup resistors. EEPROMs.
In I2C-bus addressing, the first byte af-
ter a Start condition determines the slave fixed part and a programmable part. The large capacitive loads required, a Philips
that the master selects. A slave address is eighth bit, or LSB, determines the direc- 82B715 I2C-bus extender serves as a
seven bits long and usually comprises a tion of the transfer, either read or write. buffer. The software sequence for paral-
The programmable part of the slave’s ad- lel writing to all memory devices is to set
dress allows you to connect the maxi- the port pins by writing to the PCF8575
Circuit gang-programs EEPROMs mum possible number of identical de- to command closing all switches and then
over I2C bus......................................................73 vices to the I2C bus. This number send an I2C-bus command to write to the
depends on the number of address-input CAT24WC16 EEPROMs.
LFSR provides encryption ............................74 pins the I2C device has. In Figure 1, the The software flow for reading the con-
Resistor network extends serial-data line, SDA, connects to each tents of one memory device is to set the
Schmitt trigger’s reach ..................................76 CAT24WC16 EEPROM via bidirection- port pins by writing to the PCF8575 to
Routine yields fast bit reversing
al Maxim (www.maxim-ic.com) MAX- close the switch associated with the mem-
for DSP algorithms ........................................78
352 quad SPST analog switches. The ory to read, set all the other switches to
switches derive their control from a 16- open, and then send an I2C command to
A 4- to 20-mA loop needs bit Philips (www.semiconductors. read the selected CAT24WC16 EEPROM.
no external power source ............................80 philips.com) PCF8575 I/O expander for
the I2C bus. The clock line, SCL, connects Is this the best Design Idea in this
to all memory devices. For driving the issue? Vote at www.ednmag.com.
www.ednmag.com September 13, 2001 | edn 73

design
ideas
LFSR provides encryption
Antonella Di Lillo and Giovanni Motta, Brandeis University, Waltham, MA
FSRs (linear-feedback shift registers) eration. The XOR result then connects to
L find extensive use in cryptography.

For example, the cryptographic al-
gorithms in the GSM (Global System for
B3 B2 B1 B0
the input of the LFSR. Repeating the
process at the decoder side returns the
original sequence of bits. Listing 1 pres-
Mobile communications) mo- OUTPUT ents the encryption and decryption
bile-phone system rely on the Figure 1 BIT process. To generate a pseudorandom
use of LFSRs. An LFSR comprises a reg- sequence, you load the register with a
ister containing a sequence of bits and a A linear-feedback shift register, combined with nonzero content, and the software then
feedback function. In general, this func- an XOR operation, is ideal for encryption. computes the XOR of the taps and shifts
tion is an XOR (exclusive-OR) operation all bits in the register one bit to the left.
on certain bits in the register. The list of LFSR to generate a pseudorandom se- Finally, the routine inserts the results of
these bits is a “tap sequence.” You use an quence of bits that undergo an XOR op- the XOR operation in the rightmost po-
sition (Figure 1). The program adds this
1-bit result to the sequence and repeats
LISTING 1—LFSR ENCRYPTION AND DECRYPTION the procedure to generate other bits.
LFSRs are well-suited to hardware
implementations, but their use in soft-
ware programs unfortunately often
suffers from inefficient implementa-
tions. LFSRs with few taps, or sparse
LFSRs, are easier to use because you
need calculate the XOR of only a few
bits. On the other hand, for crypto-
graphic purposes, you must avoid sparse
polynomials because the resulting algo-
rithms are easy to break. The C program
in Listing 1 has the advantage of imple-
menting the XOR of a 32-bit integer
with an efficient algorithm, thus making
an efficient way to implement the soft-
ware of an LFSR. The program encrypts
a standard input into a standard output
one character at a time. You use an LFSR
to generate eight random bits at a time,
and the routine XORs the random bits
to the current character. The encryption
key is a nonzero integer that you use as
the initial status of the register. The key
is the same for both encoding and de-
coding. The variable taps represent the
32 binary coefficients of a primitive
polynomial of degree 31. Several other
choices are possible; Listing 1 suggests
five of them in the comments. You can
safely remove the code that describes the
number of characters encrypted and the
running time to make the program even
smaller. You can download the software
from the Web version of this article at
www.ednmag.com.
Is this the best Design Idea in this issue?

Vote at www.ednmag.com.
74 edn | September 13, 2001 www.ednmag.com
design
ideas
Resistor network extends Schmitt trigger’s reach
Anthony Smith, Scitech, Biddenham, UK
he circuit in Figure 1 shows are the required upper and low-
T a familiar technique
for converting a low-
level analog signal to digital form.
Figure 1
C1
R1 IC1
74HC14
VS
er VIN thresholds, respectively;
and VTU and VTL are the Schmitt
trigger’s upper and lower
Resistors R1 and R2 set the quies- VI DIGITAL-OUTPUT switching thresholds. By meas-
VOLTAGE, VOUT
cent dc level at the Schmitt in- uring VTU and VTL for a given
verter’s input to a value roughly ANALOG-INPUT Schmitt inverter and selecting a
VOLTAGE, VIN R2
equal to the midpoint of the hys- suitable value for R3, you can
teresis band. Capacitor C1 recalculate the corresponding
0V
moves dc content from VIN, such values of R1 and R2. The circuit
that the Schmitt trigger’s input accommodates almost any val-
signal, VI, centers itself on the ues of VP and VN. The only re-
midhysteresis level. Provided that This Schmitt-trigger circuit is useful for converting an ac signal to striction is that the hysteresis
VIN is large enough to cross IC1’s digital form. (VP2VN) is sufficiently larger
threshold level, the output signal, than IC1’s hysteresis (VTU2
VOUT, provides a faithful VS VTL); otherwise, the equations
digital representation of Figure 2
can yield negative resistor
VIN. Unfortunately, the R3 values. If IC1 is a CMOS device
IC1
circuit suffers from several draw- VIN R1 74HC14 (for example, 74HC14,
VI
backs. The presence of C1 makes VOUT 74AC14, 4093B, or 40106B),
it impossible for IC1 to switch at you can use large resistances,
R2
specifically defined dc levels on thus ensuring high input im-
VIN. Furthermore, for low-fre- pedance.
0V
quency waveforms, C1 must be For cases in which it is in-
extremely large to prevent un- convenient to measure the ex-
wanted signal attenuation. Also, if act values of VTU and VTL, you
VIN is of random period or is can replace R1 and R2 with vari-
asymmetrical with time (for ex- Eliminating the input capacitor avoids problems with asymmetrical able resistors to accommodate
ample, a pulse train with low duty input waveforms. the worst-case spread in VTU
cycle), the signal at VI will not and VTL. However, because R2
swing symmetrically about the VS and R3 have a large influence on
quiescent dc level and R1, the spread of values you
Figure 3
may fail to cross one of RA need for R2 results in a broad
R3 IC1
IC1’s thresholds. You can solve all R1 74HC14 variation in the R2-R3 parallel
VIN VI
these problems by replacing C1 VOUT combination and results in an
with a resistor, as in Figure 2. RP
even broader spread of values
In Figure 2, R1 and the parallel for R1. Replacing R2 and R3 with
combination of R2 and R3 act as RB R2 a potentiometer network, as in
an attenuator that allows IC1 to 0V
Figure 3, provides a solution to
switch at specific, user-defined dc the “spread” problem. Because
levels that may be much greater R2 varies with R3, the spread in
than IC1’s switching thresholds. the R2-R3 parallel combination,
Furthermore, R2 and R3 introduce The potentiometer networks solve the problem of large spreads in and hence in R1, is narrower.
an offset that allows VIN’s lower component values. This arrangement results in
threshold to be negative if re- some fairly onerous equations
quired. R1 and R2 relate to R3 as R2 = relating the variables. However, you can
follows: R 3 (VTL VP1VTU VN ) simplify matters by observing that for a
, particular CMOS Schmitt inverter, each
VS (VP1VN + VTL1VTU ) + VTU VN1VTL VP
R 3 (VTL VP1VTU VN ) of its thresholds is a constant fraction of
R1 = ,
VS (VTU1VTL ) where VS is the supply voltage; VP and VN the supply voltage, VS. Therefore, you can

design
ideas
define VTU5UVS and VTL5LVS, is 3.495 to 25.549 kV. You can ob-
where U and L are the respective tain this range by using a parallel
fractions. This simplification re- connection of a 50-kV poten-
sults in the following equations: tiometer and a 51-kV resistor that
is in series with a 3.3-kV resistor.
R1 = The oscilloscope screen in Fig-
V (L1U) + VP (11L) + VN (U11) ure 4 illustrates the performance
R2 S ,
VS (U1L) of the example circuit, in which
VIN is a 610V triangle wave. By ad-
LVP1UVN justing the two potentiometers in
R2 = R X , and turn, we made the output wave-
VS (L1U) + VP1VN
form switch when VIN56V and
R 3 = R X1R 2 . 27.5V. Despite the interaction be-
tween the potentiometers, you can
The design procedure is to select fairly easily (with a little patience)
the desired values for VS, set the thresholds. Although the
These waveforms indicate clean hysteretic
VP, and VN and then to cal- Figure 4 circuit is not intended for preci-
switching with a triangle-wave input.
culate R1, R2, and R3 in sion applications, it does extend
terms of RX for the worst-case spread in when IC1’s hysteresis is large and the par- the range of the garden-variety Schmitt
U and L. You can then scale the values of allel combination of R2 and R3 is small. inverter and allows you to implement
R1, R2, and R3 accordingly. As an example, This scenario occurs when L50.2 and positive and negative thresholds of sev-
assume that you need to set VP at 6V and U50.7, resulting in R151.067RX.The eral tens or even hundreds of volts. More-
VN at 27.5V using a 74HC14 operating range of potentiometer RP must allow over, the circuit allows VN to be positive,
from a 5V supply. Although slight differ- you to set the quiescent value of VI any- provided that VP is sufficiently greater
ences exist between manufacturers, the where from the minimum midhysteresis than VN to avoid negative resistance val-
“typical” spread in thresholds for the band level (occurring when L and U are ues. You can obtain operation of greater
74HC14 on a 5V rail yields the following both minima), to the maximum midhys- than 10-MHz frequency if you use suit-
values: U50.5 (minimum) to 0.7 (max- teresis level (occurring when L and U are able devices for IC1. The 74AC14 or
imum), and L50.2 (minimum) to 0.44 both maxima). In this example, the val- 74HC14 yield response times of just a few
(maximum). These values are subject to ues are R250.4125RX and R350.5875RX nanoseconds with a rail-to-rail output.
the restrictions on hysteresis: (when L50.2 and U50.5) and For best high-frequency performance,
(U2L)50.09 (minimum) to 0.5 (maxi- R250.6467RX and R350.3533RX (when use low resistor values, a shunt trimmer
mum). You can intuitively see that R1 is L50.44 and U50.7). Assuming that you capacitor across R1 to provide compen-
at a maximum when IC1’s hysteresis is use resistors with 61% tolerance and po- sation, or both. Finally, use Schottky
small and the parallel combination of R2 tentiometers with 610% tolerance, you clamp diodes as in Figure 3 to protect the
and R3 is large. This scenario occurs when can accommodate the required spread in inputs of IC1 from overvoltage condi-
IC1 has a narrow hysteresis band centered R2 and R3 with an adequate margin by tions.
roughly on VS/2. In this example, R1 is a making RA51.1 kV, RP51 kV, and
maximum of 7.25RX when L50.435 and RB51.3 kV. The corresponding spread in Is this the best Design Idea in this
U50.525. Conversely, R1 is at a minimum R1 (including the tolerance in RX itself) issue? Vote at www.ednmag.com.
Routine yields fast bit reversing for DSP algorithms

Mohammed Aziz, University of Leeds, UK
f you need efficient real- 50% of the computation time,
I time performance in DSP

applications, you need an
efficient bit-reversing routine.
TABLE 1—BIT-REVERSING RUNTIME RESULTS
Length (N)
32
64
Listing 1 (msec)
10
18
Evans (msec)
159
294
Gold-Radar (msec)
200
418
depending on the input-data
dimensions and length. The
idea behind bit reversing is to
For several FFT programs, data shuffle the data by flipping the
permutation can take 10 to 128 34 549 847 address bits around the mid-

design
ideas
dle of the address length so that if ing from the input array “in-arry”
the data length is N516, 900 and writing to the bit-reversed
Figure 1 800 LISTING 1
four bits from 0000 to EVANS output array “out-arry” in paral-
700
1111 represent the address. You 600
GOLD-RADER lel to double the speed. It then
achieve data shuffling by swap- TIME 500 uses circular buffers and indirect
(mSEC) 400
ping the address bits around the addressing to go through the N el-
300
middle so that B3B2B1B0 becomes 200
ements, lending itself to simple
B0B1B2B3, which represents the 100 and straightforward data moving.
new data location. Note that this 0
32 64 128
Existing techniques, such as Evans
operation is not byte flipping un- LENGTH (N) and Gold-Rader algorithms, do
less the input-data length happens data checking and bit reversing
to be N5255 elements. Look-up- The routine in Listing 1 produces markedly faster results than before moving the data, thereby
table techniques are inefficient, other algorithms. incurring overhead. Table 1 and
because the input data may be Figure 1 give the runtime results
very long, and memory space is LISTING 1—BIT-REVERSE ALGORITHM for the different algorithms (List-
limited. For real-time DSP appli- ing 1, Evans, and Gold-Rader)
cations, you bit-reverse a data ar- simulated on a 40-MHz SHARC
ray by swapping each position in DSP (ADSP-21060) from Analog
the data array with the position of Devices (www.analog.com). The
its corresponding bit-reversed ad- runs represent three lengths of 32,
dress by using DSP architectural 64, and 128 elements and involve
features. You implement the 10,000 iterations each in simulat-
method shown in Listing 1 using ing the 2-D case.
the SHARC DSP chip.
The routine uses the data-
memory segment and program-
memory segments for input and Is this the best Design Idea in
output. This feature of the DSP- this issue? Vote at www.edn
memory architecture allows read- mag.com.
A 4- to 20-mA loop needs no external power source

Shyam Tiwari, Sensors Private Ltd, Gwalior, India
he simple circuit in Figure 1 ter at the output must not draw
T
3.5 TO 19.5 mA
4- TO 20-mA 2 4- TO 20-mA
uses a low-current-drain MAX- CURRENT
1
LOOP more than 5 mA from the output
SOURCE 1
4073H amplifier to sense the for 1% full-scale measurement ac-
3.3V LED
current flowing through a 4- to 20- curacy. The LED shows visual in-
4 5
mA loop. The circuit senses tensity variation for changing cur-
the current through a 1V re- Figure 1 3 MAX4073H 2
2OUTPUT
rent in the loop. Its main purpose is
0.5 mA
1
1OUTPUT
sistor with a fixed gain of 100 and to raise the voltage by approxi-
uses no battery or dc power supply. A current-sensing circuit derives its power from the 4- to mately 1V across the sense resistor
The low current drain of the ampli- 20-mA current loop. with respect to the power-supply re-
fier (0.5 mA) enables the circuit to turn Pin 2 of the amplifier. This in-
tap its power from the 4- to 20-mA loop series with the sensing resistor form a creased voltage gives better common-
to power the amplifier chip. Note that the voltage drop of 4 to 4.5V across pins 2 mode performance to the amplifier
current flowing in the amplifier’s pow- and 3 of the amplifier chip. The amplifi- against common-mode noise in the sens-
er-supply Pin 3 (nominally 0.5 mA but er works well over 3 to 28V, so this 4 to ing resistor and prevents the amplifier
may vary slightly) is not part of the sens- 4.5V power-supply range presents no from saturating near the power-supply
ing loop. It forms a negative offset in the problems. rails.
measurement and is not a serious prob- The output of the amplifier is linear
lem. To make this current nearly con- from 350 to 1950 mV for 4 to 20 mA Is this the best Design Idea in this
stant, a 3.3V zener diode and an LED in through the loop. The measurement me- issue? Vote at www.ednmag.com.

design
Edited by Bill Travis
ideas
Calibrate scope jitter
using a transmission-line loop
David Cuthbert, Micron Technology, Boise, ID
igital-clock-period jitter is the the same amplitude as the first pulse.
D variation in the period of a clock cy-

cle compared with a nominal (av-
erage of many cycles) clock period. To ac- PULSE
SCOPE
With the 50V pulse generator set for
1V into 50V, the generator sends a 1V
incident pulse toward the oscillo-
curately measure period jitter using an GENERATOR scope. As the incident pulse “sees,” the
oscilloscope, you must subtract the os- node at the oscilloscope consists of the
cilloscope jitter from the measured jitter. 50V scope in parallel with the two
However, oscilloscopes rarely have 50V ends of the delay loop. Therefore,
a jitter specification, so you must Figure 1 the impedance at this node is 16.7V,
determine the oscilloscope jitter. One and the reflection coefficient is 20.5.
method of measuring oscilloscope jitter You can use a transmission-line delay loop to accu- The impedance mismatch causes a
is to use the oscilloscope to measure the rately measure an oscilloscope’s jitter. pulse amplitude of 0.5V to appear at
jitter of a pulse generator with known jit- the oscilloscope and a reflected pulse
ter. The measured jitter, assuming the jit- ing on the first pulse and then configure of 20.5V to travel to the generator, where
ter has a Gaussian distribution, is the scope to measure the time between it dissipates. Two 0.5V pulses travel in op-
=(scope jitter)2R(generator jitter)2. Re- the first pulse and the delayed pulse. You posite directions through the delay loop
arranging the formula to solve for oscil- set the trigger hold-off such that the os- and meet 13 nsec later at the oscilloscope,
loscope jitter, the scope jitter is =(meas- cilloscope always triggers on the first forming a 0.5V pulse with a source im-
ured jitter)22(generator jitter)2. The pulse. The second pulse in each set of pedance of 25V.
ideal generator for measuring oscillo- pulses is the first pulse delayed through The 50V oscilloscope, in parallel with
scope jitter would have zero jitter. Figure the transmission-line delay loop. Two the 50V line to the generator, forms a
1 is a circuit for generating a calibration 50V coaxial transmission lines imple- 25V load that matches the 25V pulse
signal with near-zero timing jitter. ment the circuit and connect to the os- source impedance. The delayed-pulse
A transmission-line delay loop creates cilloscope using two BNC T adapters. amplitude at the oscilloscope is 0.5V, and
a delayed pulse at the oscilloscope. Fig- The line from the 50V generator to the a 0.5V pulse travels to the pulse genera-
ure 2 shows the circuit in operation. You 50V oscilloscope can be of any length. tor, where it dissipates. You can analyze
set the oscilloscope for internal trigger- The length of the delay-loop line deter- the circuit’s action by keeping track of
mines the delay between the first pulse where the energy goes. The 1V generator
and the delayed pulse. You set the gener- sends a 20-mW pulse down the 50V line.
Calibrate scope jitter using ator’s pulse period to approximately five When this pulse encounters the oscillo-
a transmission-line loop ..............................97 times the loop delay and the generator’s scope and delay loop, the energy splits
Excel offers painless pulse duration to approximately one-half four ways. In this split, 5 mW reflects
LCD initialization ............................................98 the loop delay. back to the generator where it dissipates,
The waveforms in Figure 2 represent 5 mW dissipates in the oscilloscope, and
Microcontroller selects a pulse period of 62 nsec and a pulse du- 5 mW enters each end of the delay loop.
minimum/maximum value ......................100 ration of 6 nsec. The delay loop consists When the two 5-mW pulses exit the de-
Circuit forms industrial-grade of 2.4m of RG-58 coax and creates a delay loop, 5 mW dissipates in the oscillo-
digital potentiometer ..................................104 layed pulse 13 nsec after the first pulse. scope and 5 mW travels to the generator,
Passive filter cleans up
The 13-nsec delay is equivalent to cali- where it dissipates. You can calibrate sev-
power-line communications......................106
brating the oscilloscope with a zero-jitter, eral oscilloscopes and one pulse genera-
77-MHz signal. The impedance relation- tor with the delay loop. Because the loop
ships are such that the delayed pulse has has near-zero jitter, the jitter that an os-
design
ideas
cilloscope measures is virtually all oscil-
loscope jitter. The loop allowed a gener-
ator with 19-psec rms jitter
to calibrate an oscilloscope Figure 2
having 3.8-psec jitter.
The delay loop has some jitter, creat-
ed by the conversion of amplitude noise
to jitter. Without the loop, generator-am-
plitude noise causes the leading edge of
each pulse to cross the oscilloscope’s trip
point either early or late. In this way, am-
plitude noise translates to jitter. The fol-
lowing formula gives jitter versus ampli-
tude noise:
AMPLITUDE NOISE
JITTER = .
dV/dt
An ideal loop would produce a delayed

pulse that is identical to the first pulse.
Amplitude noise on the delayed pulse
would be identical to that on the first
pulse; thus, jitter attributable to the noise The transmission-line delay loop creates a delayed signal with near-zero jitter for calibrating the
would cancel out. Because of signal loss oscilloscope.
in a real loop, the delayed pulse is not
identical to the first pulse. Therefore, the nal loss on the leading edge of the delayed the amount of ADC dynamic range you
amplitude noise of the delayed pulse will pulse is 0.2V. The amplitude-noise-to-jit- use, you should calibrate the scope with
be less that that on the first pulse, and a ter conversion is thus: a loop delay and amplitude that match
conversion of amplitude noise to jitter the signal to the actual system or device
250 µV
will occur. The following formula gives LOOP JITTER = × (0.20) = 143 fSEC. under test.
0.35V/nSEC
amplitude noise versus jitter in the loop:
The loop jitter of 145 fsec is so far be- Reference
AMPLITUDE NOISE
LOOP JITTER = × (SIGNAL LOSS). low the jitter noise floor of the oscillo- 1. Adler, Joe, “Jitter in clock sources,”
dV/dt
scopes under calibration that you can Application Note, Vectron International.
The pulse generator used to calibrate consider the delay loop as a zero-jitter
the oscilloscopes exhibits 250 mV of rms source. Because digital-oscilloscope jitter Is this the best Design Idea in this
noise and a dV/dt of 0.35V/nsec. The sig- is a function of the timebase setting and issue? Vote at www.ednmag.com.
Excel offers painless LCD initialization

Alberto Bitti, Eptar, Lugo, Italy
o display a font or a symbol on an eight pixels. You can easily adapt it to any
T LCD, you need to convert the desired

character into numerical data. Cre-
ating the data for an entire font set re-
other arrangement, such as the seven-by-
five-pixel format used in the eight cus-
tomizable characters found in most al-
quires specialized tools; even with these phanumeric displays. Cells inside the
tools, the task can be daunting. Alterna- yellow area represent the symbol “pixels.”
tively, you can build a font calculator us- You draw the desired font character or
ing an Excel spreadsheet. This technique symbol using a bold character such as
takes advantage of the tabular nature of “#.” The formula in Figure 2 is all that
a spreadsheet to automatically create the You edit the graphical
required initialization code. The example Figure 1
shape (yellow). A simple
in Figure 1 applies to displays arranged formula builds the initialization code (blue),
in blocks comprised of eight pixels by which is ready to paste in your application.
design
ideas
you need to obtain the initializa- of the columns K and L; then cut and
tion data. For each of the eight pix- Figure 2 paste the code into your application. Be-
els in a row, the formula tests whether the sides saving you money, this technique
pixel is blank (LEN is zero); otherwise, it is convenient and flexible. You can adapt
adds the pixel’s “weight” (1, 2, 4, 8, 16, 32, it in minutes to any language (useful
64, or 128) to the result. when you switch between assembly di-
You can prepare the spreadsheet in alects). Moreover, the method accom-
minutes. Type the formula in the first po- modates useful additions, such as insert-
sition (K2), then copy it to all eight rows ing #define KEY_ICON to name a
in a symbol (the blue area from K3 to particular data set, to suit your applica-
K9). Complete it with the separators for The formula (which, in this example, shows cell tion’s requirements.
your language of choice (commas and K2) adds pixel “weights” to obtain initialization
parentheses for C). To build an entire values.
character set, copy the whole block as
many times as necessary. To edit the type “#” (or any other character), and use Is this the best Design Idea in this
fonts, place the cursor over the cells and “Canc” to delete. After editing, select all issue? Vote at www.ednmag.com.
Microcontroller selects minimum/maximum value

icrocontroller-based systems automatic-tuning system in which the In most cases, this range produces satis-
M for measurement, sensor-data pro-

cessing, or control, sometimes re-
quire you to determine a maximum or
microcontroller acquires data and must
determine the maximum or minimum
values of the data. A simple way to deter-
factory results. The same limitation ap-
plies to the number of data sources. If you
need more data precision or more data
minimum data value. For example, in an mine maximum and minimum value in- sources, then you can use two or more
object-detection system, such as a radar volves a microcontroller, IC1, that receives bytes at the expense of added program
or sonar system, the microcontroller re- a set of data from N sources (Figure 1). complication.
ceives echo signals from multiple targets The data should be in 8-bit format. To Two approaches exist for the maxi-
and then must select the closest one; in simplify the process, consider that the mum/minimum values. In the first, the
other words, it must determine the min- data are 1-byte-long integers. In other microcontroller memory collects the re-
imum distance. Another example is an words, the data cover the range 0 to 255. ceived data and processes the data to de-
5V 5V
Figure 1
R2 R2
6 6
DATA 1 100k 100k
1 1
DATA 2 RESET RESET
C1 C1
2
DATA 3 OSC1 0.1 mF 2
0.1 mF
OSC1
3 3
DATA OSC2 ADC DATA
OSC2
INPUT INPUT
CERAMIC
CERAMIC
IC1 RESONATOR IC1
RESONATOR
MC68HC705KJ1 4 MHz MC68HC705KJ1
4 MHz
DATA N
7 7
(b)
(a)
In one approach to determining minimum and maximum values, the microcontroller stores data values in memory before processing them (a); in
another approach, it processes data on the fly (b).

design
ideas
termine maximum or minimum values
(Figure 1a). In the second approach, the LISTING 1—MEMORY-BASED MINIMUM/MAXIMUM DETERMINATION
microcontroller processes the data im-
mediately after receiving it (Figure 1b).
Listing 1 shows the program for the first
approach. Assume that a data array with
Nt8 exists in the microcontroller’s
memory. For demonstration purposes,
Listing 1 illustrates this part of the rou-
tine in lines six to eight and 17 to 21, in
which the controller loads the data reg-
isters from a predetermined table. In a
real situation, you would load the data
registers from data sources before calling
the program. The process of minimum-
value detection is based on a method
called “the bubble.” The search algorithm
starts testing the memory data array from
its end. It clears the index register (X) af-
ter completion of the program. If you
need to detect the maximum instead of
the minimum value, you need change
only one instruction in line 28.
In the second approach, the micro-
controller waits for a data value entering
the data register and, upon reception,
starts processing the value (Listing 2).
This approach needs no memory array.
This variant of the program adds two fea-
tures: First, it simultaneously selects min-
imum and maximum values of the in-
coming data and saves them in the
DATAmin and DATAmax registers. Sec-
LISTING 2—ON-THE-FLY MINIMUM/MAXIMUM DETERMINATION
ond, the routine considers a data value
equal to 0 as no data. Thus, the data range
is from 01h to ffh. For this project, you can
use the inexpensive, one-time-program-
mable MC68HC705KJ1 from Motorola
(www.motorola.com). Thus, the pro-
grams use Motorola’s assembly language.
However, the algorithms are so straight-
forward, they’re amenable to any lan-
guage and to practically any microcon-
troller. Go to the EDN Web site www.
ednmag.com for an electronic version of
the listings.

issue? Vote at www.ednmag.com.

design
ideas
Circuit forms industrial-grade
digital potentiometer
Phill Leyva, Maxim Integrated Products, Sunnyvale, CA
oth ac and dc motors in modern mechanical unit within an enclosure. It debouncing) a 40-msec fixed delay be-
B industrial systems often receive

their control from PLCs (program-
mable-logic controllers) in a control
takes power from the 10V that is former-
ly supplied to the mechanical poten-
tiometer from the motor controller. The
tween its outputs and the switch action.
To provide 0 to 10V outputs as required
by the motor controller, a single-supply,
room safely away from the process. If an solid-state unit provides a similar output rail-to-rail op amp, IC4, amplifies IC3’s
operator must manually set the motor of 0 to 10V and delivers as much as 15 output by a factor of two. The input com-
speed while observing the process, the mA to the controller. mon-mode range for this op amp—250
component of choice is usually an in- The key to the circuit is the low-pow- mV beyond either supply rail—allows it
dustrial-grade potentiometer. The wiper er, digital-potentiometer 100-kV IC3. to generate 0 to 10V outputs like a me-
of this potentiometer produces a signal Configured as a voltage divider, this IC chanical potentiometer. The circuit’s low
of 0 to 10V that feeds back to a motor provides an output of 32 discrete voltage quiescent current ranges from 86 mA for
controller in the control room. Such po- steps between its minimum and maxi- a 0V output to 186 mA for a 10V output.
tentiometers are expensive and prone to mum settings (0 and 5V). A low-power To even further lower this quiescent cur-
wear, however. Because of wear, they can linear regulator, IC1, provides a 5V sup- rent, you can choose the 200-kV version
open the control loop, allowing the mo- ply rail for IC2, IC3, and a resistor ladder of IC3. Because the op amp is stable with
tor to ramp up uncontrollably. With a few internal to IC3. PB1 and PB2 constitute a any capacitive load, it easily drives long,
components, you can implement a reli- double-pushbutton industrial switch. shielded, multiconductor cable lines back
able, low-cost, surface-mount digital po- Each high-to-low transition that PB1 pro- to the control room.
tentiometer for industrial applications duces increments the digital poten-
(Figure 1). The result is a direct drop-in tiometer’s “wiper” by one step. Depress-
replacement for the wear-prone me- ing PB2 while toggling PB1 decrements
chanical potentiometer. The digital po- the wiper by one step. IC2 is a switch de- Is this the best Design Idea in this
tentiometer occupies the same space as a bouncer that provides (in addition to the issue? Vote at www.ednmag.com.
1 IC1 3
IN OUT
MAX1615
C2 5 4
SHDN 3/5 8 3
0.1 mF + VDD H
GND 4.7 mF
2 1
C1 INC IC3
+ PB1 5 6 7
10 mF VCC 2 C5
OUT1 U/D MAX5160
35V 1 IC2 4
IN1 MAX6817 OUT2 5
W GND 4
L
3 IN2
PB2 6
GND
2
3 5 VDD
NOTES: IN+
ALL RESISTORS ARE 1%. IC4 1
C1 AND C2 ARE TANTALUM CAPACITORS. MAX4162
4 IN1 0 TO 10V
2 VSS (WIPEROUT)
Figure 1
49.9k
49.9k
This solid-state potentiometer simulates a mechanical potentiometer and fits in the same space.

design
ideas
Passive filter cleans up

power-line communications
Jose Sebastia and JJ Perez, Polytechnic University of Valencia, Spain
any applications
M require the design

of custom analog
filters (Refer-
Figure 2
ence 1). The ap-
plication for this design
required simple and low-
cost I/O filters for PLC
(power-line communica-
tions), where low power
consumption is a crucial
factor. Figure 1 shows the
filters, which use passive
components because of (a) (b)
the requirement for low
power consumption. The Without an input filter, a great deal of hash accompanies the input signal (a); the addition of the filter considerably
PLC system needs an in- cleans up the signal (b).
VCC PIC
10k TRANSIL2 1k 1 2
LINEA-A
1
RX 22 nF
10 nF
2N2287 2 10k 100 mH
2 1 2
LINEA-B
10 5.6k
1 22 nF
Figure 1 2W 1
INPUT FILTER
2N2907A
ACTIVE_TRANS
1k 2 MKT
PVT412L PVT412L
3 2 1 1 2
VCC PIC
2N2222 3
1 mF 100 mH 1 mF
1k TRANSIL1
2
TX 2 100 VCC PIC
1 mF 1mH
100
1 1
D1N4148
1 2 D1N4148
1 mF
2N2222
3
1k OUTPUT FILTER 2
RELAY 2N2222
2 3
1
A power-line-communications system needs input and output filters to eliminate interference.

design
ideas
put and an output filter.
They are 100-Hz to 20-
kHz passband filters; the
communication frequen-
cy is 5 kHz. The differ-
ence between the two fil-
ters lies in the input
impedance. The input fil-
ter must pres-
ent a 2.2-kV Figure 3
impedance, and the out-
put filter must have a
30V impedance. The cir- (a) (b)
cuit also needs a solid-
state relay, the PVT412
from International Recti- Interference and noise are evident in the output signal (a); the addition of the output filter (b) markedly reduces the
fier (www.irf.com) to iso- noise.
late the output filter.
When the circuit is active, the relay con- shows waveforms before (Figure 2a) and tion to filters: active, passive, and
nects the output filter to the line. A mi- after (Figure 2b) insertion of the input switched-capacitor,” Application Note
crocontroller controls the relay to imple- filter. Figure 3 shows waveforms before AN-779, National Semiconductor, 1991.
ment the signal-transmission and (Figure 3a) and after (Figure 3b) inser-
-reception protocols. ACTIVE_TRANS, tion of the output filter.
RELAY, and TX are the microcontroller
pins that control transmission, and RX is Reference Is this the best Design Idea in this
the pin that controls reception. Figure 2 1. Lacanette, Kerry, “A basic introduc- issue? Vote at www.ednmag.com.

design
ideas
Tricks increase utility of parallel port
Lorenzo Tazzari, Selex SNC, Alessandria, Italy
J1
n this simple application of the PLUG AC MALE
I
F1 T1 IC1
LM7805 25V
68HC68 microcontroller’s se- 2A/230V 5V
Figure 1 VI GND VO
rial-I/O utility, the goal is to 220V 10V
+ +1 mF
configure a simple circuit, driven by any 10 mF
50V
50V
LPT parallel-printer port, which you can
BRIDGE
use as a remote I/O for a PC. You can in-
100 P1
dependently program each I/O line as ei- STROBE
100
ther an input or an output. The protocol AUTOFEED
100
DB25
0O
in this application is an SPI (MISO/ 100
ERROR
MOSI/SCK) type, using synchronous se- 01
100
100
rial communications. Figure 1 shows a INITIALIZE
100
circuit that effects the connection with 02
100
SELECT IN
the PC and power supply for all I/O sig- 100
03
nals. A bus carries signals of the SPI pro- 04
100
tocol, and the LPT port can drive all the 05

100
CE (Chip Enable) signals. With this type 100

06
of bus, you drive as many as five CE sig- 100
nals, and each CE line can address four 07
100
ACKNOWLEDGE
68HC68 chips. Each microcontroller can 100
drive eight I/O lines, with each line in- BUSY
100
dependently programmable. Thus, the PAPER END
100
system can address as many as 160 I/O SELECT
ports.
Figure 2 shows a simple way to select You address as many as 160 I/O signals with this simple connection of the LPT port.
the MISO signal. You can choose which
pin of the LPT port to use in receiving 1
GND
the MISO signal. This circuit uses the P2 9
5V PONT ACKNOWLEDGE
2 E1
GND MISO 0
ULN2003 as an amplifier to drive the 10
5V
ACKNOWLEDGE
E2 PONT BUSY
critical CE signal. By joining the 3
11
CS0 BUSY
SIP and CE signals, you can con- F i g u r e 2 4 CS1 E 3
PONT PAPER END
PAPER END
12
figure a bus system in which all signals 5 CS2
E 4
PONT SELECT
SELECT
go to the bus connector. You need an ex- 13
SCK E5 PONT ERROR
6 CS3 ERROR
ternal power supply, because the LPT 14
MOSI
port cannot supply sufficient current. 7 CS4
You can connect as many as five I/O cir- 15 MISO
8 CS5
cuits. The circuit in Figure 3 contains the
DB15
68HC68 chip with its CE and address se- FEMALE IC2 5V
4.7k 4.7k 4.7k 4.7k
lection. With jumpers E12 and E13, you ULN2003A
MOSI 16 1 00
OUT0 IN0 00
SCK 15 2 01
OUT1 IN1 01
CSO 14 3 02
OUT2 IN2 02
Tricks increase utility CS1 13
OUT3 4 03
IN3 03
of parallel port ................................................77 CS2 12
OUT4 IN4
5 04
04
CS3 11 6 05
OUT5 IN5 05
Transistors tame perfidious CS4 10 7 06
OUT6 IN6 06
leakage inductance ......................................80 5V 8
9 GND 4.7k 4.7k 4.7k
PRO1
18-bit ADC uses +
1 mF
5V
PC’s serial port................................................84
This simple scheme facilitates selection of the MISO signal in the SPI protocol.

design
ideas
can select the chip’s address. It is impor- cause hardware damage. Theoretically, Is this the best Design Idea in this
tant to emphasize that the system has no using an LPT port at a baud rate of 1 issue? Vote at www.ednmag.com.
check for an address conflict arising Mbyte/sec, the technique can read or
from choosing the same address, with write 160 I/O signals in less than 16
the same CE, in more than one chip. If msec.
the conflict arises, however, it does not
V3 5V
5V
68HCG8P1
1 10k
16
VCC IDO
15 D7 2
ID1 5V
14 D6 3
MISO MISO
13 D5 4 10k
MOSI MOSI
JP1 12 D4 5 0.1 mF
SCK SCK
READER 10 11 D3 6
CE CE
10 D2 7
D0
9 D1 E13 E12
GND 8
5V
2 3 4 5 6 7 8 9
4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k
1 1 1 1 1 1 1 1
5V
P3
1
5V GND
9
R22 5V
2
47k. GND
10
CSO1D2 5V
CE E6 3
CS0 1D2
CS11D3 11
E7
CS21D4 4 CS1 1D3
E8 12
E9 CS31D5 DB15 5
CS41D6 FEMALE CS2 1D4
E10 13
SCK
E11 CS51D7 6
CS3 1D5
14
MOSI
7
CS4 1D6
15
Figure 3 8
MISO
CS5 1D7
P4
1
9
2
10
3
11
4
DB15 12
MALE 5
13
6
14
7
15
8
A 68HC68 microcontroller handles CE and address selection.

design
ideas
Transistors tame perfidious leakage inductance

n flyback converters that use pri-
I mary regulation, the loose coupling

between the power secondary and the
primary auxiliary windings often results
25 LEAKAGE EFFECT:
VPEAK=24.2V
in poor cross-regulation. This situation “CLEAN” PLATEAU:
arises mainly from the leakage induc- V=13.4V
15
tance but also comes from the level of the
primary clamp voltage. Figure 1 shows a
typical application schematic using On
5
Semiconductor’s (www.onsemi.com)
NCP1200 in an auxiliary-winding con-
figuration. This IC uses a DSS (dynamic
self-supply), but in some low-standby- 25
power applications, it is desirable to per-
manently disconnect this feature through
an auxiliary level. The DSS simply acts 215
as a standard start-up current
source until the auxiliary level Figure 2
236U 240U 244U 248U 252U
takes over. In this application, the regu-
lation takes place on the secondary side
by means of the TL431, but the primary The leakage inductance on the auxiliary-winding side causes high rectified voltages.
VINT
Figure 1 MBR20100 10 mH VOUT
16.8V AT 4.5A
100 nF
CBULK 22k
220 mF/400V COUTA COUTB COUTC
2.2 mF 2.2 mF 2.2 mF 100 mF
NCP1200P60 MUR160
8 10
1 7
VAUX 1N4148
KBU4J 2
UNIVERSAL 6 1N4148
3 VINT VOUT
MAINS
4 MTP3N60E
RG
5
10 1k
SFH6115
RUPPER
18k 1N4148
1 nF 39k
1k
100 nF
18k
RSENSE
0.33 TL431
CVCC RLOWER
1 nF
100 mF 6.8k
In this circuit, leakage inductance in the auxiliary winding can invalidate the controller’s short-circuit-protection circuitry.

design
ideas
level assumes importance in short-circuit application in which you need a precise
conditions. Each time the NCP1200’s VCC level without either heavily filter-
crosses 10V while dropping, the internal ing the secondary winding (and Figure 3 Q1
1N4148 2N3906
logic senses the eventual presence of a thus lowering the available auxiliary en- VCC
3
short circuit through the feedback pin. ergy in standby mode) or reducing the 1 2
100k
Should the circuit confirm a short circuit, primary clamp voltage to a higher dissi- R2 R1
10k 10k 4
the NCP1200 emits a safe-autorecovery, pative value. In the NCP1200 application, 6 5
low-frequency burst. However, if poor when a short circuit appears at the out- LAUX 10k
D1
coupling prevents the auxiliary winding put, the auxiliary winding properly trig- 1N4148 Q2
7 2N3904
from collapsing, in the presence of a sec- gers the short-circuit protection.
ondary short circuit, VCC never crosses
the 10V threshold, and damage to the cir- D2
C1
2.2 nF
cuit may ensue. 1N4148
Figure 2 details the effects of the leak-

age inductance when a short circuit oc-
curs at the output. As you can see, the Is this the best Design Idea in this This component arrangement creates a discrete
leakage spike pushes the auxiliary level issue? Vote at www.ednmag.com. sample-and-hold system.
well above its regular plateau voltage,
which is the value you’d like to obtain.
With the rectifying diode playing the role
of an envelope detector, the result is a fi-
nal level close to 24V, far from the 13.4V
you would expect. As a result, a
Figure 4
possibly destructive condition ex-
ists if the levels exceed the maximum rat-
ings in the controller’s data sheet. You
need to clamp the auxiliary voltage us-
ing a dissipative element, such as a zener
diode. Figure 3 shows the circuitry you
adopt to avoid the leakage-inductance
problems. The component arrangement
actually implements a self-contained
sample-and-hold system. When the main
power switch is on, capacitor C1 dis-
charges through R2 and D1, and D2 avoids
a large reverse bias of Q2’s base-emitter
junction. When the main switch opens,
the secondary voltage sharply rises, and
Node 1 becomes positive. However, be-
cause C1 discharges, Q1 remains open, By delaying the sampling time, you obtain a clean auxiliary level that is devoid of any leakage-
and VCC does not increase. inductance effects.
After a short period (adjustable via R1
or C1), Q2 closes and brings Q1’s base 17
closer to ground. VCC now increas- POWER OUTPUT
es and catches up to the level at Figure 5 16
Node 2, minus Q1’s VCE(SAT). If you cor- 15

rectly select the time delay, VCC is devoid
LEVELS 14
of any voltage spike, because you have (V) AUXILIARY OUTPUT
sampled the plateau. Figure 4 shows the 13
final result. Performing some measure-
12
ments on a 70W application board fea-
turing low standby power yields the final 11
tracking results in Figure 5. You can see 0 1 2 3 4 5
that a 4.3A change in IOUT results in a OUTPUT CURRENT (A)
change of only 420 mV in VOUT. You can

use the circuit in a primary-regulation Thanks to the circuit in Figure 3, the auxiliary winding better tracks the primary winding.
design
ideas
18-bit ADC uses PC’s serial port
Yongping Xia, Teldata, Los Angeles, CA
PC usually requires a plug-in (DTR), and Pin 7 (RTS). TX generates the input-voltage range of the MAX132 is
A ADC card to process analog signals.

However, with the circuitry in Fig-
ure 1, a PC can communicate with an 18-
clock signal for the MAX132 and pro-
vides the negative power supply. DTR
transmits serial data. RTS provides the CS
2512 to 1512 mV. Listing 1 is a C pro-
gram that displays the analog-to-digital-
conversion result on-screen. You can
bit ADC through its serial port. The port signal and the positive power supply. download Listing 1 from the Web version
provides both positive and negative pow- Both the positive and the negative sup- of this Design Idea at www.ednmag.com.
er supplies as well as control signals. IC1 plies use large capacitors for energy stor-
is an 18-bit MAX132 ADC with a serial age. When TX generates a clock signal
interface. It requires three input control or DTR sends a CS logic-low signal, the
signals, CS, DIN, and SCLK, and emits se- capacitors provide power to the MAX-
rial data, DOUT, and EOC (end-of-con- 132. The MAX132 integrates everything
version) signals. An RS-232 port has except a reference that comes from a 1.2V Is this the best Design Idea in this
three output lines: Pin 3 (TX), Pin 4 LM385 voltage-reference diode, D1. The issue? Vote at www.ednmag.com.
2k
+ + 1000 mF + 5.1k
220 mF 1N5231 10V 0.1 mF
Figure 1 1N4148 16V
V+ 602k
CS BUF OUT
DIN +
INT OUT
DOUT
4700 pF
SCLK INT IN 20k
100k 1N4148 + 32,768 Hz IC1 +
OSC2 CREF1
MAX132
XT 0.1 mF
15 pF OSC1 CREF` D1
22k 1N4148
REF` LM385
P0 1.2V
10k 20k
1N4148 15 pF P1 REF1
1N5231
P2 AGND 2
1 CD
100k P3 IN LO INPUT
2 RX 22k
IN HI +
3 TX 1N5231 ECO
V1 20k
4 DTR 1N5231 DGND
5 GND
6 DSR + 220 mF +
10 mF
7 RTS 1N4148 16V 1N5231
10k 10V
8 CTS
9 RI
You can use a PC’s serial port to communicate with an 18-bit A/D converter.
LISTING 1—SCREEN-DISPLAY ROUTINE FOR ANALOG-TO-DIGITAL-CONVERSION RESULTS
Continued on pg 86

design
ideas
LISTING 1—SCREEN-DISPLAY ROUTINE FOR ANALOG-TO-DIGITAL-CONVERSION (CONTINUED)

design
ideas
Circuit forms low-frequency circulator
he electronic circula-
T
100
15V
tor made its debut ten PORT 1
100 0.1 mF
years ago (Reference 1). 324
It functioned at VHF as a
324 OP AMP
three-port unit using a Com- 1 (FOUR PLACES)
100
linear (now part of National IC1
PORT 2 0.1 mF
Semiconductor, www.nsc. + 100
com) CLC 406 operational
amplifier. The circuit in Fig- 324 324 115V
100 1 100
ure 1 extends the circulator’s IC2
performance to four-port +
PORT 3
100
operation at low frequencies, 100
using the readily available
941 (equivalent to the 324 324
Figure 1 1
ubiquitous 741) and 100
IC3
LM318 op amps. Table 1
+ PORT 4
shows the measured data for 100
324
the 741-equivalent op amp. 100
324
Table 2 shows the measured COMPONENT QUANTITY 1
data for the LM318 op amp. IC FOUR IC4
100
The four-port circulators in R4100V 12 +
R4324V EIGHT
Figure 1 use 50V impedance
levels. The circuit can readily
accommodate other imped-
ance levels, such as 75 and An electronic circulator is useful for isolation and equalization.
600V. You can see that for
typical circulator operation at frequen-
cies below 50 kHz, you can use the 741- TABLE 1—MEASURED DATA FOR TABLE 2—MEASURED DATA
741-EQUIVALENT OP AMP FOR LM318 OP AMP
Frequency Forward Reverse Forward Reverse
(kHz) loss (dB) isolation (dB) Frequency loss (dB) isolation (dB)
Circuit forms 2 0.5 50.2 10 Hz to 100 kHz 0 Greater than 56
low-frequency circulator ............................107 20 0.5 44.1 100 kHz 0.1 Greater than 56
50 1 38 500 kHz 0.5 45
Use printer port as programmable
100 4.1 33 1 MHz 0.9 34
frequency generator ..................................108
1.6 MHz 0 29.5
Trace voltage-current curves 3.3 MHz 3 25.5
on your PC ....................................................112 equivalent op amp. For typical operation
at speeds as high as 1 MHz, you would
Circuit makes simple use the LM318 op amp. The resistors in and the components are soldered to the
FSK modulator..............................................116 Figure 1 are metal-film units with 61% vector board. The ICs use commercially
tolerances. The circulator breadboards available sockets soldered to the vector
use open (not shielded) construction, board.
www.ednmag.com October 11, 2001 | edn 107
design
ideas
You can use the electronic four-port cost version of the circulator using sur- Equalizers Applicable to High-Speed
circulators in various applications with face-mount pc-board techniques. Data Links,” Applied Microwave & Wire-
the fourth port terminated. You can con- less, June 2001, pg 86.
figure baseband-amplitude and group- References
delay equalizers using the electronic cir- 1. Wenzel, C,“Low Frequency Circula-
culator (references 2 and 3). You can also tor/Isolator Uses No Ferrite or Magnet,”
use the circuit as a low-frequency return- RF Design, July 1991.
loss bridge or as an electronic isolator. 2. Kurzrok, R, “Amplitude Equalizer is
Low-frequency op amps are available as Circulator Coupled,” Microwaves, Vol-
quads with four independent op amps. ume 10, September 1971, pg 50. Is this the best Design Idea in this
You can configure a miniaturized, low- 3. Kurzrok, R, “Circulator-Coupled issue? Vote at www.ednmag.com.
Use printer port as

programmable frequency generator
K Kanniappan, IGCAR, Tamil Nadu, India
simple and inexpensive circuit astable multivibrator in that it eliminates frequency converter). The PC controls the
A (Figure 1) and a simple C program

(Listing 1) are all you need to turn
your PC’s printer port into a program-
the tedious task of adjusting a poten-
tiometer while you watch a frequency
counter or oscilloscope. With the circuit
DAC using a three-wire serial interface.
It also uses the data lines D0 to D2 of the
data port (03378h) of the printer inter-
mable frequency generator. Using a few in Figure 1, you need only enter the de- face to send the CS (chip-select), data, and
low-cost and readily available compo- sired frequency, and the PC does the rest. CLK (clock) signals to the DAC. Depend-
nents, the circuit occupies little space and The circuit uses a MAX5130 low-power, ing on the data it receives from the PC, the
is easily attachable to the printer port. The programmable, 13-bit DAC, IC1; an OP07 DAC produces a voltage output of 0 to
circuit has advantages over a 555-based buffer; and an AD537 VFC (voltage-to- 4.0955V in 8192 steps with a step resolu-
Figure 1 20k
5V
9 10
10k VDD 5 (CLR) 13 5V

2 6 (CS) _
IC2 10k
10k OP07 5 IC3 330
3 IC1 (OUT) +
7 (DIN) 2 + AD537
MAX5130 VOUT 10 mF 14 FOUT
10k 3
PRINTER 4 8 (SCLK) 15
PORT 4 1
12 (PD) 4 (PDL) 9 (DGND) 3 (RSTVAL) 1 (OS) 13 (AGND)
R1 * 8
18 + (REF ADJ) 3.3k

0.33 mF 11 12
19
20 R2
21 1k **
22 C1
23 0.001 mF
24
25
* 0.1% MFR
D25 ** POLYSTYRENE
CONNECTOR
Turn your PC’s printer port into a programmable frequency generator with this simple circuit.
108 edn | October 11, 2001 www.ednmag.com

design
ideas
tion of 0.5 mV. Thus, a data word of These values ensure good linearity (typ- desired value. You can download Listing
03000h produces a DAC output of 0V, ically 0.01%) between VOUT and fOUT. Po- 1 from the Web version of this article at
and a data word of 031fffh produces a tentiometers P1 and P2 adjust fOUT at the EDN’s Web site, www.ednmag.com. You
DAC output of 4.0955V. Using the 2.5V lower and higher ends of the frequency can easily change the frequency range by
internal reference, the DAC output and range, respectively. The C program in changing the value of C. For example,
the data input follow the equation Listing 1 obtains the desired frequency with R1 and R2 unchanged, you can ex-
VOUT52.5(DATA/8192)3GAIN. from the user and calculates the required tend the frequency to 100 kHz by chang-
After IC2 buffers it, the DAC output output from the DAC to apply to the ing C to 0.001 mF instead of 0.01 mF. You
drives the VFC and sets its frequency out- VFC. It then works out the ACTUALDA- can also increase the frequency range by
put according to the following equation: TA to send to the DAC for mode control. using a VFC with a higher frequency ca-
fOUT 5VOUT/(10(R11R2)C1) Hz. For the The d2b routine converts the ACTUAL- pability.
values of R1, R2, and C in Figure 1 and the DATA into 16-bit binary data. The pro-
cited DAC-output range, the output of gram enables the DAC (CS) low and then
the VFC and hence the frequency of serially clocks the binary equivalent of
the programmable-frequency generator ACTUALDATA, starting one bit at a time
varies from 0 to 10 kHz in 8192 steps from the MSB to the LSB, to the data pin
with a frequency resolution of 1.22 Hz. of the DAC. With the LSB set at the data
You choose and trim the values of R1 and pin, the low-to-high transition of the
R2 to produce a current range of 0 to 1 clock latches the ACTUALDATA com- Is this the best Design Idea in this
mA for a DAC output of 0 to 4.0955V. pletely into the DAC and sets fOUT to the issue? Vote at www.ednmag.com.
LISTING 1—PROGRAMMABLE FREQUENCY GENERATOR

design
ideas
Trace voltage-current curves on your PC
Clayton Grantham, National Semiconductor, Tucson, AZ
ome years ago, one of the funda- software, such as Spice, that’s removed arithmic-scaled currents from 1 mA to 1
S mental electronic instruments was

the laboratory curve tracer. A CRT
display would sweep out terminal behav-
from hands-on, empirical analysis. Spice
models now exist for almost all electron-
ic components. Characterization analyz-
mA while measuring the voltage, 0 to 5V
(3.3V on some PCs), at each step. The cir-
cuit uses a programmable current source
ior (current versus voltage) from which ers still make the voltage-current meas- to force increasing discrete current values
you could derive mathematical models. urements but not at the design-engineer and samples the voltage at the IOUT ter-
Classic presentations of diodes, transis- level. Rather, departments are dedicated minal at each step. A classic curve tracer
tors, and other devices enlightened de- to characterizing processes and compo- continuously sweeps a voltage while
signers about linear and nonlinear oper- nents and incorporating these character- measuring the sourced current. The pro-
ation. From the displays, you could istics into the simulated models. The low- gram control resides in Excel (running in
determine the bias points for optimum cost circuit in Figure 1 allows you to Office 2000) macros that perform I/O
design performance. Today, however, you return to the hands-on approach by us- operations through the LPT1 port of the
rarely find the classic curve tracers in the ing your PC as a limited curve tracer. PC. You can download the Excel program
lab. Instead, you find design-simulation The curve tracer sweeps out seven log- from EDN’s Web site, www.ednmag.com.
Figure 1
LPT1 POWER
1
C0
14
2 RN1 10
15 D0
3 + R1 R2
16 D1 47 mF 0.1 mF
C2 4 100 100
17 D2 DAC Q2A
5 Q2B
18 D3
GND XN2401
19 6
GND D4 IC2 1000 pF
20 7 LM4130
GND D5 2.048V
21 8 4 IC3
D6 VIN 5 1
GND 9 VREF + LPV321
22 D7 4 Q1
GND GND
3 2SD601
23 10 2 2 2 IOUT=1 mA TO 1 mA
GND S6
24 11 5V COMPLIANCE
5
GND 12
25 S5
GND 13
5 R3 R4 R5 R6 R7 R9
R8
VCC IC4 2.16M 1M 316k 100k 31.6k 3.16k
10k
IC1 74HC164
LM3724 3
4.63V Q0
S1 4 3 9
RESET MR 4
MR Q1
GND 5
1 AND 2 Q2
6
Q3
8
CLK 10
Q4
10k 12 pF 1 11
A Q5
2
10k B 12 IC5
Q6
13 74HC05
Q7
100
IC6 R10
ADCV0831 3 100 1k
4 1 +
CLK 3 IC7
VIN C5
100 5 DO LMC7111 4 1000 pF
1 2 2
10k V+ 5
6
CS 2
GND
0.1 mF
ADC
Remember the classic Tek curve tracers? You can easily configure something similar on your PC.

design
ideas
The program uses the free file “In-
put32.dll” to bit-wise control
Figure 2
the parallel port’s digital I/O.
The author of the .dll file is Jonathan Ti-
tus, editorial director of Test and Mea-
surement World.You load CurveTracer.xls
with its macros, connect the circuit of
Figure 1 to the parallel port, and then run
a macro called ControlPanel.
A user form pops up in the spreadsheet
and connects the curve-tracer force and
measurement actions with the electron-
ics (Figure 2). The possible operations
are a single voltage measurement, a sin-
gle forced-current output, or a sweep of
current steps lasting 2.8 msec each and a
voltage measurement at each step. The
voltage measurements go into cells B4 to
B10 in the spreadsheet. The resulting
graph shows an x-y scatter plot of the
data in cells A4 to B10. With this use of
macros within Excel, all the graphing, This curve-tracer user form, which floats in front of an Excel spreadsheet, controls the curve trac-
analysis, and data storage common to Ex- er’s electronics.
cel are still available to use. You can test
the terminal behavior of many electron- ed by the parallel combination of R3 to ing contain the basic interface features for
ic components with this simple curve R9. For the lowest current, 1 mA, only R3 changing the current-output values and
tracer. Resistors yield a linear plot whose connects (2.048V/2.16 MV). For the measuring the voltage input. Within
slope is the resistor value (R5V/I). highest current (1 mA), all the resistors module 1, the declaration of Input32.dll
Diodes exhibit a nonlinear plot (ID5 connect in parallel (2.048V/2.16 kV). must include its directory path. To min-
ISeqVD/kT). You can also plot a diode’s ter- You select resistor values for a cumula- imize the effects of differing PC-clock
minal behavior on a logarithmic current tive half-decade change in IOUT. IOUT steps and LPT1-bus speeds in different PCs, the
scale with a simple click within Excel’s by the square root of 10 in value. With user form performs a 10-sec timing cali-
charting capabilities. Some other appli- only these seven resistors, the circuit cov- bration at initialization. This calibration
cation examples are forward-biased tran- ers three decades of current range. The attempts to set the IOUT steps during a
sistor junctions, LEDs, and relay coils. pnp pair, Q2A and Q2B, mirrors Q1’s col- sweep to 2.8 msec. The software uses this
The components in Figure 1 provide lector current to the terminal IOUT. Emit- time-delay coefficient throughout the
operation as low as 3V and low power ter-degeneration resistors R1 and R2 im- program. Also, software-calibration co-
consumption (low quiescent current). In prove the mirror’s output resistance. Shift efficients within the code minimize volt-
the PWR block, resistor network RN1 iso- register IC4 and open-drain inverter IC5 age-measurement gain and offset errors.
lates and combines eight LPT1 outputs at select which of the resistors to connect via The spreadsheet maintains these coeffi-
D0 to D7 to power the circuit. The su- program control. IC4’s input and clock cients for ease of changing. Use a volt-
pervisory circuit, IC1, monitors the volt- connect the parallel port at C0 and C2 for meter and a resistor of known value to
age from the LPT1 port. Use the LM3724 serial shift-in operation. IC5’s on-resist- calibrate. The initial gain coefficient in
4.63V option for 5V PCs and the 3.08V ance is lower than 40V. IC6 and IC7 per- the spreadsheet for a 5V PC is 5V divid-
option for 3.3V PCs. The reset output of form voltage measurements (the ADC ed by 2821 (5/25550.0196). The initial
IC1 goes back to the parallel port at ter- block). IC7, a rail-to-rail op amp buffers offset coefficient is zero. You can also cal-
minal S5 for software-error checking and the lowpass filter comprising R10 and C5. ibrate the IOUT current values in the
clears IC4 at start-up. IC1 also has a man- The serial output of IC6, D0, connects to spreadsheet. The user-form references
ual reset that provides direct user control. the parallel port at S6. IC6’s clock input these spreadsheet values. With external
If you press momentary switch SW1, the provides timing control. When IC6’s chip- calibration, you can attain better than 1%
output current resets to 1 mA. IC2 select input goes low, a conversion starts. error.
through IC5, Q1, Q2, and associated resis- Pulling IOUT above the PC’s 5V level or be-
tors R1 through R9 form a current-output low ground could result in circuit and PC
D/A converter. Servoamplifier IC3 sets damage. To be safe, operate this curve
Q1’s collector current. This current is a tracer with unpowered components. Is this the best Design Idea in this
function of IC2’s reference voltage divid- The macros in the downloadable list- issue? Vote at www.ednmag.com.

design
ideas
Circuit makes simple FSK modulator

Shyam Tiwari, Sensors Technology Ltd, Gwalior, India
he need for a compact with R1). When the input
T IC1 5V
telemetry system NL27WZ14 DC assumes a high level, the
Figure 1
poses a challenge 5 oscillator’s frequency re-
1 6
for designing a small, light, FSK OUTPUT duces by one- half with the
low-component-count sys- C1 2 introduction of a capaci-
0.01 mF
tem. Interfacing serial data 470 tor in the timing circuit via
Q1 R1
from the microprocessor is 2N2222 10k
Q1. The inverter IC can ac-
5k
also difficult because most TTL commodate an operating
INPUT
low-cost RF transmitters do C2 frequency of approximate-
0.01 mF
not accept dc levels at the in- ly 80 kHz. You can easily
put. Commercial FSK (fre- operate the FSK modula-
quency-shift-keying) modula- INPUT tor at higher frequencies,
FSK OUTPUT
tors are bulky and need many such as 4800 and 9600 Hz,
passive components. The cir- by reducing the values of
cuit in Figure 1 uses a single An FSK modulator uses a single inverter with minimal added components. the timing capacitors C1
NOT gate (inverter), an On and C2.
Semiconductor NL27WZ14 in a surface- with available transmitters. When the
mount package, to generate continuous TTL input has a low level, the circuit is a
FSK data from TTL-level signals. The continuously running oscillator, produc- Is this the best Design Idea in this
outputs from this circuit are compatible ing approximately 2400 Hz (adjustable issue? Vote at www.ednmag.com.

design
ideas
Circuit forms efficient cosine calculator
Matt Kornblum, Bradenton, FL
he circuit in Figure 1 converts a
T 610V analog voltage repre-

senting an angle between uMIN
and uMAX and emits a voltage equal to 10
Figure 1
R2
210V
R1 10k
R3
cosu. This circuit can have an accuracy of 4.64k 10k
better than 1% over 61208 or better than
0.2% over 6908. These figures represent IC1
MPY634KP
IC2
MPY634KP
1 12 12 R4
an order-of-magnitude improvement 1 2
VIN X+ OUT X+ OUT VOUT=COS U
2 15.4k IC3
over a Taylor-series estimate for the same 2
X2 X2
VO=XY/10Z VO=XY/10Z +
range and for the same number of mul- Z+
11
Z+
11
tiplications. The Taylor-series definition 6 10 6

10
Z2
for a cosine (with u in radians) is: Y+
7 Y2
Z2
4
Y+
SF 7 Y2 SF 4
θ θ θ 2 4 n
COSθ = 11 + L+ .
2! 4! n!
The series works well for high values
of n or small angles. Generally, for n54, By manipulating Taylor-series coefficients, you can obtain better accuracy when generating cosines.
significant errors start to accumulate for
angles exceeding 6458. When you use a
12
Taylor-series expansion for better accu-
racies at larger angles, the number TAYLOR-SERIES ERROR
Figure 2 10 THEORETICAL FIT
n becomes larger and demands
ACTUAL-VALUE FIT
more resources from the design. The
8
Taylor series for n54 has the form of
f(u)5a2bu21cu4, where a51, b50.5,
6
and c50.041667 (for angles in radians).
By using a least-squares curve fit to op- ERROR (%)
timize this function at n54, you can find 4
coefficients that allow you to obtain sig-

nificantly better accuracies over the de- 2
0
Circuit forms efficient
cosine calculator ............................................87 22
2120 290 260 230 0 30 60 90 120
Reference stabilizes exponential
ANGLE (8)
current ..............................................................88
Microcontroller becomes For angles greater than 6908, the revised coefficients in Figure 1 yield significant accuracy improve-
multifunctional................................................90 ments in calculating cosines.
Circuit converts pulse width
to voltage ........................................................92 sired input range without raising the val- cuit is relatively simple. Set R1 and R2
Short dc power-line pulses ue of n to more than 4. The circuit in Fig- equal to each other (for 10V maximum
afford remote control....................................94 ure 1 embodies this least-squares ap- input and aP1), and determine values for
proach. R2 and R4 by applying the following equa-
Choosing the resistor values for the cir- tions:
www.ednmag.com October 25, 2001 | edn 87
design
ideas
R3 output of IC3 is the sum of the three nificantly smaller. The constant “a” be-
R2 = , terms. Because IC1 is an inverting ampli- comes 0.9996, b50.4962, and c50.0371.
bθ2MAX
fier, the circuit configures the multipliers Then, R15R3510 kV, R258.16 kV, and
and such that the output of IC1 is positive and R4544.2 kV.
R3 the output of IC2 is negative. Choosing You can use the same approach to ef-
R4 = . the proper 0.1% resistors can improve ficiently calculate cosine and sine values
cθ4MAX
circuit accuracy to better than 1% for in a DSP system more rapidly than us-
IC1 generates the square of VIN and 2120 to 11208. You should use a lowing a look-up table.
negates it. This output sums through R2 offset op amp for best results. Figure 2
into IC3. IC2 generates the fourth power shows the Taylor-series error, the theo-
of VIN and sums it into IC3 through R4. A retical fit, and the actual fit. For a fit in a
210V reference across R1 creates the “a”- 908 range, the values change slightly, and Is this the best Design Idea in this
coefficient constant current into IC3. The the errors across the range become sig- issue? Vote at www.ednmag.com.
Reference stabilizes exponential current

Tom Napier, North Wales, PA
n an antilog converter, the differ- EXPONENTIAL
I ence between the base voltages of two

transistors sets the ratio of their col-
lector currents:
2.5V
REFERENCE
IC3
CURRENT
+
I1 / I2 = e VBE q / kT . R4
3.92k
The use of matched transistors bal- 2
R3
24.9k
ances the first-order temperature coeffi- IC1 2.49k
cient but leaves a temperature-dependent 10k +
R1 0.01 mF
gain term, q/kT. Classic antilog circuits 909 Q1 Q2 Q3
use a thermistor in the drive circuitry to CURRENT
CONTROL
correct this temperature dependency.
However, if the control input is a fraction 2.49k
of some reference voltage, as when you R2

100 R5
use a manual potentiometer or a DAC, 470
100
you can achieve an exact temperature
0.01 mF
correction by adding a second reference
transistor. Figure 1 shows three of the five
transistors in a CA3046 array. Q1 2
is the exponential current source, Figure 1 IC2
+
and Q2 is the conventional reference tran-
sistor. IC2 forces Q2’s collector to ground
so its collector current, 1 mA in this ex- The use of a second reference eliminates temperature dependency in an antilog-ratio circuit.
ample, is simply the reference voltage di-
vided by R3. Typically, this current equals through Q3 is a fraction of the main ref- 4 to 1, the output current has a four-
the maximum output required from Q1; erence—one-tenth in this example. De- decade tuning range that’s independent
lower currents result from negatively spite the chip temperature, the base volt- of temperature. The circuit in Figure 1 is
driving the transistor’s base. age of Q3 is exactly the value you need to dynamically stable, using either low-
The attenuator on the base of Q1, R1, generate a 1-to-10 current ratio. Because power or fast op amps.
and R2 reduces the effects of IC1’s offset IC3’s output supplies the reference volt-
voltage. IC3 drives the base of Q3 via a sec- age for the potentiometer, the ratio of the
ond attenuator, R4 and R5, forcing its col- two attenuators defines the full-scale- Is this the best Design Idea in this
lector to ground. The reference current current-adjustment range. If the ratio is issue? Vote at www.ednmag.com.

design
ideas
Microcontroller becomes multifunctional
microcontroller, by default, can choice is to use the microcontroller’s interrupt and RTI (real-time interrupt).
A execute only one program at a time.

What do you do if, in a given proj-
ect, you need to perform more than one
ternal timer. This microcontroller has
two timing options: timer-overflow in-
For a 2-MHz operating frequency, the
timer overflow occurs every 0.51 msec.
operation at a time? Add more micro-

controllers to the design? In certain cas- LISTING 1—ROUTINE FOR MULTIFUNCTIONAL OPERATION
es it’s unnecessary. Consider a real-life sit-
uation (Figure 1). The microcontroller
constantly generates on its Pulse output
pin a sequence of pulses with 25-msec
duration and a repetition rate of 1 or 4
sec, depending on the state of the Rate in-
put pin. LED illumination accompanies
the pulse generation. Suppose that the
microcontroller must simultaneously
and independently perform some other
functions using the rest of its six I/O pins.
You can benefit from the fact that the
pulse duration is much smaller than the
repetition period. During this relatively
long period, the microcontroller may not
just wait for the generation of the next
pulse, but, instead, it may perform some
other operation. You organize the pulse-
generating program as an interrupt-serv-
ice routine and the rest of the program as
a main program. To avoid any interfer-
ence between these parts of the software,
the interrupt-service routine execution
time should be shorter than the smallest
period of pulse repetition.
Listing 1 is the assembly routine for
multifunctional operation. To make the
interrupt program repeatable after the
predetermined time interval, the best
5V
6 MC68HC705KJ1
100k 100k
16 1
IRQ RESET CERAMIC
ON RESONATOR 0.1
2
OFF START 15 OSC1 mF
PA0 4.0 MHz
N2 3
OSC2
N1 RATE 14
PA1 25 mSEC
11 PULSE
PA4
Nt
10 510
PA5 LED
7
Figure 1
Between pulses, the microcontroller can per-
form other tasks using the software in Listing 1.

design
ideas
You can program the RTI period to be as see in Listing 1 that the microcontroller erating and switches off the LED. You can
long as 65.5 msec (with RT1-to-RT051- waits for a high level on its Start pin to download the software for multifunc-
to-1). To simplify the counters, it is rea- begin pulse generation and LED lighting. tional operation from the Web version of
sonable to choose the largest value: 65.5 During the interval between pulses, it this article at www.ednmag.com.
msec. Then, to make the repetition peri- performs the other operations, continu-
ods equal to 1 and 4 sec, you create the ously checking the state of its Start pin.
counters modulo 16 and 62 accordingly After receiving a low level on the Start Is this the best Design Idea in this
in the RTI routine (Listing 1). You can pin, the microcontroller stops pulse gen- issue? Vote at www.ednmag.com.
Circuit converts pulse width to voltage

James Mahoney, Linear Technology Corp, Milpitas, CA
he circuit in Figure 1 converts
T pulse information to a clean dc volt-

age by the end of a single incoming
pulse. In another technique, an RC filter
SAMPLE
1 mSEC
~
HOLD
SAMPLE
can convert a PWM signal to an averaged 1.5 mSEC

2 mSEC
dc voltage, but this method is slow in re-
sponding. Converting low-duty-cycle PULSE IN R2 8
10k 6
pulse information is slower yet. The cir- VCC 7
cuit in Figure 1 uses two low-input-bias- IC1D

100k LTC202
current LT1880 op amps, IC2 and IC3, VCC 9
11 10
and an LTC202 quad analog
switch, IC1A, IC1B, IC1C, and IC1D, F i g u r e 1 IC1C
LTC202
to configure the integrator and sample- C1
R1 1
and-hold stages that convert a single 49.9k
3 2 4
0.01 mF
VCC 2 16
pulse to a dc voltage. The circuit’s output IC2 1 14 15 3
ICIA LT1880 +
is stable after a single pulse. This exam- LTC202
3
C2
IC3
LT1880
1
+ IC1B
ple shows the conversion of a low-duty- VCC R3 R4 LTC202 0.01 mF 4
2
cycle positive pulse, whose width varies 19.1k 78.7k VCC/2
from 1 to 2 msec with a period of 25 T1 T2 T3
msec, to a clean dc voltage. The input
pulse starts, stops, and resets the inte- NOTE:
grator and controls the input to the sam- SWITCHES SHOWN IN SAMPLE MODE.
ple-and-hold stage. After the reset oper- V1 AT T1: 1 mSEC

ation, the positive pulse level-triggers the V2 AT T2: 1.5 mSEC
integrator, comprising R1, C1, and IC2. V3 AT T3: 2 mSEC
The sample-and-hold stage, comprising
IC1B, C2, and IC3, is in the sample mode, This circuit yields a clean dc voltage that indicates the width of an incoming pulse.
sampling the output of the integrator,
while the incoming pulse is high. 3
When the incoming pulse goes low, the

circuit disconnects the input to the sam- 2.5
ple-and-hold stage, putting it into hold

mode. The integrator then stays in the re- 2
set state until the next positive pulse ar- VOUT (V)
rives. During reset, analog switch IC1A 1.5
opens to disconnect the integra-
tor’s input, switch IC1C closes to F i g u r e 2
1
reset integration capacitor C1, and switch
IC1B opens to disconnect the input to the
0.5
sample-and-hold stage, placing the stage 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
PULSE WIDTH (mSEC)
in hold mode. Analog switch IC1D inverts
the on/off states of switch IC1C. The The circuit in Figure 1 linearly converts a pulse width to a dc voltage.
design
ideas
LT1880 op amp is a good choice for the styrene, or Teflon capacitors for C1 and The circuit operates with pulse-width in-
integrator and sample-and-hold stages C2 to minimize integrator drift and sam- formation and not duty-cycle values. The
because of its maximum input-bias cur- ple-and-hold droop rate. The voltage ra- sample-and-hold stage is an analog-
rent of 900 pA at 258C and maximum of tio that resistors R3 and R4 set establish- memory element that reveals the dc-volt-
1500 pA maximum over the full 240 to es the dc level at the positive pulse’s age equivalent for this pulse width.
+858C ambient-temperature range. An- midrange value: 1.5 msec in this exam-
other benefit of the LT1880 is its maxi- ple. Figure 2 shows input pulse width
mum input-offset-voltage drift of 1.2 versus output voltage. You can easily
mV/8C. Integrator capacitor C1 and re- modify the circuit in Figure 1 to yield dif-
sistor R1 set the conversion gain. ferent conversion gains, output levels, Is this the best Design Idea in this
You should use polypropylene, poly- and swings for different pulse widths. issue? Vote at www.ednmag.com.
Short dc power-line pulses afford remote control

Tom Hornak, Portola Valley, CA
f you face the challenge of extra zener diode, D4, creates a
I adding a second, independent-

ly controlled light source to an
existing ceiling lamp con-
Figure 1
HOT
S1
D1 12V
S2
12V D2
HOT
positive 5V dc bias in V2. The fil-
ter outputs V1 and V2 drive in-
verting Schmitt triggers IC1 and
trolled by a wall switch, you IC2. Inserting zener diode D1 by
120V AC TO LAMPS
may find that stringing a second 1N2976B 1N2976B pushing S1 in Figure 1 changes V1
power line is impossible. First, you NEUTRAL
from 0V to 5V and V2 from 5V to
can replace the wall switch by the 10V. Inserting D2 in Figure 1 by
circuit in Figure 1. Pushing the on This circuit creates dc pulses for use with control circuitry locat- pushing S2 changes V1 from 0V to
switch S1 or S2 for approximately ed at the load. 25V and V2 from 5V to 0V. Note
1 sec inserts the 12V zener that the input-protection
W2
diodes D1 or D2 in series diodes of IC1 and IC2 limit
with the hot wire of the the voltage swings of V1 and
R1
power line. During the 50 V2. The output V3 of IC3 re-
100k 100k V1 V3
push, the polarity-depend- C1
IC1 IC3 sponds to pushing S1 by a
1 mF
ent conduction of the zen- 600V positive transition and has
3
er diodes creates a small VDD 1 mF
1 mF 6 OF 74HC14 no response to pushing S2.
D4
positive (negative for D2) D 1 12V 100k 100k V2 V4
The output V4 of IC2 re-
dc component across the C
IC2 sponds to pushing S2 by a
6V D3 2
line and only slightly re- 330 mF 1 mF 1 mF positive transition and has
duces the line’s 120V-ac no response to pushing S1.
component. A control cir- W1 Figure 3 shows the sec-
cuit at the lamps’ This control circuit uses dc pulses from the circuit in Figure 1 to ond part of the control cir-
site reacts selec- Figure 2 cuit located at the lamps’
drive triacs in the circuit in Figure 3.
tively to the polarity of this site. Signals V3 and V4 in
dc pulse and controls the power to the W1 and W2. Current through capacitor C1 Figure 2 drive the clock input of toggle
two lamps. The required power rating of and resistor R1 creates a 60-Hz square flip-flops IC1 and IC2, respectively. For
the two zener diodes depends on the load wave across the 6V zener diode, D3. Diode clarity, Figure 3 doesn’t show the con-
current. The short duration and low duty D1 and filter capacitor C2 generate a dc nections of the flip-flops of Q to D and
cycle of the activation are helpful. The supply voltage of VDD55V for the control the Set terminal to VDD. When you push
1N2976 diodes in Figure 1 are rated for circuit’s active elements. Two two-stage switch S1 in Figure 1, the positive transi-
continuous dissipation of 10W. RC filters connected to W2 create V1 and tion in V3 toggles flip-flop IC1. Similarly,
Figure 2 shows the first part of the V2, with reference to W1. The filters at- when you push S2, the positive transition
control circuit located at the lamps’ site, tenuate the 120V-ac voltage between W1 in V4 toggles flip-flop IC2. Thus, you can
including the two leads of the power line, and W2 to a subvolt level in V1 and V2. An independently control the states of flip-
design
ideas
flops IC1 and IC2 by pushing S1 and S2, re- must quickly pull down the flip-flops’ Reset does not release before VDD reach-
spectively. To drive the two lamps, the Q Reset terminal, which is independent of es its full value.
outputs of the flip-flops drive the gates of VDD’s slowly dropping level. Diode D2 Note that you can use this Design Idea
triacs TR1 and TR2 via coupling resistors (driven by the 60-Hz square wave across in other applications. For example, if you
R2 and R3. The MT2 termi- omit the circuit in
nal of each triac drives the W2 Figure 3, the transi-
lamps, L1 and L2, re- 2
6 OF 74HC14 tions in V3 and V4 can
spectively. Pushing S1 Figure 3 L1 L2 D2 V5 drive an up/down
FROM
IC4 IC5
changes the state of lamp L1; 74HC74 2N6072B MT2
D4 counter that can per-
TR2
pushing S2 changes the state V3 FLIP- MT1
form an auxiliary
TO THE
of lamp L2. Thus, you have FLOP R2
C3 R4 D3
R5 FLIP-FLOP control function for a
500 2N6072B MT2 100k RESETS
independent control of 1 mF 100k device that the ac line
TR1
both lamps on a single pow- V4 FLIP- MT1 powers. If you insert
C4
er line. In this application, FLOP R3
1 mF
an additional con-
500
you want to keep each ventional switch in
W1
lamp’s terminals safely con- series with the circuit
nected to the hot and neu- Triacs independently control two loads based on signals from a pair of wall switches. in Figure 1, it can
tral wires. Therefore, you turn on and off the
make W1 the hot wire and W2 the neutral zener diode D4), capacitor C3, and resis- power to the device. If the application re-
wire. tor R4 act as an auxiliary rectifier supply- quires control signals near ground level,
With the control circuit, the state of ing voltage V5. When power experiences wire W1 should be the neutral lead of the
the flip-flops becomes uncertain if, after an interruption, V5 drops to 0V much power line, and W2 should be the hot
an interruption, the ac power returns. faster than VDD. V5 drives the cascade of lead. However, make sure that the pow-
This situation is unacceptable because inverting Schmitt triggers IC4 and IC5, ered device is not an inductive load be-
the lamps could turn on and stay on for which then quickly pull down the flip- cause it can short out the controlling dc
an uncontrollable length of time. There- flops’ Reset terminals via diode D3. When pulses.
fore, you add a power-up reset circuit power returns, the Reset terminals pull
(Figure 3). To guarantee a safe reset also up slowly via resistor R5. The R5C4 time Is this the best Design Idea in this
for short interruptions, the reset circuit constant guarantees that the flip-flops’ issue? Vote at www.ednmag.com.

design
ideas
Trigger a TTL circuit from ECL levels
Lukasz Sliwczynski, University of Mining and Metallurgy, Krakow, Poland
CL circuits typically have can use the following equation:
E
OUTPUT TRANSISTOR VCC
relatively small logic OF ECL GATE 5V
Figure 1 ∆V1VDS
spans of approximate- Q1 t P = R1C1 ln ≈ 0.08 R1C1 ,
C1 R2 VBE
ly 800 mV. Because of the small 10 nF 8.2k
span, to drive TTL circuits from OUTPUT POLARIZING
OUTPUT where DVP0.8V is the ECL
ECL levels normally entails the use RESISTOR D1 R1 Q2 span, VDSP0.15V is the voltage
(300 TO 1000V) 1.8k 2N2369
of level converters, such as the drop of the Schottky diode, and
MC10125, or comparators. Such 2VEE OR
VBEP0.6V is the voltage drop of
circuits are relatively power-hun- GND SCHOTTKY DIODE the base-emitter junctions. In
(SUCH AS BAS70, BAT 18)
gry and expensive. However, they practice, the durations are
are sometimes simply unneces- shorter than predicted because
sary. The circuit in Figure 1 allows You don’t need an expensive level-converter IC to provide a TTL- the equation does not take ac-
you to trigger some TTL circuitry level trigger from an ECL-level signal. count of the base-emitter resist-
by generating a fairly short nega- ances of Q1 and Q2. For the
tive-going pulse from the trailing edge of pacitor C1 through the Schottky diode, components in Figure 1, the duration is
the ECL signal. The main requirement D1. In this part of the operating cycle, approximately 2 msec. The crucial com-
for the circuit to work is that the rate of transistor Q2 is off, and the output volt- ponent in the circuit is D1, which must be
ECL signal be in the tens of kilohertz. age is approximately 5V. On the negative- a Schottky type, because of the voltage
Such signals sometimes appear at the rear going edge of the driving pulse, the swing of the ECL signal, which is nearly
panels of some older types of measure- charge from coupling capacitor C1 caus- the same as the base-emitter voltage of
ment equipment. Such equipment can es the base-emitter junction of Q2 to con- the conducting silicon transistor. Proper
include sampling oscilloscopes or time- duct, driving the transistor into satura- operation of the circuit occurs because of
domain reflectometers, such as the 7S12 tion. The output voltage assumes a level the voltage difference between Schottky
or 7S14 from Tektronix. In a measure- slightly below 0V. The duration of the and silicon-junction levels, which is typ-
ment setup, the circuit in Figure 1 ex- generated negative-going pulse depends ically 0.1 to 0.3V. This difference allows
ploits the sampling gate from a 7S12 on the speed with which C2 discharges. for the strong saturation of Q2 just after
plug-in unit. The discharge takes place through the the trailing edge of the ECL signal.
Figure 2 shows the waveforms associ- base-emitter junctions of Q1 and Q2 and
ated with the circuit in Figure 1. The pos- resistor R1. The duration is difficult to Is this the best Design Idea in this
itive portion of the ECL signal charges ca- calculate, but for a rough estimate, you issue? Vote at www.ednmag.com.
Trigger a TTL circuit from ECL levels ......107

Microcontroller discerns addresses
Figure 2
in RS-485 systems........................................108
PC-board layout eases
high-speed transmission ............................110
Circuit protects system
from overheating ........................................112
Network imitates thermocouples ............114
Low-cost relative-humidity transmitter
uses single logic IC ......................................116
msec, 5V negative-going trigger from an 800-mV ECL signal.

The circuit in Figure 1 provides a 2-m
www.ednmag.com November 8, 2001 | edn 107

design
ideas
Microcontroller discerns addresses in RS-485 systems
Nigel Brooke and Ted Salazar, Maxim Integrated Products, Sunnyvale, CA
ne of the many benefits of using sometimes be difficult. The program code to accommodate any specific RS-
O the RS-485 data-interface system,

unlike the RS-232 system, is its abil-
ity to implement multidrop networks.
memory in IC1, for example, has only
1k314 bits of EEPROM. You have a third
alternative—a small, low-cost external
485 address-recognition application. The
circuit works as follows: When the bus
transmits an address, IC2 in each slave
Such networks usually carry 9-bit data UART, IC2. The use of this device liber- module initiates a parity interrupt. IC1 in
words, in which the ninth (parity) bit ates the program memory you otherwise each module then reads all the data in its
identifies each word as address or data. need for a software-based UART. internal FIFO, locates the address word,
When using small microcontrollers with- An RS-485 bus can carry as many as and compares that address with its own
out a hardware UART, such as IC1 in Fig- 256 transceiver modules of the type in address stored in the eight DIP switches.
ure 1, designers must decide whether to Figure 1. IC3 is the RS-485 transceiver, A match causes the slave to clear the in-
add an external hardware UART or to and IC4 is a “microcontroller supervisor” terrupt and transmit (to the master) an
configure a UART in software. External that holds the microcontroller in a reset ASCII “A” (41h), followed by its own ad-
UARTs once represented a large increase state until a valid supply voltage is pres- dress. If the slave module reads the FIFO’s
in board area, complexity, and cost, and ent. You can download the assembly-lan- contents without finding a match, it
the available UARTs were usually overkill guage program for the microcontroller clears the current address-word interrupt
for simple microcontroller applications. from the Web version of this Design Idea and waits for the next one.
On the other hand, sparing the program at EDN’s Web site, www.ednmag.com.
memory and processor resources you The application in Figure 1 is a slave-test Is this the best Design Idea in this
need for a software-based UART can configuration, but you can modify the issue? Vote at www.ednmag.com.
1 18
RA2 RA1
2 17
RA3 RA0
3 16 DIP
RA4 VCC
OSC1 SWITCH
VCC IC4 4 33 pF CRYSTAL
MCLR
2 RESET 4 MHz
3 MAX 5 15
VSS 1
809L 1 OSC2
IC1
GND PICI6F84 33 pF
2
6 14
RBO/INT VDD VCC 3
7 13
RB1 RB7
8 12 4
RB2 RB6
9 11 5
RB3 RB5
10
RB4 6
VCC 1M 1M 1M 1M 1M 1M 1M 8
VCC
10k VCC VCC
1
DIN
2 14 10k 8
DOUT VCC 1 VCC
RO IC3 7
3 13 B 7
SCLK TX 2
IC2 12 RE MAX3088 6
4 A 6
CS MAX3100 RX 3
VCC 11 DE 5
RTS GND
10 4
CTS
10k 9 DI
5 X1
IRQ CRYSTAL
6 (3.6864 MHz) 33 pF
SHUTDOWN SHUTDOWN 8
Figure 1 7 X2
GND 33 pF
Adding a small UART, IC2, and microcontroller, IC1, to the RS-485 transceiver, IC3, forms a slave data-transceiver module that responds to its own net-
work address.
108 edn | November 8, 2001 www.ednmag.com

design
ideas
PC-board layout eases high-speed transmission

Gregory Adams, Moorestown Microwave Co, Moorestown, NJ
s digital techniques move you can model them as
A to higher speeds, de-

signers become aware
of the need to treat pc-board
Figure 1 GAP
WIDTH
THICKNESS (0.01 IN.)

coupled “microstrip”
lines (Figure 1). On the
other hand, if the traces
traces as RF transmission lines. In are in a layer with
these lines, you strive to hold the ground planes above and
line impedance, Z0, to a constant below them, then you
value—typically, 50V—and to can model them as cou-
terminate the line with the same A microstrip transmission line has traces on one side of a pc board and a pled “striplines” (Figure
impedance. Data families such as ground plane on the other side. 2). In the stripline case,
ECL, PECL, and LVDS send data you assume that the pair
over a pair of traces known as a of transmission lines is
WIDTH
balanced transmission sandwiched between the
Figure 2 GAP
line. One line switches two ground planes and
high, while the other switches that the board thickness-
low. As with other high-speed es to the top and ground
logic families, you must hold the planes are equal. Tables 1
transmission-line impedance and 2 show the line
constant and properly terminate width required to hold
the line. If the spacing between Z0o constant at 50V for
THICKNESS (0.01 IN.)
the pair of traces is large, then you various values of the gap
can design the traces as simply between the two traces.
two 50V transmission lines. On A stripline transmission line has two traces embedded in the pc board and Table 1 applies to the mi-
the other hand, if the spacing be- ground planes above and below. crostrip case with lines
tween the traces is less than sev- on top of the board;
eral times the board thickness, then the sion line. The Z0o of a differential pair is Table 2 applies to the stripline case with
effect of one trace on the other changes always lower than the Z0 value of a single lines sandwiched between equally spaced
the characteristic impedance of the line. trace having the same width on the same ground planes. Note that the trace widths
In RF parlance, when equal voltages board. To hold the impedance of a trans- are much smaller in the stripline case be-
drive the two lines, the resulting imped- mission line to some required value, you cause of the second ground plane. Both
ance of each individual line to ground is must make the traces narrower than tables assume a board thickness of 0.01
called Z0 Even, or Z0e. When equal and would be the case with a single trace. in. You can directly scale the line widths
opposite voltages, as with differential sig- Generally, this fact is good news for dig- and gaps for other dielectric thicknesses.
naling, drive the two lines, the impedance ital designers who need to make those In every case, the dielectric material is
of one line to ground is called Z0 Odd, or transmission lines fit between the vias FR-4 with a dielectric constant of 4.6. The
Z0o. You need to concern yourself only under a dense BGA chip. tables use the old DOS version of HP’s
with Z0o, because it applies the to the im- If the traces are on the top of a board Appcad, a program HP distributes as
pedance of a differential-data transmis- with a ground plane under them, then freeware. The newer versions of this pro-
gram do not handle coupled lines. To cal-
TABLE 1—DIMENSIONS FOR TABLE 2—DIMENSIONS FOR culate the impedance, Z0 Odd, of differ-
50V V MICROSTRIP 50V V STRIPLINE ential transmission lines of other
dimensions, you can download a copy of
Gap (in.) Width (in.) Gap (in.) Width (in.)
Appcad from www.geocities.com/gregs
0.005 0.011 0.005 0.0055
downloadpage.
0.01 0.0142 0.01 0.0075
0.015 0.0158 0.015 0.0083
0.02 0.0166 0.02 0.0086
0.025 0.0171 0.025 0.0087 Is this the best Design Idea in this
` 0.0185 ` 0.0088 issue? Vote at www.ednmag.com.

design
ideas
Circuit protects system from overheating
Kerry Lacanette, Maxim Integrated Products, Sunnyvale, CA
he two-chip circuit
T in Figure 1 pro-
vides fan con-
trol and overtemperature
Figure 1 3.3V
4.5 TO 24V
250-mA FAN
warning and shutdown IC1

signals to protect systems MAX6665ASA45
from excessive heat. The
+ FAN OUT
circuit monitors the tem-
_
perature of the pc board TFAN
TEMPERATURE
and the die temperature SENSOR TFAN
of a CPU, an FPGA, or
+
another IC with an on- WARN
TFAN _
chip temperature-sensing 158
transistor. IC1 is a temper- HYST
ature detector and fan 1, 4, 88 + OT
3.3V
driver for cooling fans TFAN _
308
with nominal operation FAN ON 10k
of 250 mA. At low tem-
peratures, the cooling fan
is off, minimizing noise 3.3V
and fan wear. When the

CPU,
system temperature in- FPGA, OR IC2
creases to more than ASIC DXP MAX6512UT125
458C, IC1’s factory-pro- 2.2 nF TEMPERATURE
+
grammed temperature DXN SENSOR
_ TOVER
TFAN
comparator causes the HYST
FAN OUT fan-drive pin
to go active, pulling the 5, 108
fan’s lower power-supply
terminal to ground, thus
providing low-side drive
to the fan. The fan can ac-
commodate supply volt- This circuit provides fan control and overtemperature protection for systems and high-power digital ICs.
ages as high as 24V. After
the fan activates, the system temperature down signal. While IC1 monitors board resistor and to the power supply’s shut-
normally either continues to rise at a temperature, IC2 monitors the die tem- down terminal. If either the board tem-
slower rate or drops somewhat. If the perature of another chip—typically, a perature or the chip temperature exceeds
temperature drops far enough, the fan CPU, an FPGA, or an ASIC. The target IC the maximum safe rating, the system
turns off. To avoid causing the fan to con- must have a small-signal p-n junction, shuts down before damage can occur. IC1
tinuously turn on and off, IC1 provides usually a substrate pnp, for temperature should be in a location that allows it to
hysteresis of 1, 4, or 88C, which you can measurement. IC2 forces current through measure the temperature of interest. De-
set by the HYST pin. sense junction, measures the resulting pending on the system, this location
If a thermal problem, such as excessive voltage, and calculates the temperature of could be near a “hot spot” or in the cool-
power dissipation or blocked ventilation the junction. IC2 then compares this tem- ing fan’s airflow path. The traces between
paths, exists, system temperature may perature with a preset threshold. When IC2 and the remote-sensing junction
continue to increase. IC1 has two outputs the junction temperature exceeds the should be reasonably short and separat-
that detect this condition. WARN be- threshold, 1258C in this case, IC2’s output ed from high-speed data traces.
comes active when the temperature ex- pin goes active; you can use it to shut
ceeds 608C, and the OT output becomes down the system.
active when the temperature exceeds The open-drain shutdown outputs of Is this the best Design Idea in this
758C. You can use OT as a system-shut- IC1 and IC2 connect to a common pullup issue? Vote at www.ednmag.com.

design
ideas
Network imitates thermocouples
hermocouples find widespread use (Reference 1). But keep in mind that the
T for temperature measurement in sys-

tems. During system design or test-
ing, you must observe the system’s re-
TABLE 1—CORRECTION FOR
COLD-JUNCTION TEMPERATURE
Temperature Voltage Voltage
voltages in the book apply only to a cold-
junction temperature of 328F. The work-
ing temperatures are always different, so
sponse at different temperatures. (88F) at 3288F (mV) at 10088F (mV) you must recalculate the voltages. As-
However, it’s inconvenient to heat a ther- 550 11.71 10.19 suming that the ambient temperature is
mocouple every time you need to check 855 18.82 17.3 approximately 1008F, you can find the
a system’s performance. You can use the 900 19.89 18.37 thermocouples’ output voltages by sub-
simple trick of touching the thermocou- 1070 23.91 22.39 tracting 1.52 mV from the 328F value
ple with a hot soldering iron, but this (Table 1). You can calculate the values of
method provides only rough, approxi- pedance of the thermocouple imitator the divider resistors using the following
mate results. The simple network in Fig- must be low, and the output must con- equation: RU5RL(VCC/VOUT21), where
ure 1 allows you to set a number of volt- nect to ground between tests. RU is the upper divider resistor, RL is the
ages equal to the thermocouples’ outputs Figure 1 shows the thermocouple im- lower divider resistor, VCC is the power-
at given temperatures. A thermocouple’s itator for four temperatures. To obtain supply voltage, and VOUT is the output
output is relatively in the tens of milli- low output impedance, you set R2, R4, R6, voltage. To make the output-voltage ad-
volts. The low level entails the use of a and R8 to 1.3V. To satisfy the between- justment easier, the upper divider resis-
high-gain amplifier as a signal condi- tests grounding requirement, the motor consists of a 200V potentiometer in
tioner. These high-gain amplifiers are mentary SPDT key switches connect to series with a fixed resistor.
sensitive to noise. Susceptibility to noise the chain in a way that, when you press
is not a problem when the amplifier con- no switch, the output connects to References
nects to a thermocouple, thanks to the ground. By pressing a switch, you obtain 1. The Temperature Handbook, Omega
thermocouple’s output impedance of ap- one of the predetermined voltages from Engineering Inc, 2000.
proximately 1V. But during system test- dividers R1/R2, R3/R4, R5/R6, or R7/R8 at
ing, substituting a high-impedance the output. Assume, for example, imita-
source for the thermocouple can result in tor-equivalent temperatures of 550, 855, Is this the best Design Idea in this
noise pickup that can drive the amplifier 900, and 10708F.You can find the voltages issue? Vote at www.ednmag.com.
into saturation. Hence, the output im- from a Chromel-Alumel thermocouple
Figure 1 5V
200 200 200 200

5508F 8558F 9008F 10708F
R1 R7 NC NC NC NC
R3 R5
182 210 301 501
COM COM COM COM
10.2 mV
NO
NO NO N0 VOUT
17.3 mV
18.4 mV
22.4 mV
R2 R4 R6 R8
1.3 1.3 1.3 1.3
This network allows you to emulate thermocouple outputs at various temperatures.

design
ideas
Low-cost relative-humidity transmitter
uses single logic IC
Shyam Tiwari, Sensors Technology Ltd, Gwalior, India
he low-cost percentage-relative-
T humidity radio transmitter in

Figure 1 operates in a cold-
storage warehouse for vegetable storage
Figure 1
ENABLE
1
2
IC1A
74HC132
3 4
5
IC1B
74HC132
6
10
9
IC1C
74HC132
8
ANTENNA
28-CM-LONG
COPPER WIRE
at temperatures of 1 to 58C. It is general- R2
1k
ly difficult to collect such data from a R1
4.7M
low-temperature area with high humid- C2
C1 220 TO 300 pF 100 pF L1
ity and low illumination. The transmit- 0 TO 100% RELATIVE-
HUMIDITY SENSOR
ter design is simple: It uses a readily avail-
able, capacitor-type percentage-relative- C4 C3
22 pF 5 pF
humidity sensor for which the capacitor NOTES:
L1 IS SIX TURNS OF 22-GAUGE WIRE WITH 5-MM DIAMETER.
value increases with humidity. Generally, L2 IS 18 TURNS OF 22-GAUGE WIRE WITH 5-MM INNER DIAMETER.
these sensors offer accuracies well with-
in 5%. Humirel (www.humirel.com) rel- This percentage-relative-humidity transmitter uses 10- to 50-MHz, tunable RF, and 1- to 2-kHz
ative-humidity sensors work well with on/off amplitude modulation.
this circuit; you can also use other types
with low leakage resistance. The R1C1 R2C2, equating to a 10- to 50-MHz RF quency, then you can reduce R1 to 1 MV,
product gives the time constant for the band. The last inverter is a power driver changing the modulating signal to the
audible-modulating, 1- to 2-kHz signal for the tuned filter and antenna. The cir- range of 10 to 20 kHz.
oscillator, which you can gate to stop the cuit requires a 3 to 5V battery. Two AAA
communication. This oscillator starts the cells can power it for approximately 15 Is this the best Design Idea in this
RF oscillator, which has a time constant, days. If you need a high modulating fre- issue? Vote at www.ednmag.com.

design
ideas
Circuit compensates
optocoupler temperature coefficient
J Michael Zias, Acme Electric Corp, Cuba, NY
hen using an optocoupler in a
W
10k 6
1
linear application, you
Figure 1 5 8 12V
should consider its gain 4 10k
2 3
drift with temperature. Traditional sin- 100V
IC2
+
IC1 1
gle- and dual-transistor-output devices H11AV1 402 LM358
2 2
4
have a notable gain drift with tempera-
ture. In recent years, some temperature-
compensated optocouplers have ap-
peared. However, another option is to use 2200 pF
1
6
two optocouplers or a dual optocoupler 10k
5
with appropriate feedback to make the 2
4 VOUT
drift of one device cancel the drift of the IC3
402
other. The circuit in Figure 1 accom- 402 H11AV1
plishes that task by using a differential
amplifier with the drift treated as a com-
mon-mode signal. In operation, it is in- By using two optocouplers instead of one, you can cancel temperature-dependent gain drift.
teresting to apply a dc signal to the input
and use digital voltmeters to simultane-
A a 1
ously monitor the output of each opto- INPUT GAIN = a = • ,
coupler and the differential amplifier.
a
A
OUTPUT 1 + Ab b 1+
1
Apply a heat gun and observe the indi- Ab
vidual outputs change rapidly where a/b is the ideal closed-loop gain
while the amplifier output moves Figure 2 and is multiplied by the loop-gain error
b
term. Given that the error term is small
(from the large gain A of the op amp), the
Circuit compensates optocoupler Control-system feedback theory explains the
gain of the system is seen as the ratio of
temperature coefficient ................................93 operation of the circuit in Figure 1.
the gains (current-transfer ratios) of the
Soft-start controller is much more slowly. This result occurs optocouplers. You can also easily find this
gentle on loads ..............................................94 even with optocouplers from different same ratio by setting the voltages to the
Method offers fail-safe manufacturers. With optocouplers of the op-amp inputs equal. The input and out-
variable-reluctance sensors ........................96 same type, you can observe good drift put signals for this analysis are currents,
cancellation. Parts from the same manu- which precision resistors translate to volt-
Circuit efficiently switches
facturer and dual devices give outstand- ages. The optocouplers in this design are
bipolar LED......................................................98
ing results. You can use individual opto- not particularly fast devices, so the phase
Circuit forms adjustable couplers instead of dual devices to meet delays could cause oscillation without a
bipolar clamp ..............................................100 safety-agency spacing requirements. feedback capacitor. You choose its value
Analog switch expands I2C interface ......102 To examine the method in control-sys- empirically by applying a pulse at the in-
tem terms, consider Figure 2, which put and observing the rise time and over-
Circuit safely applies power to ICs ..........104 shows one amplifier, a, in the forward shoot at the output.
Simple circuit forms path and another amplifier, b, in the feed-
peak/clipping indicator ..............................104 back path. Also consider the following Is this the best Design Idea in this
equation: issue? Vote at www.ednmag.com.
design
ideas
Soft-start controller is gentle on loads

Douglas Sudjian, Resonext Communications Inc, San Jose, CA
he control circuit in Figure 1 IC1’s output changes state, driving the age across Q2 and Q3 changes according
T senses a given load and automatical-

ly soft-starts the load by synchro-
nously adjusting the power to that load.
signal diode, D5, into and out of conduc-
tion. R6, R7, and C3 create a delay such
that the voltage at Q6’s gate decays slow-
to the time constant of R8 and C4. The ad-
ditional current that Q3 sources to C2 in-
creases the voltage rate of change at pins
You can also manually adjust the power ly to allow for the load’s switch-closure 6 and 7 of IC2. IC2, a TLC555CP, is a low-
delivered to the load by controlling the noise or missed ac cycles. Once Q6 turns power timer configured as a monostable
phase angle of the line voltage across the off, the voltage at the base of Q2 rises to a multivibrator.
load. The phase-angle adjustment for higher reference level, which voltage di- In the monostable mode, the timer is-
every ac half cycle covers 0 to 1808. When vider R3 and R4 sets. The bias current of sues a positive pulse output every time a
the isolation transformer, T1, senses the transistor pair Q2 and Q3 slowly passes negative-going trigger pulse arrives at Pin
load current in the ac ground return, through Q3 as the differential input volt- 2 of IC2. The output pulse width corre-
LINE
115V AC 15A 12V
R3
R2
20k 68k
50k 10k
1%
20k 5.1k 20k
22k 22k 1% 0.1 mF
Q1 Q2 Q3
Figure 1 1W 1W
2N3096 2N3096
2N3096 Q4
51k 53.6k
1% 8 4 2N3094
D1 0.047
1N4002 7 mF
D3 3
R8 10k
1N4001 R4 IC2
121k
54.9k 6 TLC555CP 5
1% R9
1%
D4 75k
45.3k
D2 1N5242 + C2
1% 2 1
AC-LINE 12.1V
+
C1 O.1 mF
INPUT 100 mF 16V 0.01 mF
20V
R1
2Ok
(NOT LINE GND) 12V
R7
100k 0.1 mF R6
8 51k D5
100k
5 1N4148 C4
NEUTRAL T1 1k +
3
2
6 22 mF
IC1 7 16V
220 pF LM311 Q6
560k 2 24k 2N7000
+ 1N4148
1
2:50
4
C3 +
10 mF
16V
1k 1M
100k
This soft-start circuit protects the load from large inrush currents.

sponds to the time it takes the voltage on
capacitor C2 to ramp from 0V to 2/3 VCC.
With a constant current essential-
ly charging C2, the charging is lin- Figure 2 AC 0
LINE
ear, and the output at IC2’s Pin 3 is pro- POWER TO LOAD
portional to the current set by R2. The
full-wave bridge, with D3 and D4 and fil- IC2
ter capacitor C1, forms a dc power sup- PIN 2
12
ply for the timer/controller. The com- IC2
0
PIN 3
mon cathode node for D1 and D2 pulls to
ground via R1 every time the line volt-
age approaches 0V. Q1 turns on and sup- 12
VOLTAGE
plies a negative-going trigger to Pin 2 of ACROSS R9
8
12
IC5 11
MAC223-8FP VOLTAGE AT Q5
MOC3052
340 COLLECTOR
1 4 0.01 mF
0
R5 MOV
30k
2 6
The circuit in Figure 1 provides soft-starting by adjusting the phase angle of the power applied to
Q5
47 the load.
2N3094
IC2. This pulse uses its negative edge to is floating; you must not tie these
provide a minimum pulse width of 200 grounds together. The design in Figure
msec to the base of Q4. The feedback pair 1 has successfully controlled fans and
150 Q4 and Q5 provides signal inversion and high-amperage universal motors (100
limits the current drawn from the 12V mA to 11A). One example is a router for
supply rail through IC3. When sufficient woodworking. By soft-starting these
LED current develops, the MOC3052 high-torque motors, the reaction torque
triac driver latches on and generates a (to the input current) that the user feels
gate current in the power triac, trigger- disappears. Moreover, other soft-start de-
ing it into the conducting state. Once the signs need two switches. The design in
power triac latches on, the triac driver Figure 1 needs only one on-off switch
LOAD enters its off state, even if the LED cur- (located at the load). Thus, less danger
INPUT rent still exists. exists for incurring an accidental starting
The power triac’s gate voltage falls be- condition. Figure 2 shows some of the
low the optocoupler’s threshold and waveforms associated with the circuit in
cannot hold the optocoupler. The longer Figure 1. T1 is a signal transformer that
the phase delay from the zero-crossing you can modify by wrapping two turns of
trigger, the smaller the conduction an- 14-gauge wire around the bobbin to act
gle and power delivered to the load. R5 as the primary winding.
facilitates on-off switching of the triac-
driver LED by providing a path for leak-
age currents. Potentiometer R2 provides
variable power to the load (to provide
motor-speed control, for example). R2
varies the dc-source current that charges
C2 every ac half-cycle. Note that the sig- Is this the best Design Idea in this
nal ground with respect to earth ground issue? Vote at www.ednmag.com.
design
ideas
Method offers fail-safe
variable-reluctance sensors
Phil Levya, Maxim Integrated Products, Sunnyvale, CA
ariable-reluctance sensors are the cable or sensor. The circuit in Figure the steel bar supplies the necessary mag-
V preferred for industrial and automo- 1 is a fail-safe variable-reluctance sensor netic flux. The rotating target causes a
tive environments, because they sus- for low- to medium-speed operation.
tain mechanical vibration and operation
change in reluctance and, hence, a change
The circuit comprises L1; R1; and a in the amount of magnetic flux conduct-
to 3008C. In most applications, they sense quad RS-422/RS-485 receiver, IC1. It pro- ed. This change produces a correspon-
a steel target that is part of a rotating as- vides the complementary, independent ding change in the current induced in L1.
sembly. Because the unprocessed signal output signals VOUT and VOUT. Table 1 lists R1 converts the L1 current to a time-vary-
amplitude is proportional to target speed, the resulting fail-safe modes. The supply ing voltage. This voltage goes to the in-
a sensor whose signal-processing circuit- voltage can be 10V, 12V, or the control puts of IC1, whose input-voltage range of
ry is designed for high speed ceases to system’s 24V-dc source. Coil L1 consists 625V, input threshold of 60.2V, and
function at some lower rate of rotation. of 2600 turns of #32 magnet wire wound typical input hysteresis of 45 mV enable
Hall-effect sensors are preferable for on a 0.8-in. steel bar of 0.2-in. diameter, the VR sensor to operate at low speeds.
speeds of several pulses per second, but with 0.125 in. protruding from the sen- The separate, complementary outputs
they require the attachment of a magnet sor face. A magnet attached to the back of come from separate, ESD-protected in-
to the rotating assem-
bly. They’re thus prone TABLE 1—FAIL-SAFE MODES (TWO CYCLES OF VOUT OR VOUT)
to failure when the (VOUT, VOUT) Mode
magnet is broken or (1,0) then (0,1) or (0,1) then (1,0) Normal mode, both pulses valid
damaged. Neither vari- (1,0) then (0,0) or (0,0) then (1,0) Failure, valid VOUT pulse, VOUT failure, cable failure, or partial sensor failure*
able-reluctance nor (0,1) then (0,0) or (0,0) then (0,1) Failure, valid VOUT pulse, VOUT failure, cable failure, or partial sensor failure*
Hall-effect sensors of- Always (1,1) Short-circuited cables or failure in IC1
fers fail-safe detection Always (0,0) Severed cables, failure in IC1 or failure in Q1 and Q2
of the processed signal
*System remains functional in failure modes.
in the event of failure in
10 TO 24V
Figure 1 STEEL
5V 1
ROTATING IN OUT 3 5V
TARGET IC2
4 MAX1615
5V R2
G 5
SHDN + 1k
12 16 4 C2
G VCC 5/3
C1 4.7 mF
2 0.1 mF GND
A1
2
IC1 VOUT
MAX3095
Q1
1
L1 R1 B1 Y1 3
47k
7
B2
10V
6
A2
8 R3
GND Y2 5 1k
VOUT
10
A3 Y3 11
9 B3 Q2 GND
14 A4 Y4 13
BAR 15
B4
MAGNET
NOTE: Q1, Q24FAIRCHILD FDV303N.
This circuit provides a fail-safe, low- to medium-speed variable-reluctance sensor.

design
ideas
puts. IC1’s outputs Y1 and Y2 can source IC1. Figure 2 illustrates low- (Figure 2a) For 3V applications, replace IC1 with a
as much as 10 mA. They alternately and medium-speed (Figure 2b) opera- MAX3096 IC.
switch the logic-level, n-channel MOS- tion for the sensor. For 5V-supply appli-
FETs Q1 and Q2, which in turn provide cations in which you can locate a micro-
VOUT and VOUT. A low-dropout regulator, controller close to the sensor, you need Is this the best Design Idea in this
IC2, provides the 5V power source for only L1, R1, and IC1 for a direct interface. issue? Vote at www.ednmag.com.
Figure 2
CHANNEL 1 CHANNEL 1
FREQUENCY FREQUENCY
4.958 Hz 752.4 Hz
CHANNEL 3 CHANNEL 3
PEAK TO PEAK PEAK TO PEAK
270 mV 5.70V
(a) (b)
These waveforms represent operation at 4.9 Hz at 2.4 revolutions/sec (a) and 752.4 Hz at 376.2 revolutions/sec (b). Channel 1 is VOUT, Channel 2 is VOUT,
and Channel 3 is the voltage across R1.
Circuit efficiently switches bipolar LED

Spehro Pefhany, Trexon Inc, Toronto, ON, Canada
he circuit in Figure 1 represents 5V
T one method to switch a bipo-

lar, two-color LED using an
SPDT mechanical switch or relay. This
Figure 1
12V
RED GREEN
Figure 2
RS
130
SPDT
circuit wastes power and does not work SPDT
properly if the power-supply voltage is GREEN RED
not substantially more than the sum of D1
the LEDs’ forward voltages. The circuit is, D2
D2
therefore, marginal, to the point of be-
ing unusable, with a 5V supply and a red RA RB
D1
or green LED, which typically has a total
forward voltage of 4V. You can use a cir-
R1 R2
cuit resembling a flip-flop (Figure 2) that This switching circuit wastes power and does
doesn’t suffer the disadvantages of the not work with low supply voltages. 750 1.8k
circuit in Figure 1. It adds only one
VCE(SAT) voltage to the VF of each LED, so costs less than a dime for the parts, which
plenty of headroom exists with a 5V sup- include three resistors and two inexpen- In this “flip-flop” switch, the only losses come
ply and a series resistor to control the sive, general-purpose npn transistors, from the VCE(SAT) and the base currents of the
LEDs’ current. The circuit in Figure 2 such as the 2N4401 or the C8050. In this transistors.
design
ideas
example, D1 is red (VF151.6V), and D2 is base drive is a function of the VF of the power supply. The circuit requires only
green (VF252.4V). Based on D2, the driven LED, so you can calculate the base two connections, rendering it ideal for
green LED, you can calculate that resistors, using a forced beta of 20, as fol- front-panel use. Because the 130V resis-
R S5(5V22.4V20.1V)/0.02A5125V lows: tor is in series with the power supply, any
(use 130V for 19 mA). R1520(VF120.7V)/ILED15720V part of the circuit beyond RS can short
As a result, using a single resistor, D1 (use 750V). to ground without causing damage.
has a current of 25 mA. If it is desirable R2520(VF220.7V)/ILED251.8 kV.
to have equal or arbitrarily different cur- The base drive reduces the actual LED
rents, you can insert an additional resis- current by 5%, which is visually negligi-
tor in one leg of the switch to increase the ble. As a bonus, the circuit does not in- Is this the best Design Idea in this
effective RS for that switch position. The troduce any switching glitches into the issue? Vote at www.ednmag.com.
Circuit forms adjustable bipolar clamp

Pautasso Luciano, Nichelino, Italy
he easy way to clamp a signal to a
T given value is to use two zen-

er diodes, connected back-to-
back. This method has several disadvan-
F i g u r e 1
VIN
2
1
3 +
8
IC1A
TL082
15V
1
680
6
1
5 +
IC1B
TL082
7
VOUT
tages. The accuracy of the clamping

4 15V 390k
depends on the tolerance of the zener 115V 1%
diodes, and the clamping is not ad- 2 1 8
D1
IC2A
justable, except by changing diodes. The TL082
1
3 +
circuit in Figure 1 is a bipolar clamper 4
1N4148
with a range of 61 to 610V, with the 390k 115V

1%
clamping level a function of the input
VCLAMP. IC1A, IC1B, and IC3A are unity-gain
15V 6
buffers. IC2A is a positive clamper, and 8 1
IC2B
D2
2 7
IC2B is a negative clamper. Figure 2 shows 1 TL082
IC3A 1 5 + 1N4148
the transfer function, with VCLAMP set at 3
TL082
VCLAMP +
25V. You can change VCLAMP over the
range of 21 to 210V and thereby change 115V
the clamping level. If VIN is within

2VCLAMP to 1VCLAMP, then VOUT 5VIN. If This circuit provides adjustable clamping over the range of 61 to 610V.
VIN exceeds VCLAMP, then VOUT5VCLAMP.
To explain how the circuit works, assume open switch. The feedback loop around D, D2 conducts, and D1 is an open switch.
four cases, with four values of VIN. Basi- IC2A regulates the anode of D1 to 5V and
cally, the circuit works in two modes: the the output of IC2A to 4.4V. In cases B and Is this the best Design Idea in this
linear mode, in which diodes D1 and D2 C, both diodes are open switches. In Case issue? Vote at www.ednmag.com.
are open switches, and the clamped
mode, in which the diodes are closed
OUTPUT
switches. Table 1 gives results for the 10
Figure 2
four cases. In Case A, the input is 7V, 8
VCLAMP is 25V, D1 conducts, and D2 is an 6 OUTPUT
4 CLAMPED
TABLE 1—RESULTS FOR CLAMPED INPUT 0

2
AND LINEAR MODES 210 25 22 0 5 10
OUTPUT 24
Case VIN (V) VOUT (V) Mode
CLAMPED 26
A 7 5 Clamped 28
B 3 3 Linear 210
C 13 13 Linear
D 17 15 Clamped With VCLAMP set at 25V, the output clamps firmly at 65V.

design
ideas
Analog switch expands I2C interface
Luca Vassalli, Maxim Integrated Products, Sunnyvale, CA
erhaps the most effective way to devices could have the same address in mand). You can switch the three auxiliary
P gain board space and increase com-

ponent density is to minimize
wiring on the board. A widely used ar-
some application. In Figure 1, analog
switch IC1, which is I2C-controlled, con-
nects auxiliary branches that contain de-
buses on the fly. Power-up sets the
switches to soft mode, an off state with
12-msec switching time. Then, a com-
chitecture that allows such miniaturiza- vices with the same address to the main mand byte of 0b11000000 sets the
tion is the I2C bus. Comprising only a I2C bus. IC2 and IC3, for example, have switches to hard mode (400-nsec switch-
bidirectional data line, SDA, and a clock the same address but are located on dif- ing time). Subsequent commands select
line, SCL, this bus requires no chip selects ferent auxiliary buses. the desired auxiliary bus. Command
or other additional connections. Micro- The arrangement in Figure 1 prevents 0b1000011, for example, selects auxiliary
controllers from Philips, Microchip, and the master from addressing multiple bus 1. The main I2C bus includes neces-
other manufacturers include dedicated slaves at the same time. If that situation sary pullup resistors, and the auxiliary
I2C interfaces, but you can also imple- occurs, the data becomes corrupted dur- buses include weaker pullups that ensure
ment the interface in software. To coming a master-read protocol, and all slaves a high state when you deselect the bus.
plete this task, you associate a 7-bit ad- may not receive data during a master- The circuit in Figure 1 allows you to add
dress with each master or slave trans- write protocol. The analog switch accepts three times more devices on the bus. For
ceiver and factory- or pin-program the bidirectional signals as required for the a wider selection, you can replace the
device with two to four address options. SDA line. The switch has low on-state re- MAX4562 with a MAX4572, whose 14
An increasing number of slaves now in- sistance, adds almost no leakage on the switches allow you add as many as seven
clude the I2C interface, but some of their lines, and provides four selectable slave auxiliary buses.
128 address locations are reserved for addresses. You simultaneously control
special functions, so not all locations are the switches by using the simple Send- Is this the best Design Idea in this
available to a designer. Yet, two or more Byte protocol (address plus 8-bit com- issue? Vote at www.ednmag.com.
VDD
IC2
ADDRESS: 0250 ADDRESS: 0251 ADDRESS: 0252
Figure 1
SDA SCL SDA SCL SDA SCL
2250k
AUXILIARY I2C
BUS 1
VDD
IC1 IC3
MAX4562 ADDRESS: 0250 ADDRESS: 0251 ADDRESS: 0252
22
COM3 NO3 50k
NO1A AUXILIARY I2C

COM1
BUS 2
NO1B
VDD
COM4 NO4 SDA SCL SDA SCL SDA SCL
NO2A 2250k
COM2 AUXILIARY I2C
NO2B
BUS 3
ADDRESS: 0298
SDA SCL A1 A0
MICROCONTROLLER VDD
WITH I2C INTERFACE
225k
SDA MAIN
SCL I2C BUS
This I2C-controlled analog switch expands by three the number of devices connected to the bus.

design
ideas
Circuit safely applies power to ICs
Clayton Grantham, National Semiconductor, Tucson, AZ
V SAFE
upervisory circuits normally
S
VIN (<30V) (3.1 TO 5.5V)
monitor a microprocessor’s
supply voltage, asserting reset Figure 1 R3 R4
4k 1M Q2
to the IC during power-up, power-down, 5 NDS8947
VCC
and brownout. In this way, the circuit en- R1
sures that the supply voltage is stable be- 1M IC1
LM3722
fore the microprocessor boots, thus pre- Q1 4
MR 3.08V
2SD601
venting code-execution errors. Many RESET 3 Q3
analog and digital ICs also need a well- GND R5 2SD601
behaved start-up of their supply to avoid R2 1M
120k 1, 2
latch-up and logic-state errors. In addi-
tion to low-supply conditions, low-volt-
age CMOS circuits need overvoltage pro-
tection from any supply runaway. The This LM3722 configuration connects only safe voltages to sensitive ICs.
additional components in Figure 1 ex-
tend IC1’s supervisory functions to con- Adjustment of R2 for an exact overvolt-
nect VIN to VSAFE only when VIN is within TABLE 1—VSAFE HYSTERESIS age value nullifies VBE1’s accuracy error.
set limits. This function protects circuit- OVER TEMPERATURE Table 1 shows typical setpoints over tem-
ry at the VSAFE terminal from power-up VSAFE 088C 2588C 5088C perature. If you need further error re-
transients and overvoltage damage. As a On (V) VIN increasing 3.2 3.2 3.2 duction, you could exchange Q2 for a
supervisory circuit, IC1 asserts a reset sig- Off (V) VIN increasing 6.1 5.5 4.9 comparator and voltage reference. For
nal that is delayed by more than 100 msec On (V) VIN decreasing 6 5.4 4.8 VIN within the set limits, 3.1 to 5.5V, the
whenever VIN decreases below the pre- On (V) VIN decreasing 3.1 3.1 3.1 circuit draws only 16 mA. A total of 5 mA
cisely trimmed reset threshold. You can flows into both the R1 and R4 nodes, and
custom-select the reset threshold from is Q2’s pullup resistor; R5 limits Q3’s base 6 mA flows into R3’s node. R3 protects IC1
2.32 to 4.63V. You can also use current. Using Q1 as an inexpensive 0.6V by providing current limiting of less than
a manual input, MR, to assert the reset switch, resistor dividers R1 and R2 set the 6 mA) for high voltages at VIN. The typi-
signal. overvoltage threshold according to the cal IC1 current of 6 mA through R3 in-
This application uses IC1’s delayed re- equation VOV 5VBE1(R11R2)/R2. An increases the undervoltage setpoint by 24
set signal to control switch Q2. The delay ternal 22-kV resistor at IC1’s MR input mV.
ensures that VIN is stable before applica- provides Q2’s pullup. Typical VBE1 accu-
tion to VSAFE. Q3 inverts and isolates IC1’s racy and temperature-coefficient errors Is this the best Design Idea in this
reset signal to control the gate of Q2. R4 are 610% and 22 mV/8C, respectively. issue? Vote at www.ednmag.com.
Simple circuit forms peak/clipping indicator

Steven Hageman, Agilent Technologies, Santa Rosa, CA
he simple peak detector in Figure simultaneously apply to both left and positive peaks to pass while disconnect-
T 1 is the result of a need for a single-

5V-supply, level/clipping indicator
for a multimedia-PC sound system. The
right stereo inputs. The output is suitable
for driving a bar-graph display or for ana-
log-to-digital conversion and display
ing the op amp from the hold capacitor,
C1, on negative peaks. Also, because the
diodes have an OR connection, the cir-
design is unique in that it detects both with a microprocessor. The circuit oper- cuit detects only the larger peak from the
stereo channels on a single peak-hold ca- ates as a dual positive-peak-detector cir- left or right stereo input. The values
pacitor. All the adjustments in the circuit cuit. The dual diode, D1, serves to allow shown in Figure 1 are for standard 200-

design
ideas
mV-rms line-input levels, such as those
5V
you’d find on a PC’s sound-card
Figure 1 0.1 mF
line input. Your personal prefer-
ence or exact needs might require other
performance parameters, and you can LEFT 0.1 mF 8
3 +
AUDIO
easily adjust these values. IC1A 1
R4 LMC662CM
The gain for both stereo channels is 100k 2 _ D1
equal to 11R2/R3. The circuit as shown 4
BAV70
has a gain of 5. For a full-scale 200-mV-
rms input, this gain produces an output
R3 R2 R1
of approximately 1.4V. This value is con- 49.9k 200k 1k
venient for this application, which uses PEAK
OUTPUT
three green LEDs, two yellow LEDs, and `
one red LED to show the relative peak C1
RIGHT 5 1 mF
+
levels of the stereo channels. Nominal, AUDIO
R5
IC 1B
7
0.1 mF LMC662CM
full-scale line input of 200 mV rms lights 100k
6 _
two of the green LEDs. “Attack time” is
the time it takes the peak detector to re-
spond to 69% of an input-signal peak, or
one time constant. The time constant This simple circuit provides peak detection and clipping indication for a PC’s stereo channels.
R1C1 sets the attack time. In this circuit,
the attack time is 1 msec. The decay time compared with R21R3). The decay time easily obtain them by following the
is the time it takes the peak to decay to in this case is 250 msec, because that val- design equations above.
31% of its original value, or one time ue produces a pleasing-looking bar-
constant. This time equals (R21R3)C1 graph display. Some applications may Is this the best Design Idea in this
(assuming that R1 is negligibly small need different response rates; you can issue? Vote at www.ednmag.com.

design
ideas
Software makes full use of 8051’s interrupt system
Deng Yong, Shanghai Jiaotong University, China
he program in Listing 1 uses a pseu-
T do-RETI instruction to provide a

five-priority-level interrupt system
for the 8051P microcontroller. The inter-
LISTING 1—FIVE-PRIORITY-LEVEL INTERRUPT SYSTEM FOR 8051P
rupt-priority order, from high to low, is

INT0 IT0 INT1 IT1 INTP. Before the
pseudo-RETI instruction arrives in the
IT0 or IT1 interrupt-service routine, the
address of the first instruction, which is
after the pseudo-RETI instruction, goes
back into the stack. The internal, nonad-
dressable flip-flop associated with IT0 or
IT1 clears to acknowledge a higher inter-
rupt after execution of the pseudo-RETI
instruction, while the IT0 or IT1 inter-
rupt-service routine executes continu-
ously until the RETI instruction arrives.
Hardware circuits can exchange the INT1
and INT2 interrupts, and software can set
the IT1 and IT2 interrupts.
You can download Listing 1 from the
Web version of this article at www.
ednmag.com.
Is this the best Design Idea in this issue?
Vote at www.ednmag.com.
Software makes full use

of 8051’s interrupt system..........................111
Improve FET-based gain control ..............112
Circuit improves on bias
for GaAs FETs ................................................114
Build your own bypass-
capacitor tester ............................................116
DAC and op amp provide
variable-control voltage..............................118
Logic offers complementary-
switch control................................................120
Circuit measures currents
in dc servo motor ........................................122
www.ednmag.com December 6, 2001 | edn 111

design
ideas
Improve FET-based gain control

Ron Mancini, Texas Instruments, rmancini@ti.com
ne problem with standard FET tween R3 and RDS creates VDS from the
O
7V
gain-control circuits is output voltage, according to the fol-
increased noise when you Figure 1 + lowing equation:
use the FET as a part of a resistive at- TLC071 VOUT
R DS
tenuator in series with an op amp. 2 VDS = VOUT =
R DS + R 3
This configuration attenuates the sig-
17V
nal before amplification; hence, it re- 0.076
0.1V = 5 .
quires much higher gain bandwidth VIN
R1 R2 R3 0.076 + R 3
and better noise performance from 27k 3k 24k
the op amp. When you substitute the You can calculate R3 as 24.5 kV and
FET for the gain-setting resistor in a RA
select 24 kV. The parallel value of R2
noninverting op-amp circuit, distor- 100k J271 and R3 determine the maximum cir-
VC
tion limits the circuit configuration to RB cuit gain. Selecting R2 as 3 kV yields R1
applications in which the input volt- 100k equal to 27 kV and a maximum gain
age is less than a few hundred milli- of 237. The measured gain at
volts. The FET imposes this limita- The drain-source resistance of the FET controls the gain VC5VGS50V is 236.1, which corre-
tion, because the channel-depletion of the op-amp stage. lates well with the calculated value. RA
layer is a function of VDG and and RB are feedback resistors that
VGS. The improved circuit in linearize the FET’s VGS versus RDS
Figure 1 uses the FET 8 transfer function. You can nor-
as part of the feed- F i g u r e 2 mally obtain adequate lineariza-
RA=27k
back loop. The voltage across tion with equal-value resistors,
the FET is limited in this ap- 7 but you can also control the
plication, and the noise per- slope of the transfer function by
formance is good. An added setting the resistor ratio. The
bonus is improved linearity 6
RA=51k
graph in Figure 2 shows that RA
performance. The transfer modifies the transfer function
function for the improved cir- and linear control-voltage range
cuit is as follows (Reference 1): 5 (VGS). The p-channel FET, J271,
R 2R 3 requires a positive control volt-
R2 + R3 + age, but you can use a negative
V R4 RA=100k
1 OUT =1G = . control voltage with an equiva-
VIN R1 FET-CONTROL 4
VOLTAGE lent n-channel FET, such as the
When R21R35R1 and R45
(V)
J210. The circuit is versatile and
RDS (FET drain-source resist- provides low distortion, wide
3
ance), the transfer function re- range, good linearity, and low
duces to 2G511R2||R3/RDS. cost. The TLC071 op amp has
The minimum drain-source low input-bias currents and has
2
resistance for the FET on hand, provisions for input offset-volt-
J271, is 76V at VGS50V. The age correction.
actual VDS at the inception of
distortion varies with each 1 Reference
FET, but keeping VDS lower 1. Mancini, Ron, “Op amps
than 200 mV usually prevents for everyone,” Texas Instru-
distortion. In the design in Fig- 0 ments, September 2000, pg 3.
210 220 230 240
ure 1, the FET drain-source GAIN
voltage is limited to approxi- Is this the best Design Idea in
mately 100 mV to prevent dis- The ratio RA/RB in Figure 1 controls the slope of the gain-control this issue? Vote at www.
tortion. The divider action be- transfer function. ednmag.com.
112 edn | December 6, 2001 www.ednmag.com

design
ideas
Circuit improves on bias for GaAs FETs
Tom Roberts, Anritsu Co, Morgan Hill, CA
t’s important to properly sequence
I the bias applied to an RF/mi-

crowave GaAs FET or a MMIC
(monolithic-microwave-IC) amplifier.
Figure 1
15V
C2
0.1 mF
50V +
3
IN IC1
LT1085
OUT
2 8V
V1
VDD
These devices are extremely sensitive to
drain and gate voltage levels as well as to + 10 mF ADJ 301
10% 1
the order in which these biases turn on 3.01k 35V + 10 mF
and off. A GaAs-FET amplifier that uses 10%
two bias voltages—a negative supply, 35V
Q1 1.62k
VGG, on its gate and a positive supply,VDD, 2N3904
on its drain—requires that VGG be pres- V2
ent before the application of VDD. When 1k 25V VGG
powering down the amplifier, VDD must

go to 0V before VGG changes from its neg- 15V
ative value to 0V. Figure 1 shows a com-
monly used disable circuit found in many In disabled mode, this circuit supplies a potentially damaging 1.25V to the drain of a GaAs FET or a
voltage-regulator data sheets. The circuit MMIC.
uses a 2N3904 switching transistor to pull
the ADJ pin to ground to disable the volt-
0.1 mF
age regulator. The circuit does not set the 50V Q2
output of the regulator to 0V but instead 5% CBCP69
3
IC1 2 8V V1
sets the output to the regulator’s reference 15V IN LT1085 OUT
VDD
voltage, 1.25V. The condition in which a + 10 mF ADJ
35V R1 301
GaAs FET or MMIC has 0V on the gate 10%
1k 1
1% + 10 mF
1%
and 1.25 on the drain can result in dam- 35V
age to the device. For example, M/A- 1.62k 10%
R2 1%
Com’s MAAM26100-PI MMIC power
4.7k
amplifier requires 8V for VDD and 1%
25V for VGG. With 1.25V on VDD Figure 2 Q1
and 0V on VGG, the MMIC draws ap- 2N3904
D2
proximately three times its nominal drain 25V V2
VGG
current, sufficient to cause destructive 1k CMOSG2-3
failure. Figure 2 shows an improved cir- 1% C1
+
cuit for the adjustable regulator. D1

A medium-power pass transistor, Q2, a MBZ5226 10 mF
3.3V 10V
Central Semiconductor CBCP69, con- 25V 5% 10%
nects to the input of the voltage regula-
tor to disable the regulated output volt- This circuit provides safe power-up and power-down sequencing for sensitive GaAs FETs and
age. In disabled mode, the voltage at the MMICs.
regulator’s output is 0V. In enabled mode,
Q1 saturates and activates a voltage di- from 25V to 0V and the regulator (in other words, at 0V). The RC time con-
vider comprising R1 and R2. Q2 saturates, switching from 8V to 0V. To ensure that stant of the Schottky-diode leakage re-
and the output swings from 0 to 8V. Be- VGG remains at 25V after disabling IC1, sistance, the FET gate resistance, and C1
cause of the propagation delay of the you can exploit the high FET gate resist- is long compared with the RC time con-
transistor switching network, the 8V out- ance and the low-leakage Schottky-diode stant at VDD. As well as having low reverse
put switches from 0 to 8V after the 25V characteristic. The combination of high leakage, D2 has an inherently low (0.1V)
supply switches from 0 to 25V. D1 sets gate resistance of the GaAs FET, the low- forward drop.
the disable threshold of the 25V supply leakage Schottky diode, D2, and the 10-
to approximately 24V to minimize the mF capacitor, C1, provides a high VGG RC Is this the best Design Idea in this
delay between the 25V supply switching time constant when the 25V supply is off issue? Vote at www.ednmag.com.

design
ideas
Build your own bypass-capacitor tester
Carl Pugh, Pugh Magnetics, Newark, CA
ost circuits use bypass capaci- Q1 and Q2, and associated components. input pulse and produces a pulse with
M tors and can deliver substandard

performance if the capacitors have
poor pulse characteristics. Few if any ar-
A voltage reducer/shaper uses a trimmer
capacitor, C1; a 100-pF capacitor, C2; and
a 200V resistor, R1. An amplifier uses a
fast rise and fall times. The output from
the Q3 drives Q4, causing that transistor
to conduct for approximately 40 nsec.
ticles cover how to test bypass capacitors 2N3906 transistor, Q3, and associated You can obtain interesting results when
for pulse characteristics. The circuit in components, and a power amplifier uses testing capacitors with long leads and
Figure 1 tests these characteristics. It a PN2222A transistor, Q4, and associat- then testing the same capacitors with
charges the capacitor under test through ed components. C1, C2, and R1 produce a short leads, corroborating the universal
100 kV for approximately 1 msec and fast rise- and fall-time, 0.7V pulse when advice to keep leads short.
then discharges it through 10V for ap- the multivibrator’s output switches neg-
proximately 40 nsec. The cycle then re- ative. Because the Q3 transistor has no Is this the best Design Idea in this
peats. The circuit uses a double-sided bias, it conducts only at the peak of the issue? Vote at www.ednmag.com.
copper-clad pc board. All the compo-
nents except the 10V resistor connect to
one side of the board, so they can bene-
fit from shielding by the cast-aluminum
enclosure (Figure 2). All leads are as short
as possible and as close as possible to the
copper-clad board. The layout is such
that you don’t need the oscilloscope
probe’s ground lead; the ground on the
probe contacts a ground post on the pc
board. The ground posts, feedthroughs,
Figure 2
connections to the capacitor under test,
and oscilloscope probes use vector-board
Components all connect to
terminals.
one side of the pc board, and
The circuit comprises an astable mul-
a cast-aluminum cover pro-
tivibrator using two 2N3904 transistors,
vides shielding.
6-32 SCREW
Figure 1 CAST-ALUMINUM ENCLOSURE
FOUR PLACES
20V 20V 20V
20V
20V 20V
2k 71.5k 71.5k
R1 20V 100k
0.01 mF
2k 200 Q3
C1
2N3906
Q1 5.5 TO 30 pF
2N3904 Q4 TO OSCILLOSCOPE
PN2222A 10 DIFFERENTIAL INPUT
0.01 mF Q2 C2
1N4148 2N3904 100 pF
1k
CAPACITOR
1N4148 UNDER TEST
20V 20V
+
0.1 mF 10 mF GROUND
NOTE:
ADJUST TRIMMER CAPACITOR
FOR GOOD WAVESHAPE/AMPLITUDE.
Test the pulse characteristics of bypass capacitors using this simple circuit.

design
ideas
DAC and op amp provide variable-control voltage
Chad Olson, Maxim Integrated Products, Sunnyvale, CA
5V
arly DACs contained standard R-
E
5V IC1
2R ladder networks, and pro- 5V
MAX837
duced a negative output volt- Figure 1 OUT IN
0.1 mF 10 IC1
age. These early DACs, such as the mF MAX837 0.1 mF
0.1 mF 0.1 mF GND
MAX7837/7847 and the MAX523, re-
quire both positive and negative supply IC2
68HC912B32
rails to accommodate their negative out- VDD REF
put. With the transition to single-supply CS CS

ICs, however, many modern DACs oper- IC3 249k 499k
MOSI DIN OUT
MAX541
ate with a single supply rail and an in- 5V
verted R-2R ladder network. The invert- SCK SCLK
0.1 mF
5
ed R-2R network produces a positive DGND AGND
2
output voltage. Despite the popularity of IC4
MAX4162
single-supply ICs, some applications still + 2
require a negative control voltage. Figure
0.1 mF
1 shows a circuit that satisfies this re-
quirement. The circuit contains a mod- 15V
ern, inverted R-2R ladder DAC and one
op amp. In comparison with older DACs This compact circuit allows microcontroller IC2 to generate a variable negative voltage.
LISTING 1—TRIANGLE-WAVE GENERATOR

design
ideas
containing standard R-2R ladders, this from 0 to 2.5V. Op amp IC4 inverts and the listing from the Web version of this
approach offers lower supply voltages, amplifies this output to produce a 0 to article at www.ednmag.com.
higher speed, and smaller packages. The 25V output. For test purposes, the soft-
DAC, IC3, operating with a 2.5V reference ware routine in Listing 1 commands the
voltage from IC1 and driven by micro- microcontroller to generate a 0 to 25V Is this the best Design Idea in this
controller IC2, produces an output swing triangle-wave output. You can download issue? Vote at www.ednmag.com.
Logic offers complementary-switch control

Yen-Hsu Chen, Analog Integrations Corp, Hsinchu, Taiwan
he complementary-switch con- can program the delay times. The delay kV because of the limited current avail-
T troller in Figure 1 uses a few invert- can be as short as 50 nsec and as long as able from the inverter IC.
er gates to provide drive signals for several milliseconds. This range provides
the complementary switches. Comple- flexible, optimized control for target de- Is this the best Design Idea in this
mentary-switch configurations find vices. R1 and R2 should be larger than 2 issue? Vote at www.ednmag.com.
widespread use in synchronous-rectifi-
D1
cation circuits, charge pumps, full-bridge 1N5819
control circuits, and other cir-
Figure 1
cuits. The circuit in Figure 1 pro-
vides not only a complementary drive 3
IC1B 4 B
signal but also a deadtime delay on both R1
rising and falling edges. The high-speed C1
1 IC1A
inverter gates use IC1, a 74HC04 CMOS A A
D2
circuit, and 1N5819 Schottky diodes D1 1N5819
and D2. The 74HC04 inverter features C
symmetrical input thresholds,VIHMIN and
VILMAX, at 70 and 30% of the supply volt- R2
5 6
IC1C
age, respectively. In Figure 1, IC1A inverts
the signal at Node A to produce A. When
C2
A rises, C1 rapidly charges through D1. 9 IC1D 8
C
Output B drops immediately because of SN74HC04
IC1B’s inversion. However, Output C
drops after a delay time that R2 and C2 This circuit provides drive for complementary switches with programmable deadtimes.
determine because D2 is reverse-biased.
The following formula gives the delay
time, t1 (Figure 2):
A
0.7 VDD
t1 = 1R 2C 2 ln = 1R 2C2 ln 0.7.
VDD
When A falls, C1 discharges through
R1. Output B rises after a delay A
time that R1 and C1 determine. C2 Figure 2
B
discharges rapidly through D2, and out- t2
put C rises immediately. The following
formula gives the delay time, t2:
C
V 10.3 VDD t1
t 2 = 1R1C1 ln DD =
VDD
1R1C1 ln 0.7.
C
By inverting C, IC1D can provide C a
signal with the same polarity as B. By se-
lecting values for R1, C1, R2, and C2, you By manipulating the resistor and capacitor values in Figure 1, you can program t1 and t2.

design
ideas
Circuit measures currents in dc servo motor
Shyam Tiwari, Sensors Technology Private Ltd, Gwalior, India
he simple circuit design in Figure
T
2 TO 30V DC
1 lets you measure all com-
ponents of a current flowing Figure 1
in a dc servo motor. The rectified output
of the circuit uses ground as a reference,
so you can measure the output by using R1
a single-ended A/D converter. The cur- 0.1 H-BRIDGE AND
rent-sense resistor, R1, has a value of + M 2 DRIVER CIRCUIT
0.1V. The Zetex (www.zetex.com) DC

4 5 4 5 MOTOR
ZXCT1010 IC converts the differential ZXCT1010
ZXCT1010
signal across R1 to a single-ended signal. SENSED V+
3 3
Two of these ICs form a signal rectifier. OUTPUT

VOLTAGE V2 100
The single-ended signal makes measure-
ment by an A/D converter cost-effective,
small, and frugal in power consumption. With this simple circuit, you can measure the currents in a dc servo motor.
The method also makes it possible to
measure current from many sources at a bit A/D converter suffices to digitize the nent. The unfiltered signal has 300-kHz
time, such as in robots that use multiple signal. If an average value of the current response to ac current.
servo motors. Measurement accuracy is is of interest, then you can place an av-
approximately 63%, which is adequate eraging capacitor between the V1 and Is this the best Design Idea in this
in most dynamic systems. Hence, an 8- V2 terminals to remove the ac compo- issue? Vote at www.ednmag.com.

design
ideas
Analog switch lowers relay power consumption
Steve Caldwell, Maxim Integrated Products, Chandler, AZ
esigners often use relays as elec-
D trically controlled switches.

Unlike transistors, their
switch contacts are electrically isolated
Figure 1 2.5V
S1
from the control input. However, the
power dissipation in a relay coil may ren- D1
der the device unattractive in battery-
+
powered applications. You can lower this C1
100 F
dissipation by adding an analog switch 2
6
that allows the relay to operate at a low- R2 5
er voltage (Figure 1). The power that a re- 27k
4
lay consumes equals V2/RCOIL. The circuit IC1
1
lowers this dissipation after actuation by
applying less than the normal 5V oper- R1
+ MAX4624
C2 4.7
ating voltage. Note that the voltage re- 0.15 F 3
quired to turn a relay on the pickup volt-
age is greater than the pickup voltage
required to keep in on the dropout volt-
age. The relay in Figure 1 has a 3.5V By using an analog switch, you can reduce a relay’s power consumption.
pickup voltage and a 1.5V dropout volt-
age. The circuit allows the re- low enough to allow C1 to
lay to operate from an inter-
TABLE 1—RELAY POWER DISSIPATION charge rapidly but high
Voltage Current Total power dissipation
mediate supply voltage of (V) (mA) (mW) enough to prevent the surge
2.5V. Table 1 compares the re- 5 (normal operating voltage) 90 450 current from exceeding the
lay’s power dissipation with 3.5 (pickup voltage) 63 221 peak current specified for the
the fixed operating voltages 2.5 (circuit of Figure 1) 45 112 analog switch.
applied and with the circuit in IC1’s peak current is 400
Figure 1 in place. voltage. The RC time constants are such mA, and the peak surge current is
When you close S1, current flows in the that C1 charges almost completely before IPEAK(VIN VD1)/(R1 RON), where RON
relay coil, and C1 and C2 begin to charge. the voltage across C2 reaches the logic is the on-resistance of the analog switch
edn01121di2809
The relay remains inactive because the threshold of the analog switch. When C2 (typically 1.2). The value of C1 depends
supply voltage is lower than the pickup reaches that threshold, the analog switch on the relay characteristics and on the
Heather
connects C1 in series with the 2.5V sup- difference between VIN and the relay’s
ply and the relay coil. This action turns pickup voltage. Relays that need more
Analog switch lowers the relay on by boosting the voltage turn-on energy need larger values of C1.
relay power consumption ............................57 across its coil to 5V, which is twice the You select the values for R2 and C2 to al-
Analog-input circuit serves supply voltage. As C1 discharges through low C1 to charge almost completely be-
any microcontroller........................................58 the coil, the coil voltage drops back to fore C2’s voltage reaches the threshold of
2.5V minus the drop across D1, but the the analog switch. In this example, the
Transistor tester fits into your pocket ........60 relay remains on because its coil voltage time constant R2C2 is approximately sev-
Circuit combines power supply is above the relay’s 1.5V dropout voltage. en times (R1RON)C1. Larger R2C2 values
and audio amplifier ......................................62 Component values for this circuit de- increase the delay between switch closure
Supply derives 5 and 3.3V
pend on the relay characteristics and the and relay activation.
from USB port ................................................62
supply voltage. The value of R1, which
protects the analog switch from the ini- Is this the best Design Idea in this
tial current surge through C1, should be issue? Vote at www.ednmag.com.
www.ednmag.com December 20, 2001 | edn 57
design
ideas
Analog-input circuit serves any microcontroller
Steven Hageman, Agilent Technologies, Santa Rosa, CA
he simple ADC in Figure 1 is per-
T fect for getting analog signals into a

purely digital microcontroller. Using
just five surface-mount parts, you can 5 3
assemble it for less than 50

cents (1000), which is ap- Figure 1 Q3 Q4 XN02401
RAMP OUTPUT
proximately half the cost of a single- 100k
chip-ADC approach in the same vol- 1 4 2 TO MICRO-
PROCESSOR
ume. Moreover, this design takes only GENERAL-
1
one pin from the microcontroller to op- PURPOSE-
C1 I/O PIN
erate. Although you can purchase many 5 0.1 F
Q2
microcontrollers with built-in ADCs, in 3
some circumstances, this solution is im- A
VIN
practical. For example, you might have 0 TO 4V 2 6
Q1
an all-digital microcontroller already de- DC R1
signed in. In this design, a USB-com- 100k
patible, digital-only microcontroller 4 XN04601

needed analog input at low cost for a A A
consumer application. The basic analog
portion of the circuit in Figure 1 uses With two transistor arrays and three discrete components, you can configure an analog front end
clever transistor arrays from Panasonic for a microcontroller.
(www.panasonic.com). Q1/Q2 and Q3/Q4
are single-package, multiple-transistor The basic operations are as follows: C1VL
K = VIN ,
arrays. The Q1/Q2 array forms a voltage- 1. Set the ADC pin as a low output to dT
to-current converter. The voltage on Q1’s discharge C1. where VL is the voltage level of the mi-
emitter is a diode drop higher than the 2. Reset a suitable timer-counter in the crocontroller’s zero-to-one conversion, K
voltage on Q1’s base. The VBE drop in Q2 microcontroller. is the scaling factor that relates to the
returns the original input voltage to the 3. Set the ADC pin as an input. voltage-to-current conversion of the in-
top of R1; R1 then converts that voltage 4. Allow the timer to count until it put stage and timer resolution, and dT is
to a current. reads as logic 1 in the microcon- the time count of the conversion cycle.
The Q3/Q4 array forms a standard cur- troller, or let the timer count to some Because C1VL is also a constant for a giv-
rent-mirror circuit. The current flowing suitably long value, which suggests en circuit, you can combine it with K to
in Q3’s collector matches the current that the input is essentially zero. form a single conversion constant of K1.
forced in Q4’s collector.Q4’s collector has 5. Stop the timer counter. Hence, you can reduce the equation to
high impedance, so Q4 provides a suitable 6. Convert to the timer count by some K1/dTVIN.
current source. The current from Q4 suitable scaling factor to an ADC In this case, the test code was written
charges C1 at a rate that is proportional reading. for Microchip Technology’s (www.mi-
to the input voltage. The values in Fig- 7. Start over for the next conversion. crochip.com) PIC16F84 microcontroller.
ure 1 allow for a range of conversion The conversion from the ramp time to This device has a measured VL of 1.28V;
times of 3 msec for an input of 4V to 56 a logic 1 on the microcontroller pin de- the counter has a resolution of 1 sec. It’s
msec for an input of 0.1V. The design ex- pends on the following factors: probably best to empirically determine
ploits the fact that most general-purpose ● the logic-1 switching level of your the factor K1. Set up the counter resolu-
microcontrollers have a bidirectional microcontroller; tion as desired, allow the microcontroller
I/O-port structure. That is, you can pro- ● the input voltage and, hence, the to make and display that conversion time
gram a port pin as either an input or an ramp rate of C1; or send it through a debugger, and, giv-
output. When you set a pin as an input, ● the value of C1, which sets the ramp en that you have an exact VIN, K1 is then
it has very high input impedance, so it rate; easy to determine. In this case, K1 turned
can follow the ramp as C1 charges up. ● the value of R2, which sets the ramp out to be 2V5700 sec11,400.
When you program a pin as an output, rate; and The constant K1 serves to convert the
you can set it low, and it discharges C1 for ● the microcontroller’s timer reso- raw timer count to a voltage. To obtain
the next conversion cycle. This action lution. high resolution, you normally use float-
gives you the basic operation of a single- You can boil down these variables to ing-point math. If you need to display the
slope analog-to-digital-conversion cycle. the following equation: value, floating-point math might be ap-

design
ideas
propriate, but most applications entail sentation (0 to 255) for an input range proximately 5% with no adjustments.
reading a potentiometer or some other of 0 to 4V. If you scale the timer/counter The resolution is a function of the timer
system level. In such applications, the by 64, instead of a count of 5700 sec for resolution and how tight the code makes
output is a bar-chart display or some an input of 2V, you obtain 89. Then, if the conversion loop. The resolution can
control value. Thus, you waste micro- you want this 89 to correspond to a half- be many times the absolute accuracy.
controller resources by using floating- scale value of 128, the value of K1 be- Moreover, the converter is monotonic.
point math throughout the conversion comes 11,392. A 16-bit unsigned word
process. With careful selection of circuit easily accommodates this value, and you
components, fixed-point math can usu- need no floating-point math in the con- Is this the best Design Idea in this
ally provide, for example, an 8-bit repre- version. The accuracy of this ADC is ap- issue? Vote at www.ednmag.com.
Transistor tester fits into your pocket

Jean-Bernard Guiot, DCS AG, Allschwil, Switzerland
t can be helpful to rapidly TABLE 1—TESTING RESULTS entire circuit inside a small
I and easily determine the po-

larity (npn or pnp) and func-
tion of a transistor. The pocket-
Test D1 D2 S1 Comments
1
2
On Off Off Wrong connection? Invert C and B.
Off On Off Wrong connection? Invert C and B.
housing, such as one measuring
203060 mm. You can effect
the external connections to the
transistor tester in Figure 1 is device under test with wires ter-
3 Off Off Off Device under test shorted (bad).
ideal for quickly testing without minated in alligator clips or by
4 On On Off Device under test is OK if test 5 or 6 is OK.
regard to such parameters as using a connector. It is practical
5 On Off On Device under test is pnp.
gain and frequency response. and economical to use a five-
6 Off On On Device under test is npn.
You connect the transistor, or pole DIN plug with the pinout
device under test, between the collectors, direction, then only one LED turns off. If shown in Figure 2a. This pinout allows
T, of an astable multivibrator. Thus, the the device conducts in both directions, you to easily connect any transistor, re-
VCE voltage of the device under test is al- then both LEDs turn off. You can leave gardless of the arrangement of the CBE
ternately positive and negative. Two the base of the device unconnected to connections. Figure 2b shows the S1
LEDs connected in an antiparallel con- check for excessive leakage current or switch connections. S1 is a DPDT switch
figuration to the device alternately light short circuits between base and collec- with three positions:
as long as the device is not conducting. tor or base and emitter. Using the switch, ● Position 1 is On, with no base cur-
The frequency of the multivibrator is a S1, you can connect the base to the col- rent (S1 open).
function of the values of C and RB. If the lector to inject current into the base of ● Position 2 is Off (middle position).
device under test conducts in only one the device under test. Table 1 sums up ● Position 3 is On, with base current
9V
the behavior of the tester. (S1 closed).
You can also test diodes
connected between C and E,
RC RB RB RC
FETs, small thyristors, and Is this the best Design Idea in this
DEVICE UNDER triacs. You can mount the issue? Vote at www.ednmag.com.
TEST
C E
TO C OF DEVICE
B TO BATTERY UNDER TEST
Figure 2
Figure 1 S1 RT
1 2 3 1 2 3
T C C T C
E
B
0V C
E
NOTES:
TRANSISTORS (T) ARE BC108, BC547, 2N3904, 2N2222...
CAPACITORS (C) ARE 100 nF. TO CIRCUIT TO RT
RC=470, RB=39 k AND RT=3.9 k.
LEDs ARE PREFERABLY RED. (a) (b)
This simple tester allows you to test the polarity and function of a A DIN connector (a) allows you to easily connect transistors; a DPDT switch
transistor. provides various testing options (b).

design
ideas
Circuit combines power supply and audio amplifier
Susanne Nell, Breitenfurt, Austria
he circuit in Figure 1 can help if
T
110 OR 220V AC
MAIN SUPPLY
you must transfer dc power and au- 36V DC
1 BRIDGE 24V DC
dio over a pair of copper wires. One IC1 470 F
2 +4
application for such a circuit is a low-cost 1 VIN LM317
VOUT
2 +
+ C1
door-opening system with speech input. T2 ADJ
15 F
1
TRANSFORMER LOAD 2
The circuit uses only one IC, the well- 3
+
680 F 150
known LM317, a low-cost power- 2 LOUDSPEAKER
Figure 1 1
supply regulator. Using this chip,
RP WM34
you can modulate the adjustment-pin in- 100k ELECTRET
put with the audio signal from an electret MICROPHONE
condenser microphone, connected be-

tween the output and the adjustment ter- A novel circuit uses the adjustment pin of a regulator IC to provide audio amplification.
minals of the IC. The LM317 regulates
the output in such a way that the voltage must follow the voltage on RP, you obtain the microphone signal. For proper oper-
on the microphone is always 1.25V dc. a low-impedance audio signal riding on ation, the LM317 needs to deliver a min-
This application uses a WM34 electret the output dc voltage. imum current of 4 mA from its output
microphone, which comes in a standard The microphone directly modulates terminal. If your design uses no loud-
10-mm capsule from Panasonic and is the adjustment pin, so a smoothing ca- speaker, you can connect a load resistor
common in low-cost equipment. You can pacitor, such as C1, for noise and hum to sink this 4 mA. Designs using low-im-
use nearly any electret capsule, because does not influence the level of the audio pedance loudspeakers must also have
the well-regulated voltage on the micro- signal. C1 shunts some of the audio sig- load resistors. You must add the ac cur-
phone never exceeds 1.25V. Every electret nal to ground, but the LM317 compen- rent in the audio signal to the minimum
capsule contains an integrated JFET- sates for the loss with internal gain. To current requirement of 4 mA. For an 8
based impedance converter that trans- avoid excessive losses in the LM317, use loudspeaker, you need a minimum resis-
lates speech into a current flowing from a capacitor with as low a value as possi- tive load of 470 to avoid distortion.
the source to the drain terminal. This ble. The circuit works well without a ca-
current through the microphone modu- pacitor, but values as high as 47 F do not
lates the voltage on the variable resistor, present a problem. Using RP, you can ad- Is this the best Design Idea in this
R . Because the output of the LM317 just the dc output voltage and the gain for issue? Vote at www.ednmag.com.
P
Supply derives 5 and 3.3V from USB port

Chad Olson, Maxim Integrated Products, Sunnyvale, CA
he circuit in Figure 1 derives its high or low configures the chip for charging the low-battery output, LBO, to shut-
T power from a USB port and produces

5 and 3.3V supply rails for portable
devices, such as digital cameras, MP3
ing a 4.2 or 4.1V battery, respectively. To
protect the battery, IC1’s final charging
voltage has 0.5% accuracy. The CHG ter-
down, SHDN, causes IC2 to disconnect its
load in response to a low battery voltage.
The internal source impedance of a lithi-
players, and PDAs. The circuit allows the minal allows the chip to illuminate an um-ion battery makes IC2 susceptible to
port to maintain communications while, LED during charging. oscillation when its low-battery-detec-
for example, charging a lithium-ion bat- IC2 is a step-up dc/dc converter that tion circuitry disconnects a low-voltage
tery. IC2 boosts the battery voltage, VBATT, boosts VBATT to 5V and delivers currents battery from its load. As the voltage drop
to 5V, and IC3 buck-regulates that 5V as high as 450 mA. Its low-battery detec- across the battery’s internal resistance
output down to 3.3V. IC1, a lithium-ion tion circuitry and true shutdown capa- disappears, the battery voltage increases
battery charger, draws power from the bility protect the lithium-ion battery. By and turns IC2 back on. For example, a
USB port to charge the battery. Pulling its disconnecting the battery from the out- lithium-ion battery with 500-m inter-
SELI terminal low sets the charging cur- put, “true shutdown” limits battery cur- nal resistance, sourcing 500 mA, has a
rent to 100 mA for low-power USB ports, rent to less than 2 A. An external resis- 250-mV drop across its internal resist-
and pulling SELI high sets 500 mA for tive divider between VBATT and ground ance. When IC2’s circuitry disconnects
high-power ports. Similarly, pulling SELV sets the low-battery trip point. Connect- the load, forcing the battery current to
design
ideas VBUS
1
IN BATT
VBATT
2 4.7 F 2.2 F LITHIUM-ION

D USB SELV
316 IC1 GND BATTERY
CONNECTOR
MAX1811
zero, the battery voltage immediately in- D+
3
EN
4
creases by 250 mV. GND SELI
500 mA
The n-channel FET at LBO Figure 1 CHARGING

CHG 100 mA
10k
LED
eliminates this oscillation by adding hys-
teresis to the low-battery-detection cir- VBATT 5V
cuitry. The circuit in Figure 1 has a low- 22 H
BATT OUT
LX
battery trip voltage of 2.9V. When VBATT + +
R1 47 F 0.1 F
drops below 2.9V, LBO opens and allows 604k 47 F
GND
SHDN to switch high, turning on the 100k LBI
R2 R3 IC2
FET. With the FET turned on, the paral- 249k 1.3M MAX1747
lel combination of 1.3 M and 249 k FB
eliminates oscillation by setting the bat- LBO
tery turn-on voltage to 3.3V. The turn-

off and turn-on points are according to SHDN
the following equations: 5V

3.3V
IN
R1 + R 2 OUT
22 H
VBATT (TURN − OFF) = VLBI × , SHDN LX
R2 10 F IC3 +
MAX1837 150 F
FB
GND
where VLBI0.85V, and
R1 + R ′2 Drawing power from a USB port, this circuit generates 5 and 3.3V supply voltages for portable
VBATT (TURN − ON) = VLBI × ,
R ′2 applications.
where Finally, a step-down converter, IC3, Is this the best Design Idea in this
R 2R 3 provides buck regulation to convert 5V issue? Vote at www.ednmag.com.
R 2′ = . to 3.3V and delivers currents as high as
R2 + R3 250 mA with efficiency exceeding 90%.

EDN Design Ideas 2001

Uploaded by

Copyright:

Available Formats

You might also like

EDN Design Ideas 2001

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

EDN Design Ideas 2001

Uploaded by

Copyright:

Available Formats

design

Edited by Bill Travis and Anne Watson Swager

strike potential reduces to half.

charge toward VCC. IC1D’s low output +

This trigger circuit generates a high-frequency-pulse series to strike a preheated lamp.

www.ednmag.com January 4, 2001 | edn 113

W supplies, you must usually replace

114 edn | January 4, 2001 www.ednmag.com

Circuit yields ultralow-noise VGA

A able-gain amplifiers are available to-

116 edn | January 4, 2001 www.ednmag.com

GND VCC IC2 + 10 mF

An ADC controls the gain-setting codes for the circuit in Figure 1.

118 edn | January 4, 2001 www.ednmag.com

Sequential channel selector simplifies software

A is useful for a variety of applications

120 edn | January 4, 2001 www.ednmag.com

Negative-going transitions increment the counter at counts 1, 2, and 3.

T based programmable timer with two

An MC68HC11 mC provides flexible timing functions.

124 edn | January 4, 2001 www.ednmag.com

With an internal error amplifier that

works as a peak-current PWM controller, 18k

combining fixed-frequency operation at

The input-voltage rejection stays within 1V from 130 to 260V ac.

www.ednmag.com January 18, 2001 | edn 143

Four-way remote control uses series transmission

ity constraints and uses a

You can use this system as

the total transmission time

parallel to serial. The data

144 edn | January 18, 2001 www.ednmag.com

146 edn | January 18, 2001 www.ednmag.com

D7 TO D9 9-BIT DATA PACKET

RECEIVED DATA KEEP EMISSION ALIVE

VALID-TRANS THREE IDENTICAL DATA

RX_OK '70 mSEC

LOGIC LEVEL FOR

HIGH INPUT LEVEL: DATA IS ENABLED TIME

148 edn | January 18, 2001 www.ednmag.com

Analyze LED characteristics with PSpice

R ogy have lead to LEDs’ widespread characteristics of

IFWD=ISz(eV /NzV 21).

150 edn | January 18, 2001 www.ednmag.com

510V reveal a stan-

Programmable-gain amplifier is low-cost

N gain amplifiers are avail-

152 edn | January 18, 2001 www.ednmag.com

Y itors to keep a close eye on power-

A PC hardware-monitor IC can also monitor weather-station characteristics.

154 edn | January 18, 2001 www.ednmag.com

To: Design Ideas Editor, EDN Magazine

Entry blank must accompany all entries. (A separate entry

Your vote determines this issue’s winner. Vote now at

156 edn | January 18, 2001 www.ednmag.com

With an internal error amplifier that

works as a peak-current PWM controller, 18k

combining fixed-frequency operation at

The input-voltage rejection stays within 1V from 130 to 260V ac.