Microprocessor

● Aryan Thapliyal (21HCS4124)

● Ayush Karn (21HCS4129)
● Drishti Singh (21HCS4199)
● Shivansh Shukla (21HCS4181)
● Vaibhav Dubey (21HCS4189)
● Yash Bhatt (21HCS4194)
 What is a processor?
Control Unit

Input ALU Output

Memory Unit

A processor is an integrated electronic circuit that performs the

calculations that run a computer. A processor performs
arithmetical, logical, input/output (I/O) and other basic instructions
that are passed from an operating system.
 Micro Processor
Control Unit

Input ALU Output

Memory Unit

A micro processor is a compact processor with small sized

transistors.
 What is a register?
A processor register is a quickly accessible location available to a
computer's processor.

All CPU operations are performed on registers.

Speed Comparison:
Secondary Storage < Primary Storage(RAM) < cache < Registers
Internal microprocessor architecture
● Before a program is written or any instruction investigated, the internal
configuration of the microprocessor must be known.
● In a multiple core microprocessor each core contains the same programming
model, where each core runs a separate task or thread simultaneously.
● The programming model of 8086 through Core-2 is considered program visible
● These registers are used during programming and are specified by the
instructions.
● Other registers considered to be program invisible
● They are not addressable directly during applications programming but may be
used indirectly in system programming.
Types of registers

1.Multipurpose Registers- General purpose registers are extra registers that are
present in the CPU and are utilized anytime data or a memory location is
required. These registers are used for storing operands and pointers.

2.Special Purpose Registers-To store machine state data and change state
configuration, special purpose registers are employed. In other words, these can
also be defined as registers that are used to carry out instruction execution. The
special-purpose registers include RIP, RSP, and RFLAGS.

3.Segment Registers- These generate memory addresses when combined with

other registers in the microprocessor. There are either four or six segment
registers in various versions of the microprocessor.
Programming Model
Multipurpose Registers
RAX (accumulator) :
RAX is referenced as a 64-bit register (RAX),
32-bit register(EAX),
16-bit register (AX), or
as either of two 8-bit registers (AH and AL).
The accumulator is used for instructions such as multiplication, division, and some of
the adjustment instructions.
In the 64-bit Pentium 4 and Core2, RAX holds a 64-bit offset address, which allows 1
terabyte of memory to be accessed through a 40-bit address bus.
In the future, Intel plans to expand the address bus to 52 bits to address 4P (peta)
bytes of memory.
RBX (base index):
RBX , addressable as RBX, EBX, BX, BH, or BL.
The BX register (base index) sometimes holds the offset address of a location in the memory
system in all versions of the microprocessor.
In the 80386 and above, EBX also can address memory data.
In the 64-bit Pentium 4 and Core2, RBX can also address memory data.

RCX (count):
RCX addressable as RCX, ECX, CX, CH, or CL,.
It is a general-purpose register that also holds the count for various instructions.
In the 80386 and above, the ECX register also can hold the offset address of memory data.
In the 64-bit Pentium 4, RCX can also address memory data.
Instructions that use a count are the repeated string instructions (REP/REPE/REPNE); and shift,
rotate, and LOOP/LOOPD instructions.
RDX (data) :
RDX is addressable as RDX, EDX, DX, DH, or DL,.
It is a general-purpose register that holds a part of the result from a
multiplication or part of the dividend before a division.
In the 80386 and above, this register can also address memory data.
RBP(base pointer) :
RBP is addressable as RBP, EBP, or BP.
It points to a memory location in all versions of the microprocessor for
memory data transfers.
RDI (destination index) :
RDI, which is addressable as RDI, EDI, or DI.
It addresses string destination data for the string instructions.
RSI (source index):
RSI is used as RSI, ESI, or SI.

The source index register often addresses source string data for the string instructions.

RSI also functions as a general-purpose register.

As a 16-bit register, it is addressed as SI;

As a 32-bit register, it is addressed as ESI; and

As a 64-bit register, it is addressed as RSI.

R8 through R15 :
These registers are only found in the Pentium 4 and Core2 if 64-bit extensions are enabled.

Older software does not use these registers and most applications will not use these until
64-bit processors are common.
SPECIAL PURPOSE REGISTERS

● RIP ( Instruction Pointer )

I. RIP addresses the next instruction in a section of memory
defined as code segment.
II. This register is IP (16 bits) when the microprocessor operates
in real mode.
III. EIP(32 bits) when the 80386 and above operate in the
protected mode.
● RSP( Stack Pointer)
I. RSP addresses an area of memory called the stack. The stack
memory stores data through this pointer.
II. This register is referred to as SP if used as a 16-bit register and
ESP if referred to as a 32 bit register.
● RFLAGS
I. RFLAGS indicate the condition of the microprocessor and
control its operation.
II. The 8086-80286 contain a FLAG register (16 bits) and the
80386 and above contain an EFLAG register (32-bit
extended flag register)
 RFlags
● C (Carry)
○ Carry holds the carry after addition or the borrow after subtraction.
○ Sometimes for DOS function calls the carry flag also indicates error
conditions.
● P (Parity)
○ Parity is a logic 0 for odd parity and a logic 1 for even parity.
○ Parity is the count of ones in a number expressed as even or odd.
● A (auxiliary carry)
○ The auxiliary carry holds the carry (half-carry) after addition or the borrow
after subtraction between bit positions 3 and 4 of the result.
● Z ( Zero )
○ The zero flag shows that the result of an arithmetic or logic operation is
zero.
○ If, Z = 1, the result is zero; if Z = 0, the result is not zero.
● S ( Sign )
○ The sign flag holds the arithmetic sign of the result after an arithmetic or
logic instruction executes.
○ If S = 1, the sign bit (leftmost bit of a number) is set or negative; if S = 0, the
sign bit is cleared or positive.
● T ( trap )
○ The trap flag enables trapping through an on-chip debugging feature.
○ If the T flag is enabled (1), the microprocessor interrupts the flow of the
program on conditions as indicated by the debug registers and control
registers.
○ If the T flag is a logic 0, the trapping ( debugging ) feature is disabled.
○ The Visual C++ debugging tool uses the trap feature and debug registers to
debug faulty software.
● I ( Interrupt )
○ The interrupt flag controls the operation of the INTR ( interrupt request) input pin.
○ If I = 1, the INTR pin is enabled; if I = 0, the INTR pin is disabled.
○ The state of the I flag bit is controlled by the STI (set I flag) and CLI ( clear I flag )
instructions.

● D ( direction )
○ The direction flag selects either the increment or decrement mode.
○ If D = 1, the registers are automatically decremented; if D = 0, the registers are
automatically incremented.\
○ The D flag is set with the STD (set direction) and cleared with the CLD ( clear
direction) instructions.
● O (overflow)
○ Overflows occur when signed numbers are added or subtracted.
○ An overflow indicates that the result has exceeded the capacity of the machine.
○ For unsigned operations, the overflow flag is ignored.

● IOPL (I/O privilege level)

○ IOPL is used in protected mode operation to select the privilege level for I/O devices.
○ If the current privilege level is higher or more trusted than the IOPL, I/O executes without hindrance.
○ If the IOPL is lower than the current privilege level, an interrupt occurs, causing execution to suspend.
○ An IOPL of 00 is the highest or most trusted and an IOPL of 11 is the lowest or least trusted.
● NT (nested task)
○ The nested task flag indicates that the current task is nested within another task in
protected mode operation.

● RF (resume)
○ The resume flag is used with debugging to control the resumption of execution after
the next instruction.

● VM (virtual mode)
○ The VM flag bit selects virtual mode operation in a protected mode system.
○ A virtual mode system allows multiple DOS memory partitions that are 1M byte in
length to coexist in the memory system.
● VIF (virtual interrupt) :
○ The VIF is a copy of the interrupt flag bit available to the
Pentium–Pentium 4 microprocessors.

● AC (alignment check) :
○ The alignment check flag bit activates if a word or doubleword is
addressed on a non-word or non-doubleword boundary.
○ Only the 80486SX microprocessor contains the alignment check bit.
● VIP (Virtual Pending Interrupt):
○ VIP provides information about a virtual mode interrupt for the
Pentium–Pentium 4 microprocessors.
○ This is used in multitasking environments to provide the operating system
with virtual interrupt flags and interrupt pending information.

● ID (identification) :
○ The ID flag indicates that the Pentium–Pentium 4 microprocessors support
the CPUID instruction.
○ The CPUID instruction provides the system with information about the
Pentium microprocessor, such as its version number and manufacturer.
 SEGMENT REGISTERS

These additional registers, generate memory addresses when combined

with other registers in the microprocessor.
● CS (Code Segment) - It is used for addressing memory location in the code
segment of the memory, where the executable program is stored.
● DS (Data Segment) - It points to the data segment of the memory where
the data is stored.
● ES (Extra Segment) - It also refers to a segment in the memory which is
another data segment in the memory.
● SS (Stack Segment) - It is used for addressing stack segment of the
memory. The stack segment is that segment of memory which is used to
store stack data.
● FS and GS
○ The FS and GS segments are supplemental segment registers
available in the 80386–Core2 microprocessors.
Paging in Microprocessor 80386
What is Paging ?
The memory paging mechanism located within the 80386 microprocessor and
above allows any physical memory location to be assigned to any linear address.

By paging we convert linear address to physical address.

However paging is not a necessary mechanism for the 80386 microprocessor. It

can be enabled and disabled as per the will of the user using the control registers
which are discussed ahead.
When paging technique is used for memory management, the paging unit takes
the output of the segmentation unit, which is called the linear address, and
subsequently converts the linear address into a physical address. If paging is not
in use, the linear address simply maps directly onto the physical address.
Linear Address -

A linear address is a 32-bit address in the processor’s linear address space. Just
like the physical address space, the linear address space is also a flat memory
model and it is unsegmented. The linear address space consists of all the
segments and system tables which are used to define a system.

Basically , Linear Address is the address generated by a system program.

Physical Address -
Physical Address is the actual memory location accessed by a system program.

In protected mode, the 32-bit 80386 microprocessor provide a usual physical

address space of 232 bytes or 4 Gbytes. Therefore, the processor can address up
to 4 Gbytes memory locations through its address bus.
Why Paging ?
The major objectives of using the paging memory management technique are as
follows -

1. Address Translation
2. Protection
3. Demand Paging
Control Registers -
The paging unit is controlled by the contents of the microprocessor’s control
registers.
There are four control registers labelled CR0 to CR3 in the microprocessor 80386.
Size of each control register is 32 bits.
They are only available in the protection mode of 80386 microprocessor.
Structure of the Control Registers -
The structure of the control registers is given below -
1. Protection Enable (PE) -

All the control registers are available only if the PE bit is set to 1. This
indicates that the microprocessor 80386 is in protection mode.

2. Math Coprocessor (MP) -

If MP is set to 1 then Math Coprocessor is available. It is used to execute

instructions like floating point instructions.

3. Emulate Coprocessor (EM) -

This bit is made 1 in absence of Math Coprocessor so that if coprocessor

instruction is encountered then it will be executed by a chip emulator. If
MP=0 and EM=0 then error is encountered on coprocessor instruction.
4. Task Switch (TS) -

This bit is made 1 to indicate task switch is performed by the 80386

microprocessor.

5. Extension Type (ET) -

If ET = 1 then 80387 Math Coprocessor is in use. If ET = 0 then 80287 Math

Coprocessor is in use.

6. Paging Enabled (PG) -

If PG = 1 then paging is enabled. By segmentation we convert logical address to

linear address and by paging we convert Linear address to physical address. If
PG=0 then linear address will be physical address.
Real Mode Memory Addressing
What is Real Mode Memory Addressing ?
● Real mode is a memory-addressing scheme and operating state for
computer microprocessors. In real mode, the memory that can be accessed
by a program — usually random access memory (RAM) — is not managed or
buffered in any way by the hardware, software or basic input and output
services (BIOS).

● Real mode operation allows the microprocessor to address only the first 1M
byte of memory space—even if it is the Pentium 4 or Core 2 microprocessor.
● The first 1 Megabyte of memory is called the real memory, conventional
memory, or DOS memory.

● DOS operating system requires that the microprocessor operates in the real
mode.

● Windows operating system does not use the Real mode .

Which microprocessors use ?
● The microprocessor 80286 and above operate in either the real or protected
mode.

● Only the 8086 and 8088 operate exclusively in the real mode.

● In the 64-bit operation mode of the Pentium 4 and Core 2, there is no real
mode operation, hence it cannot execute real mode applications; hence,
DOS applications will not execute in the 64-bit mode unless a program that
emulates DOS is written for the 64-bit mode.
Segments and Offsets
● A combination of a segment address and an offset address accesses a memory location in
the real mode.

● Segment Address - The segment address, located within one of the segment registers,
defines the beginning address of any memory segment.

● Segments in the real mode always have a length of 64K bytes.

● Offset Address - The offset address selects any location within the 64K byte memory
segment.
The figure below shows the segment plus offset addressing scheme to select a memory location.

The segment register in Figure 2–3 contains 1000H, yet it addresses a starting segment at location
10000H. In the real mode, each segment register is internally appended with a 0H on its rightmost end.
This forms a 20-bit memory address, allowing it to access the start of a segment.
● The segment and offset address is sometimes written as 1000:2000 for a
segment address of 1000H with an offset of 2000H.

● Some addressing modes combine more than one register and an offset
value to form an offset address. When this occurs, the sum of these values
may exceed FFFFH.

● When the F000H and 3000H are added, they form a l6-bit (modulo 16) sum
of 2000H used as the offset address; not 12000H, the true sum. Note that
the carry of 1 ( F000H + 3000H = 12000H) is dropped for this addition to
form the offset address of 2000H. The address is generated as 4000:2000
or 42000H.
Default Segment and Offset Registers
● The microprocessor has a set of rules that apply to segments whenever
memory is addressed. These rules, which apply in the real and protected
mode, define the segment register and offset register combination.

● The code segment register is always used with the instruction pointer to
address the next instruction in a program. This combination is CS:IP
● Another of the default combinations is the stack. Stack data are referenced
through the stack segment at the memory location addressed by either the
stack pointer (SP/ESP) or the pointer (BP/EBP).

● These combinations are referred to as SS:SP (SS:ESP), or SS:BP (SS:EBP).

● Other defaults are shown in the following Table for addressing memory
using any Intel microprocessor.
Protected Mode Memory
Addressing
Kaam wahi, steps nayi
What it does?
● Protects a particular segment from direct access by the
microprocessor
● Allows the processor to address the complete memory (within
and above the first 1M)
How?

Segment Register
selects describes
Selector Descriptor Memory Segment

The segment registers instead of containing segment address, contains a

selector, which selects a descriptor which describes a memory segment.
descriptor - The descriptor contains information about the segment, including
its starting address, length and access rights.
Each descriptor is 8 bytes in length.

selector - Selects one of the descriptor from the two descriptor tables, each
containing 8192 descriptors.

Space required by descriptor table?

8x8192 = 64KB
Descriptor table
The two descriptor tables are:

1. Global Descriptor Table - contains segment definitions that apply to all

programs.

2. Local Descriptor Table - Usually unique to a particular application.

Base - Starting location of memory segment

Limit - Last offset address found in a segment

80286 has a 16 bit limit (216 = 64K), so it can access memory segment of size 1 to
64K bytes.

80386 through Pentium 4 has 20 bit (220 = 1M), so it can access memory segment
of size 1 to 1M bytes (or 4K to 4G bytes, by using G bit)
G - Granularity bit allows a segment length of 4K to 4G bytes in steps of 4K bytes

AV - Available bit, 0 : not available, 1 : available

D - 0 : 16 bit instructions, 1 : 32 bit instructions

Access right byte - controls access to the protected mode segment. This byte
describes how the segment functions in the system.
Example
Base = 10000000H
Limit = 001FFH
G=0
Last address = Base + Limit = 10000000H + 001FFH = 100001FFH

If G = 1 in the same base and limit,

Last address = Base + Limit = 10000000H + 001FFFFFH = 101FFFFFH

As, G=1 means multiplying limit by 4K

Access rights byte
● Controls access to protected mode segment

● If segment goes beyond its limit, program is interrupted by microprocessor

indicating a general protection fault

● Can specify whether a data segment can be written or is write protected

Selector in Segment Register

Selector TI RPL
15 3 2 1 0

RPL - Request privilege level. 00 is highest privilege, 11 is lowest privilege

TI - 0 : Global descriptor table, 1 : Local descriptor table

Selector - Jaisa naam waisa kaam

Program invisible register
These registers are not directly accessed by software.

They are used to access and specify the address of descriptor tables.

GDTR (global descriptor table register) and IDTR (interrupt descriptor table
register) - contain the base address of the descriptor table and its limit.

LDTR (local descriptor table register) - used to load a selector, just like SR

TR(task register) - holds selector, which access a descriptor that defines a task
 Flat
Mode
Memory
Flat Memory Model
● Flat memory model(Linear memory model) refers to a memory addressing
paradigm in which “memory appears to program as a single contiguous
address space.”
● The CPU can directly address all of the available memory locations without
having to resort to any sort of paging and segmentation.
● Flat mode is only available in Pentium 4 and Core 2 that have enabled their
64-bit extension.
 FLAT MODE MEMORY
● No Segmentation - Doesn’t use segment registers.
● Doesn’t select the memory address of a segment using the base and limit in the
descriptor.
● Most used is IA32 compatible mode
● Easier to understand.
● Paging is allowed.
● Little protection.
64- bit Flat Memory Model
FFFFFFFFFF H

Linear Address

00000F0000 00000F0000 H

● 40 bit address
● Represented as 10 hexa-digits

0000000000 H
8086
 KEY Points
● 8085 - Accumulator Based microprocessor
● 8086 - General Purpose Register Based microprocessor

● Concurrency in Fetching, Decoding, and Execution and Pipelining

because of the Instruction Queue(Asynchronous operation of EU and
BIU)

● Full list of differences : 8085 vs 8086

 8086 MicroProcessor
● Intel 8086 was launched in 1978.
● It was the first 16-bit microprocessor.
● This microprocessor had major improvement over the execution
speed of 8085.
● It is available as 40-pin Dual-Inline-Package (DIP).
● + 5V Power Supply
● 8086 has a 20 bit address bus ,that can access upto 220 memory
locations ( 1 MB)
 Bus Interface Unit (BIU)
The function of BIU is to:
● Fetch the instruction or data from memory.
● Write the data to memory.
● Write the data to the port.
● Read data from the port.
To increase the execution speed, BIU fetches as many as six instruction bytes ahead to
time from memory.
All six bytes are then held in first in first out 6 byte register called instruction queue.
Then all bytes have to be given to EU one by one.
This pre fetching operation of BIU may be in parallel with execution operation of EU,
which improves the speed execution of the instruction.
 Execution Unit (EU)
The function of Execution Unit is to:
● To tell BIU where to fetch the instructions or data from.
● To decode the instructions.
● To execute the instructions
The EU contains the control circuitry to perform various internal operations. A decoder
in EU decodes the instruction fetched memory to generate different internal or
external control signals required to perform the operation. EU has 16-bit ALU, which
can perform arithmetic and logical operations on 8-bit as well as 16-bit.
THANK
YOU ● Aryan Thapliyal (21HCS4124)
● Ayush Karn (21HCS4129)
● Drishti Singh (21HCS4199)
● Shivansh Shukla (21HCS4181)
● Vaibhav Dubey (21HCS4189)
● Yash Bhatt (21HCS4194)