DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

ACHARYA INSTITUTE OF TECHNOLOGY

SOLDEVANAHALLI, BENGALURU
LIST OF EXPERIMENTS AND EVALUATION SHEET
Sub: VLSI Lab Code: 18ECL77
Name: Sem/Sec:

Sl. CO1 CO2 CO3 CO4 Total Faculty

No Name of the Experiment (10M) Marks Sign
(10M) (10M) (10M)
(40M)
1a Capture the schematic CMOS Inverter for
different widths of inverter and compute
Propagation delay rise time and fall time
Draw the layout for inverter for Wp/Wn
1b
=40um/20um using optimum layout methods
and verify DRC and LVS extract parasitic
and compute pre layout and post layout
simulation
2a Draw the schematic of 2 input NAND gate
for different strengths X,2X and 4X and
compute Propagation delay rise time and fall
time
2b
Draw the layout for 2 input NAND for
Wp/Wn =40um/20um using optimum layout
methods and verify DRC and LVS extract
parasitic and compute pre layout and post
layout simulation
3a Draw the schematic of common source
amplifier with PMOS mirror circuit and
measure UGB and amplification Factor for
different transistor parameters
3b
Draw the layout of common source amplifier
using optimum layout methods verify DRC
and LVS extract parasitic and compute pre
layout and post layout simulation
4a Capture the Schematic of a 2 – Stage
Operational Amplifier and measure the
following: UGB, Bandwidth. Gain Margin
and Phase Margin with and without coupling
capacitance
Use the Op-Amp in the Inverting and Non-
4b Inverting configuration and verify its
functionality
Draw the layout of common source amplifier
using optimum layout methods verify DRC
and LVS extract parasitic and compute pre
layout and post layout simulation
5a Write Verilog code for 4 bit UP/Down
asynchronous reset counter and verify the
functionality using Test bench
Synthesis the design by setting area and time
5b
constraints and find the Critical Path and
Maximum Frequency of Operation
6a Write Verilog code for 4 bit adder and verify the
functionality using Test bench
Synthesis the design by setting area and time
constraints and identify Critical path, Maximum
6b delay, Total number of cells, Power requirement
and Total area required
7a Write Verilog code for UART and verify the
functionality using Test bench
Synthesis the design by setting area and time
constraints Tabulate the Area, Power and Delay
7b for the Synthesized netlist and Identify Critical
path
8a Write Verilog code for 32 bit ALU and verify
the functionality using Test bench
8b Synthesis the design by setting area and time
constraints Tabulate the Area, Power and Delay
for the Synthesized netlist and Identify Critical
path
9 Latch and Flip-Flop
Synthesize the design and compare the synthesis
report (D, SR. JK)
10 Internal Assessment
Total Marks