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Questa* Intel® FPGA Edition
Simulation User Guide

Updated for Intel® Quartus® Prime Design Suite: 23.2
Answers to Top FAQs:

Q What simulators do you support?
A Simulator Versions and Licensing on page 4
Q What do I need for simulation?
A Simulation Essential Elements on page 8
Q What are the simulation stages?
A Overview of Simulation Tool Flow on page 10
Q What are logical libraries?
A Specifying Logical Libraries on page 12
Q How do I compile into libraries?
A Compilation Command Examples on page 25
Q How do I run RTL simulation?
A Performing RTL Simulation on page 35
Q How do I simulate my IP?
A Simulating Designs that have IP on page 37
Q How do I run gate-level simulation?
A Performing Gate-Level Simulation on page 39
Q What are the known issues and limitations?
A Intel FPGA Support Forums: Simulation
Q Do you have training on simulation?
A Intel FPGA Simulation Training
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Contents
Contents
1. Introduction to the Questa* Intel® FPGA Edition Simulator............................................ 4

1.1. Simulator Versions and Licensing............................................................................. 4
1.1.1. Comparing Simulator Versions..................................................................... 6
1.2. Accessing Siemens EDA-Provided Simulator Documentation........................................ 6
1.3. Document Prerequisites..........................................................................................7
2. Intel FPGA Simulation Basics.......................................................................................... 8
2.1. Intel FPGA Simulation Essential Elements..................................................................8
2.2. Overview of Simulation Tool Flow........................................................................... 10
2.2.1. Compilation Stage....................................................................................10
2.2.2. Elaboration Stage.................................................................................... 11
2.2.3. Simulation Stage..................................................................................... 12
2.3. Simulation Tool Flow.............................................................................................12
2.3.1. Specifying Logical Libraries........................................................................12
2.3.2. Compiling Files Into Library Directories....................................................... 13
2.3.3. The Intel Quartus Prime Simulation Library..................................................15
2.3.4. Understanding Elaboration........................................................................ 18
2.3.5. Commands To Configure and Run Simulation............................................... 20
2.3.6. Intel FPGA Simulation Generic Workflow......................................................21
2.4. Supported Simulation Types and Hardware Description Languages..............................22
2.4.1. Supported Simulation Types...................................................................... 22
2.4.2. Supported Hardware Description Languages................................................ 22
3. Simulating with Questa Intel FPGA Edition................................................................... 24
3.1. Types of Questa Intel FPGA Edition Commands........................................................ 24
3.2. Commands to Invoke Questa Intel FPGA Edition.......................................................24
3.3. Commands to Compile, Elaborate, and Simulate...................................................... 25
3.3.1. Compilation Command Examples............................................................... 25
3.3.2. Finding Logical Library Names in Simulation Library Compiler Output.............. 28
3.3.3. Elaboration Command Examples................................................................ 28
3.3.4. Simulation Command Examples................................................................. 29
3.3.5. Complete Tcl Script Example......................................................................30
3.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries.................. 31
3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation.............................. 31
3.5.1. Commands Defined in msim_setup.tcl........................................................ 32
3.5.2. Example Using msim_setup.tcl without Customization...................................33
3.5.3. Example my_sim.tcl Simulation Script........................................................ 33
3.5.4. Passing In Custom Compilation and Elaboration Options for msim_setup.tcl..... 34
3.5.5. Finding All Custom Variables......................................................................34
3.6. Performing RTL Simulation with Questa Intel FPGA Edition.........................................35
3.6.1. Simulating an RTL Design without IP Variants or Platform Designer Systems.... 36
3.6.2. Simulating an RTL Design that has IP Variants or Platform Designer Systems... 37
3.7. Performing Gate-Level Simulation with Questa Intel FPGA Edition............................... 39
3.7.1. Post-Synthesis and Post-Fit Netlists for Simulation........................................39
3.7.2. Files Required for Gate-Level Simulation..................................................... 40
3.7.3. Step 1: Generate Gate-Level Netlists for Simulation......................................41
3.7.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level
Simulation.............................................................................................. 43
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Contents
3.7.5. Step 3: Determine Elaboration Options for Gate-Level Simulation................... 43

3.7.6. Step 4: Assemble and Run the Gate-Level Simulation Script.......................... 44
4. Revision History for Questa Intel FPGA Edition Simulation User Guide......................... 45
4.1. Questa Intel FPGA Edition Simulation User Guide Archive.......................................... 45
A. Intel Quartus Prime Pro Edition User Guides................................................................ 46
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1. Introduction to the Questa* Intel® FPGA Edition

Simulator
Simulation is an essential step in the Intel® Quartus® Prime software design process
that allows you to verify your design's behavior before configuring the FPGA device.
This document describes how to use the Intel provided Questa* Intel FPGA simulators
to simulate a design that targets an Intel FPGA device. Intel provides two different
versions of the Questa* Intel FPGA simulator:
• Questa* Intel FPGA Edition
• Questa Intel FPGA Starter Edition
The two simulators are different in terms of performance, but are identical in features
and usage, as described later. Going forward, this document uses the name Questa
Intel FPGA Edition to refer to both simulators, unless otherwise noted.
This document organizes information into the following chapters:

1. This introductory chapter describes simulator version support and enablement, as
Simulator Versions and Licensing on page 4 describes.
2. Intel FPGA Simulation Basics on page 8—explains fundamental aspects of Intel
FPGA design simulation for any supported simulator.
3. Simulating with Questa Intel FPGA Edition on page 24—steps through RTL and
gate-level simulation using the Questa Intel FPGA Edition simulator.
1.1. Simulator Versions and Licensing

There are two versions of the Questa* Intel FPGA simulator available: Questa Intel
FPGA Edition and Questa Intel FPGA Starter Edition. Both editions are available from
the FPGA Software Download Center page. You must purchase Questa Intel FPGA
Edition along with your purchase of the Intel Quartus Prime software. Questa Intel
FPGA Edition is known as the paid edition when distinguishing between the two
editions. Questa Intel FPGA Starter Edition is free to all users and is known as the free
edition.
The Intel Quartus Prime Pro Edition software and the Intel Quartus Prime Standard
Edition include both the free and paid editions of the software.
Both the free and paid editions require licenses for performing elaboration and
simulation, but not for compilation. Simply installing Questa Intel FPGA Edition is
insufficient for running simulations. For all editions, you must first obtain licenses and
install the simulators before running any simulations, as Intel FPGA Software
Installation and Licensing describes.
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any ISO
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the 9001:2015
application or use of any information, product, or service described herein except as expressly agreed to in Registered
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
1. Introduction to the Questa* Intel® FPGA Edition Simulator
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Table 1. Intel Quartus Prime and Questa Intel FPGA Edition Version Support
Questa Intel FPGA Licensing Supported Intel Performance Difference
Edition Version Quartus Prime Version
Questa Intel FPGA Licenses are required and must be Intel Quartus Prime Pro Reduced speed and instance
Edition version 2023.1 purchased. Each edition supports the Edition version 23.2 count(1) capacity limits in
same user interface commands, GUI (Windows, Linux) comparison with Siemens EDA
options, and behavior as the Questa* Core.
Siemens EDA Questa* Core
simulator.
Questa Intel FPGA Licenses are required but are free. Intel Quartus Prime Pro Reduced speed and instance
Starter Edition 2023.1 Each edition supports the same user Edition version 23.2 count capacity limits in
interface commands, GUI options, (Windows, Linux) comparison with Siemens EDA
behavior, and number of module Questa* Core. The Starter
instances as the Siemens EDA Edition has further reduced
Questa* Core simulator. performance levels.
Questa Intel FPGA Licenses are required and must be Intel Quartus Prime Reduced speed and instance
Edition version 2021.2 purchased. Each edition supports the Standard Edition count capacity limits in
same user interface commands, GUI version 21.1 (Windows, comparison with Siemens EDA
options, and behavior as the Linux) Questa* Core.
Siemens EDA Questa* Core
simulator.
Questa Intel FPGA Licenses are required but are free. Intel Quartus Prime Reduced speed and instance
Starter Edition 2021.2 Each edition supports the same user Standard Edition count capacity limits in
interface commands, GUI options, version 21.1 (Windows, comparison with Siemens EDA
behavior, and number of module Linux) Questa* Core. The Starter
instances as the Siemens EDA Edition has further reduced
Questa* Core simulator performance levels.
Other Supported Third-Party Simulators
The current version of the Intel Quartus Prime Pro Edition software also supports the
following third-party simulator versions:
Table 2. Intel Quartus Prime Pro Edition Supported Simulators

Vendor Simulator Version Platform Supports
Siemens EDA
Verification IP
Aldec Active-HDL* 13.0 Windows* 64-bit No
Aldec Riviera-PRO* 2023.04 Windows, Linux, 64-bit No
Cadence Xcelium* Parallel Simulator 22.09.001 Linux 64-bit Yes
Siemens EDA QuestaSim* Simulator(2) 2022.4 Windows, Linux, 64-bit Yes
Synopsys* VCS*, VCS MX T-2022.06- Linux 64-bit Yes

SP2-3
Related Information
Siemens EDA AXI Verification IP Suite
(1) Instance count is the number of Verilog modules or VHDL entity instances in the simulation.
(2) QuestaSim is the generic name for Questa Core and Questa Prime simulators from Siemens
EDA.
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1.1.1. Comparing Simulator Versions

The Intel Quartus Prime software includes Questa Intel FPGA Edition and Questa Intel
FPGA Starter Edition. These editions have the same functionality and user interface
(GUI and command-line) as the Siemens EDA Questa* Core simulator. The only
difference between these Intel FPGA editions and the Siemens EDA Questa Core
simulator is in performance and capacity, as the following table shows:
Table 3. Simulator Performance Comparison

Metric Questa Intel FPGA Questa Intel FPGA Questa Core Questa Prime
Edition Starter Edition
(Paid Edition) (Free Edition)
(3)
Cost Free with Intel Free Sold by Siemens EDA Questa Prime is the
Quartus Prime as their middle tier Siemens EDA high end
software purchase simulator. simulator.
Features Same as Questa Core Same as Questa Core Full featured
Performance 2-6X slower than 40% slower than Full performance

Questa Core(4) Questa Intel FPGA
Edition (Paid Edition)
(5)
Capacity Maximum of 5000 Maximum of 5000 No limit

non-Intel Quartus non-Intel Quartus
Prime simulation Prime simulation
library instances library instances
Advanced Verification Not Supported Not Supported Not supported, but Questa Prime includes
features such as can be purchased as these features.
randomization an add-on.
System C support Supported Supported Not supported, but Questa Prime includes
can be purchased as this feature.
an add-on.
1.2. Accessing Siemens EDA-Provided Simulator Documentation

Use the following method to access the Siemens EDA-provided Questa Intel FPGA
Edition User Guide. This document provides a full reference to all Questa Intel FPGA
Edition simulator commands and options.
1. Launch the Questa Intel FPGA Edition GUI. You can launch the application at the
command line by running the vsim command without arguments, as Commands
to Invoke Questa Intel FPGA Edition on page 24 describes.
2. From the Help menu, click on the Questa Intel FPGA Edition PDF bookcase menu
item to open the PDF for the user guide.
Note: The PDF user guide and other PDF documentation is in the
<installation>/docs/pdf_docs directory, where <installation> is the
Questa Intel FPGA Edition installation location.
(3) The user guide for Questa Intel FPGA Edition is essentially the same as the Questa Core user
guide.
(4) Actual performance is design and test case dependent.
(5) Actual performance is design and test case dependent.
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1.3. Document Prerequisites

This document assumes the following prerequisite knowledge:
• Basic understanding of FPGA design flows and practices, as Intel Quartus Prime
Pro Edition User Guide: Getting Started describes.
• Familiarity with the Verilog HDL language, including Verilog HDL modules, module
instances, module parameters, and hierarchies of Verilog HDL modules.
• A basic understanding of design simulation.
Note: Although this document focuses on simulation flows for Verilog HDL and SystemVerilog
HDL design files, you can easily apply these concepts to simulation of VHDL design
files. For example, a Verilog HDL module is equivalent to a VHDL entity. A Verilog HDL
parameter is equivalent to a VHDL generic, and so on.
Related Information
• IEEE Standard Verilog Hardware Description Language
• Self-Guided Lab: Introduction to Simulation and Debug of Intel FPGAs
• Intel Quartus Prime Pro Edition User Guide: Getting Started
• Introduction to Logic Circuits and Logic Design with Verilog
• Logic Design and Verification Using SystemVerilog
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2. Intel FPGA Simulation Basics

This chapter provides a high-level explanation of Intel FPGA simulation basic concepts
and workflows that apply to all simulators that the Intel Quartus Prime software
supports. An understanding of these basic concepts provides a foundation for
performing simulation using your supported simulator of choice.
While the details of using a particular simulator vary, the basic foundational concepts
and tasks of FPGA design simulation are common to all supported simulators. Some
simulators provide a GUI to execute the commands that this chapter describes using a
command-line flow.
2.1. Intel FPGA Simulation Essential Elements

The following describes the essential elements required for Intel FPGA design
simulation.
Design
An Intel Quartus Prime design typically consists of a top-level design module

containing a hierarchy of module instances, defined in one or more HDL files. The
design that you intend to simulate is known as the Design Under Test (DUT).
Testbench
To simulate the DUT (that is, a design), you must also provide a separate Verilog HDL
module (referred to as the testbench module) that instantiates the DUT and additional
logic to stimulate the DUT and to capture the output from the DUT. The testbench
module can include a hierarchy of module instances related to the testbench, but that
are not part of the design. You define the testbench modules in one or more HDL files.
Top-Level Testbench
A top level testbench module is the testbench module that instantiates all other design
and testbench related modules. This is the module you simulate.
HDL Design and Testbench Files
Simulating a design requires HDL design files, and one or more HDL testbench files.
Intel Quartus Prime designs typically consist of several modules that you define in
multiple HDL files. These files can include HDL files generated by Intel Quartus Prime
tool, such as Intel Quartus Prime Platform Designer.
Some of the modules instantiated in the design may be common to many designs.
Examples of some common modules are low-level primitives, like AND and OR gates,
and more complex blocks, such as multipliers and FIFOs.
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The low level modules common to many designs are known as simulation library
modules, and the files defining those modules are known as simulation library files.
The Intel Quartus Prime software installation provides various simulation library files,
as The Intel Quartus Prime Simulation Library on page 15 describes.
The combination of design and testbench files includes all the modules that are
instantiated in the top-level testbench module hierarchy, including all of the modules
for the design, because the design is instantiated within the testbench hierarchy.
Executable Simulation Model
In order to simulate a design you must first generate an executable simulation model
of the top-level testbench by running a set of simulator specific commands. You must
then run the executable model to perform simulation. Running the executable model
may require simulator specific commands. The executable model is typically a set of
binary files specific to a simulator.
Simulator Commands
You must run one or more simulator commands to generate the executable simulation
model and then to run the executable simulation model. The commands require the
following inputs to generate an executable model of the top-level testbench module
that you can simulate, as the figure Inputs and Commands to Generate and Run the
Executable Model shows:
• The name of the top-level testbench module.
• The HDL design files, including files generated by tools such as Platform Designer,
simulation library files, and testbench files.
Figure 1. Inputs and Commands to Generate and Run the Executable Simulation Model
my_top
Top-Level Testbench
Module Name
my_design.sv
my_testbench.sv One or More
library1.sv Simulator Commands
library2.sv
Executable
Simulation
Model
Command to
Run Simulation
Simulation
Running
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Since you must run several commands to create and run the executable model to
perform simulation, you can place the calls to the commands into one or more
simulation scripts for convenience. These scripts can be Linux shell scripts, Tcl scripts,
Perl, or Python scripts. Commands to Compile, Elaborate, and Simulate describes
these commands in detail.
2.2. Overview of Simulation Tool Flow

The various simulator commands that you use to generate and run the executable
model are all part of the simulation tool flow. A simulation tool flow consists of
executing the following three stages of the simulation, in that order:
1. Compilation
2. Elaboration
3. Simulation
You run simulator specific commands at each stage in the flow.
2.2.1. Compilation Stage

In the first stage of simulation you run compilation commands.
Inputs to a Compilation Command
The compilation command takes as input one or more design files, testbench files, and
simulation library files.
What Does a Compilation Command Do?
A compilation command does the following:

1. Reads the files that you specify as arguments to the command.
2. Analyzes the content of the files, which includes checking for syntax errors and
other issues.
3. Stores the analyzed content (such as the module definitions) in a directory in a
simulator specific proprietary format. The directory is known as a library directory.
You can also specify the directory as an input argument.
This step of storing the analyzed content of HDL files in a library directory is
known as compiling the files into a library directory, or simply compiling a file.
Compiling a file is similar to running Intel Quartus Prime Analysis & Synthesis, in that
the analyzed file content is stored in design database directory. The compilation is also
loosely analogous to compiling a C/C++ file into an object file, where the object file is
stored in a separate directory.
The library directory contains the definitions of all modules that are defined in the files
that you compiled into the library. You use these module definitions in the elaboration
stage. You may need to run multiple compilation commands to compile all the files
into library directories.
Compilation Command Example
Consider a design example that has two design files, foo.sv and bar.sv, and one
testbench file, my_testbench.sv.
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To compile these files, you first create a new directory, for example my_work. Next,
you run the simulator specific compilation command that takes in the file names and
directory name as inputs, as File and Directory Name Input to Simulator Specific
Compilation Command shows. Once the command runs successfully, one or more files
appear in the my_work library directory. The directory contains the definitions of all
modules the three HDL files define, in a proprietary format that only the simulator
understands.
Figure 2. File and Directory Name Input to Simulator Specific Compilation Command
“my_work_directory”
foo.sv
Compilation
/usr/design/bar.sv Command
../../my_testbench.sv
my_work_directory
2.2.2. Elaboration Stage

The elaboration stage follows the compilation stage. In the elaboration stage you
typically run just one elaboration command. This elaboration command can take
several inputs. At the minimum, elaboration requires as input the top-level testbench
module name, and the list of library directories that the compilation stage creates.
Figure 3. Elaboration Stage Inputs and Output

“/usr/design/my_design_lib_directory”
“common_library_directory”
“my_testbench_lib_dir”
“my_top_tb”
Elaboration
Command
Executable
Simulation
Model
The output of the elaboration command is the executable simulation model for the
top-level testbench. The executable simulation model comprises one or more
simulator-specific files and directories. For more details about the elaboration stage,
refer to Understanding Elaboration.
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2.2.3. Simulation Stage

The commands that apply to the simulation stage actually run the simulation. The
input to simulation stage commands is the executable simulation model that you
generate during the elaboration stage, along with other inputs, such as how long to
simulate, and which signals to capture for waveform viewing and dumping.
As Files and Directories for Executable Model of my_top_tb shows, the output of the
simulation stage is simply the output from a simulation run, which can include
messages issued by HDL modules, files written out by the simulator such as waveform
dumps, and any GUI display of simulation in progress.
Figure 4. Files and Directories for Executable Model of my_top_tb
Executable
Simulation
Model
Simulation
Command
Output of
Simulation
Run
2.3. Simulation Tool Flow

The simulation tool flow begins with the compilation stage that compiles files into
logical libraries using simulator specific compilation commands.
The next stage is elaboration, where you run the elaboration command to generate an
executable simulation model. In the final stage, you run the executable simulation
model to run the simulation.
The following topics describe these simulation tool flow concepts in more detail:
1. Specifying Logical Libraries
2. Compiling Files into Library Directories
3. Understanding Elaboration
4. Commands to Configure and Run Simulation
2.3.1. Specifying Logical Libraries

Some simulator commands for compilation and elaboration require you to specify a
logical library name as input.
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A Logical library is simply a name (typically short and readable) that represents a
physical library directory. For example, logical library name foo can represent physical
directory /users/jsmith/design1/bar. The simulator commands translate the
logical library name to a physical directory name by reading in a library mapping file.
The simulator commands require only the physical directory names.
The mapping of logical library names to physical directory names is known as library
mapping, which you must define. You typically store the library mapping in a separate
text file in a proprietary text format, with each line containing a single logical library
name and the corresponding library directory path. You can either update the file
manually, or by using a simulator specific command (if available). This library mapping
file often has a fixed simulator specific name and a fixed location. Therefore, you do
not generally specify the library mapping file as an argument to simulator commands,
even though the file is read by the commands.
A logical library name is an optional argument to many simulator commands. If you do

not specify a logical library name for such commands, the default value is work.
Therefore, you must map the logical library name work to a physical directory name.
Some simulators add a default library mapping for the work library if you do not
specify a mapping in a library mapping file. It is legal to map multiple logical library
names to a single library directory.
Example library mapping file with logical library names foo_lib and
common_sim_lib:
foo_lib : /users/john/designs/foo_dir
common_sim_lib : /usr/sim/common/libraries
Note: syntax of library mapping file varies with simulator
2.3.1.1. Why Do We Need Logical Library Names?
Using logical library names instead of physical directory names in command

invocations and in HDL files (especially VHDL files) simplifies some aspects of
simulation. Use of logical library names makes it easier to port simulation scripts when
moving the scripts across machines and disks because you only need to update the
library mapping to reflect any new library directory paths in the new environment.
For example, Intel recommends compiling Intel Quartus Prime simulation library files
into fixed logical library names. You can then map the logical library names to
appropriate library directory paths.
2.3.2. Compiling Files Into Library Directories

Many simulators include commands to compile one or more files, specified in some
order, into a single library directory. You specify the library directory by specifying its
logical library name. Some simulators have one command for compiling Verilog HDL or
SystemVerilog files, and a different command for compiling VHDL files.
The following section describes the various commands for compiling files into library
directories.
Related Information
Compilation Command Examples on page 25
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2.3.2.1. Inputs to Compilation Commands
Compilation commands accept the following inputs:

• An ordered list of one or more HDL file names, usually file names separated by
spaces.
Note: The file order is important in some cases, as Order of Files for Compilation
Commands explains.
• (Optional) Command line options to configure the compilation behavior, as
Compilation Command-Line Options describes.
• (Optional) The name of the logical library or a library directory name. When not
specified, the logical library default value is the work library, as Specifying Logical
Libraries describes.
Note: 1. You can compile two or more files using a single compilation command if you can
compile them into the same library, and they require the same compilation
options. The compilation command can take a list of HDL files as input.
2. You can compile files defining modules that are not part of the design or
testbench. The elaboration stage ignores such modules. In fact, in practice, you
typically compile many more modules than are required to simulate the top-level
testbench module.
The compilation command generates outputs, as Compilation Stage on page 10

describes.
2.3.2.2. Order of Files for Compilation Commands
The order of files that you specify to compilation commands is irrelevant for Verilog
and SystemVerilog files in many instances. The main exception is when there are files
defining SystemVerilog packages, or other files that import or otherwise refer to those
SystemVerilog packages.
Important: You must compile the files defining the SystemVerilog packages before compiling the
files that import or refer to those packages. Otherwise, the compilation command
errors out when compiling files that import or refer to those SystemVerilog packages.
For example, suppose file multp_pkg.sv defines the SystemVerilog package multp,
and the file my_design.sv imports package multp:
• If you compile both multp_pkg.sv and my_design.sv with a single compilation

command, you must ensure that multp_pkg.sv occurs before my_design.sv.
• If you compile multp_pkg.sv and my_design.sv using separate compilation
commands, you must ensure that you run the command that is compiling
multp_pkg.sv first.
VHDL has stricter requirements for ordering the files. For example, when a VHDL file
foo.vhd refers to a logical library name lib1, you must compile the files into lib1
first, before compiling foo.vhd into another library.
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2.3.2.3. Compilation Command Line Options
Some of the optional command-line arguments for the compilation command (not
including HDL file names and library names) include:
• The type of file for compilation (Verilog HDL, SystemVerilog, or VHDL).
• The values of the Verilog macros to pass in.
• The directories containing verilog "include" files. These are files included in a
Verilog HDL file using the `include construct.
• Simulator-specific optimization switches.
2.3.2.4. Module Definitions in Library Directories
A library directory can contain one or more module definitions, as well as other
elements, such as SystemVerilog package definitions.
A library directory can store only one module definition per module. For example, if
the adder.sv and adder_fast.sv files define the same module adder, but have
different implementations (perhaps adder_fast.sv implements a fast adder), then
compiling both files into the same library directory with a single compilation command
results in a compilation error. However, you can compile the adder.sv and
adder_fast.sv files into different library directories.
You can also replace an existing module definition in a library with another module
definition with the same module name. For example, if a library directory already
includes a module definition for adder (from compiling file adder.sv), and you
compile the adder_fast.sv file into that library directory, the existing module
definition in the library directory is replaced with the module definition from
adder_fast.sv.
2.3.3. The Intel Quartus Prime Simulation Library

The Intel Quartus Prime software includes the Intel Quartus Prime simulation library.
This library is comprised of Verilog HDL and VHDL files in the following directory:
<quartus_installation>/quartus/eda/sim_lib
This library includes simulation models for all low-level blocks that you instantiate in
your design. The library includes the following different types of low level blocks:
Table 4. Low Level Blocks in Simulation Library

Low-Level Blocks Description
Gate-Level Primitives Gate-level primitives include simple, non-parameterized modules, such as AND gates and flip-
flops. altera_primitives.v and altera_primitives.vhd define the gate-level primitives.
These primitives are only used in RTL designs. Post-synthesis and post-fit netlists do not include
these primitives. Rather, these netlists include ATOMs, as Post-Synthesis and Post-Fit Netlists for
Simulation describes.
Basic IP Function Previously known as "megafuctions," these are basic parameterized blocks for functions such as
Blocks FIFOs and multipliers. Only RTL designs use these blocks. Post-synthesis and post-fit netlists do
not include these blocks.
ATOMs Also known as WYSIWYGs, ATOMs are the lowest level primitives in an Intel Quartus Prime
design. There are different ATOM primitives, all of them parameterized modules with varying
complexity. They represent the hardware blocks on the FPGA. For example there are ATOM
continued...
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Low-Level Blocks Description
modules that represent the I/O pins and buffers, FPGA lookup tables, DSP blocks, RAM blocks,
and periphery blocks, such as high speed transceivers and hardened Ethernet and PCIe blocks.
You are not expected to instantiate ATOMs directly in your RTL. Rather, the ATOMs are
instantiated in the RTL files that the Intel Quartus Prime software generates. Since the Intel
Quartus Prime synthesis maps the design to ATOMs, the post-synthesis and post-fit netlists are
netlists of ATOMs, known as ATOM netlists. The Fitter places and routes the ATOM netlist.
HDL Library Files You compile the HDL library files into fixed logical locations, as Compiling Files into Library
Directories describes. You must not compile the libraries for Questa Intel FPGA Edition. Instead
use the included precompiled libraries.
Note: For Questa Intel FPGA Edition, do not use the Simulation Library Compiler to compile
the libraries. You must use the Questa Intel FPGA Edition precompiled libraries for this
simulator. Refer to Why You Should Only Use Precompiled Questa Intel FPGA Edition
Libraries.
2.3.3.1. The Intel Quartus Prime Simulation Library Compiler

The Intel Quartus Prime Simulation Library Compiler is an Intel Quartus Prime
software GUI and command-line tool that generates simulation scripts. You can use
these scripts to automatically compile the Intel Quartus Prime software simulation
libraries for a given simulator, device family, and hardware description language
(Verilog HDL or VHDL).
Note: For Questa Intel FPGA Edition, do not use the Simulation Library Compiler to compile
the libraries in Questa Intel FPGA Edition. Instead, you must use the Questa Intel
FPGA Edition precompiled libraries included with this simulator.
2.3.3.2. Running the Simulation Library Compiler in a Terminal

You can run the Intel Quartus Prime Simulation Library Compiler in a terminal without
launching the Intel Quartus Prime software GUI.
The following example command generates the Questasim compile.do simulation

script that compiles all Verilog HDL simulation files for the specified Intel Agilex® 7
device family.
quartus_sh –simlib_comp -family agilex7 -tool modelsim \
-language verilog -gen_only -cmd_file compile.do
To view all available command-line options, you can run the following command:
quartus_sh --help=simlib_comp
2.3.3.3. Running the Simulation Library Compiler in the GUI
To automatically compile all required simulation model libraries for your design in your
supported simulator using the Simulation Library Compiler GUI, follow these steps:
1. In the Intel Quartus Prime software, click Tools ➤ Launch Simulation Library
Compiler.
2. Specify options for your simulation tool, language, target device family, and output
location, and then click OK.
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Note: Once the simulation model compilation starts, the compilation may require
from 15 minutes to a full hour, depending on your system. Although the
compilation messages may appear paused or incomplete, the compilation is
still running correctly.
3. Use the compiled simulation model libraries to simulate your design. for
information about running simulation, refer to Simulating with Questa Intel FPGA
Edition or to your supported EDA simulator's documentation.
Figure 5. Simulation Library Compiler GUI
2.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
After you generate the simulation script using the Simulation Library Compiler, you
may need to inspect the script to identify the logical library names for use with your
elaboration command (vsim).
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To identify the logical library names for Intel Quartus Prime simulation libraries in the
generated script, search for all of the lines that begin with vmap, such as the following
line:
vmap altera_ver "./verilog_libs/altera_ver"
The first argument to vmap is the logical library name (altera_ver). The second
argument is the physical directory where the library content is stored. This second
argument is irrelevant for Questa Intel FPGA Edition because you do not run the
command.
Questa Intel FPGA Edition installation includes its own library mapping in the
modelsim.ini file. This file maps the above logical library names to physical
directories within the installation path. Therefore when you run elaboration command
vsim -L altera_ver in Questa Intel FPGA Edition, the tool locates the correct
physical library corresponding to logical library altera_ver.
2.3.4. Understanding Elaboration

Simulator elaboration is analogous to the linking step in C/C++ programming that
produces an executable binary file.
You can run elaboration with a single command that accepts the following inputs and
generates an executable model for the top-level testbench module name:
• An ordered list of logical library names. You can specify the ordered list of logical
library names either explicitly on the elaboration command line, or by ordering
them in the library mapping file. If reading from the library mapping file, the
simulator uses the order of logical libraries in the library mapping file.
• (Optional) Elaboration options.
• Top-level testbench module name.
• (Optional) The name of the logical library containing the top-level testbench
module definition. If omitted, the top-level testbench module defaults to the work
library.
The elaboration command does not read any HDL files. The elaboration command only
reads the library directories containing the module definitions.
An important part of elaboration is to find the module definitions for all the module
instances in the top-level testbench module hierarchy. This identification is described
as binding the module instances to their module definitions, or linking the module
instances to their module definitions. Understanding the binding process during
elaboration is important when debugging common elaboration errors, as Elaboration
Binding Phase on page 19 describes.
Related Information
Elaboration Command Examples on page 28
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2.3.4.1. Elaboration Binding Phase
Elaboration works in a top-down manner to bind module instances in the following

order:
1. Elaboration finds the top-level testbench module definition, given the module
name and the library that contains the module definition as input. Typically, you
compile the top-level testbench module into the work library. For example,
specifying the top-level testbench module as foo with no library name, is
equivalent to specifying the top-level testbench module as work.foo.
2. Elaboration reads the module definition, and identifies all the module instances in
the top-level testbench module.
3. Elaboration attempts to find the module definitions for all instances in the top-
level testbench, one instance at a time.
For example, for an instance inst1 of module foo in the top-level testbench
module tb, elaboration attempts to find the definition of module foo by searching
for foo in the first library in the ordered list of library directories. If elaboration
cannot find the module definition in the first library directory, it searches in the
second library directory, and so on.
Once elaboration finds the definition of foo in a library directory, it stops
searching for the definition. Therefore, if foo is defined in multiple library
directories, elaboration uses only the first instance, and ignores any other
instances. In this way, elaboration binds inst1 to foo.
4. Elaboration attempts to find all of the module instances within foo, and then to
find the module definitions for those instances using the same process that
elaboration followed for binding foo.
5. Elaboration recursively attempts to bind all the module instances within the foo
module's hierarchy before processing other instances in the top-level testbench
tb.
6. The elaboration stage ends in one of the following ways:
• All instances in in top-level testbench hierarchy are bound to modules, and
elaboration succeeds.
Or:
• An error is generated because elaboration cannot bind one or more instances
in the top-level testbench module hierarchy to modules.
2.3.4.2. Elaboration Checks
The elaboration command performs several checks. For example, elaboration verifies
that the module definitions are consistent with their instantiations. This check
confirms that a module’s ports and parameter definitions match the corresponding
module instances.
2.3.4.3. Elaboration Options
There are many simulator specific elaboration options that you can specify. One
common elaboration option preserves specific signal names so that their waveforms (a
record of how the signals change with time) can be recorded during simulation. The
rationale behind this option is explained below.
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The elaboration stage generally includes an optimization step. The optimization step
attempts to build an optimized executable simulation model that can run faster or
consume less memory during simulation.
There are many signals (defined as wire, reg, or logic variables) in a typical design
and testbench hierarchy. At the end of a simulation, any signal can produce a
simulation waveform.
The optimization step may be unable to fully optimize the executable simulation model
if most of the signals in the testbench hierarchy are preserved. Therefore, it is best to
limit the signals that you preserve to those that require waveforms during simulation.
You can specify the signals to preserve at varying level of granularity. For example,
you can specify specific signal names, or all signals within a module instance.
Related Information
Passing In Custom Compilation and Elaboration Options for msim_setup.tcl on page
34
2.3.5. Commands To Configure and Run Simulation

Once you generate the executable simulation model during elaboration, you can run
the executable simulation model to simulate the top-level testbench module.
There are several different methods to configure and run simulation. The following are
some of the typical simulator commands and options that you can use for simulation:
• You can specify which signals that you want the simulator to record during
simulation. You must ensure that those signals are preserved during the
elaboration stage, as Elaboration Options on page 19 explains.
The simulator writes the waveforms of these signals to a simulator proprietary
database during simulation. You can view the waveforms in a GUI after simulation.
Note: You cannot record or display signals in encrypted HDL files with the
simulator.
• You can specify the amount of simulation time to simulate the top-level testbench
module. For example, you can specify a simulation time of 1 milliseconds.
• You can specify an option to wait for simulation licenses. This option is applicable
when using floating simulation licenses. Some simulators exit immediately if there
are no available floating licenses for simulation.
Related Information
Simulation Command Examples on page 29
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2.3.6. Intel FPGA Simulation Generic Workflow

The following describes the high level workflow for simulation of any Intel Quartus
Prime design using any supported simulator:
Figure 6. Generic Intel FPGA Simulation Workflow

1 3
Identify Files & Testbench Compile Into Libraries
HDL
Sim File work
Library .v, .vhd, .ip
Files .qsys Lib A
“top”
Test Lib B 5
Bench Simulation
Run
Elaborate Top-Level
Testbench
Assemble Simulation Script

2 4
1. Identify all of the HDL simulation files, including design files, simulation library
files, and HDL testbench files.
2. Identify the top-level test bench module for simulation.
3. For each HDL simulation file, determine the logical library for compilation, and any
compilation options for compiling the file.(6)
4. Determine any simulator-specific elaboration options required for elaborating the
top- level testbench module, as Understanding Elaboration describes.
5. Use the information gathered in previous steps to assemble a simulation script to
compile, elaborate, and simulate the design. This script must include commands to
perform the following:
• Compile the simulation files into libraries, as Compiling Files into Library
Directories describes.
• Elaborate the Top-Level testbench, as Understanding Elaboration describes.
• Run the executable simulation model to simulate the testbench and the
design, as Commands to Configure and Run Simulation describes.
The Intel Quartus Prime software can generate simulator-specific simulation scripts to
automate some of the simulation processing in your preferred simulation environment.
The Intel Quartus Prime software can generate a simulator specific simulation script
for an IP core, or a Platform Designer system, for use in RTL simulation, as Supported
Simulation Types and Hardware Description Languages on page 22 describes. The
script includes commands to compile all the IP RTL files, as well as an elaboration
command with any simulator specific options.
(6)
In general, you can compile most HDL simulation files into the default work library.
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The Intel Quartus Prime software can generate a simulation library compilation script
for a given simulator, device family, and language. This script includes commands to
compile the simulation library files for the specified simulator, device family, and
language. You can use this script for RTL simulation and gate-level simulation, as
Supported Simulation Types and Hardware Description Languages on page 22
describes.
2.4. Supported Simulation Types and Hardware Description

Languages
2.4.1. Supported Simulation Types

You can run different types of simulation, depending on the stage of the Intel Quartus
Prime design flow:
Table 5. Supported Simulation Types

Simulation Type Description Occurs
RTL Simulation of an RTL design consisting of one or more RTL files that you Can perform before
provide as input to the Intel Quartus Prime software. These RTL files Intel Quartus Prime
typically also include the files that the Intel Quartus Prime Platform Synthesis
Designer generates for Intel FPGA IP and systems. You can only simulate
HDL RTL files.(7). The RTL files can instantiate low level blocks, such as
primitives, basic IP functions, and ATOMs, as The Intel Quartus Prime
Simulation Library on page 15 describes.
Post-Synthesis The Intel Quartus Prime software can generate a Verilog HDL or VHDL Must perform after
Simulation (Gate- gate-level netlist after the synthesis stage completes, but before the Intel Quartus Prime
Level) Fitter stage runs. The resulting netlist is the post-synthesis netlist. The synthesis
Intel Quartus Prime EDA Netlist Writer tool generates the post-synthesis
netlist. The post-synthesis netlist is a netlist of low level blocks called
ATOMs. The post-synthesis netlist is a purely functional netlist.
Post-Fit Simulation The Intel Quartus Prime EDA Netlist Writer can generate a Verilog HDL or Must perform after
(Gate-Level) VHDL gate-level netlist after the Fitter stage completes. The resulting Intel Quartus Prime
netlist is the post-fit netlist. The post-fit netlist is a netlist of ATOMs that Fitter
the Fitter placed and routed on the FPGA device. The post-fit netlist is a
purely functional netlist.
Note: The post-fit netlist includes chip locations of ATOM instances in
commented lines. The post-synthesis netlist does not include this
data.
Note: the Intel Quartus Prime software supports post-fit functional simulation, but does not
support post-fit timing simulation.
2.4.2. Supported Hardware Description Languages

The Intel Quartus Prime software provides the following hardware description
language (HDL) support for EDA simulators.
(7) You must first convert the non-HDL files to HDL files prior to simulation
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Table 6. HDL Support

Language Support Description
VHDL • For VHDL simulation, you compile design files, testbench files, and Platform designer generated
RTL files using simulator commands.
• For all supported simulators other than Questa Intel FPGA Edition, you must also compile
simulation models from the Intel FPGA simulation libraries.
• Many of the Intel Quartus Prime simulation models and IP RTL files are implemented in Verilog or
SystemVerilog only. Therefore, you may require a simulator that is capable of VHDL and Verilog
HDL mixed language simulation.
Verilog / • For Verilog or SystemVerilog simulation, you compile design files, testbench files, and Platform
SystemVerilog Designer generated RTL files using simulator commands.
• For all supported simulators other than Questa Intel FPGA Edition, you must also compile
simulation models from the Intel FPGA simulation libraries.
• There are some IP RTL files that are implemented in VHDL only. Therefore, you may require a
simulator that is capable of VHDL and Verilog HDL mixed language simulation.
Mixed HDL • If your design is a mix of VHDL, Verilog HDL, and SystemVerilog files, you must use a mixed
language simulator.
• The Questa Intel FPGA Edition software supports native, mixed-language (VHDL/Verilog HDL/
SystemVerilog) simulation.
If you have a VHDL-only simulator and need to simulate Verilog HDL modules and IP cores, you
can either acquire a mixed-language simulator license from the simulator vendor, or use the
Questa Intel FPGA Edition simulator.
Schematic • You cannot simulate a schematic in any of the simulators that the Intel Quartus Prime software
supports.
• To perform RTL simulation of the schematic, you must convert the schematic to HDL format and
run RTL simulation on the HDL. The Intel Quartus Prime Pro Edition software cannot perform
schematic conversion.
• To perform post-synthesis or post-fit simulation, you must first compile the schematic based
design in the Intel Quartus Prime software, generate a gate-level Verilog HDL or VHDL simulation
netlist, and perform simulation on the gate-level netlist.
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Send Feedback
3. Simulating with Questa Intel FPGA Edition

This chapter describes how to use the Intel-provided Questa Intel FPGA Edition
simulator to simulate Intel Quartus Prime designs.
3.1. Types of Questa Intel FPGA Edition Commands

You execute commands included with Questa Intel FPGA Edition to compile HDL files
into library directories, elaborate the top-level testbench to generate the executable
model of the top-level testbench, and to simulate the top-level testbench.
Questa Intel FPGA Edition supports the following types of commands:

• Linux or Windows commands that you run at a Linux terminal, a Windows shell, or
as a Windows shortcut. These commands run executable files.
• Tcl commands. These commands occur in a Tcl script file that you provide as input
to Questa Intel FPGA Edition. The script is also known as a “do” file.
Note: This document uses Linux conventions in examples and command explanations. You
must make appropriate adaptations if using Windows commands. This document
specifies any non-trivial adaptations as required.
3.2. Commands to Invoke Questa Intel FPGA Edition

You can run any of the following commands at a Linux or Windows terminal to invoke
the Questa Intel FPGA Edition simulator after proper installation and licensing. For
information on installation and licensing, refer to Simulator Versions and Licensing.
Table 7. Commands to Invoke Questa Intel FPGA Edition

Running shell command Result
vsim (without arguments) Invokes the Questa Intel FPGA Edition GUI. Also creates an interactive Tcl shell for you
to run Tcl commands.
vsim -c Invokes the Questa Intel FPGA Edition in command-line mode, and creates an
interactive tcl shell for you to run Tcl commands.
vsim -do run.do Invokes the Questa Intel FPGA Edition GUI and runs the Tcl commands in the run.do
file, inside the GUI Tcl shell.
vsim -c -do run.do Invokes the Questa Intel FPGA Edition in command-line mode, and runs the Tcl
commands in the run.do file inside the Tcl shell.
Related Information
Intel FPGA Software Installation and Licensing
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3.3. Commands to Compile, Elaborate, and Simulate

This section describes the various Tcl commands to compile, elaborate, and simulate
the design. You can include these commands in a Tcl script such as run.do, and
provide that script as input to simulator commands, as Commands to Invoke Questa
Intel FPGA Edition describes.
The following examples illustrate use of these commands. The complete example
appears at the end of this section. Review the examples in sequence because later
examples omit steps or explanations that earlier examples provide.
Note: These examples only illustrate a small set of commands and options. Refer to Siemens
EDA Questa Intel FPGA User Guide for a comprehensive command reference, as
Accessing Siemens EDA-Provided Simulator Documentation describes.
Related Information
• Compilation Command Examples on page 25
• Elaboration Command Examples on page 28
• Simulation Command Examples on page 29
• Complete Tcl Script Example on page 30
3.3.1. Compilation Command Examples

The first step in the Questa Intel FPGA Edition simulation flow is compiling all the
source files into libraries, as the following compilation command examples show.
3.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library

The following example compiles the foo.sv file that defines module my_foo into the
my_lib logical library. The logical library is mapped to physical directory /tools/
libraries/my_lib.
1. Create the library directory by running the vlib Tcl command:
vlib /tools/libraries/my_lib
The command creates the directory /tools/libraries/my_lib and adds a

Questa Intel FPGA Edition proprietary file to the directory indicating that it is a
library directory.
2. Map logical library my_lib to the library directory /tools/libraries/my_lib
by running the vmap Tcl command:
vmap my_lib /tools/libraries/my_lib
This command copies the modelsim.ini file from the Questa Intel FPGA Edition
installation to a local directory (if a local modelsim.ini does not already exist),
and adds the library mapping to modelsim.ini. View the library mapping by
opening the modelsim.ini file and searching for my_lib. The mapping is a
single line, such as the following:
my_lib = /tools/libraries/my_lib
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3. Compile foo.sv to logical library my_lib by running the vlog Tcl command:
vlog -sv foo.sv -work my_lib
The -sv option specifies that the file type is SystemVerilog. After you run this
command successfully, the /tools/libraries/my_lib directory contains the
module definition of my_foo.
To run above steps 1 through 3, you first create and add the following lines to a
run.do file:
vlib /tools/libraries/my_lib
vmap my_lib /tools/libraries/my_lib vlog -sv foo.sv -work my_lib
quit
The Tcl command quit exits the Tcl shell so that the vsim command can complete.
Next, you can run one of the commands to invoke Questa Intel FPGA Edition, as
Commands to Invoke Questa Intel FPGA Edition on page 24 describes.
Note: • Alternatively, you can also type each Tcl command individually in the interactive
Tcl shell that you launch by running vsim -c (or just vsim to invoke the GUI and
the interactive Tcl shell).
• Some Tcl commands, such as vlog, vcom, vlib, and vmap are also available as
Linux and Windows commands.
• For help on all vlog options, run vlog-help all. To get help on a specific
option such as -suppress, run vlog -help -suppress.
3.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library

(work)
The following example illustrates use of Tcl commands to compile a file into the default
library. You must add the commands to a .do file that you then run at a terminal
using the vsim command, as Compilation Example 1 describes.
The following Tcl command compiles design1.sv to the work library, without explicit
reference to the default library name:
vlog -sv design1.sv
Note: The vlog command automatically creates the library directory work and the logical
library work. Therefore, there is no need to create an explicit work directory and map
it using the vmap and vlog commands.
However, If you want to specify a particular library location for work, such as /
tools/libraries/my_work, then you must use the vmap and vlib commands,
along with the logical library name work, as Compilation Example 1 shows:
vlog -sv design1.sv
quit
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3.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo
The following example illustrates use of Tcl commands to compile all files into a logical
library. You must add the commands to a .do file that you then run at a terminal
using the vsim command, as Compilation Example 1 describes.
The following commands create the logical library foo and compile all .sv files in the
current directory into foo:
vlib /tools/libraries/somedirectory
vmap foo /tools/libraries/somedirectory
vlog -sv -work foo *.sv
quit
3.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro
FAST Set to 1
The following example illustrates use of Tcl commands to compile all files into a library
with a Verilog macro. You must add the commands to a .do file that you then run at a
terminal using the vsim command, as Compilation Example 1 describes.
The following is only a partial example, as it does not include the quit command:
vlog -sv +define+FAST=1 foo.sv
3.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package

my_pkg and File foo.sv Imports my_pkg
The following example compiles both files into the lib1 library. This is a partial
example since it does not include the quit command.
vlog -sv my_pkg.sv foo.sv -work lib1
In this example, the order of HDL files matters because SystemVerilog package files
are present. In general, you must specify all SystemVerilog package files before the
files that import the package files.
3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package

my_pkg and File foo.sv Imports my_pkg
After you compile all source files into libraries, the next step is to elaborate the top-
level testbench module. Therefore, if you create a single Tcl script for both compilation
and elaboration, you place the elaboration command after the compilation commands.
The elaboration command accepts as input the top-level testbench module name, and
the list of library directories that you create in the compilation step.
vlog -sv my_pkg.sv -work lib_sv
vlog -L lib_sv -sv foo.sv -work lib1
In this example, the second vlog command must specify -L lib_sv to refer to the
SystemVerilog package. This is a partial example, as it does not include the
commands to create logical libraries lib_sv and lib1, and also excludes the quit
command.
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3.3.2. Finding Logical Library Names in Simulation Library Compiler

Output
After you generate the simulation script using the Simulation Library Compiler, you
may need to inspect the script to identify the logical library names for use with your
elaboration command (vsim).
To identify the logical library names for Intel Quartus Prime simulation libraries in the
generated script, search for all of the lines that begin with vmap, such as the following
line:
vmap altera_ver "./verilog_libs/altera_ver"
The first argument to vmap is the logical library name (altera_ver). The second
argument is the physical directory where the library content is stored. This second
argument is irrelevant for Questa Intel FPGA Edition because you do not run the
command.
Questa Intel FPGA Edition installation includes its own library mapping in the
modelsim.ini file. This file maps the above logical library names to physical
directories within the installation path. Therefore when you run elaboration command
vsim -L altera_ver in Questa Intel FPGA Edition, the tool locates the correct
physical library corresponding to logical library altera_ver.
3.3.3. Elaboration Command Examples

After you compile all source files into libraries, the next step is to elaborate the top-
level testbench module. If you decide to create a single Tcl script for both compilation
and elaboration, you must place the elaboration command after the compilation
commands. The elaboration command accepts as input the top-level testbench module
name, and the list of logical libraries that may include the Intel Quartus Prime
simulation libraries and any other libraries that you create during compilation. The
following examples illustrate use of the elaboration command.
Related Information
Understanding Elaboration on page 18
3.3.3.1. Elaboration Example 1: Elaborate the Test Top-level Testbench Module
In the following example, the file defining the module test is compiled into the
top_lib library. All other testbench and design related RTL files are compiled into the
lib1, lib2, and top_lib libraries.
You can elaborate the testbench module test with the following single Tcl command:
vsim -L work -L lib1 -L lib2 -L top_lib top_lib.test
The order of libraries is relevant because the vsim command searches for module
definitions in the order you specify, as Elaboration Binding Phase describes.
Note: You must ensure that the first -L entry in all vsim commands is always -L work,
because this alters the way that Questa Intel FPGA Edition searches for module
definitions. This technique also helps to eliminate issues caused by duplicate modules
shared by multiple IP.
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This example command does not preserve any internal signals, which means that you
cannot capture the waveforms for those signals during simulation.
Note: When the vsim Tcl command completes, the executable simulation model for module
test automatically loads into memory so that subsequent Tcl commands can simulate
the test module.
3.3.3.2. Elaboration Example 2: Elaborate the Test Top-level Testbench Module

and Preserve All Signals
The following example is the same as Elaboration Example 1, except that the following
example preserves all signals so that you can later view their waveforms during or
after simulation.
You can elaborate the testbench module test with the following single Tcl command:
vsim -voptargs=”+acc” -L work -L lib1 -L lib2 \
-L top_lib top_lib.test
The voptargs option value '+acc' directs vsim to preserve all signals. In general,
preserving all signals is not a best practice because it can slow down simulation. You
should only preserve a subset of signals whenever possible. Refer to the Siemens EDA
Questa Intel FPGA Edition User Guide for various options to preserve a subset of
signals in the testbench hierarchy.
3.3.3.3. Elaboration Example 3: Elaborate Top-Level Testbench Module my_test
The following elaboration example assumes that all modules within the top-level
module my_test hierarchy are compiled into the default library work.
vsim my_test (or vsim -L work test)
In this case, the library work is implicit. That is, you can replace test in the above
command with work.test.
3.3.4. Simulation Command Examples

You run simulation commands after compilation and elaboration commands.
A single Tcl script for the whole simulation flow includes compilation commands,
followed by the elaboration command, followed next by simulation commands.
Related Information
Commands To Configure and Run Simulation on page 20
3.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing
Waveforms of All Top-Level Signals in the Testbench
The following example runs simulation until the end, while capturing the waveforms of
all top-level signals in the testbench:
add wave *
run -all
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With the add wave command, you can view the signal waveforms live during the
simulation run, and you can also save the waveforms as a waveform file (.wlf) for
later viewing.
3.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while

Capturing Waveforms of All Top-Level Signals in the Hierarchy
The following example runs simulation until the end, while capturing the waveforms of
all top-level signals in the testbench:
add wave -r /*
run 30us
Since the command captures all signals, the elaboration command must preserve all
signals using the -voptargs=”+acc” command.
3.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing
Waveforms of Top-Level Design Instance
For the following example, the design instance path is /tb/dut. This example runs
the simulation until the end, while capturing the waveforms of the top-level design
instance for later viewing:
log /tb/dut/*
run 30us
With the log command, you cannot view the signal waveforms live during the
simulation run, but you can save the waveforms to a waveform file (.wlf) for viewing
after the simulation run.
3.3.5. Complete Tcl Script Example

In the following complete Tcl script example, the design consists of two design files,
top.sv and ip1.sv. The testbench consists of one file, test1.sv, with the top-level
testbench module name of test.
There are two tcl scripts: comp.tcl that only compiles the source files, and the top-
level script sim.tcl, that sources comp.tcl and then elaborates the testbench
module and runs simulation.
comp.tcl creates the logical library design_lib, compiles design files into
design_lib, and compiles the testbench file test1.sv into the work library.
Content of comp.tcl
vlib /usr/sim/design_lib_dir
vmap design_lib /usr/sim/design_lib_dir
vlog -sv -work design_lib top.sv ip1.sv
vlog -sv test1.sv
sim.tcl sources comp.tcl to compile the source files, runs vsim with the
voptargs=”+acc” argument to preserve all signals, then specifies that all signal
waveforms must be captured. Finally sim.tcl runs simulation without a time limit.
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Content of sim.tcl:
source comp.tcl
vsim -t ps -voptargs=”+acc” test
add wave -r /*
run -all
quit
To run sim.tcl in the GUI and see the live simulation waveforms, you run the following
command at the terminal:
vsim -do sim.tcl
3.4. Why You Should Only Use Precompiled Questa Intel FPGA
Edition Libraries
You should only use the precompiled libraries included with the Questa Intel FPGA
Edition simulator. Otherwise, you may exceed the 5000 module instance limit of
Questa Intel FPGA Edition.
The precompiled libraries included in Questa Intel FPGA Edition are specially created
so that Questa Intel FPGA Edition recognizes them as Intel libraries and does not
count their instances towards the 5000 module instances limit.
The Intel Quartus Prime library source files are simply RTL files. Therefore, if you
compile the library source files using vlog and vcom commands, Questa Intel FPGA
Edition does not recognize those modules as part of the Intel Quartus Prime simulation
library, and hence counts them towards the 5000 limit. For this reason, you should
only use precompiled Questa Intel FPGA Edition libraries.
3.5. Generating a msim_setup.tcl Simulation Script for RTL

Simulation
Understanding this section is a prerequisite for performing RTL simulation of designs
that include Intel FPGA IP. Platform designer generates a msim_setup.tcl
simulation script in the mentor directory by default when you generate simulation
files for IP variants or Platform Designer systems. You can also run the ip-setup-
simulation command to generate a single msim_setup.tcl file for all IPs in the
Intel Quartus Prime design. The msim_setup.tcl script is suitable for both
Questasim and Questa Intel FPGA Edition.
The msim_setup.tcl script defines “aliases” (similar to Tcl procedures, or Tcl

commands), for performing compilation and elaboration. This document refers to
these aliases as Tcl commands. You can call these Tcl commands from another Tcl
script after sourcing msim_setup.tcl, as Example Simulation Script illustrates.
msim_setup.tcl also defines variables that you can use to customize the
commands. For example, you can add your own Verilog HDL compilation options to all
the files you are compiling, and you can add your own elaboration options to the
elaboration commands.
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Example ip-setup-simulation Command
The following shows an example ip-setup-simulation command:

ip-setup-simulation --quartus-project=foo.qpf
This command creates multiple subdirectories in the directory that you run the
command. The subdirectories for Questa Intel FPGA Edition are the common and
mentor directories. The mentor directory contains the msim_setup.tcl simulation
setup script.
The following shows an example command with several options:

ip-setup-simulation --quartus-project=<my proj> --output-directory=<my_dir> \
--use-relative-paths --compile-to-work
The following are some useful command-line options for ip-setup-simulation:

• compile-to-work—compiles all simulation files into a single work library.
• use-relative-paths—uses relative paths whenever possible.
• output-directory—specifies the directory where the output generates.
• ip-setup-simulation –-help—lists all command-line options.
Note: You can alternatively invoke ip-setup-simulation from the Intel Quartus Prime
software GUI by opening the project, then selecting Tools ➤ generate Simulator
Setup Script for IP and entering appropriate values in the dialog box.
3.5.1. Commands Defined in msim_setup.tcl

msim_setup.tcl defines the following commands:
Table 8. Commands Defined in msim_setup.tcl

Command Description
dev_com Compiles all Intel Quartus Prime simulation libraries into appropriate logical libraries using vlog
and vcom commands. This command does not actually compile any files when run by Questa Intel
FPGA Edition, as Why You Should Only Use Precompiled Libraries describes.
com Compiles all Platform Designer generated RTL files into appropriate logical libraries using vlog
and vcom commands.
elab Elaborates the top-level module (the module name is the value of the tcl variable
TOP_LEVEL_NAME ). This command specifies the ordered list of logical libraries using -L option,
as well as any other elaboration options required for Intel FPGA IP and simulation models.
elab_debug Same as the elab command, except that it adds the voptargs=”+acc” option to preserve
visibility of all signals in the design, which allows you to dump out their waveforms during
simulation for debugging.
ld Calls dev_com, com, and elab, in that order.
ld_debug Calls dev_com, com, and elab_debug, in that order.
file_copy Copies any memory files (such as .mif and .hex files) into the mentor folder so they are
available for simulation. The simulator expects these files to be present in the directory in which
you run it from. This command is different in that you call it when sourcing msim_setup.tcl,
and the command does not need an explicit call.
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3.5.2. Example Using msim_setup.tcl without Customization

The following is a simple example that illustrates use of the msim_setup.tcl file for
a design that does not require passing in any specific compilation options or
elaboration options.
This example has a single my_design.sv design file, and one tb.sv testbench file
that defines the top-level module tb. The design instantiates an Intel FPGA IP variant.
The example also includes the ./mentor/msim_setup.tcl Tcl script that Platform
Designer generates, as Generating a msim_setup.tcl Simulation Script describes.
The example includes the manually created Tcl script ./mentor/my_sim.tcl that
compiles, elaborates, and simulates the testbench. ./mentor/my_sim.tcl includes
the following lines. Lines beginning with # are comments. You run the script by calling
vsim -do my_sim.tcl from within the mentor directory.
3.5.3. Example my_sim.tcl Simulation Script

The following example simulation script compiles, elaborates, and simulates the
testbench, as Example Using msim_setup.tcl without Customization on page 33
describes.
# this script must be in the same directory as msim_setup.tcl
# create work library

vlib work
# compile design and testbench files into work library

vlog -sv my_design.sv tb.sv
# source the file to define the commands such as com and

# elab_debug, and to call file_copy to copy any IP memory files
# (such as .hex and .mif files) to this directory.
source ./msim_setup.tcl
# compile quartus simulation libraries. This command will not do

# anything when called by Questa Intel FPGA Edition, since we use
# precompiled quartus simulation libraries.
dev_com
# compile IP RTL files

com
# toplevel module name to be simulated. This is the top-level

# testbench module
set TOP_LEVEL_NAME “tb”
# call elaboration command.

elab_debug
# add waveforms
add wave -r /*
# run simulation
run -all
# exit simulation
quit
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3.5.4. Passing In Custom Compilation and Elaboration Options for

msim_setup.tcl
Sometimes you may need to add custom compilation options to the vlog or vcom
commands that the dev_com and com commands call, or add your own elaboration
options to the elaboration commands called by the elab and elab_debug
commands.
To pass in custom Verilog HDL compilation options (which apply only to vlog
commands), you simply set the USER_DEFINED_VERILOG_COMPILE_OPTIONS
variable to the command-line options that you want to pass in. You set the
USER_DEFINED_VERILOG_COMPILE_OPTIONS variable before calling dev_com or
com.
The following example Tcl file shows passing in the Verilog HDL compilation option
+define+FAST_SIM:
...
source msim_setup.tcl
…
set USER_DEFINED_VERILOG_COMPILE_OPTIONS “+define+FAST_SIM”
dev_com
com
…
To pass in custom VHDL compilation options (which apply only to vcom commands),
set the USER_DEFINED_VHDL_COMPILE_OPTIONS variable to the command-line
options that you want to pass in, similar to the Verilog HDL example.
To pass in custom elaboration options (which only apply to vsim commands), set the
USER_DEFINED_ELAB_OPTIONS variable to the command-line options that you want
to pass in, as the following example Tcl file with the elaboration option -nocvg shows:
…
source msim_setup.tcl
dev_com
com
set USER_DEFINED_ELAB_OPTIONS “-nocvg”
elab
…
Related Information
Elaboration Options on page 19
3.5.5. Finding All Custom Variables

To find all variables that can be set in your script to customize the vlog or vcom
commands, search the msim_setup.tcl file for variable names in all capital letters.
As an example, the following are the lines for the variable TOP_LEVEL_NAME in
msim_setup.tcl:
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "my_ip1"
}
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3.6. Performing RTL Simulation with Questa Intel FPGA Edition

RTL simulation refers to simulating the design files that are the input for design
compilation in the Intel Quartus Prime software. All Intel Quartus Prime design files for
simulation must be available as Verilog HDL, SystemVerilog, or VHDL files. You must
first convert any schematic based files (such as .bdf) to HDL files for simulation
purposes.
Figure 7. Questa Intel FPGA Edition RTL Simulation Flow

1 3
Identify Files, Options, Libraries Map Logical Libraries
HDL 5
Sim File Elaborate Top Testbench
Files .qsys
“top”
Test
Bench
Determine
Simulator-Specific work
Elaboration Options Run Simulation
lib2 6
Compile Into Libraries
2 4
1. First identify all of the design files required for simulation, and for each file
determine any simulator specific compilation options, and the logical library to
compile into, as Compiling Files Into Library Directories on page 13 describes.
Note: This step is not necessary for RTL files that Platform Designer generates
because Platform Designer also generates a simulation script that compiles
all the IP RTL files into appropriate logical libraries.
2. Determine the simulator-specific elaboration options required for elaborating the
top-level testbench module, and the simulation commands to simulate the
module.
3. Map the logical library to the library directory by running the vmap Tcl command.
4. Use the vlog and vcom commands to compile the files into appropriate logical
libraries.
5. Use the vsim command to elaborate the top-level testbench. Refer to Elaboration
Command Examples on page 28.
6. Specify simulation commands, such as add wave or log, to capture the signal
waveforms. The run command runs the executable simulation model for the top-
level testbench generated by the elaboration. The quit command to ends the
simulation run.
Note: If simulating an IP example design, be aware that IP example designs for simulation
include a testbench to simulate the example design, and a simulation script that
executes all of the commands to perform compilation, elaboration, and simulation.
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3.6.1. Simulating an RTL Design without IP Variants or Platform Designer

Systems
The following describes simulation of an RTL design that does not include any IP
variants (.ip files) or Platform Designer Systems (.qsys files).
Files Required for RTL Simulation

• Your HDL design files and testbench files.
Note: Questa Intel FPGA Edition does not require the Intel Quartus Prime
simulation library files because these files are precompiled and included in
Questa Intel FPGA Edition.
As with any simulation, the RTL simulation flow consists of running simulator specific
commands in three stages: compilation, elaboration, and simulation. You can place
the compilation commands in one Tcl script, and the elaboration and simulation
commands in another Tcl script.
RTL Simulation—Compilation Stage
At the compilation stage, you compile your HDL design files and testbench files using
vlog and vcom commands, as Commands to Compile, Elaborate, and Simulate
describes.
Do NOT compile the library files using Questa Intel FPGA Edition. Instead, use the
precompiled Intel Quartus Prime simulation libraries included in Questa Intel FPGA
Edition, by specifying their logical names in the elaboration command. For more
details, refer to Why You Should Only Use Precompiled Questa Intel FPGA Edition
Libraries
RTL Simulation—Elaboration Stage
At the elaboration stage, you add one vsim command to elaborate the top-level
testbench and generate an in-memory executable simulation model. Elaboration
requires the top-level testbench module name, the logical library names for the
precompiled Intel Quartus Prime simulation libraries, and any logical library names
that you may have created when compiling your own design and testbench files.
To identify and use the logical library names for quartus simulation libraries:
1. Generate a Questasim simulation script for the appropriate device family, by
running the Simulation Library Compiler, as Running the Simulation Library
Compiler describes. The generated script contains the commands to compile the
Intel Quartus Prime simulation library files into appropriate logical libraries.
2. Obtain the logical library names of the precompiled Intel Quartus Prime simulation
libraries by inspecting the script generated in step 1, as Viewing Simulation Library
Compiler Output describes.
3. Specify the logical library names to the vsim command using the -L option, along
with any other elaboration options, as Elaboration Options on page 19 describes.
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RTL Simulation—Simulation Stage
At the simulation stage, you specify the simulation commands, such as add wave or
log, to capture the signal waveforms. You specify the run command to run simulation
(that is, to run the executable simulation model for the top-level testbench generated
by the elaboration command). Finally you specify the quit command to end the
simulation. The following three lines show an example of this:
add wave -r /*
run -all
quit
Refer to examples of common simulation commands in Simulation Command

Examples.
3.6.2. Simulating an RTL Design that has IP Variants or Platform Designer

Systems
Note: If you intend to simulate an Intel FPGA IP example design generated by Platform
Designer, be aware that the example design also includes a testbench to simulate the
example design, and a top-level simulation script that you can run to execute all the
commands to perform compilation, elaboration, and simulation. Refer to the IP user
guide or the IP Example Design user guide to generate the example design files for
simulation including a top-level simulation script.
The following describes simulation of an RTL design that includes IP variants (.ip
files) or Platform Designer systems (.qsys files).
Files Required for RTL Simulation

• Your HDL design files, Platform Designer generated IP RTL files, and testbench
files.
Note: Questa Intel FPGA Edition does not require the Intel Quartus Prime
simulation library files because these files are precompiled and included in
Questa Intel FPGA Edition. Rather, use only the precompiled libraries that
Questa Intel FPGA Edition includes, as Why You Should Only Use
Precompiled Questa Intel FPGA Edition Libraries describes.
As with any simulation, the RTL simulation flow consists of running simulator specific
commands in three stages: compilation, elaboration, and simulation. You can place
the compilation commands in one Tcl script, and the elaboration and simulation
commands in another Tcl script.
3.6.2.1. Compilation Stage - Simulation with IP

The following describes the compilation stage of RTL simulation with one or more IP
variants or Platform Designer systems in the design.
1. Compile your HDL design files and testbench files using vlog and vcom
commands, as section Commands to Compile, Elaborate, and Simulate describes.
2. Do NOT compile the Intel Quartus Prime simulation library files using Questa Intel
FPGA Edition. Instead use the precompiled Intel Quartus Prime simulation libraries
included in Questa Intel FPGA Edition by specifying their logical library names in
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the elaboration command, as Elaboration Command Examples on page 28

illustrates. Also refer to Why You Should Only Use Precompiled Questa Intel FPGA
Edition Libraries.
3. Generate a simulation script for compiling IP RTL files. You can generate a single
msim_setup.tcl simulation script that compiles IP RTL simulation files for all of
your IP variants (.ip files) and Platform Designer systems(.qsys files), as
Generating a msim_setup.tcl Simulation Script describes.
4. Source the generated msim_setup.tcl file in your compilation script as,
Example my_sim.tcl Simulation Script illustrates.
3.6.2.1.1. Customizing the Generated Simulation Script
You can customize the msim_setup.tcl simulation script that ip-setup-

simulation generates.
You may need to customize the simulation script to pass in non-default compilation
options to IP source files. You can accomplish this by setting Tcl variables in your top-
level Tcl script, as Passing In Custom Compilation and Elaboration Options for
msim_setup.tcl describes.
To obtain specific compilation options for an IP, if any, refer to the Platform Designer
generated top-level simulation script for the IP’s example design.
3.6.2.2. Elaboration Stage - Simulation with IP
The msim_setup.tcl simulation script that Platform Designer generates includes the
vsim elaboration command with all the logical library names for Intel Quartus Prime
simulation libraries, and any other elaboration options or simulation models that
specific Intel FPGA IP may require. You can use this elaboration command line as a
reference to build your own elaboration command.
Alternatively, you can call the elaboration command in your own Tcl script. You can
customize the script to elaborate your top-level testbench module, and pass in any
additional elaboration options, as necessary. Refer to Passing In Custom Compilation
and Elaboration Options.
Note: Some Intel FPGA IP may require additional elaboration options. While many of these
options are already present the generated msim_setup.tcl, some of the options
may only be in the Platform Designer generated top-level simulation script for the IP’s
example design.
3.6.2.3. Simulation Stage - Simulation with IP
During the simulation stage, you specify the simulation commands, such as add wave
or log, to capture the signal waveforms. You specify the run command to run
simulation (that is, to run the executable simulation model for the top-level testbench
generated by the elaboration command). Finally, you specify the quit command to
end the simulation. The following three lines show an example of the simulation stage
command:
add wave -r /*
run -all
quit
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3.7. Performing Gate-Level Simulation with Questa Intel FPGA

Edition
The Questa Intel FPGA Edition simulator supports the Intel Quartus Prime software
gate-level simulation libraries. The Intel Quartus Prime software can write gate-level
(technology mapped) netlists for simulation.
Gate-level simulation refers to simulating either a post-synthesis netlist or a post-fit

netlist of an FPGA design. For a description of post-synthesis and post-fit netlists, refer
to Post-Synthesis and Post-Fit Netlists for Simulation.
Figure 8. Gate-Level Simulation Steps

1 3
Generate Gate-Level Netlists
Determine
Elaboration Options
for Gate-Level Simulation
Simulation
Identify Files Running
HDL
Sim File
Files .qsys
“top”
Test
Bench
Run Simulation Script
Identify Compilation Options 4
2
The gate-level simulation flow includes the following steps:

• Step 1: Generate Gate-Level Netlists for Simulation
• Step 2: Identify Simulation Files and Compilation Options for Gate-Level
Simulation
• Step 3: Determine Elaboration Options for Gate-Level Simulation
• Step 4: Assemble and Run the Gate-Level Simulation Script
3.7.1. Post-Synthesis and Post-Fit Netlists for Simulation

During compilation, the Intel Quartus Prime Compiler first synthesizes the design into
a netlist (a set of module instances interconnected by wires) of low-level device family
specific ATOM blocks. This is also known as technology mapping. ATOMs are logical
representations of various Intel FPGA hardware blocks, such as lookup tables, DSPs,
and memory blocks. The netlist that results from Intel Quartus Prime synthesis is the
post-synthesis netlist. Refer to Intel Quartus Prime Simulation Library.
In the next stage of Intel Quartus Prime compilation, the Fitter takes the post-
synthesis netlist as input, and produces a place and route solution for the ATOMs in
the target FPGA that you specify. The netlist that results from place & route is the
post-fit netlist.
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The Intel Quartus Prime software can generate post-synthesis and post-fit netlists for
simulation in Verilog HDL or VHDL format as Step 1: Generate Gate-Level Netlists for
Simulation on page 41 describes. Generally, The post-fit netlist has associated
routing and cell (that is, ATOM) delays. However, the Intel Quartus Prime software
does not support simulating a post-fit netlist with timing delays. In other words, the
Intel Quartus Prime software supports post-fit functional simulation, but does not
support post-fit timing simulation.
3.7.2. Files Required for Gate-Level Simulation

Gate-level simulation of Intel Quartus Prime designs generally requires the following
minimum files:
• The post-synthesis or post-fit Verilog HDL (.vo) or VHDL (.vho) netlist file for the
design. You generate these files in the Intel Quartus Prime software. You generate
these files as Step 1: Generate Gate-Level Netlists for Simulation describes.
• Testbench related files, including the top-level testbench file that instantiates the
Intel Quartus Prime design, as Intel FPGA Simulation Essential Elements describes.
• The Intel Quartus Prime simulation library files. See the following important note.
Note: Do not compile the simulation library files for Questa Intel FPGA Edition. Rather, you
must use the precompiled libraries that the Questa Intel FPGA Edition installation
provides, by specifying their logical library names to the vsim command, as Finding
Logical Library Names in Simulation Library Compiler Output describes. To understand
why you must use precompiled libraries, refer to Why You Should Only Use
Precompiled Questa Intel FPGA Edition Libraries.
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3.7.3. Step 1: Generate Gate-Level Netlists for Simulation

The Intel Quartus Prime EDA Netlist Writer (quartus_eda on the command line)
allows you to write gate-level (technology mapped) netlists for simulation and other
applications.(8)
The EDA netlist writer can generate a Verilog Netlist (.vo file) or a VHDL Netlist (.vho
file) for the following types of design ports:
• Single-bit signal types
• One-dimensional arrays
• Two-dimensional arrays
The EDA Netlist Writer does not support complex data types, such as enums, stucts,
unions, or interfaces, at the external boundary of the design or the design partition.
To the run the EDA Netlist Writer GUI to generate a gate-level netlist for simulation:
1. In the Intel Quartus Prime software, click Assignments ➤ Settings ➤ EDA Tool
Settings to specify generation options for the Questa Intel FPGA Edition simulator.
Figure 9. Specifying EDA Netlist Writer Settings for Questa Intel FPGA Edition
2. To compile your design to the desired stage, perform one of the following:
• To generate the post-synthesis netlist for simulation, double-click Analysis &
Synthesis on the Compilation Dashboard
• To generate the post-fit netlist for simulation, double-click Fitter on the
Compilation Dashboard.
(8) Gate-level simulation can be slower and harder to debug for larger designs and therefore may
not be suitable as the primary means of validation.
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Figure 10. Compiler Stages in Compilation Dashboard
3. To start EDA Netlist Writer, click EDA Netlist Writer on the Compilation
Dashboard. The EDA Netlist Writer generates the netlist, according to your
specifications from step 1.
Figure 11. EDA Netlist Writer Command in Compilation Dashboard
Alternatively, you can start the EDA Netlist Writer by running the quartus_eda
command in a shell, with a set of command-line options that specify the type of netlist
to produce. To view all the command line options related to simulation, run
quartus_eda –-help=simulation.
Table 9. quartus_eda Command Options

quartus_eda Options Option Description
--simulation Specifies generation of a Verilog (.vo) or VHDL (.vho) gate-level

simulation netlist.(9)
--tool Specifies the supported simulator that reads the netlist. Supported
options are:
• modelsim, questa_oem, vcs, vcs_mx, xcelium,
rivierapro, activehdl, verilogxl.
--format Specifies the supported language format of the simulation output

gate-level netlist. Supported options are verilog or vhdl.
--resynthesis Specifies that quartus_eda creates a Verilog Quartus Map (.vqm)

netlist. The software can resynthesize the netlist as an RTL input,
from the gate-level netlist. Only use this option with partitions
containing core logic only, not periphery. The sub-option is a flag
only and takes no arguments.
continued...
(9)
This option overrides any Intel Quartus Prime Settings File (.qsf) setting.
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quartus_eda Options Option Description
--partition Specifies an individual partition by name for netlist output. For no

partition argument, the entire design writes out to a single file. The
partition argument takes the name of a partition in the design. You
can use the --partition option with the --simulation
(.vo, .vho) and --resynthesis (.vqm) output.
--exclude_sub_partitions Flag that limits the output to the netlist for the partition you specify.
This flag is only valid with the --partition option. The software
instantiates subpartitions as module instances in the netlist. The
sub-option is a flag only and takes no arguments.
You can specify the root_partition as the partition name in the
--partition option to get the top level partition, which is useful
when using the --exclude_sub_partitions flag.
--module_name Renames a partition in the output netlist file. By default, the

software uses the partition name as the module name in the netlist
file. This option is only valid when you use the --partition
option. You can rename any module using --
module_name=abc=xyz.
The output netlist file name format is: <revision>.<partition
name>.<vo or vho>. By default, the Intel Quartus Prime software
writes the netlist file to the simulation directory (for example,
simulation/questa), unless you specify an output_directory
(using a command line option or .qsf assignment).
Related Information
• Intel Quartus Prime Pro Edition User Guide: PCB Design Tools
• Generating a VQM Netlist for other EDA Tools
3.7.4. Step 2: Identify Simulation Files and Compilation Options for Gate-
Level Simulation
Before you can elaborate the top-level testbench module (that instantiates the gate-
level netlist module), you must determine the appropriate logical library and simulator
specific options for compilation, similar to the examples that Elaboration Command
Examples on page 28 illustrates.
The .vo and .vho netlist files generated by the Intel Quartus Prime software
generally do not require specific compilation options.
3.7.5. Step 3: Determine Elaboration Options for Gate-Level Simulation

You must specify the logical library names of Intel Quartus Prime simulation libraries
to the vsim command, as Finding Logical Library Names in Simulation Library
Compiler Output.
You can additionally choose the simulator specific options to elaborate the top-level
testbench module as you wish. However, there are some specific elaboration options
required to simulate some of the Intel FPGA IP.
The .vo and .vho netlist files generated by the Intel Quartus Prime software
generally do not require specific compilation options.
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3.7.6. Step 4: Assemble and Run the Gate-Level Simulation Script

Once you determine the compilation options and logical library name for each
simulation file, you can create the vsim elaboration command. You can then create a
Tcl script containing the appropriate commands to compile, elaborate, and simulate
the design, as the following example Tcl script for gate-level simulation illustrates.
In this example, the post-fit verilog netlist is top.vo, the testbench file is test.sv,
and the top-level testbench module is test. All files compile into the work library.
vlog -sv top.vo test.sv
vsim -t ps -L work test
add wave -r /*
run -all
quit
You can save the script as sim.tcl, and run sim.tcl in the Questa Intel FPGA
Edition GUI using the vsim -do sim.tcl command.
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Send Feedback
4. Revision History for Questa Intel FPGA Edition

Simulation User Guide
Document Version Intel Quartus Changes
Prime Version
2023.06.26 23.2 • Updated version numbers in Simulator Versions and Licensing topic.
• Added new Comparing Simulator Versions topic.
2023.06.07 23.1 • First version of document.
4.1. Questa Intel FPGA Edition Simulation User Guide Archive

For the latest and previous versions of this user guide, refer to Questa Intel FPGA
Edition Simulation User Guide. If an IP or software version is not listed, the user guide
for the previous IP or software version applies.
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A. Intel Quartus Prime Pro Edition User Guides

Refer to the following user guides for comprehensive information on all phases of the
Intel Quartus Prime Pro Edition FPGA design flow.
Related Information
• Intel Quartus Prime Pro Edition User Guide: Getting Started
Introduces the basic features, files, and design flow of the Intel Quartus Prime
Pro Edition software, including managing Intel Quartus Prime Pro Edition
projects and IP, initial design planning considerations, and project migration
from previous software versions.
• Intel Quartus Prime Pro Edition User Guide: Platform Designer
Describes creating and optimizing systems using Platform Designer, a system
integration tool that simplifies integrating customized IP cores in your project.
Platform Designer automatically generates interconnect logic to connect
intellectual property (IP) functions and subsystems.
• Intel Quartus Prime Pro Edition User Guide: Design Recommendations
Describes best design practices for designing FPGAs with the Intel Quartus
Prime Pro Edition software. HDL coding styles and synchronous design
practices can significantly impact design performance. Following recommended
HDL coding styles ensures that Intel Quartus Prime Pro Edition synthesis
optimally implements your design in hardware.
• Intel Quartus Prime Pro Edition User Guide: Design Compilation
Describes set up, running, and optimization for all stages of the Intel Quartus
Prime Pro Edition Compiler. The Compiler synthesizes, places, and routes your
design before generating a device programming file.
• Intel Quartus Prime Pro Edition User Guide: Design Optimization
Describes Intel Quartus Prime Pro Edition settings, tools, and techniques that
you can use to achieve the highest design performance in Intel FPGAs.
Techniques include optimizing the design netlist, addressing critical chains that
limit retiming and timing closure, optimizing device resource usage, device
floorplanning, and implementing engineering change orders (ECOs).
• Intel Quartus Prime Pro Edition User Guide: Programmer
Describes operation of the Intel Quartus Prime Pro Edition Programmer, which
allows you to configure Intel FPGA devices, and program CPLD and
configuration devices, via connection with an Intel FPGA download cable.
• Intel Quartus Prime Pro Edition User Guide: Block-Based Design
Describes block-based design flows, also known as modular or hierarchical
design flows. These advanced flows enable preservation of design blocks (or
logic that comprises a hierarchical design instance) within a project, and reuse
of design blocks in other projects.
A. Intel Quartus Prime Pro Edition User Guides
730191 | 2023.06.26
• Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration

Describes Partial Reconfiguration, an advanced design flow that allows you to
reconfigure a portion of the FPGA dynamically, while the remaining FPGA
design continues to function. Define multiple personas for a particular design
region, without impacting operation in other areas.
• Intel Quartus Prime Pro Edition User Guide: Third-party Simulation
Describes RTL- and gate-level design simulation support for third-party
simulation tools by Aldec*, Cadence*, Siemens EDA, and Synopsys that allow
you to verify design behavior before device programming. Includes simulator
support, simulation flows, and simulating Intel FPGA IP.
• Intel Quartus Prime Pro Edition User Guide: Third-party Synthesis
Describes support for optional synthesis of your design in third-party synthesis
tools by Siemens EDA, and Synopsys. Includes design flow steps, generated
file descriptions, and synthesis guidelines.
• Intel Quartus Prime Pro Edition User Guide: Third-party Logic Equivalence
Checking Tools
Describes support for optional logic equivalence checking (LEC) of your design
in third-party LEC tools by OneSpin*.
• Intel Quartus Prime Pro Edition User Guide: Debug Tools
Describes a portfolio of Intel Quartus Prime Pro Edition in-system design
debugging tools for real-time verification of your design. These tools provide
visibility by routing (or “tapping”) signals in your design to debugging logic.
These tools include System Console, Signal Tap logic analyzer, system
debugging toolkits, In-System Memory Content Editor, and In-System Sources
and Probes Editor.
• Intel Quartus Prime Pro Edition User Guide: Timing Analyzer
Explains basic static timing analysis principals and use of the Intel Quartus
Prime Pro Edition Timing Analyzer, a powerful ASIC-style timing analysis tool
that validates the timing performance of all logic in your design using an
industry-standard constraint, analysis, and reporting methodology.
• Intel Quartus Prime Pro Edition User Guide: Power Analysis and Optimization
Describes the Intel Quartus Prime Pro Edition Power Analysis tools that allow
accurate estimation of device power consumption. Estimate the power
consumption of a device to develop power budgets and design power supplies,
voltage regulators, heat sink, and cooling systems.
• Intel Quartus Prime Pro Edition User Guide: Design Constraints
Describes timing and logic constraints that influence how the Compiler
implements your design, such as pin assignments, device options, logic
options, and timing constraints. Use the Interface Planner to prototype
interface implementations, plan clocks, and quickly define a legal device
floorplan. Use the Pin Planner to visualize, modify, and validate all I/O
assignments in a graphical representation of the target device.
• Intel Quartus Prime Pro Edition User Guide: PCB Design Tools
Describes support for optional third-party PCB design tools by Siemens EDA
and Cadence*. Also includes information about signal integrity analysis and
simulations with HSPICE and IBIS Models.
• Intel Quartus Prime Pro Edition User Guide: Scripting
Describes use of Tcl and command line scripts to control the Intel Quartus
Prime Pro Edition software and to perform a wide range of functions, such as
managing projects, specifying constraints, running compilation or timing
analysis, or generating reports.
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Questa* Intel® FPGA Edition

Simulation User Guide

Answers to Top FAQs:

Online Version 730191

1. Introduction to the Questa* Intel® FPGA Edition Simulator............................................ 4

Questa* Intel® FPGA Edition Simulation User Guide Send Feedback

3.7.5. Step 3: Determine Elaboration Options for Gate-Level Simulation................... 43

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1. Introduction to the Questa* Intel® FPGA Edition

This document organizes information into the following chapters:

1.1. Simulator Versions and Licensing

Other Supported Third-Party Simulators

Table 2. Intel Quartus Prime Pro Edition Supported Simulators

Aldec Active-HDL* 13.0 Windows* 64-bit No

Aldec Riviera-PRO* 2023.04 Windows, Linux, 64-bit No

Cadence Xcelium* Parallel Simulator 22.09.001 Linux 64-bit Yes

Siemens EDA QuestaSim* Simulator(2) 2022.4 Windows, Linux, 64-bit Yes

Synopsys* VCS*, VCS MX T-2022.06- Linux 64-bit Yes

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1.1.1. Comparing Simulator Versions

Table 3. Simulator Performance Comparison

Features Same as Questa Core Same as Questa Core Full featured

Performance 2-6X slower than 40% slower than Full performance

Capacity Maximum of 5000 Maximum of 5000 No limit

1.2. Accessing Siemens EDA-Provided Simulator Documentation

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1.3. Document Prerequisites

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2. Intel FPGA Simulation Basics

2.1. Intel FPGA Simulation Essential Elements

An Intel Quartus Prime design typically consists of a top-level design module

HDL Design and Testbench Files

Executable Simulation Model

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2.2. Overview of Simulation Tool Flow

You run simulator specific commands at each stage in the flow.

2.2.1. Compilation Stage

Inputs to a Compilation Command

What Does a Compilation Command Do?

A compilation command does the following:

Compilation Command Example

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2.2.2. Elaboration Stage

Figure 3. Elaboration Stage Inputs and Output

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2.2.3. Simulation Stage

Figure 4. Files and Directories for Executable Model of my_top_tb

2.3. Simulation Tool Flow

2.3.1. Specifying Logical Libraries

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A logical library name is an optional argument to many simulator commands. If you do

Note: syntax of library mapping file varies with simulator

2.3.1.1. Why Do We Need Logical Library Names?

Using logical library names instead of physical directory names in command

2.3.2. Compiling Files Into Library Directories

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2.3.2.1. Inputs to Compilation Commands

Compilation commands accept the following inputs: