Computer Architecture- Model Questions for Internal

1. Define and give mathematical expressions for CPI, MIPS rate, Amdahl’s Law in context of Speed-
up.
2. Explain with the timing diagram, the effect of conditional branch on instruction pipeline
operation. Discuss other drawbacks of pipeline.
ANS-
Instruction pipelining is a technique used in the design of modern microprocessors,
microcontrollers, and CPUs to increase their instruction throughput—that is, the number of
instructions that can be executed in a unit of time.

When a branch instruction moves from the fetch stage to the execute stage, the fetch stage gets the
next instruction in memory after the branch. If the branch is not taken, no time is wasted. If the branch
is taken, the fetched instruction must be thrown out and a new one fetched. To go faster, the pipeline
needs more stages. Let's look at breaking down the instruction processing further.

1. Fetch instruction (FI): Get the next instruction into a temporary storage.
2. Decode instruction (DI): Understand what the instruction is telling the computer to do.

3. Calculate operands (CO): Figure out the data addresses the instruction needs to use.
4. Fetch operands (FO): Retrieve the data from memory that the instruction needs.

5. Execute instruction (EI): Actually perform the operation the instruction asks for.
6. Write operand (WO): Store the result of the operation back into memory.
The diagram shows that using these 6 pipeline stages can reduce the time for 9 instructions from 54
units to 14 units.

The FO and WO stages access memory. If the six stages are not equal in time, there will be
some waiting at different pipeline stages. Another problem is the branch instruction, which can
make several instruction fetches invalid. Interrupts are a similar unpredictable event.

The example shows the effects of the branch instruction, using the same program as before. Let's
say instruction 3 is a branch to instruction 15, but we don't know until it's executed. The pipeline
here just loads the next instruction (4) and keeps going.

The drawbacks of pipelining:

• Pipeline Stalls: Delays when waiting for data from previous stages.
• Complexity: More intricate system design and harder maintenance.
• Overhead Costs: Extra resources needed for managing stages.
• Parallelization Issues: Some tasks can’t be effectively parallelized.
• Scaling Limits: Adding more stages eventually leads to less benefit.
Computer Architecture- Model Questions for Internal

3. Discuss Different Hazard in instruction pipeline with timing diagram and examples.
ANS-
i. Structural Hazards: These take place when many instructions concurrently use the same
hardware resource. A structural risk appears, for instance, when two instructions must
access the memory unit simultaneously. Conflict and execution delays may result from this.

ii. Data Hazards: When there is a reliance between instructions that impacts how they are
executed, data risks occur. A data risk, for instance, might happen when one instruction
depends on the outcome of an earlier instruction that hasn’t been finished yet. This can
result in mistakes or delays.

iii. Control Hazards: Control risks emerge as a result of the programmes’ branching structure.
The pipeline is required to foresee the result of a conditional branch instruction before it is
actually executed. Incorrect predictions result in control hazards, which waste cycles.

4. Derive the formula for speed-up of K-Stage pipeline. (Do the numerical given in assignment.)
5. Discuss in brief various branch prediction techniques to optimize the performance of pipeline
with neat diagrams.
6. Discuss with neat diagrams Set-Associative cache organisation.
7. Discuss with neat diagrams Direct Mapped cache organisation.
ANS-

DIRECT MAPPING
In direct mapping cache, instead of storing total address information with data in
cache only part of address bits is stored along with data.
The new data has to be stored only in a specified cache location as per the mapping
rule for direct mapping. So it doesn't need replacement algorithm.

8. Discuss with neat diagrams Associative Mapped cache organisation.

ANS-

ASSOCIATIVE MAPPING
Computer Architecture- Model Questions for Internal

In associative mapping both the address and data of the memory word are stored.
The associative mapping method used by cache memory is very flexible one as well
as very fast.
This mapping method is also known as fully associative cache.