METHODOLOGY

Design Specifications
 Specify the working and requirements of the processor.
 Designing the 16-bit processor with data and instruction memory.
 The instruction sets like arithmetic operations, error checker and logical operations
are designed.
 Design two separate instruction and data memory modules.
 Design the Finite State Machine (FSM) as control logic to control the execution steps.

Design of various modules

1. Processor
 Define the inputs ‘DIN’, ‘Resetn’, ‘Clock’, ‘Run’ and ‘err_process_mem’.
 Define the outputs ‘DOUT’, ‘ADDR’, ‘IM’, ‘DM’, ‘DONE’ and ‘W_D’.
 Define the internal registers and wires ‘Gin’, ‘Ain’, ‘Addsub’, ‘IR_in’,
‘ADDR_in’, ALU_and, ‘rX_in’, ‘pc_incr’, ‘DOUT_in’, ‘sp_decr’, ‘sp_incr’ and
‘pc_in’. These are the control signals for various operations.
 ‘Tstep_D’ and ‘Tstep_Q’ registers are used for FSM control and ‘Select’ register
used for the multiplexer select signal.
 ‘IR’, ‘BusWires’, ‘A’ and ‘data_out’ are used as data registers, and the ‘G’ as ALU
output.
 We define the flags such as ‘z’ for zero, ‘n’ for negative and ‘c’ for carry.
 For enable the registers we define ‘R_in’ signal.
 Define the ‘III’, ‘rX’ and ‘rY’ are as instruction fields.
 ‘shift_type’ is used for specify the type of shift operation.
FSM logic
Using different instructions and control signals define the 6 states of FSM (T0
to T5) and their transitions.
 Implement the registers for storing the intermediate values and results and also the
arithmetic and logical operations.
 Bus wires are designed for transfer the data between the other parts of the
processor.
 The next step (‘Tstep_D’) id determined on the basis of current step(‘Tstep_Q’).
 We load appropriate data into internal buses on the basis of select line.
Control FSM Flip-Flop
We define two always blocks,
The first always block is triggered at positive edge of clock or the falling edge of
‘Resetn’ or falling edge of ‘clock’. If ‘Resetn’ is low or if there is an ‘err’ or
‘err_process_mem’ resets ‘Tstep_Q’ to ‘3’b000’. Otherwise, it sets ‘Tstep_Q’ to the
value of ‘Tstep_D’.
The second always block triggers at any change in the inputs. And it calculates
checksum of the lower 16 bit of ‘IR’. And if the check sum is does not match the
 upper 8 bits of ‘IR’. Set ‘err’ as 1’b1, otherwise set ‘err’ to 1’b0. This is the error
detection we can implement the hamming code for error the correction.

2. Decoder
 Implement 3-bit input (w) and 8-bit one encoded output (y) for decode the register
addresses when enable E is active.
3. Register
 Implement a 16 bit register with input as ‘Buswires’, ‘Resetn’, ‘r_in’, ‘Clock’,
‘pc_incr’, ‘sp_decr’, ‘sp_incr’. And output as 16-bit ‘r’.
 If ‘Resetn’ is low the ‘r’ is set as 0x0000. If ‘r_in’ is high then load the value from
Bus wires into registers.
 Else it checks the program counter (‘pc_incr’) if it is high increment the value of r
by 1. Else it checks the stack pointer decrement (‘sp_decr’) if it is high, decrement
the value of r by 1.
 In last it checks the stack pointer increment (‘sp_incr’) if it is high, increment the
value of r by 1.
4. Instruction memory
 Define the inputs such as ‘Address’ of 16 bits, ‘data’ of 24 bit, write
enable(‘wren’), ‘IM’ and ‘clock’. And the output as ‘q’. Implement read and write
functionality based on these inputs, this is designed for selecting the multiple pre-
defined instruction sets.
5. Data memory
 Define the inputs such as ‘Address’ of 16 bits, ‘data’ of 24 bit, ‘DM’, write
enable(‘wren’) and ‘clock’. And the output as ‘q’ of 24 bit. Based on these we
implement the read and write operations.

Integration
 Define the top processor module as “processor_top_module_new_harv_err_ctr1”, in
which we will integrate the individual modules to form a core system.
 Model the processor, instruction memory and data memory modules, and connect the
internal signals by ‘DIN1’, ‘DIN2’, ‘DOUT’, ‘ADDR’, ‘IM’, ‘DM’, ‘W_D’ and
‘err_process_mem’.
 The output of instruction and data memory are merged to form single input ‘DIN’ to
the processor.

Testing
 This is the functionality verification of integrated system. Here we will verify the
integrated system by using testbench.
 The testbench signals ‘Clock_tb’, ‘Resetn_tb’ and ‘Run_tb’ are initialized.
 Start the processor by applying the reset. And implement a clock signal generator.
 Run the simulation to observe the behaviour and functionality of the designed
processor.

Verifying and Debugging

  Verification of functionality: - Assuring that all the instructions are executed
correctly. And check the interaction between processor and memory modules.
 Debugging: - Identify the issues related to the control signals, timing or data handling
and fix them.

Block Diagram