ASIC Design Flow

VLSI DESIGN
TYPES OF VLSI IMPLEMENTATION

ASIC Implementation
 FPGA Implementation

TYPES OF VLSI DESIGN

Front End Design / Logic Design

 Back End Design / Physical Design
Design Hierarchy
 ASIC Design Flow
System Specification

Partitioning
ENTITY test is
Architectural Design
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design

Circuit Design Placement

Physical Design Clock Tree Synthesis

Physical Verification
DRC
LVS and Signoff Signal Routing
ERC

Fabrication
Timing Closure
Packaging and Testing

Chip

4
 1. Design Entry / Options

Schematic Design
Hardware Description Language (HDL) Based Design
 Schematic Design
SPICE
•Small Design
PSPICE •Transistor Based Design
TSPICE
HSPICE
Hardware Description Language
(HDL)
 Why Hardware Description
Language (HDL) ?

•Large Design
•Gate Based Design
2. Logic Synthesis
 Elements of Logic Synthesis
 It is the process converting of high level description into gate level netlist.

 HDL Code to Netlist.

 Netlist- Interconnection between nodes. (Description of Logic Cells and their

interconnections)

 Synthesizer – Tool to Perform Synthesis

Synthesize Platform
 Physical Design Cycle/Flow
 The input of the physical design cycle is a circuit diagram and
the output is the layout of the circuit.

Circuit Partitioning

Floorplanning & Placement
Deadspace

Routing

v
Layout Compaction

Extraction and Verification

Basic scheme of cell-based design

 Planning on
chip area
Basic scheme of cell-based design

to place cells

area to route wires

 Mapping logical
Placement
gates (cells) onto
locations for cells
Routing

route wires
Lee Maze Routing
Lee Maze Routing
Contd..,
 Partitioning – Divide a large system into ASIC sized pieces

 Prelayout Simulation – Check to see if the design functions correctly

 Floor planning- area of each block can be estimated & arrange the blocks of
netlist on the chip
 Placement- Decide the exact locations of cells in a block

 Routing- Make the interconnections between modules

 Extraction – Determine the resistance and capacitance of the Interconnect

 Post Layout Simulation - Check to see the design still works with the added
loads of the interconnect
 Physical verification

Physical verification is a process whereby an IC layout design is

checked via EDA software tools to see if it meets certain criteria.

Verification involves DRC (Design rule check),

 LVS (Layout versus schematic),
ERC (Electrical Rule Check)
Parasitic Extraction
 DRC Check
•The Design Rule Checker helps ensure that a layout design conforms to the
physical constraints required to produce it.

•These constraints can be a requirement of the design itself, such as reducing

noise, or a requirement of the process used to produce the design.

Steps
• Define or select a design rule.
• Run the design check using the defined or selected rule.
• Load the results.
• View any errors that were found.
 ERC Check
 ERC (Electrical rule check) involves checking a design for all electrical
connections that are considered dangerous. This might include checking for

• well and substrate areas for proper contacts and spacing thereby ensuring
correct power and ground connections.
• unconnected inputs or shorted outputs.
• gates connected directly to supplies.

LVS Check

LAYOUT VERSUS
SCHEMATIC
 LVS Check
 Layout Versus Schematic (LVS) is the class of electronic design automation (EDA) verification
software that determines whether a particular integrated circuit layout corresponds to the original
schematic or circuit diagram of the design.

 Comparison: The extracted layout netlist is then compared to the netlist taken from the
circuit schematic. If the two netlists match, then the circuit passes the LVS check.

Used to Find out

•Shorts: Two or more wires that should not be connected have been and must be separated.

•Opens: Wires or components that should be connected are left dangling or only partially
connected. These must be connected properly to fix this.

•Component Mismatches: Components of an incorrect type have been used (e.g. a low Vt
MOS device instead of a standard Vt MOS device)

•Missing Components: An expected component has been left out of the layout.

•Parameter Mismatch: Components in the netlist can contain properties.

 Parasitic Extraction

 Parasitic extraction is extracting

internal capacitance and resistances
effects in both the designed devices and the
required wiring interconnects of an electronic
circuit.

 Detailed device parameters, parasitic

capacitances, parasitic resistances and parasitic
inductances, commonly called parasitic
devices, parasitic components, or simply
parasitic.
 Mask Generation – GDSII / Stream

Physical
design
Data GDSII (Stream)

GDS- Graphic Database System

Masks

Wafer

30
 JOB OPPORTUNITIES - AREAS

opportunities
 Summary
•Logic Synthesis - RTL to Netlist.

• Netlist- Interconnection between nodes. (Description of Logic Cells and

their interconnections)

• Physical Synthesis – Netlist to Layout

• Physical verification is a process whereby an IC layout design is checked

via EDA software tools

• Parasitic extraction is extracting internal capacitance and resistances

• Tape Out Format of ASIC Flow - GDSII (Graphic Database System

Information Interchange)
THANK YOU