BIT102 SLM Library - SLM - Unit 08

Digital Electronics Unit 8
Unit 8 Combinational Circuits – Part II

Structure:
8.1 Introduction
Objectives
8.2 BCD adder and BCD Subtractor
8.3 Parity Checker/Generator
8.4 Multiplexer and Demultiplexer
8.5 Encoder and Decoders
Encoder and Priority Encoder
Decoder
8.6 BCD to Seven Segment Display Decoder/Driver
8.7 Magnitude Comparators
8.8 Summary
8.9 Terminal Questions
8.10 Answers
8.1 Introduction
In the previous unit we studied the basics of combinational circuits. We have
also studied some of the combinational circuits like adders, subtractors,
ripple carry adders and other related concepts. In this unit we study some
other combinational circuits. We study BCD adder and BCD subtractors,
Parity Checker/Generator, Multiplexer and Demultiplexer, encoders,
decoders. We also study BCD to Seven segment display decoder.
Objectives:
After studying this unit, you should be able to:
 explain the working of BCD adders and subtractors
 attribute the requirement of parity checker
 describe the functions of multiplexers and demuliplexers
 illustrate the function of encoder and decoder
 describe the function of BCD to Seven segment Display Decoder/Driver
 define the function of comparator and explain the operation of two bit
comparator.
Sikkim Manipal University B2072 Page No.: 193

8.2 BCD adder and BCD Subtractor

BCD adder is a circuit that adds two BCD digits and produces sum output
digit which is also a BCD.
The figure 8.1 shows the block diagram of BCD adder.
Figure 8.1: BCD adder
The two BCD numbers along with input carry are added in the top 4 bit
binary adder1 to produce binary sum. When output carry is equal to zero
(i.e. when sum ≤ 9 and Cout=0), 0(zero) is added to the binary sum. When it
is equal to one (i.e. when sum > 9 or Cout=1), binary 0110 is added to the
binary sum through the bottom 4 bit binary adder 2. The output carry
generated from bottom binary adder 2 can be ignored because it supplies
information already available at the output carry terminal.
BCD Subtractor:
A BCD subtractor is a circuit that subtracts two BCD digits and produces
difference output digit which is also a BCD. This BCD subtractor does the
subtraction using either 9’s complement method or 10’s complement
method. So let us see the concept 9’s complement and 10’s complement
before explaining the operation of BCD subtractor.
The nines' complement of a number is obtained by subtracting each

digit by 9.
For example, 9’s complement of a number 5 is 9-5 =4. So 4 is the answer
Similarly, 9’s complement of 564 = (999-564) = 435. So 435 is the answer.
10’s complement of a number is formed by obtaining 9’s complement of a
number and adding 1 to the 9’s complement.
Therefore, 10‘s complement = 9’s complement +1.
For example, 10’s complement of a number 5 is 9-5 =4 +1 =5 where 4 is
the 9’s complement of 5.
Similarly, 10’s complement of 564 = (999-564)+1= 435+1=436. So 436 is
the answer.
Subtraction using 9’s complement:
Subtraction using 9’s complement is obtained as follows
1) Find 9’s complement of a negative number (i.e. subtrahend)
2) Add the minuend to it. i.e. first number
3) If carry is generated, add the carry to the result, otherwise, find the 9’s
complement of the result.
The figure 8.2 shows the logic diagram to perform BCD subtraction using
9’s complement method.

Figure 8.2: BCD Subtractor using 9’s complement method
The first binary adder finds the 9’s complement of a negative number
(i.e. subtrahend). It does this by inverting each bit of BCD number and
adding decimal 10(1010) to it. Let us find 9’s complement of 2.
0010 : BCD for 2
1101 : inverting each bit
+ 1010 : Add 102(1010)
__________________
10111 : 9’s complement of 2.
(Carry ignored)
Next two binary adders perform the BCD addition. The last adder finds the
9’s complement of the result if the carry is not generated; otherwise, it adds
carry to the result.
Subtraction using 10’s complement:
Subtraction using 10’s complement is obtained as follows:
1) Find 10’s complement of a negative number (i.e. subtrahend)
2) Add it the minuend. i.e., first number
3) If carry is generated, ignore the carry, otherwise, find the 10’s
complement of the result.
The figure 8.3 shows the logic diagram to perform BCD subtraction using
10’s complement method.
Figure 8.3: BCD Subtractor using 10’s complement method

The first binary adder finds the 10’s complement of a negative number
(i.e. subtrahend). (i.e., 9’s complement +1). Next two 4 bit binary adders
perform the BCD addition. The last 4-bit binary adder finds the 10’s
complement of the result if the carry is not generated; otherwise, carry bit of
the result is ignored.
Self-Assessment Questions
1. BCD adder is a circuit that adds two BCD digits and produces sum
output digit which is also a BCD. (State true or false)
2. BCD subtractor does the subtraction using either _______ complement
method or __________ complement method.
3. _____________ of a number is formed by obtaining 9’s complement of
a number and adding 1 to the 9’s complement.
8.3 Parity Checker/Generator

In digital system it is often required to reduce the probability of errors during
the transmission of digital data by using parity generator/checker. A circuit
that generates parity bit in the transmitter is called parity generator and the
circuit which checks parity in the receiver is called parity checker. Parity
generator is of two types. They are odd parity generator and even parity
generator. The parity checker circuit produces a check bit and is very similar
to the parity generator circuit. If the check bit is 1, then it is assumed that the
received data is incorrect. The check bit will be 0 if the received data is
correct.
A parity bit is used for the purpose of detecting errors during the
transmission of binary information. A parity bit is an extra bit attached with a
binary message to make the total number of 1's either odd or even. In case
of even parity, the parity bit is chosen so that the total number of 1's in the
coded message is even. In case of odd parity, the parity bit is chosen so
that the total number of 1's in the coded message is odd.

The figure 8.4 shows the block diagram of a 4 bit parity checker/generator.
Figure 8.4: Block diagram of a 4 bit parity checker/generator
The table 8.1 shows the parity genertor/checker bits for digital data.
Table 8.1: Parity genertor /checker bits for digital data
When used as a parity checker:

If Po=0, the parity of A, B, C, D, Pi is odd.
If Po=1, the parity of A, B, C, D, Pi is even.
When used as a parity generator:
For odd parity, A, B, C, D, Po, Pi should be 0.
For even parity, A, B, C, D, Po, Pi should be 1
Exclusive – OR gates are useful for generating and checking a parity bit that
is used for detecting/correcting errors during the transmission of binary data
over communication channels.
Now let us consider truth table for even parity checker shown in the
table 8.2.

Table 8.2: Truth table for even parity checker
The K –map for Pe is given as follows.

The figure 8.5 shows the logic diagram of even parity generator/checker.
Figure 8.5: Logic diagram of even parity generator/checker
The four bits in the message together with parity bit are transmitted to the
destination where they are applied to the parity checker circuit. The parity
checker circuit checks for possible errors in the transmission. Suppose even
parity is used at the transmitter, then the bits received should have even
number of 1’s. This is indicated by E=0. If error occurs during transmission,
then E=1 indicating error in the received message.
Similarly we can generate the circuit for odd parity generator /checker as
shown in figure 8.6.

Figure 8.6: Logic diagram of odd parity generator/checker
Activity 1:
Generate an even parity generator/checker for the transmission of the
binary data 1010101?
4. A _________ bit is an extra bit attached to a binary message to make
the total number of 1's either odd or even.
5. _______________ gates are useful for generating and checking a
parity bit that is used for detecting/correcting errors during transmission
of binary data over communication channels.
8.4 Multiplexer and Demultiplexer

Multiplexing is the operation of sending one or more analog or digital signals
over a common transmission line at different times or speeds and as such,
the device we use to do that is called a Multiplexer or Mux. A multiplexer
accepts many inputs but gives only one output. On the other hand, a
demultiplexer functions exactly in the reverse way of a multiplexer. A
demultiplexer accepts only one input and gives many outputs. Generally

multiplexer and demultiplexer are used together, for the communication

systems that are bi- directional.
A device that performs the multiplexing is called a multiplexer (MUX), and a
device that performs the reverse process is called a demultiplexer (DEMUX
or DMX). One of the applications of multiplexing is in computer networks,
where in multiple digital data streams are combined into one signal over a
shared medium. The aim is to share an expensive resource.
Now let us study digital multiplexers and demultiuplexers in the following
sections.
Multiplexer:
Multiplex means many to one. The multiplexer, or “MUX” is a combinational
logic circuit designed to switch one of several input lines to a single common
output line by the application of a control signal or select line. In other
words, Multiplexer is a combinational logic circuit that can select one of
many inputs and send it to the single output.
Multiplexers operate like very fast acting multiple position rotary switches
connecting or controlling multiple data input lines called “channels” one at a
time to the output. This concept is shown in figure 8.7.
Figure 8.7: Multiplexer as a switch
In the figure 8.7, the data select switch selects one of the available
inputs I1 to In and send it to the single output line Y. So, multiplexer acts like
a switch that has multiple inputs and single output (refer to figure 8.7 (b)).
Multiplexers are also known as data selectors because they can “select”
data of each input line. Generally, the selection of each input line in a

multiplexer is controlled by an additional set of inputs called control lines or

select lines. And according to the binary condition of these control inputs,
either “HIGH” or “LOW” the appropriate data input is connected directly to
the output.
The schematic symbol for a multiplexer is an isosceles trapezoid as shown
in figure 8.8.
Figure 8.8: Symbol for a multiplexer
Inputs I0, I1, … In-1 are connected to the multiplexer on the longer parallel
side and output Y is connected on short parallel side. But people may use
rectangular symbol for convenience.
A digital multiplexer involves data input and output lines that take on
either 0 or 1. So naturally the select line also accepts binary 0 or 1 for
selecting the particular input line.

The figure 8.9 shows the general block diagram of a digital multiplexer.
Figure 8.9: General block diagram of a digital multiplexer.
A multiplexer with 2n data input lines has n number of “control” or select

lines and these select lines are used to select the input line to connect it to
the output. For example a 2 to 1 mux has 2 input lines and 1 select line,
here n=1. Similarly, a 8 to 1 mux has 8 input lines and 3 select line, here
n=3 since 23=8. So it is possible to select any one of the eight inputs using
3 control lines. In larger multiplexers, using n selection pins, 2n input signals
can be multiplexed. For example, 4 selection pins are required to multiplex
9 to 16 input signals and 5 selection pins are required to multiplex
17 to 32 input signals. The selected input pin can be determined by the
binary values on the selection pins. Normally a signal called strobe (G) is
also incorporated and this helps in cascading and selecting the multiplexers
when it is desired to construct multiplexer for larger number of inputs.
Multiplexers that are used frequently are 2-to-1, 4-to-1, 8-to-1, and 16-to-1
multiplexers. Since digital logic uses binary values, for a given number of
selection lines, powers of 2 (2, 4, 8, 16) are used to control the number of
inputs signals.
Now let’s study some of the digital multiplexers.

2:1 Multiplexer:
The 2:1 multiplexer has two inputs and only one output. Since it has 21 = 2
inputs, it requires n=1 select line. The figure 8.10(a) shows the schematic
symbol of 2-to-1 multiplexer and the figure 8.10(b) shows the equivalent
switch of the multiplexer. One of the selected input lines can be connected
to the single output using the select line “Sel” input. This select input may be
represented as “S” for our convenience as is shown in the figure 8.10.
Figure 8.10: (a) Schematic symbol of a 2-to-1 Multiplexer

(b) Switch Equivalent switch
I0 and I1 are two input signals, S is the select line, and Y is the output signal.
When S=0, I0 is selected and connected to the output line (i.e. out line), so
whatever the data value available on I0 is steered on to the out line. Similarly
when S=1, I1 is available on out line. The operation of 2:1 Mux is
represented in the truth table shown in the table 8.3.
Table 8.3: Truth table for 2-to-1 Mux
Select input Data inputs Output
S I0 I1 Y
0 0
0 0 1 I0
1 0
1 1
0 0
1 0 1 I1
1 0
1 1

For a 2-to-1 multiplexer shown in figure 8.8, the Boolean equation for output
in terms of inputs can be written as follows:
This means, output Y will be equal to I0 when selection line S is 0 and Y is

equal to I1 when S is 1. The output Y may take the value based on the data
inputs. This is shown in the truth table 8.3.
In order to realize the 2-to-1 multiplexer using gates, it requires 2 AND gates,
a NOT gate and an OR gate.
The figure 8.11 shows the logic diagram of 2 to 1 multiplexer.
Figure 8.11: Logic diagram of 2 to 1 multiplexer
4:1 Mux (4-to 1 mux): This Mux has 4 inputs and one output line. It selects
one of the input lines and connects it to the output line using 2 select lines.
The figure 8.12 shows the symbol of 4 to1.
Figure 8.12: Logic symbol of 4:1 Mux
The A, B, C and D are the data inputs and S0 and S1 are the select lines.
Depending on the conditions or binary values of select lines, one of the
inputs will be selected and that selected input data line is connected to the

output lines Y. So whatever the data present on the selected data input will
be available on the output line Y.
The truth table of 4- to-1 Mux is shown in the table 8.4.
Table 8.4: Truth table of 4 to 1 Mux
The output Y=A only when S0=0 and S1=0. This is represented in equation
as Similarly we can write the equation for other
inputs as well. So the final Boolean equation for a 4-to-1 multiplexer is:
Figure 8.13: Logic circuit diagram of 4 to1 Mux.

8:1 Multiplexer: This Mux has 8 inputs and single output line. It selects one
of the input lines and connects it to the output. To select the input, it uses
3 select lines. The figure 8.14 shows the symbol of 8 to1.
Figure 8.14: Logic symbol of 8- to-1 Mux
A, B,C,D,E,F,G and H are the eight data inputs and S0, S1 and S2 are the
3 select lines. Depending on the binary values of select lines, one of the
data inputs will be selected and that selected input data line is connected to
the output lines Y. So whatever the data present on the selected data input
will be available on the output line. For example, if the selected data input
line has 0, then same data 0 will be available on the output line.
The truth table of 8 to1 Mux is shown in the table 8.5.
Table 8.5: Truth table of 8 to 1 Mux

Boolean equation for a 8-to-1 multiplexer is:
Figure 8.15: Logic circuit diagram of 8 to1 Mux.
Demultiplexer: Demultiplex means 1 to many. De multiplexer or DeMux is

a combinational logic circuit designed to switch the single data input to one
of several outputs lines by using control lines or select lines. Since it

distributes the data available on the single data input line to one of the
output lines, De multiplexer is also called data distributor.
A Demultiplexer functions exactly in the reverse of a multiplexer. A
demultiplexer accepts only one input and distributes it to one of many
outputs.
The figure 8.16 shows the general block diagram of a digital Demultiplexer.
Figure 8.16: General block diagram of a digital Demultiplexer.
A Demultiplexer single data input line has 2n number of output lines and n
number of “control” or select lines. Select lines are used to select the output
line to connect it to the input line. For example a 1 to 2 demux has 1 input
line, 2 output lines and 1 select line, here n=1. Similarly, 8 to 1 mux has
1 input line, 8 output lines and 3 select lines. Since 23=8, n=3 which means
only 3 select lines are enough to select 8 output lines.
Now we will study some of the digital Demultiplexers.
1:2 Demultiplexer
A 1:2 Demultiplexer or 1-to-2 demultiplexer has only one input and two
outputs. It has only one select line. Using this select line, it selects one of
the output lines and connects the input to this selected output line. So
whatever the data present at the input line will be available at the selected
output line.

The figure 8.17 shows schematic of a 1 to 2 demultiplexer. A demultiplexer

can also be equated to a controlled switch.
Figure 8.17: Schematic of a 1 to 2 Demultiplexer
When select line Sel or S=0, the output line Y0 is selected and the input data
line “D” is connected to output line Y0 and when S=1, it selects the output
line Y1 and input D is connected to Y1. So whatever the data (0 or 1) present
on data line D will be available on the selected output line.
1:4 Demultiplexers
A 1:4 Demultiplexer or 1 to 4 demultiplexer has only one input and four
outputs. It has only two select lines. Using these select lines, it selects one
of the output lines and connects the input to this selected output line. The
figure 8.18 shows the logic symbol of a 1 to 2 Demultiplexer. It truth table is
shown in the table 8.10.
Figure 8.18: Logic symbol of a 1 to 4 Demultiplexer

When select line Select lines S1=0 and S0=0, the output line Y0 is selected
and the input data line “D” is connected to output line Y0 and when S1=0,
and S0=1, it selects the output line Y1 and input is connected to this Y1. So
whatever the data (0 or 1) that is present on the input line will be available
on the selected output line. Similarly depending on the condition of select
lines, other outputs will be selected and input data will be made available on
the selected output line.
The table 8.6 shows the truth table of 1- to- 4 Demultiplexer.
Table 8.6: Truth table for 1- to-4 Demultiplexer
Notice that there are 4 outputs (Y0, Y1, Y2 and Y4) and only one input D. The
input is transferred to the output corresponding to the decimal equivalent of
control inputs. For example, when S1S0 = 00, decimal equivalent is 0. So,
input (D) is transferred to Y0. The equations for the various outputs are
given as:
Y0 = S1’S0’D
Y1 = S1’S0D
Y2 = S1S0’D
Y3 = S1S0D

Figure 8.19 shows the logic diagram of a 1- to -4 Demultiplexer.
Figure 8.19: logic diagram of a 1 to 4 Demultiplexer
1- to- 8 Demultiplexer: A 1:8 Demultiplexer (or 1-to-8 demultiplexer) has

only one input and eight outputs. To select these eight ouputs, it uses three
select lines. These Select lines select one of the output lines and connect
the input to selected output line.
The table 8.7 shows the truth table of 1 to 8 DeMux.
Table 8.7: Truth table of 1 to 8 DeMux

The figure 8.20 shows logic diagram of 1-to-8 Demultiplexer.
Figure 8.20: Logic diagram of 1 to 8 Demultiplexer
Where D is the data input, S0, S1 and S2 are the control inputs. Y0,Y1,…Y7
represent the outputs.
8.5 Encoder and Decoders

In this section you study the concepts of encoder and decoders. We will
begin with encoders first and then we will look at the decoder.
8.5.1 Encoder and Priority Encoder
The term ‘encode’ means generating a code for information that consists of
numbers or characters or symbols. An encoder is a combinational circuit
that produces an n bit binary code corresponding to the digital input that

represents some information such as decimal number or octal number or

character. It accepts an active level (i.e. HIGH) on one of its inputs and
converts it into coded output such as binary or BCD.
An encoder has 2n input lines and n output lines and one of the input lines is
activated at a given time and generates n bit output code at the output lines
corresponding to the input that is activated. The figure 8.21 shows the logic
symbol of a typical encoder.
Figure 8.21: Logic symbol of typical encoder
Now let us study some of the encoders.

4 to 2 Encoder:
A 4 to 2 encoder has four input lines and two output lines. So it takes in
4 bits and gives out 2 bits. The logic diagram of a single bit 4 to 2 line
encoder is shown in figure 8.22 and its truth table is shown in the table 8.8.
Table 8.8: Truth table of 4 to 2 encoder
From the truth table, the output Y0 is HIGH only when either input I2 or I3 is
HIGH. So we can represent this using OR function as:
Y0 = I1 +I3

Similarly, Y1= I2 +I3. Now we can implement the logic diagram of 4 to 2

encoder is shown in figure 8.22.
Figure 8.22: Logic diagram of the 2 to 4 encoder
Here I0 input is not necessary because the binary code for it is always zero
when there are no other HIGH inputs.
The encoder has the limitation that only one input can be active at any given
time. If two inputs are simultaneously active, the output produces an
undefined combination. To prevent this we make use of the priority encoder.
Priority encoder:
A priority encoder is a digital circuit in which when two or more inputs are
activated at the same time, the input having the highest priority will take
precedence. An example of a single bit 4 to 2 priority encoder is shown in
figure 8.23. Its truth table is shown in the table 8.9.
Figure 8.23: Block diagram of 4 to 2 priority encoder

D0, D1, D2, D3 are the four inputs and Y0, Y1 are the two outputs. Input D3
has the highest priority and D0 has the lowest priority. That means if D3 = 1
then Y1 Y0 = 11 irrespective of the other inputs. Similarly if D3 = 0 and D2 = 1
then Y1 Y0 = 10 irrespective of the other inputs.
Table 8.9: Truth table of 4 to 2 priority encoder
The logic diagram of a 4 to 2 priority encoder is shown in figure 8.24.
Figure 8.24: Logic diagram of 4 -to -2 priority encoder
Priority encoders can be easily connected in arrays to make larger encoders,

such as a 16 to 4 encoder made from six 4 to 2 priority encoders (four
encoders having the signal source connected to their inputs, and two
encoders that take the output of the first four as input).

8.5.2 Decoder
A decoder is a logic circuit that accepts a set of encoded inputs that
represents a binary number and activates only the output that corresponds
to that input number. In other words, a decoder circuit looks at its inputs,
determines which binary number is present there, and activates the one
output that corresponds to that number and all other outputs remain
inactive. The functionality of a decoder is exactly the reverse of an encoder.
Decoder is much like a Demultiplexer but it does not have any data input.
The logic symbol of a general decoder is shown in figure 8.25 with N inputs
and M outputs.
Figure 8.25: Logic symbol of a general decoder
Since there are N inputs whose value may 0 or 1, there are possible input
combinations or codes. For each of these input combinations, only one of
the M outputs will be active (HIGH) and all the other outputs are LOW. AND
gates are used in the decoder when HIGH output is required since when all
the input of an AND gates are “high” the output will also be “high”. So, AND
gate can be considered as the simple decoder. Sometimes decoders are
designed to produce active-LOW outputs, where only the selected output is
LOW while all others are HIGH. This active LOW is indicated by the
presence of small circles on the output lines in the decoder diagram. NAND
gates are used in the decoder when LOW output is required.
Also you can notice that some decoders do not utilize all of the possible
input codes but only certain ones. For example, a BCD-to-decimal decoder

has a four-bit input code and ten output lines that correspond to the ten
BCD code groups 0000 through 1001. Decoders of this type are often
designed so that if any of the unused codes are applied to the input, none of
the outputs will be activated.
Some decoders have one or more ENABLE inputs that are used to control
the operation of the decoder.
A digital decoder has multiple inputs and multiple outputs and it produces a
coded output from the coded inputs. Hence, input and output codes are
different i.e., if there is an n-bit input code then decoder produces 2n output
code.
Decoders are used in many applications like 7 segment display, multiplexing
of the data. Decoders are widely used in the memory system of a computer
for decoding of the memory address.
Now let us study some decoders.
A 2-to-4 Line Decoder: A 2-to-4 Line Decoder has 2 inputs and four ouputs.
It detects the binary code present at its inputs and decodes it and indicates
decoded information by activating one of the output lines. Figure 8.26 shows
the logic diagram of a 2-to-4 decoder. The table 8.10 shows the truth table
of a 2-to-4 decoder.
Figure 8.26: Logic symbol of 2-to-4 Line Decoder

The Boolean expression for the outputs is as follows:
The figure 8.27 shows the logic diagram of 2-to-4 Line Decoder
Figure 8.27: 2-to-4 Line Decoder
A slightly more complex decoder would be the n-to-2n type binary decoders.
With n-to-2n binary decoders, maximum of ‘2n’ outputs are generated from
‘n’ coded inputs which carry information. For ‘n’ bit coded input, if there are
any unused combinations then number of outputs of the decoder can be
less than 2n. From the above discussion, we can say that a decoder can
produce a maximum of 2n outputs. In digital systems, apart from 2 to 4
decoder, various types of decoders like 3-to-8 decoder or BCD to decimal
decoder or 4-to-16 decoder are used. Two 2-to-4 decoders along with
enable signal can be used to construct a 3-to-8 decoders.
Activity 2:
Draw the logic diagram of BCD to Decimal Decoder.

6. A multiplexer with 2n data input lines requires ________ number of
“control” or select lines to select the input line.
7. A 4: 1 Mux selects one of the input lines and connects it to the output
line using 2 select lines. (State true or false)
8. De multiplexer is also called _____________.
9. ____________ accepts an active level (i.e. HIGH) on one of its inputs
and converts it into coded output such as binary or BCD.
8.6 BCD to Seven Segment Display Decoder/Driver

Sometimes it is required to display the information like numerical data or
alphanumeric (numbers and letters) by the digital system in a form that can
be understood easily by the user or operator. A 7-segment LED (Light
Emitting Diode) display provides a very convenient way of displaying
information or digital data in the form of numbers, letters or even alpha-
numerical characters. An LED display emits light as current is passed
through the individual segments. The driving circuit is required to produce
up to 20mA of current to illuminate individual segment. So an integrated
circuit (IC 7446/47) called BCD to 7-segment decoder/driver is used. The
figure 8.28 shows the circuit diagram of BCD to 7-segment decoder/driver.
Figure 8.28: BCD-to-7-segment decoder/driver

The decoder/drivers segments get illuminated depending on the number or

character to be displayed. Suppose we want to display the number 3,
segments a, b, c, d and g would need to be illuminated. The figure 8.29
shows the segment elements that are illuminated while displaying various
decimal digits.
Figure 8.29: 7-Segment Display Elements for all decimal digits.
10. LED stands for_____________________.
11. Which of the following is the BCD-to-7-segment decoder/driver
(a) IC 7446 (b) IC 7464 (c) IC 77446 (d) IC 6446
8.7 Magnitude Comparators

A magnitude comparator is a combinational logic circuit which compares
magnitude of two binary numbers and determines if one number is greater
than, lesser than, or equal to the other number. It is a multiple output
combinational logic circuit. If two binary numbers are considered as A and B,
the magnitude comparator gives three outputs for A > B, A < B, and A = B.
The figure 8.30 shows the block diagram of an ‘n’ bit comparator.
Figure 8.30: Block diagram of a n bit comparator

Comparators can be used in a central processing unit (CPU) or

microcontroller in branching software.
1-bit magnitude comparator:
A one bit magnitude comparator compares two 1-bits, (A and B) inputs and
produce the three output conditions which are as follows:
A < B, A=B and A >B.
The figure 8.31 shows the logic symbol of a 1- bit comparator.
Figure 8.31: Logic symbol of a 1- bit comparator
The operation of a single bit digital comparator can be expressed as truth

table shown in the table 8.11.
Table 8.11: Truth table for Single Bit Comparator
The expressions for the outputs are as follows:

The logic diagram of a single bit comparator is shown in figure 8.32.
Figure 8.32: Logic diagram of a single bit comparator

2 bit Magnitude Comparator: A two bit magnitude comparator compares
two 2-bits, (A and B) inputs and produces the three output conditions which
are as follows:
A < B, A=B and A >B. Input A represents A1A0 bits and input B represents
B1B0 bits.
The operation of a two bit digital comparator can be expressed as a truth
table shown in the table 8.12.
Table 8.12: Truth table for Two Bit Comparator

Using K map shown in figure 8.33, we can simplify the equations for all the
three conditions A>B, A=B and A < B as follows:
Figure 8.33: K-map for 2 bit comparator.

The figure 8.34 shows the logic diagram of a two bit comparator.
Figure 8.34: Logic diagram of a two bit Magnitude comparator
Multi-bit Magnitude Comparator:

Multi-bit magnitude comparators can be constructed to compare whole
binary words to produce an output if one word is larger, equal to or less than
the other. A very good example of this is the 4-bit Magnitude Comparator.
4 bit Magnitude Comparator:
A 4 bit magnitude comparator compares two 4-bit words with each other to
produce the relevant output with one word connected to input A and the
other connected to input B.

The logic symbol of a 4 bit magnitude comparator is shown in figure 8.35.
Figure 8.35: Logic symbol of a 4 bit magnitude comparator
The figure 8.36 shows logic diagram of a 4 bit magnitude comparator.
Figure 8.36 : Logic diagram of a 4 bit Magnitude comparator

As shown in the figure, a 4 bit comparator has three outputs, A>B, A=B and
A < B.
Comparators are also available in the form of ICs (Integrated Circuits).
Examples of the comparator include the CMOS 4063 and 4585 and the
TTL 7485.
The figure 8.37(a) shows the pin diagram of IC 7485 which is a 4 bit
comparator. The input words are A3A2A1A0 and B3B2B1B0 where A3 and B3
are the most significant bits (MSBs) and A0 and B0 are Least significant bits
(LSBs). The figure 8.37(b) shows logic symbol of IC 7485. The table 8.13
shows the function table for IC 7485.
Figure 8.37: (a) Pin diagram of IC 7485 (b) Logic symbol of IC 7485.

Table 8.13: Function table for IC 7485
12. A ____________________is a combinational logic circuit which
compares the magnitude of two binary numbers and determines if one
number is greater than, less than, or equal to the other number.
13. IC 7485 which is a ________bit comparator.
Glossary:
BCD adder: A digital circuit that adds two BCD digits and produces sum
output digit which is also a BCD.
Parity generator: A circuit that generates parity bit.
Parity bit: An extra bit attached with a binary message to make the total
number of 1's either odd or even.
Multiplexing: The operation of sending one or more analog or digital
signals over a common transmission line at different times or speeds.
MUX: A device that performs the multiplexing.
Demultiplexer: A digital circuit that accepts only one input and distributes it
to one of many outputs.
Encoder: A combinational circuit that produces bit binary code
corresponding to the digital input.

Decoder: A logic circuit that accepts a set of encoded inputs and decodes
them and indicates the decoded information by activating corresponding
output.
Magnitude comparator: A combinational logic circuit which compares
magnitude of two binary numbers and determines if one number is greater
than, less than, or equal to the other number.
8.8 Summary
Let us recapitulate the important concepts discussed in this unit:
 BCD adder is a circuit that adds two BCD digits and produces sum
output digit which is also a BCD.
 A BCD subtractor is a circuit that subtracts two BCD digits and
produces difference output digit which is also a BCD.
 10’s complement of a number is formed by obtaining 9’s complement of
a number and adding 1 to the 9’s complement.
 A circuit that generates parity bit in the transmitter is called parity
generator and the circuit which checks parity in the receiver is called
parity checker.
 The multiplexer, or “MUX” is a combinational logic circuit designed to
switch one of several input lines to a single common output line by the
application of a control signal or select line.
 A demultiplexer accepts only one input and distributes it to one of many
outputs.
 An encoder is a combinational circuit that produces an n bit binary code
corresponding to the digital input that represents some information such
as decimal number or octal number or character.
 A decoder is a logic circuit that accepts a set of encoded inputs that
represents a binary number and activates only the output that
corresponds to that input number.
 An integrated circuit (IC 7446/47) is the BCD to 7-segment
decoder/driver.
 A magnitude comparator is a combinational logic circuit which
compares magnitude of two binary numbers and determines if one
number is greater than, less than, or equal to the other number.

8.9 Terminal Questions

1. Explain the working of BCD adders.
2. Discus parity generator/checker.
3. What is a multiplexer? Explain the operation of a 4 to 1 multiplexer.
4. Explain the operation of a 1 to 4 demuplexer.
5. What is an encoder? Explain the operation of priority encoder.
6. Write a note on decoders.
7. Explain a BCD-to-7-segment decoder/driver.
8. What is a comparator? Explain the working of 2 bit comparator.
8.10 Answers
1. True
2. 9’s , 10’s
3. 10’s
4. Parity
5. Exclusive OR
6. n
7. True
8. Data distributor
9. Encoder
10. Light Emitting Diode
11. (a) IC 7446
12. Magnitude comparator
13. 4
Terminal Questions
1. BCD adder is a circuit that adds two BCD digits and produces sum
output digit which is also a BCD. Refer to section 8.2 for more details.
2. In digital system it is often required to reduce the probability of errors
during the transmission of digital data by using parity generator/checker.
Refer to section 8.3.
3. The multiplexer, or “MUX” is a combinational logic circuit designed to
switch one of several input lines to a single common output line by the
application of a control signal or select line. Refer to section 8.4.

4. A 1:4 Demultiplexer has only one input and four outputs. It has only two
select lines. Using these select lines, it selects one of the output lines
and connects the input to this selected output line. Refer to section 8.4.
5. An encoder is a combinational circuit that produces an n bit binary code
corresponding to the digital input that represents some information such
as decimal number or octal number or character. Refer to section 8.5.
6. A decoder is a logic circuit that accepts a set of encoded inputs that
represents a binary number and activates only the output that
corresponds to that input number. Refer to section 8.5.
7. An integrated circuit (IC 7446/47) is called BCD to 7-segment
decoder/driver. Refer to section 8.6.
8. A magnitude comparator is a combinational logic circuit which compares
magnitude of two binary numbers and determines if one number is
greater than, less than, or equal to the other number. Refer to
section 8.7.

BIT102 SLM Library - SLM - Unit 08

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

BIT102 SLM Library - SLM - Unit 08

Uploaded by

Copyright:

Available Formats

Digital Electronics Unit 8

Unit 8 Combinational Circuits – Part II

Sikkim Manipal University B2072 Page No.: 193

8.2 BCD adder and BCD Subtractor

Figure 8.1: BCD adder

The nines' complement of a number is obtained by subtracting each

Sikkim Manipal University B2072 Page No.: 195

Figure 8.2: BCD Subtractor using 9’s complement method

Figure 8.3: BCD Subtractor using 10’s complement method

8.3 Parity Checker/Generator

Sikkim Manipal University B2072 Page No.: 198

Figure 8.4: Block diagram of a 4 bit parity checker/generator

When used as a parity checker:

Sikkim Manipal University B2072 Page No.: 199

Table 8.2: Truth table for even parity checker

The K –map for Pe is given as follows.

Sikkim Manipal University B2072 Page No.: 200

Figure 8.5: Logic diagram of even parity generator/checker

Sikkim Manipal University B2072 Page No.: 201

Figure 8.6: Logic diagram of odd parity generator/checker

8.4 Multiplexer and Demultiplexer

Sikkim Manipal University B2072 Page No.: 202

multiplexer and demultiplexer are used together, for the communication

Figure 8.7: Multiplexer as a switch

Sikkim Manipal University B2072 Page No.: 203

multiplexer is controlled by an additional set of inputs called control lines or

Figure 8.8: Symbol for a multiplexer

Sikkim Manipal University B2072 Page No.: 204

Figure 8.9: General block diagram of a digital multiplexer.

A multiplexer with 2n data input lines has n number of “control” or select

Sikkim Manipal University B2072 Page No.: 205

Figure 8.10: (a) Schematic symbol of a 2-to-1 Multiplexer

Sikkim Manipal University B2072 Page No.: 206

This means, output Y will be equal to I0 when selection line S is 0 and Y is

Figure 8.11: Logic diagram of 2 to 1 multiplexer

Figure 8.12: Logic symbol of 4:1 Mux

Sikkim Manipal University B2072 Page No.: 207

The figure 8.13 shows the logic diagram of 4 to 1 multiplexer.

Figure 8.13: Logic circuit diagram of 4 to1 Mux.

Sikkim Manipal University B2072 Page No.: 208

Figure 8.14: Logic symbol of 8- to-1 Mux

Sikkim Manipal University B2072 Page No.: 209

Boolean equation for a 8-to-1 multiplexer is:

The figure 8.15 shows the logic diagram of 8 to 1 multiplexer.

Figure 8.15: Logic circuit diagram of 8 to1 Mux.

Demultiplexer: Demultiplex means 1 to many. De multiplexer or DeMux is

Sikkim Manipal University B2072 Page No.: 210

Figure 8.16: General block diagram of a digital Demultiplexer.

Sikkim Manipal University B2072 Page No.: 211

The figure 8.17 shows schematic of a 1 to 2 demultiplexer. A demultiplexer

Figure 8.17: Schematic of a 1 to 2 Demultiplexer

Figure 8.18: Logic symbol of a 1 to 4 Demultiplexer

Sikkim Manipal University B2072 Page No.: 212

Sikkim Manipal University B2072 Page No.: 213

Figure 8.19 shows the logic diagram of a 1- to -4 Demultiplexer.

Figure 8.19: logic diagram of a 1 to 4 Demultiplexer

1- to- 8 Demultiplexer: A 1:8 Demultiplexer (or 1-to-8 demultiplexer) has

Sikkim Manipal University B2072 Page No.: 214

The figure 8.20 shows logic diagram of 1-to-8 Demultiplexer.

Figure 8.20: Logic diagram of 1 to 8 Demultiplexer

8.5 Encoder and Decoders

Sikkim Manipal University B2072 Page No.: 215

represents some information such as decimal number or octal number or

Figure 8.21: Logic symbol of typical encoder