G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Silicon Carbide MOSFET VDS = 3300 V
N-Channel Enhancement Mode RDS(ON)(Typ.) = 50 mΩ
ID (TC = 100°C) = 44 A

Features Package
• Softer RDS(ON) v/s Temperature Dependency D
• LoRing™ - Electromagnetically Optimized Design

G
• Smaller RG(INT) and Lower QG G
• Low Device Capacitances (COSS, CRSS) RoHS

N
• Industry-Leading UIL & Short-Circuit Robustness KS

I
S
• Robust Body Diode with Low VF and Low QRR D = Drain
• Normally Off-Stable Temperature up to 175°C

R
G = Gate
• Optimized Package with Separate Driver Source Pin TO-247-4 S = Source REACH

E
KS = Kelvin Source

E
Advantages Applications

N E
• Compatible with Commercial Gate Drivers • Traction

I L
• Low Conduction Losses at all Temperatures • Solar String Inverters
• Reduced Ringing • EV- Fast Chargers

G P
• Faster and More Efficient Switching • Pulsed Power
• Lesser Switching Spikes and Lower Losses • Switched Mode Power Supply

N M
• Better Power Density and System Efficiency • Energy Storage
• Ease of Paralleling without Thermal Runaway • Solid State Transformers

E SA
• Superior Robustness and System Reliability • Solid State Circuit Breakers

Absolute Maximum Ratings (At TC = 25°C Unless Otherwise Stated)

Parameter Symbol Conditions Values Unit Note
Drain-Source Voltage VDS(max) VGS = 0 V, ID = 100 µA 3300 V
Gate-Source Voltage (Dynamic) VGS(max) -10 / +25 V
Gate-Source Voltage (Static) VGS(op) Recommended Operation -5 / +20 V
TC = 25°C, VGS = -5 / +20 V 63
Continuous Forward Current ID TC = 100°C, VGS = -5 / +20 V 44 A Fig. 15
TC = 135°C, VGS = -5 / +20 V 32
Pulsed Drain Current ID(pulse) tP ≤ 3µs, D ≤ 1%, VGS = 20 V, Note 1 235 A Fig. 14
Power Dissipation PD Tc = 25°C 536 W Fig. 16
Non-Repetitive Avalanche Energy EAS L = 11.2 mH, IAS = 20.0 A 2250 mJ
Operating and Storage Temperature Tj , Tstg -55 to 175 °C

Thermal/Package Characteristics
Values
Parameter Symbol Conditions Unit Note
Min. Typ. Max.
Thermal Resistance, Junction - Case RthJC 0.21 0.28 °C/W Fig. 13
Weight WT 6.2 g
Mounting Torque TM Screws to Heatsink 1.1 Nm

Note 1: Pulse Width tP Limited by Tj(max)

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 1 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Electrical Characteristics (At TC = 25°C Unless Otherwise Stated)

Values
Parameter Symbol Conditions Unit Note
Min. Typ. Max.
Drain-Source Breakdown Voltage VDSS VGS = 0 V, ID = 100 µA 3300 V
Zero Gate Voltage Drain Current IDSS VDS = 3300 V, VGS = 0 V 1 µA
VDS = 0 V, VGS = 25 V 100
Gate Source Leakage Current IGSS nA
VDS = 0 V, VGS = -10 V -100

G
VDS = VGS, ID = 10.0 mA 2.5 3.50
Gate Threshold Voltage VGS(th) V Fig. 9
VDS = VGS, ID = 10.0 mA, Tj = 175°C 2.40

N
VDS = 10 V, ID = 40 A 15.3
Transconductance gfs S Fig. 4

I
VDS = 10 V, ID = 40 A, Tj = 175°C 16.4
VGS = 20 V, ID = 40 A 50 65

R
Drain-Source On-State Resistance RDS(ON) mΩ Fig. 5-8
VGS = 20 V, ID = 40 A, Tj = 175°C 105
Input Capacitance Ciss 7301

E
Output Capacitance Coss 130 pF Fig. 11

E
Reverse Transfer Capacitance Crss 12.3

E
Coss Stored Energy Eoss 84 µJ Fig. 12
VDS = 1000 V, VGS = 0 V

N
Coss Stored Charge Qoss 254 nC

L
f = 1 MHz, VAC = 25mV

I
Effective Output Capacitance (Energy
Co(er) 168
Related)

G P
pF Note 2
Effective Output Capacitance (Time
Co(tr) 254
Related)

N M
Gate-Source Charge Qgs VDS = 1000 V, VGS = -5 / +20 V 120
Gate-Drain Charge Qgd ID = 40 A 100 nC Fig. 10

E SA
Total Gate Charge Qg Per IEC607478-4 340
Internal Gate Resistance RG(int) f = 1 MHz, VAC = 25 mV 1.2 Ω
Turn-On Switching Energy
EOn 1222
(Body Diode) Tj = 25°C, VGS = -5/+20V, RG(ext) = 3 Ω, L =
µJ Fig. 22,26
Turn-Off Switching Energy 60.0 µH, ID = 50 A, VDD = 1700 V
EOff 533
(Body Diode)
Turn-On Delay Time td(on) 74
Rise Time tr VDD = 1700 V, VGS = -5/+20V 37
RG(ext) = 3 Ω, L = 60.0 µH, ID = 50 A ns Fig. 24
Turn-Off Delay Time td(off) Timing relative to VDS, Inductive load 32
Fall Time tf 18

*The chip technology was characterized up to 200 V/ns. The measured dV/dt was limited by measurement test setup and package.
Note 2: Co(er), a lumped capacitance that gives same stored energy as C OSS while V DS is rising from 0 to 1000V.
Co(tr), a lumped capacitance that gives same charging times as COSS while V DS is rising from 0 to 1000V.

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 2 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Reverse Diode Characteristics

Values
Parameter Symbol Conditions Unit Note
Min. Typ. Max.
VGS = -5 V, ISD = 20 A 4.1
Diode Forward Voltage VSD V Fig. 17-18
VGS = -5 V, ISD = 20 A, Tj = 175°C 3.5
Continuous Diode Forward Current IS VGS = -5 V, Tc = 100°C 49 A

G
Diode Pulse Current IS(pulse) VGS = -5 V, Note 1 196 A
Reverse Recovery Time trr 154 ns
VGS = -5 V, ISD = 50 A, VR = 1700 V

N
Reverse Recovery Charge Qrr 740 nC
dif/dt = 500 A/µs, Tj = 25°C

I
Peak Reverse Recovery Current Irrm 17 A
Reverse Recovery Time trr 204 ns

R
VGS = -5 V, ISD = 50 A, VR = 1700 V
Reverse Recovery Charge Qrr 2840 nC
dif/dt = 500 A/µs, Tj = 175°C

E
Peak Reverse Recovery Current Irrm 38 A

N E E
G I PL
N
E SA M

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 3 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Figure 1: Output Characteristics (Tj = 25°C) Figure 2: Output Characteristics (Tj = 175°C)

N G
R I
E E
I N L E
N G M P
ID = f(VDS, VGS); tP = 250 µs ID = f(VDS, VGS); tP = 250 µs

E SA
Figure 3: Output Characteristics (VGS = 20 V) Figure 4: Transfer Characteristics (VDS = 10 V)

ID = f(VDS, T);
j tP = 250 µs ID = f(VGS, T);
j tP = 100 µs

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 4 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Figure 5: On-State Resistance v/s Temperature Figure 6: On-State Resistance v/s Drain Current

N G
R I
E E
I N L E
N G M P
RDS(ON) = f(T,j VGS); tP = 250 µs; ID = 40 A RDS(ON) = f(T,I
j D); tP = 250 µs; VGS = 20 V

E SA
Figure 7: Normalized On-State Resistance v/s Temperature Figure 8: On-State Resistance v/s Gate Voltage

RDS(ON) = f(T);
j tP = 250 µs; ID = 40 A; VGS = 20 V RDS(ON) = f(T,V
j GS); tP = 250 µs; I D = 40 A

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 5 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Figure 9: Threshold Voltage Characteristics Figure 10: Gate Charge Characteristics

N G
R I
E E
I N L E
N G
VGS(th) = f(T);

M P
j VDS = VGS; ID = 10.0 mA ID = 40 A; VDS = 1000 V; Tc = 25°C

E SA
Figure 11: Capacitance v/s Drain-Source Voltage Figure 12: Output Capacitor Stored Energy

f = 1 MHz; VAC = 25mV Eoss = f(VDS)

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 6 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Figure 13: Transient Thermal Impedance Figure 14: Safe Operating Area (Tc = 25°C)

N G
R I
E E
I N L E
N G M P
Zth,jc = f(tP,D); D = tP/T ID = f(VDS, tP); Tj ≤ 175°C; D = 0

E SA
Figure 15: Current De-rating Curve Figure 16: Power De-rating Curve

ID = f(TC); Tj ≤ 175°C PD = f(TC); Tj ≤ 175°C

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 7 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Figure 17: Body Diode Characteristics (Tj = 25°C) Figure 18: Body Diode Characteristics (Tj = 175°C)

N G
R I
E E
I N L E
N G M P
ID = f(VDS, VGS); tP = 250 µs ID = f(VDS, VGS); tP = 250 µs

E SA
Figure 19: Third Quadrant Characteristics (Tj = 25°C) Figure 20: Third Quadrant Characteristics (Tj = 175°C)

ID = f(VDS, VGS); tP = 250 µs ID = f(VDS, VGS); tP = 250 µs

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 8 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Figure 21: Inductive Switching Energy v/s Drain Current Figure 22: Inductive Switching Energy v/s Drain Current
(VDD = 1500V) (VDD = 1700V)

N G
R I
E E
I N L E
N G M P
Tj = 25°C; VGS = -5/+20V; RG(ext) = 3 Ω; L = 60.0µH Tj = 25°C; VGS = -5/+20V; RG(ext) = 3 Ω; L = 60.0µH

E SA
Figure 23: Inductive Switching Energy v/s RG(ext) Figure 24: Switching Time v/s RG(ext)
(VDD = 1700V) (VDD = 1700V)

Tj = 25°C; VGS = -5/+20V; IDS = 50 A; L = 60.0µH Tj = 25°C; VGS = -5/+20V; IDS = 50 A; L = 60.0µH

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 9 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Figure 25: Inductive Switching Energy v/s Temperature Figure 26: dV/dt v/s RG(ext)
(VDD = 1700V) (VDD = 1700V)

N G
R I
E E
I N L E
N G M P
Tj = 25°C; VGS = -5/+20V; RG(ext) = 3 Ω; IDS = 50 A; L = 60.0µH Tj = 25°C; VGS = -5/+20V; IDS = 50 A; L = 60.0µH

E SA
Figure 27: High Current IV

ID = f(VDS); tP ≤ 3 µs; VGS = 20 V

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 10 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Gate Charge Circuit Gate Charge Waveform

VDS

G
VGS

Gate Voltage (VGS)

N
D.U.T RLoad

R I
E
ID VDD
IG(cont)

N E E
I L
QGS QGD

G P
Gate Charge (QG)

Switching Time Circuit

N
E SA M Switching Time Waveform

90%
Same device as the D.U.T.
LLoad
-5 V VGS 10%

VDS
10% 10%
VDS
VGS
VDD
D.U.T.
RG
90% 90%
ID td(on) td(off)
tr tf
ton toff

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 11 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Switching Energy Circuit Switching Energy Waveform

EON = ∫ ID x VDS x dt EOFF = ∫ ID x VDS x dt

Same device as the D.U.T.
LLoad
-5 V Irr

G
VDS

I N
VDS
VGS
VDD

R
D.U.T.
RG

E E ID

I N L E IDS

N G M P
E SA
Reverse Recovery Circuit Reverse Recovery Waveform

D.U.T.
LLoad IF
-5 V
trr
IF
0 Level
VGS 90%
VDD
Same device
as the D.U.T. dIrr/dt in 10%
RG Irr
to 90% range

10%

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 12 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Package Dimensions
TO-247-4 Package Outline

0.62(15.75) 0.19(4.83)
0.516(13.10)
0.635(16.13) 0.205(5.21)
0.557(14.15)
0.5(12.7)
0.216(5.49) 0.487(12.38)

G
0.236(6.0) 0.075(1.91)
0.25(6.35) 0.529(13.43)
0.085(2.16)
0.037(0.95)
0.049(1.25)

N
0.237(6.04)

I
0.248(6.30)
0.145(3.68)
0.2(5.10)

R
0.64(16.25)
0.695(17.65)
Ø 0.138(3.51)

E
0.118(3.0) Ø 0.144(3.65)
0.917(23.30)
0.929(23.60)

E
Ø 0.283(7.18) REF

E
0.093(2.35)
0.104(2.65)

I N PL 0.09(2.29)

G
0.1(2.54)
0.156(3.97)
0.172(4.37)

N
0.681(17.31)

M
0.701(17.82)

E SA
0.042(1.07)
0.052(1.33)
0.1(2.54) BSC
0.2 (5.08) BSC
0.021(0.55)
0.027(0.68)
0.042(1.07)
0.063(1.60)
0.094(2.39)
0.116(2.94)

Recommended Solder Pad Layout Package View

Case(D)
Ø 0.088(2.24)

Ø 0.067(1.7)

0.1(2.54)
G
0.1(2.54) D
0.2(5.08)
S KS

NOTE
1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER.
2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS.
3. THE SOURCE AND KELVIN-SOURCE PINS ARE NOT INTERCHANGABLE. THEIR EXCHANGE MIGHT LEAD TO MALFUNCTION.

Rev 21/May Latest Version at: www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K.pdf Page 13 of 14

G2R50MT33K TM

3300 V 50 mΩ SiC MOSFET

Compliance
RoHS Compliance
The levels of RoHS restricted materials in this product are below the maximum concentration values (also referred to as the threshold
limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive 2011/65/EC (RoHS 2), as
adopted by EU member states on January 2, 2013 and amended on March 31, 2015 by EU Directive 2015/863. RoHS Declarations for this
product can be obtained from your GeneSiC representative.
REACH Compliance

G
REACH substances of high concern (SVHCs) information is available for this product. Since the European Chemical Agency (ECHA) has
published notice of their intent to frequently revise the SVHC listing for the foreseeable future, please contact a GeneSiC representative to

N
insure you get the most up-to-date REACH SVHC Declaration. REACH banned substance information (REACH Article 67) is also available

I
upon request.

Disclaimer

E R
GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice.

E
GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any

E
intellectual property rights is granted by this document.

I N L
Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft
navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal

G P
injury and/or property damage.

N M
Related Links

E SA
• SPICE Models: https://www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K_SPICE.zip
• PLECS Models: https://www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K_PLECS.zip
• CAD Models: https://www.genesicsemi.com/sic-mosfet/G2R50MT33K/G2R50MT33K_3D.zip
• Gate Driver Reference: https://www.genesicsemi.com/technical-support
• Evaluation Boards: https://www.genesicsemi.com/technical-support
• Reliability: https://www.genesicsemi.com/reliability
• Compliance: https://www.genesicsemi.com/compliance
• Quality Manual: https://www.genesicsemi.com/quality

Revision History
• Rev 21/May: Updated switching time and switching energy data
• Supersedes: Rev 21/Jan

www.genesicsemi.com/sic-mosfet/

Rev 21/May Published by GeneSiC Semiconductor, Inc.

Copyright© 2021 GeneSiC Semiconductor Inc. 43670 Trade Center Place Suite 155, Dulles, VA 20166; USA
All Rights Reserved. Page 14 of 14
Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

GeneSiC Semiconductor:
G2R50MT33K