1.

Consider a 32-bit computer with a clock frequency of 500 MHz, and the structure of
the computer shown as bellows.
Control and state registers
- Program counter, PC
- Instruction register, RI
- Memory address register, MAR
- Memory buffer register, MBR
- Program status word, PWS
The memory is byte addressed and requires two cycles for reading and writing
operations.
a) Indicate the elemental operations needed to execute the MIPS32 instructions
a-1 lw R1, (R2)
a-2 addi R0, R1, 10
a-3 LW R1, 8(R2)
b) If the average number of clock cycles needed to execute an instruction is 25,
calculate the average number of instructions executed by this computer in one
second.
c) If the computer executes 200 MIPS, what is the average number of cycles per
instruction?
d) The following control signals activated in a clock cycle.
C1: T8, C1
C2: R, Td
C3: R, C2
C4: RC= R1, T3, SC
- Indicate the elemental operations corresponding to these control signals.
- What is the machine instruction corresponding to these control signals?
2. A 32-bit computer as the shown in Exercise 1 has 32 registers, and a memory
addressed by bytes with two cycles for reading and writing operations. Consider the
instruction ADD, R1, addr. This instruction adds the value stored in R1 to the value
stored in the memory address addr, and stores the result in the register R1.
a) Show a possible format for this instruction, having into account that the computer
has 100 machine instructions and the addresses are represented using 32 bits.
b) Indicate the elemental operations and control signals needed to execute the
previous instruction.

3. A computer has a five-stage instruction pipeline of one cycle each. The five stages
are: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Instruction
Execution (IE), and Operand Store (OS). Consider the following code sequence, which
is to be run on this computer.
Load -1, R1 ; R1 <= -1;
Load 5, R2 ; R2 <= 5;
Again: Sub R2, 1, R2 ; R2 <= R2 - 1;
Add R1, R2, R3 ; R3 <= R1 + R2;
Bnn Again ; branch to Again if result is Not Negative;
Add R4, R5, R6 ; R6 <= R4 + R5;
Add R6, R4, R7 ; R7 <= R4 + R6;
a. Analyze the execution of the above piece of code in order to calculate the number
of cycles needed to execute the above code without pipelining, assuming that each
instruction requires exactly 5 cycles to execute.
b. Calculate (using the Gantt’s chart) the number of cycles needed to execute the
above code if the pipeline described above is used. Assume that there is no
forwarding hardware and that when branch instructions are fetched, the pipeline
will “stall” until the target address is calculated and the branch decision is made.
Ignore any data dependency.
c. Repeat (b) above if data dependency is considered with the remaining conditions
the same.
d. Calculate the percentage of improvement due to the use of pipeline in each of
the above cases (b) and (c)

4. A computer has a five-stage instruction pipeline of one cycle each. The five stages are:
Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Instruction Execution (IE),
and Operand Store (OS).
Stages IF ID OF IE OS
Latencies (ps) 200 170 150 220 150
Consider the following code sequence, which is to be run on this computer.
li $a0, 5
move $t0, $a0
li $t1, 0
loop : beq $t0, 0, end
add $t1, $t1, $t0
sub, $t0, $t0, 1
b loop
end: move $v0, $t1
a. Calculate total time to execute the above code without pipelining, assuming that each
instruction requires exactly 5 cycles to execute.
 b. Calculate total time for these instruction in pipeline (using the Gantt’s chart). Assume that
there is no forwarding hardware and that when branch instructions are fetched, the pipeline
will “stall” until the target address is calculated and the branch decision is made. Ignore any
data dependency.
c. Repeat (b) above if data dependency is considered with the remaining conditions
the same.
d. Calculate the percentage of improvement due to the use of pipeline in each of
the above cases (b) and (c)

5. Consider the following loop.

loop: LW R1,0(R1)
AND R1,R1,R2
LW R1,0(R1)
LW R1,0(R1)
BEQ R1,R0,loop
Assume that perfect branch prediction is used (no stalls due to control hazards), that
there are no delay slots, and that the pipeline has full forwarding support. Also
assume that many iterations of this loop are executed before the loop exits.
a) Show a pipeline execution diagram for the third iteration of this loop, from the
cycle in which we fetch the first instruction of that iteration up to (but not including)
the cycle in which we can fetch the first instruction of the next iteration. Show all
instructions that are in the pipeline during these cycles (not just those from the third
iteration).
b) How often (as a percentage of all cycles) do we have a cycle in which all five-
pipeline stages are doing useful work?