: SP ack] Udo i (Can be inteuupted in the followeng ways. 4) By an extemal Signal gewerated by a ple peripheral. 2) By 20 intemal Signal genecated by a Special inshuctten in the program 8) By an intemal Signal generated due to an excepberal Conclitren, ich occurs while execuling au instiucton Sw genual, the procens gf wleuuplivig the normal progeant exceutten to cauyouk a specific task/work ts ceffered to m6 inleupt: The inteuupt is Mmbated by a signal qereraked by An extemal clevice of by a Signal gencated intemal CO the Procersor- When a NP xeceives ao ioteuupt signal, ik Stops execubing the se cueut novmal proguat, saves the status then the precersoy execures specific task xequerted Dak is execubed in Acsponse apt Savice Sulsoutine (1S) iste to Stackto jo the. deshoabow mastable. Type O cotermupt Car0F be We have 4o womb an iss which takes toe ie .- Ww emot cenditen when av nyald duvisiovy Ocours ie aod the addus a ISS iS Stored segesia 20d —_ disabled 19 any way) desived acter OY tndicale Iss Should be Stored in memory (© the inteuupt veetoy table: 2) Single - step loteuupt ( Type-1 totenupt) When the Sap /Trace Flag is Set to one, the Goss Peccenor will automatically geneake a type-1 interest after execuben g each imsbucbon - he user can conile an 'S5 foy type-1 inteuupr to halt the poocersoy temporarily and reliom the Contant to the user so that after erceubre of each insbuchow, the proces status can be verified. mabeally geal a Low -to high bausitenYD Break pent fuccher , which executes 2 Pogae coviadt to ws. OF upto the desived potnt and thew aelam the The breakpoint injeupl 1s Initiated by executor gf "INT 3 tnatuetons » is inienupt will be wselul to debug a prgiany ley Execuling Whe progianr part by part + 5) Overstow interxupt (Type-4 intermpt) dn 8086 processor the overflow Slag (OF) will be set 'f the Signed arithmetic operation deneaats a result whose Size is larger than the Size of destuation rzgister Janemory - Dung suc cencitions the type- 4 intewupt cam be used fo indicate an enor condition. The type-4 inieuupt is initiated by "INTO" (nstucken- One way Of detecting the overflow exror is to ster the artthrutcMTR ond uM pins Gf BORE Bre called hardware intermupls ° M Abe 290 type voleumpl, vocludiog witer predefined Bod Keseved itenunpts can be initiated by apply a Wah signal to INSTR Bo of GORE: Vihen appled $9 INI2 PH and ate enabled aber > thigh Signal 16 hardware nieuwe fs the processor ws an wiewupt ackrewledge exele te act the type number g toe soremipt fem Hoe device lich cend the intemupl Sigal. The hacluare inteuupt MMI 16 men --~wmaskable aa hos Wah paomty thaw foleuupk initiated though inte. 2254 software — progammable TWMER / COUNTER adh CerkmP three 16-bit te opeats 19 several | dlevices ae pin- for ~ pin Neal in funcbOn- Teord Register 8254 intanal block diagyam The device Cevitan thiee lo- bit Counlers . The bre advan ~ tage gq these counters 16 that we can load a count in them, sta then and S&P them witb jnckuchon 10 owt be Softwau - program -d to interface the #25a/sn to the systert w dat basic functous fe has three + Programming tbe modes @ 8298 164 + loading the count vegi sls + Reading the Count values Read / Wate Logs te RD, WR, CS & Addvers Rives bo &Ay cue Connected Tt melude 5 Signals Yo mode, the RD and ue signe ww pheuphaal 4o \oR and loWWoite Cou tint Count Wate Counter 2 Wate Contoct borMeade _o = trteupt_ on Tenia Count The output will be iobally how after wmode set operation. aftr Loading the counter , the output will x/emoaiy Row while Counting and ew terminal count, the eutput will be cove trig , unty xeLooded again Mode 4 — Prograrmmable Que - Shot afte Poadiug the courtet, toe output will zeman Row dbe Aisi edge gy the gate input - The curpur will @o ered, Fore theoseman tugh umbl one ball gj Count pod go Low for the \f the count is odd, counts and Low oteer balf for even vuumber Count: the eutput oil! be high for (Count+t!)/2 for Gout -')/2 Couils - Tas mode 1g sed fot qo oes baud cat fer $2514 USART- Mode 4 - Softwau Srggeed Stovbe he output 1s fugh atta mele 1s set aod alo ‘og Ceunbrg On terminal Count, the eutpit will go Low for ew clock pexed and becemes high again Ths -mode Can be weed edge gf bigger ip eo Al count .Read tack crod is available Reads § Waites @ tbe same Rend & rine 4 Ae Sune Counter Ca0oct be ierleaved counter cam be Interdeaved. Feats 8253 /54 * St has & indepeodent te-bit down ceuitu. + tt can handle Yes fem ve to to mig. DACKS k— Dra [+> DACKI K— DRQ2 [> DACK2 k— DRQ3 [> DACK3Functional Block Diagvam G 8257 “Whe fochenal blocks of $253 are data + bubfer, Yead/woite Aogic , Ceontrof togie aod 4 aumbers Z ema channels. Each channel has -hoo Programmable 16-bit register SUEmteatele, ic the startin ‘sed to program 8 eddies a memory focaten foy OMA data tans A2Bister f5 Ved 45 PrOgyam aod a 2- ut nod 200th ex 2 14-bit count value Code for type y OMA transfer. The addasye 10 the addsees Atgister is automatically incremented aflig Mes seed covite / verihy traveler. In xtod transfer the dala is Ravefeed fren r memory to To devices - m Woitt Mansfer the dam is thamsfercd fem Yo devices to memory, Varfratien 2 OMA addwser Without gqernrabre opeations geuera the ONA a 5 s the DMA embry and To Cutol Siguals- e Toe 3253 has a ast mocle st register Sod status Aegistes Tbe roode set xegiste i wed to poogiam vaueus fealuus %B1B BBP) 3) BB B, /B, |B, |B, |B, /B./3 | 3 top DMA on terminal count “————> | = Enable auto reload >> I = Enable channel 0 = Disable auto reload > 0 = Disable channel - 3 Word to be loaded in mode set register of 8257380 The format of the ¢ e725(0). The bits BB »B,, EF 3 respectively qisable it In the mode loaded in mode. set regi ister of 8257 is shown in A one in th © set register are used to enable/disable channel-0,1,2 Vill enable a Particular channel and a zero will > if the bit B priority and iP it zero then the eh ,channel its priority js made channel-2 has lowest priority vis s annels wil] have 48 lowest. In fixe, “tt to one, then the channels will have rotating - €d priority. In rotating priority, after servicing | priotity the channel-0 has highest priority and In mode et register Be. » if the bit B ne EMW is set to one, then the of write signals (MEMW and 1OW) will be extended ang inthe s io Gne then is oe stopped at the terminal count The bit B channel-2. When bit Bis set to ong ‘ct the auto load feature for DMA joaded in channel-2 count and then the hannel-3 count and address registers are terminal count. Therefore ctively whenever the channel-2 reaches when th fchannels available for DMA reduces from four to three. The format of status repist Slats of $257 during slave mode to know B,.B, and B, of status regis ler of 8257 is shown in fi c). The proceso: erminal count status of th ster indicat S the terminal count status of channel-0. el Aone in these bit POSitions indicate th el has reached Status bits are cleared after a read operati n by micropr or. The bit B ster is tailed update flag and a one in this bit Position indicat the channe egis reloaded from channel-3 Tegisters in the auto load mod ar will be similar to that of interfacing 82 h 8086. Microprocessor send control word to sah on Of the required DMA channels. Once th fg r B¥ice require a DMA, it will asser signal high Bibs asserted high and if the channel is enabled then the D Request) as high ive a high s: nal on its HOLD pin, it wil in then drive all its tri-state (address, data and d send an acknowled:8255, 82594 Priovity Inteuup Gontaoller, 8255 A The sassa is a genera) purpose programmable 0 data frem Vo to Mteuipt used wit almost t bidivecbenal device designed 40 transfer the Yo undey cevtain conditens It can be S- bt amy ciclo processor: Te comsisle Of three Yo jpovts- forts y e2554 $255 4 has 3 por, le PoRTA, PoRTB and PORTC Port A centain one @-lt autput lateh/butfer aod ene S-bort Ye buffer, PORT B is similac to PORTA- PoRT C can be cplit inte two parle ic PoRTC ower CPco-fes) Bed PORTS ucper (Pca - 4) by toe Gontedl Load. Wese tbace posts au divided into two Gooups- Group A wocludes PORTA aod Uppey PORT C « Group ® iwcludes PORTB and love PORTC - Operabng Medes 8255 & has thie differeut Operating wodes. («Mode 0 - \n tis wmode, Port A acd B is msed as 100 “bit ports aod port C m+ boo 4-bit ports. Each be poogammed in eittir Input mod8255 Architecture The following figure shows the architecture of 8255A - — + GROUP A suemies 7 rower —— ono BLOIRECTIONAL DATA BUS, RESET} Data Bus Buller is a to stah buffer, Which is weed to interface the miioprocewsoY to the system data fous. Dala 1s trawsrmitted ©Y veceived by the buffer a4 per the suchen bY oe CPU, Contact words and status infovmater 1s alse trams ferred UArting this bus Read/Write Coutrot Logic Mis Hock (s sespeusble Cy Qutoeiling iotanal ardextiod| transfer g date / Contact | ciatus word Mi accepts toe imput fom Woe cev addyes and Centool buses £S_ (Chip Select) A 1OW om thé i/p Selects the Chip aoc\ enables toe Cemmunicationt between the $255 and CPU CS A, Ap Result cc) ° ° PorTA ° ° ! foRTB °° 4 oO porTc ° \ ' Contaot Registee 1 x x No SdlectionRD (Read) Ws Contest Sigual emaries the Read opuabiou- Wen tre Sigual is low, the micropsocesoy piads (he data frem the Selected 17 povt GY the $255. Mo aod Ay These input Signals work with RD WR and enc Of the contaot Sgual. ® Ao RD we ts Resatt: °° °° ° 1 oO y alle PORT A > Date Bis 2 L ° ' ° PORT B > Oxtn Bus ° ° IL ° Porte > Peta us. oO ake ov ° ° t ° ° Datetrr > Porth8255A -8259 A The 8259 1s known as the Poogiammable Intexupt Coutootler (Pic) microprocessor - 8259 chip combines the cmulti intemupt Mput Seve to single inieuupt output. Ths provides 8 -intertupls Svew Ro te IeF+ feats : + Ths chip is desgoed fo1 s085 and S086. + Tt cam be poogiammed either in edge triggeed or in level toiggered mode + * We mask individual bits of Internist Request Register. * Clock Cycle is “ot weeded. Block diagyvamn Descuph er _ Date Bus Buffer: cen Weck ve wied 10 Commupleate betoeen a254 aod Go0ss/ GosG by acbuga 96 puffer. Tr takes the contact word from eoss| soaG 2! Send it & toe e25q. rt trasfers the opcode G the eclectec) jnteuupts Bod addy ess BF \se to tbe otper connected MaoParce*soy. Tt Can amaximumn S- bit at A EMeMTA DATABUS IT DATABUS CONTROL READ WRIE CONTROL LOGIC INTERRUPT MASK REGISTER (Rg)cs I 28 K Vee WR 2 27 Ao RD 3 26 - INTA D; 4 25 & IR Deol 5 24 & IR, Ds} 6 23 IRs Dy 7 22 & IR, D; 4} 8 21 © IR; D4 9 20 IR, D; & 10 19 K IR, Dp 4 II 18 F IRo CASy © 12 17 > INT CAS, 4} 13 16 > SP/EN Gnd + 14 15 CAS)