FACULTY OF ELECTRICAL ENGINEERING

UNIVERSITI TEKNOLOGI MALAYSIA

SEEL4743: BASIC DIGITAL VLSI DESIGN

INDIVIDUAL ASSIGNMENT
HOMEWORK 1: MOSFET
1 MAY 2023
SECTION 2

Lecturer:
DR. MUHAMMAD AFIQ NURUDIN BIN HAMZAH

NAME MATRIC NO.

MUHAMMAD AMANULLAH BIN ABDUL SALAM A20EE0134

 INDIVIDUAL HOMEWORK 1: MOSFET

1. Determine the operating region of PMOS and NMOS in Table 1 and Table 2 respectively.
Show the manual hand calculation of the drain current and verify the value using LTSPICE
simulation. Assume long channel MOSFET and ignore channel length modulation. Include the
LEVEL=1 or the standard SPICE parameters as in appendix in your simulation.

a) PMOS

Table 1: PMOS characteristics

VGS (V) VDS (V) VB (V) W/L ID ID Mode of
(calculation) (simulation) operation
-0.9 -1.5 1.0 1.50/0.25 8.312µA 8.311µA Pinch-off
saturation
-1.2 -2.0 3.0 0.75/0.25 5.541µA 5.541µA Pinch-off
saturation

Case 1:

|VGS | = 0.9V
VTp changes value due to body effect
VTp = VT0 + 𝛾[ √|−2∅𝐹 + VSB | − √|−2∅𝐹 | ]
VSB = VS - VB = 0 – 1 = -1V
VTp =−0.40 + (−0.4)[ √|−2(0.3) + (−1)| − √|−2(0.3)| ]
= -0.5961V
|VTp | = 0.5961V

|VGS | > |VTp | : PMOS ‘ON’

|VGS - VTp | = |-0.9 – (-0.5961) | = 0.3039V
|VDS | = 1.5V > |VGS - VTp | : Pinch-off saturation region

𝑘′ 𝑊
I𝐷 = | | ( ) (|VGS − VTp |)2
2 𝐿
30µ 1.50
I𝐷 = (0.25) ( 0.3039)2
2
= 8.312µA
Figure 1: Schematic of PMOS circuit case 1

Figure 2: Simulation result for PMOS

Figure 3: Error log for PMOS simulation

Case 2:

|VGS | = 1.2V
VTp changes value due to body effect

VTp = VT0 + 𝛾[ √|−2∅𝐹 + VSB | − √|−2∅𝐹 | ]

VSB = VS - VB = 0 – 3 = -3V
VTp =−0.40 + (−0.4)[ √|−2(0.3) + (−3)| − √|−2(0.3)| ]
= -0.8491V
|VTp | = 0.8491V

|VGS | > |VTp | : PMOS ‘ON’

|VGS - VTp | = |-1.2 – (-0.8491) | = 0.3509V
|VDS | = 2V > |VGS - VTp | : Pinch-off saturation region

𝑘′ 𝑊
I𝐷 = | | ( 𝐿 ) (|VGS − VTp |)2
2
30µ 0.75
I𝐷 = (0.25) ( 0.3509)2
2

= 5.541µA

Figure 4: Schematic for PMOS case 2

 Figure 5: Simulation result for PMOS

Figure 6: Error log for PMOS simulation

 b) NMOS

Table 2: NMOS characteristics

𝑉𝐺𝑆 (𝑉) 𝑉𝐷𝑆 (𝑉) 𝑉𝐵 (𝑉) W/L 𝐼𝐷 𝐼𝐷 Mode of
(𝑐𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑖𝑜𝑛) (𝑠𝑖𝑚𝑢𝑙𝑎𝑡𝑖𝑜𝑛) operation
1.6 0.5 0.0 2.50/0.25 529µA 529µA Linear
1.2 1.4 -1.0 1.20/0.25 90.90µA 90.90µA Pinch-off
saturation

Case 1:

VGS = 1.6V, VTn = 0.43V

VGS > VTn : NMOS ‘ON’
VGS - VTn = 1.6-0.43 = 1.17V
VDS = 0.5V < VGS - VTn : Linear region

𝑊 VDS 2
I𝐷 = 𝑘 ′ ( 𝐿 ) [(VGS - VTn )VDS − )]
2
2.50 0.52
ID = (115µ) (0.25) [(1.17)0.5 − )] = 529µA
2

Figure 7: Schematic for NMOS case 1

Figure 8: Simulation result for NMOS

 Figure 9: Error log for NMOS simulation

Case 2:

VGS = 1.2V
VTn changes value due to body effect
VTn = VT0 + 𝛾[ √|−2∅𝐹 + VSB | − √|−2∅𝐹 | ]
VSB = VS - VB = 0 – (-1) = 1V
VTn = 0.43 + 0.4[ √|−2(−0.3) + (1)| − √|−2(−0.3)| ]
= 0.6261V

VGS > VTn : NMOS ‘ON’

VGS - VTn = 1.2-0.6261 = 0.5739V
VDS = 1.4V > VGS - VTn : Pinch-off saturation region

𝑘′ 𝑊
I𝐷 = ( ) (VGS − VTn )2
2 𝐿
115µ 1.20
I𝐷 = (0.25) ( 0.5739)2
2
= 90.90µA
 Figure 10: Schematic for NMOS case 2

Figure 11: Simulation result for NMOS

Figure 12: Error log for NMOS simulation

2. Based on Figure 1 below, answer the following questions.
(a) The operating region of both PMOS and NMOS.
(b) The drain current, IDS of the transistor.
(c) Plot the I-V characteristics of IDS-VGS and IDS-VDS for part 1 using LTSPICE. You
must do simulation for both standard transistor parameters of 0.25 𝜇m process and
BSIM3 (level 49). Submit must attach .op file in the report.

PMOS

VGS = VG - VS
= -0.3 – (-0.9)
= 0.6V

VDS = VD - VS
= -1.5 – (-0.9)
= -0.6V

𝑊/𝐿= 5/3

VTp = -0.4V
VGS > VTp : PMOS ‘OFF’: Cut-off region
I𝐷 ≈ 0𝑉

There may be some current due to sub-threshold conductance, but the value is negligible.

Figure 13: Schematic for PMOS circuit (Level 1)

Figure 14: Simulation result for PMOS LEVEL=1

Figure 15: Error log for PMOS LEVEL=1

 Figure 16: VDS vs IDS for LEVEL=1 (PMOS DC Sweep Simulation)

Figure 17: VDS vs IDS for LEVEL=1 (PMOS DC Sweep Simulation with cursor)

Figure 18: VGS vs IDS for LEVEL=1 (PMOS DC Sweep Simulation)

Figure 19: VGS vs IDS for LEVEL=1 (PMOS DC Sweep Simulation with cursor)
 Figure 20: Schematic for PMOS circuit (LEVEL49-BSIM3)

Figure 21: PMOS Operating Point Output (LEVEL 49-BSIM3)

Figure 22: PMOS Spice Error Log (LEVEL 49-BSIM3)

 Figure 22: VDS vs IDS for (PMOS DC Sweep Simulation)

Figure 23: VDS vs IDS for (PMOS DC Sweep Simulation with cursor)

Figure 24: VGS vs IDS for (PMOS DC Sweep Simulation)

Figure 25: VGS vs IDS for (PMOS DC Sweep Simulation with cursor)
NMOS

VGS = 1.6 – 0.5

= 1.1V

VDS = 2 – 0.5
= 1.5V

VTn = 0.43V

VGS > VTn : NMOS ‘ON’

VGS - VTn = 1.1-0.43 = 0.67V

VDS = 1.5V > VGS - VTn : Saturation region

𝑘′ 𝑊
I𝐷 = ( ) (VGS − VTn )2(1+λVDS )
2 𝐿
115µ 5
I𝐷 = (1) ( 0.67)2 (1+(0.06) (1.5))
2
= 140.67µA

Figure 26: NMOS DC Biasing Circuit Schematic Diagram (LEVEL1)

Figure 27: NMOS Operating Point Output (LEVEL 1)

Figure 28: NMOS Spice Error Log (LEVEL 1)

 Figure 29: VDS vs IDS for LEVEL=1 (NMOS DC Sweep Simulation)

Figure 30: VDS vs IDS for LEVEL=1 (NMOS DC Sweep Simulation with cursor)

Figure 31: VGS vs IDS for LEVEL=1 (NMOS DC Sweep Simulation)

Figure 32: VGS vs IDS for LEVEL=1 (NMOS DC Sweep Simulation with cursor)
 Figure 33: Schematic for NMOS circuit (LEVEL49-BSIM3)

Figure 34: Simulation result for NMOS (LEVEL49-BSIM3)

Figure 35: Error log for NMOS simulation (LEVEL49-BSIM3)

 Figure 36: VDS vs IDS for (NMOS DC Sweep Simulation)

Figure 37: VDS vs IDS for (NMOS DC Sweep Simulation with cursor)

Figure 38: VGS vs IDS for (NMOS DC Sweep Simulation)

Figure 39: VGS vs IDS for (NMOS DC Sweep Simulation with cursor)
DISCUSSION

Table 3: Comparison of MOSFET Parameters

MOSFET 𝑉𝐺𝑆 (𝑉) 𝑉𝐷𝑆 (𝑉) 𝑉𝐵 (𝑉) W/L 𝐼𝐷 𝐼𝐷 Mode of
(𝑐𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑖𝑜𝑛) (𝑠𝑖𝑚𝑢𝑙𝑎𝑡𝑖𝑜𝑛) operation
Level 1 BSIM3

PMOS -0.3 -1.5 -0.9 5/3 0.00µA -1.21pA -610fA Cut-off

region (off)
NMOS 1.2 1.4 -1.0 1.20/0.25 140.674µA 140.674µ 190.697 Saturation
A µA region due
to Pinch-
off

By comparing the values of the parameters acquired from the calculation and the
simulation for both LEVEL1 and BSIM3, Table 3 summarizes the results obtained for both the
given PMOS and NMOS circuit. Based on the simulation, it can be seen that the ID values of
the two MOSFETs are quite near to one another when using LEVEL1 simulation, with such
little calculation mistakes. This is because the theoretical computation and LEVEL1 simulation
both use the same standard transistor values. The model is full, thus there are no discontinuities,
but there are significant changes when they are compared to the values produced from BSIM3
simulation. As they are not in the optimal state due to a number of circumstances, this is typical
in real-world and even simulated scenarios.

CONCLUSION

Based on the entire assignment, it can also be inferred that we can determine a
MOSFET's operating condition, whether it is in cut-off region, linear region, or saturation
region, by calculating a PMOS or NMOS parameter for threshold voltage, gate-source current,
and drain-source current. I was unable to observe short-channel effects like velocity saturation
because they were completely ignored throughout the experiment. Nevertheless, the
assignment gave me a general idea of how to approach a circuit with different operation regions
due to various occurrences. As they are not in the optimal state due to a number of
circumstances, this is typical in real-world and even simulated scenarios.
As a result of variations in the MOSFET characteristics, simulations utilising the
LEVEL1 and BSIM3 simulation models would produce different results for the drain current,
I. Due to unclear real-world elements, however, D experimental findings could differ even
more than those of the BSIM3 simulation, and theoretical calculations can be quickly
confirmed using the LTSpice simulation.
REFERENCE
PMOS VS NMOS: Focus on Two Main Forms of MOSFET. (2022, October 25). Wevolver.
https://www.wevolver.com/article/pmos-vs-nmos-focus-on-two-main-forms-of-
mosfet

Anysilicon. (2022, July 3). Introduction to NMOS and PMOS Transistors - AnySilicon.
AnySilicon. https://anysilicon.com/introduction-to-nmos-and-pmos-transistors/

BSIM3 Model (BSIM3 MOSFET Model) - ADS 2009 - Keysight Knowledge Center. (n.d.).
https://edadocs.software.keysight.com/pages/viewpage.action?pageId=5908900#app-
switcher

LEVEL1 Model (MOSFET Level-1 Model) - ADS 2009 - Keysight Knowledge Center. (n.d.).
https://edadocs.software.keysight.com/pages/viewpage.action?pageId=5908967