Detailed BIU and CU

BIU unit and CU in 8086 in very detailed

The Intel 8086 microprocessor, a 16-bit microprocessor, is designed with a unique architecture that
includes two main units: the Bus Interface Unit (BIU) and the Execution Unit (EU). Understanding these
units is crucial for grasping how the 8086 operates. Let's delve into the details of each unit.

Bus Interface Unit (BIU)

The Bus Interface Unit is responsible for interfacing with the system buses. Its main tasks include
fetching instructions from memory, reading and writing data to memory and I/O ports, and handling
address generation. Here are the key components and functions of the BIU:

1. Instruction Queue:
The BIU contains a 6-byte instruction queue. This prefetch queue fetches instructions from
memory ahead of time and stores them. This allows the CPU to execute instructions
without waiting for them to be fetched, thus improving efficiency through pipelining.
2. Segment Registers:
The BIU contains four segment registers: CS (Code Segment), DS (Data Segment), SS (Stack
Segment), and ES (Extra Segment). These registers hold the upper 16 bits of the starting
address of each segment, allowing the 8086 to access a 1 MB memory space despite having
only 16-bit address registers.
Code Segment Register (CS): Points to the segment containing the executable program.
Data Segment Register (DS): Points to the segment containing data.
Stack Segment Register (SS): Points to the segment containing the stack.
Extra Segment Register (ES): Used for additional data segment purposes.
3. Instruction Pointer (IP):
The IP register holds the offset address of the next instruction to be executed within the
code segment.
4. Address Generation:
The BIU generates the 20-bit physical address by combining the segment base address
from the segment registers with the offset address from the IP or other pointer/index
registers.
5. Bus Control:
The BIU manages control signals for read and write operations and coordinates data
transfers over the system bus. It handles memory read/write cycles and I/O operations.

Execution Unit (EU)

The Execution Unit is responsible for executing instructions. It decodes instructions, performs
arithmetic and logic operations, and controls the general-purpose and special-purpose registers. Here

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 are the key components and functions of the EU:

1. General-Purpose Registers:
The EU contains eight general-purpose registers, which can be used for a variety of
purposes, including arithmetic operations, data storage, and address calculation.
AX (Accumulator): Used for arithmetic, logic operations, and data transfer.
BX (Base): Primarily used for addressing memory.
CX (Count): Used in loop and string operations.
DX (Data): Used in arithmetic operations and I/O operations.
These registers can be accessed in their entirety as 16-bit registers or as 8-bit registers
(AH/AL, BH/BL, CH/CL, DH/DL).
2. Special-Purpose Registers:
Instruction Decoder: Decodes the fetched instruction to determine the operation to be
performed.
Arithmetic Logic Unit (ALU): Performs arithmetic operations (addition, subtraction, etc.)
and logic operations (AND, OR, XOR, NOT).
Flag Register: Contains status flags that indicate the outcome of operations and control
the execution flow (e.g., Zero Flag, Carry Flag, Sign Flag, Overflow Flag).
3. Pointer and Index Registers:
SP (Stack Pointer): Points to the top of the stack in the stack segment.
BP (Base Pointer): Used to access data on the stack.
SI (Source Index): Used for string and memory array operations.
DI (Destination Index): Used for string and memory array operations.
4. Control Unit:
Coordinates the execution of instructions by controlling the operation of the ALU, registers,
and other components of the EU.

Interaction Between BIU and EU

The BIU and EU operate in a loosely coupled manner. While the EU executes one instruction, the
BIU fetches the next instruction from memory. This parallelism increases the overall processing
speed.
The BIU fetches instructions from memory into the instruction queue. The EU retrieves the next
instruction from the queue, decodes it, and executes it.
The BIU handles memory addressing and data transfers, allowing the EU to focus on instruction
execution and arithmetic/logic operations.

By dividing the workload between the BIU and EU, the 8086 microprocessor achieves efficient
instruction processing and effective use of the system bus, making it a powerful and versatile CPU for
its time.

give me in more detailed

Certainly! Let's delve deeper into the details of the Bus Interface Unit (BIU) and Execution Unit (EU) in
the Intel 8086 microprocessor.

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 Bus Interface Unit (BIU)

The BIU is responsible for handling all bus operations such as instruction fetching, reading and
writing data from/to memory and I/O ports. It works independently of the EU to improve the overall
efficiency of the microprocessor. Here’s a more detailed look into its components and functions:

1. Instruction Queue:
The instruction queue in the BIU is a 6-byte First-In-First-Out (FIFO) buffer. This queue
allows the BIU to fetch up to six bytes of instructions in advance, which can then be quickly
accessed by the EU for execution.
By prefetching instructions, the BIU can overlap instruction fetching with instruction
execution, significantly increasing throughput by reducing idle times.
2. Segment Registers:
The 8086 has four 16-bit segment registers that allow it to address a 1 MB memory space
through a segmentation mechanism. Each segment register holds the base address of a
segment.
Code Segment Register (CS): This register holds the base address of the code segment,
where executable instructions are stored. The value in CS is shifted left by 4 bits and added
to the Instruction Pointer (IP) to get the physical address of the next instruction.
Data Segment Register (DS): This register holds the base address of the data segment,
where most data variables are stored. It is used by default for most data operations.
Stack Segment Register (SS): This register holds the base address of the stack segment. It
is used during stack operations such as PUSH and POP.
Extra Segment Register (ES): This register is used for string operations and additional data
segments.
3. Instruction Pointer (IP):
The IP register works in tandem with the CS register to point to the next instruction to be
executed. The physical address of the next instruction is calculated by adding the shifted
value of CS to the value in IP.
4. Address Generation:
The BIU combines the 16-bit segment address from the segment registers with a 16-bit
offset (from IP or other pointer/index registers) to form a 20-bit physical address. This
allows access to 1 MB of memory space despite the 8086 having 16-bit address registers.
5. Bus Control:
The BIU controls the data and address buses, manages read and write operations, and
generates necessary control signals. It ensures that data transfers between the CPU and
memory or I/O ports are correctly timed and coordinated.

Execution Unit (EU)

The EU is responsible for decoding and executing instructions fetched by the BIU. It contains the
arithmetic logic unit (ALU), control circuits, and registers needed for instruction execution. Here’s a
detailed breakdown of its components and functions:

1. General-Purpose Registers:
The EU has eight general-purpose registers, each 16 bits wide. These registers can be used
for a variety of operations and can be accessed in full (16-bit) or split into two 8-bit halves.
AX (Accumulator): Used for arithmetic operations, logic operations, and data transfer. It
can be accessed as AX (16-bit), AH (high 8-bit), and AL (low 8-bit).

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 BX (Base): Primarily used for indexed addressing and data manipulation. It can be accessed
as BX, BH, and BL.
CX (Count): Used in loop and string operations. It can be accessed as CX, CH, and CL.
DX (Data): Used in arithmetic operations, I/O operations, and data transfers. It can be
accessed as DX, DH, and DL.
2. Special-Purpose Registers:
Instruction Decoder: The instruction decoder interprets the fetched instruction and
determines the operations to be performed.
Arithmetic Logic Unit (ALU): The ALU performs arithmetic operations like addition,
subtraction, multiplication, division, and logic operations like AND, OR, XOR, and NOT.
Flag Register: This register contains status flags that indicate the results of operations and
control certain aspects of the CPU's operation. Key flags include:
Zero Flag (ZF): Set if the result of an operation is zero.
Sign Flag (SF): Set if the result of an operation is negative.
Carry Flag (CF): Set if there is a carry out from the most significant bit in an arithmetic
operation.
Overflow Flag (OF): Set if there is a signed overflow.
Parity Flag (PF): Set if the number of set bits in the result is even.
Auxiliary Carry Flag (AF): Set if there is a carry from the lower nibble (useful for BCD
operations).
Direction Flag (DF): Controls the direction of string operations.
Interrupt Enable Flag (IF): Enables or disables interrupts.
3. Pointer and Index Registers:
SP (Stack Pointer): Points to the top of the stack in the stack segment. It is used during
push and pop operations.
BP (Base Pointer): Used to access data on the stack. It is typically used in high-level
language procedure calls to reference parameters and local variables.
SI (Source Index): Used for string operations and as a general-purpose index register for
memory addressing.
DI (Destination Index): Used for string operations and as a general-purpose index register
for memory addressing.
4. Control Unit:
The control unit within the EU coordinates the execution of instructions by controlling the
ALU, registers, and other components. It ensures that each step of the instruction cycle
(fetch, decode, execute) is carried out correctly.

Interaction Between BIU and EU

Parallelism and Pipelining:

The BIU and EU work in parallel to increase the efficiency of the CPU. While the EU is busy
executing an instruction, the BIU fetches the next instruction(s) into the instruction queue.
This overlapping of operations is a form of pipelining, which improves the instruction
throughput.
Instruction Fetching:
The BIU fetches instructions from memory and places them into the instruction queue.
When the EU needs to execute an instruction, it pulls it from the queue. If the queue is
empty, the EU must wait for the BIU to fetch more instructions.
Address Calculation:
When the EU needs to access memory (for example, to fetch an operand or store a result), it
provides the necessary offset. The BIU uses the segment registers and this offset to

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 calculate the physical address and performs the memory operation.
Data Transfer:
Data transfers between the CPU and memory or I/O devices are managed by the BIU. The
EU initiates these transfers, and the BIU handles the actual read/write operations on the
bus.

By splitting the responsibilities between the BIU and EU, the 8086 microprocessor can achieve more
efficient operation and better performance. This division of labor allows for the simultaneous fetching
of instructions and execution of operations, leveraging the strengths of both units.

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