Birla Institute of Technology & Science, Pilani

Work-Integrated Learning Programmes Division

First Semester 2023-2024
Mid Semester Exam
(EC-2 Regular)
Course No. : MEL ZG632
Course Title : ANALOG IC DESIGN
Nature of Exam : Closed Book
Pattern of Exam : Typed Only No. of Pages =
Weightage : 30% No. of Questions = 5
Duration : 2 Hours
Date of Exam :
Note:
1. Please follow all the Instructions to Candidates given on the test portal.
2. Assumptions made if any, should be stated clearly at the beginning of your answer.

Important. The following equations may be used. The equations may not be reproduced verbatim in
the text box, but equations with correct substitutions from the question are required for step marking.
Only final answers without steps will fetch only partial marks. For full marks, please fill in all the
steps involved in solving the question.

1. Current of n-MOSFET in saturation

2. Small signal output resistance of n-MOSFET in saturation

3. Small signal transconductance of n-MOSFET in saturation

4. Small signal output resistance of n-MOSFET Cascode

5. Small Signal gain of Source degenerated CS amplifier

6. Small Signal gain of CD amplifier

Where R’L is RL||RS.

Q.1.
For amplifier shown below VDD = 2.5 V. All transistors are in saturation. Neglect body effect.
Channel length modulation is to be neglected for DC analysis. Find: -
(i) The DC voltage at the gates of the pMOSFETs. (2)
(ii) Small signal output resistance at node Vout. (2)
(iii) Small signal differential gain (2)

Total 6 Marks
Q.2.
For amplifier shown below VDD = VSS= 0.9 V. RL= 5 K. The bias current I_BIAS is 0.1 mA.
Neglect body effect. Find: -
(i) Find V_BIAS for DC volage of 0 V at Vout. Assume λ =0 (2)
(ii) Find small signal gain . Assume λ =0 (2)
(iii) Find V_BIAS for DC volage of 0 V at Vout, if λ = 0.2 (2)

Total 6Marks
Q.3.
Consider the cascode current mirror shown in figure below having I in = 0.1 mA. Neglect body effect.
Neglect channel length modulation for DC analysis. Find
(i) Small signal output resistance rout. (3)
(ii) Minimum DC Vout for Q2 and Q4 to be in saturation (3)
Total 6Marks
Q.4.
Consider the circuit shown below shown in figure below having I bias = 0.1 mA. Neglect body effect.
Neglect channel length modulation for DC analysis. Find
(i) Transconductance gm (1)
(ii) Small signal output resistance rout. (1)
(iii) Small signal gain (1)
(iv) If the gain is to be increased by 20% by increasing the width of only Q1, find the new
gain, new transconductance, and new width. (3)
Total 6Marks
Q.5.
Consider the circuit shown below shown in figure below. VDD = 1.8 V, RD = 10 K and RS = 5 K
Neglect body effect. DC voltage at Vout_D = 1.2 V. at Find
(i) The width of the mosfet for transconductance gm = 0.6 mA/V (1)
(ii) V_Bias. (1)
(iii) Small signal gain at Vout_D (2)
(iv) Small signal gain at Vout_S (2)
Total 6Marks