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VLSI Design :Lecture 4
CMOS Inverter Static Characteristics
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

TTL Nosie Margins
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Noise Margin
For MOSFET Inverters
V IH , V IL are operational
points of inverter where
dVout /dVin = -1
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Resistive Load Inverter
𝑉𝐷𝐷
𝐼=
𝑅𝐿
VGS=VDD
VGS=0
V0 (VDS)
Ratioed logic
Trade off Power vs. Speed vs. VOL

4
MOSFET Current Equations
′ 𝑊𝑉 𝑉
𝑘𝑛 𝑜𝑣 𝐷𝑆
1. 𝐼𝐷 = Small VDS
𝐿
′ 𝑊(𝑉 − 𝑉𝐷𝑆 )𝑉
𝑘𝑛 𝑜𝑣 2 𝐷𝑆
2. 𝐼𝐷 = As VDS Increases (VDS < VGS-VT) : Linear Region
𝐿
𝐺𝑆 − 𝑉𝑇 )
′ 𝑊(𝑉
𝑘𝑛 2
3. 𝐼𝐷 = VDS > VGS-VT) : Saturation Region
2𝐿
′𝑊
𝑘𝑛 𝐾𝑛 (𝑉𝐺𝑆 − 𝑉𝑇 )2
𝐾𝑛 = 𝐼𝐷 =
𝐿 2
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Calculation of VOH
VOut = VDD - RL IR
VOH = VDD
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Calculation of VOL
Ratioed logic
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Calculation of VIL
Differentiating both sides with respect to Vin
𝑑𝑉0
[ 𝑑𝑉𝑖 = -1]
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Calculation of VIH
Differentiating both sides with respect to Vin
𝑑𝑉0
[ 𝑑𝑉𝑖 = -1]
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𝐾𝑛 (𝑉𝐺𝑆 − 𝑉𝑇 )2
𝐼𝐷 =
2
Trade off
Power vs. VOL
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Enhancement-Load nMOS Inverter
➢ Relatively simple fabrication process ➢ Two separate power supply

➢ VOH level is limited to VDD - VT ➢ VOH = VDD
➢ High Static Power
➢ Ratioed ?? Tradeoffs?
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Depletion-Load nMOS Inverter
Depletion-type nMOS load is more complicated & requires additional processing steps
➢ VOH = VDD
➢ Single power supply
➢ High Static Power
➢ Ratioed ?? Tradeoffs?
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Depletion-Load nMOS Inverter
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The CMOS Inverter
It is the nucleus of all digital designs
Assumed infinite off-resistance for VGS < VTH and finite on-resistance for VGS > VTH
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Important properties of static CMOS
➢ Rail-to-Rail O/p : The high and low output levels equal VDD and GND, respectively. This
results in high noise margins.
➢ Ratioless: The logic levels are not dependent upon the relative device sizes, so that the
transistors can be minimum size.
➢ In steady state, there always exists a path with finite resistance between the output and
either VDD or GND.
➢ The input resistance of the CMOS inverter is extremely high, the steady-state input current
is nearly zero.
➢ A single inverter can theoretically drive an infinite number of gates (or have an infinite fan-
out) and still be functionally operational. However, increasing the fan-out also increases the
propagation delay.
➢ No direct path exists between the supply and ground rails under steady-state operating
conditions (this is, when the input and outputs remain constant). The absence of current
flow (ignoring leakage currents) means that the gate does not consume any static power.
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The PMOS Load Line
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CMOS Inverter Load Characteristic
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CMOS Inverter Load Characteristic
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CMOS Inverter VTC
The VTC of the inverter hence exhibits a very narrow transition zone. This results from the
high gain during the switching transient, when both NMOS and PMOS are simultaneously
on, and in saturation. In that operation region, a small change in the input voltage results in
a large output variation.
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CMOS Inverter Switching Threshold
The Switching Threshold, VM , is the point where Vin = Vout .
This can be calculated:
» Graphically, at the intersection of the VTC with Vin = Vout
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For Short Channel Devices
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Increasing the width of the PMOS moves VM towards VDD
Increasing the width of the NMOS moves VM towards GND
𝞫 -> VM (250 nm VDD = 2.5 V)
3 -> 1.22 V
2.5 -> 1.18 V
2 -> 1.13 V
Since it not making much
difference
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Noise Margin
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Noise Margin
For VIL
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Noise Margin
For VIH
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Static Loss
➢ Causes for High Static Power Consumption
Effect of Decreasing VDD on Delay
𝐾1 𝐶𝐿 𝐾2𝐶𝐿
𝑃𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛 𝐷𝑒𝑙𝑎𝑦 (𝑡𝑝𝑑) = = 2`
𝐼𝐷 𝑉𝐷𝐷−𝑉𝑡ℎ
Effect of Decreasing Vth on Power
• Intel estimated leakage power consumption at more than 50W for a

100nm technology node.
• Leakage depends strongly on a Threshold voltage (Vth) of the transistor
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Static Loss
2/3/2024 31

Static Loss
➢ Reducing Static Loss
• Device Level Techniques
Tunnel Field Effect Transistors
CNFETs
• Circuit Level Techniques when using CMOS
[3] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage c rre mecha sms

and leakage reduction techniques in deep-submicrometer CMOS c rc s,” Pr ceed gs f he
IEEE, vol. 91, no. 2, pp. 305–327, Feb. 2003.
2/3/2024 32

Static Loss
Multiple VDD for Power Reduction
[5] M. Pedram and J.M. Rabaey, “P wer aware design Me h d l g es,”

[Online]. Available: https://www.springer.com/gp/book/9781402071522
2/3/2024 33

Static Loss
Challenges of Multi-VDD Design
➢ The additional supply voltage VDD needs to be created

on-chip by a dc to dc converter.
➢ Area overhead, and in power consumption for the converter.
➢ Level-shifters are required between different supply domains.
➢ Multiple Routing
2/3/2024 34

Static Loss
Multi-Vth Design
[5] M. Pedram and J.M. Rabaey, “P wer aware design Me h d l g es,”

[Online]. Available: https://www.springer.com/gp/book/9781402071522
35
2/3/2024
Static Loss
Challenges of Multi-Vth Design
➢ ADDITIONAL MASKS
➢ FOR EACH SUCH OPTION, THE DESIGN LIBRARY MUST BE

ELECTRICALLY CHARACTERIZED, MODELED FOR ALL
DESIGN TOOLS
36
2/3/2024
Thank you
2/3/2024 37

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VLSI Design :Lecture 4

CMOS Inverter Static Characteristics

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

For MOSFET Inverters

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Trade off Power vs. Speed vs. VOL

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Differentiating both sides with respect to Vin

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Differentiating both sides with respect to Vin

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

➢ Relatively simple fabrication process ➢ Two separate power supply

➢ High Static Power

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

𝞫 -> VM (250 nm VDD = 2.5 V)

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

Effect of Decreasing VDD on Delay

• Intel estimated leakage power consumption at more than 50W for a

• Leakage depends strongly on a Threshold voltage (Vth) of the transistor

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

[3] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage c rre mecha sms

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

[5] M. Pedram and J.M. Rabaey, “P wer aware design Me h d l g es,”

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

➢ The additional supply voltage VDD needs to be created

➢ Area overhead, and in power consumption for the converter.

➢ Level-shifters are required between different supply domains.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

[5] M. Pedram and J.M. Rabaey, “P wer aware design Me h d l g es,”

➢ FOR EACH SUCH OPTION, THE DESIGN LIBRARY MUST BE

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

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