Course: Machine Learning (2EC602).

Experiment 8: Implementation of control section of the single-cycle data path

for MicroMIPS.
Name: Vedant A. Rokad
Roll No.: 21BEC106

Lab Exercise:

Que
Implementation of control section of the single-cycle data path for MicroMIPS.

Source Code and Output

module
datapath_SC(opcode,fn,RegWrite,RegDst,RegInSrc,ALUSrc,Add_Sub,LogicFn,FnClass,DataR
ead,DataWrite,BrType,PCSrc);
input [5:0]opcode,fn;
//input clk;
output reg RegWrite,ALUSrc,Add_Sub,DataRead,DataWrite;
output reg [1:0]RegDst,RegInSrc,LogicFn,FnClass,BrType,PCSrc;

always@(opcode) begin
case(opcode)
6'b001111 : begin
RegWrite = 1;
RegDst = 0;
RegInSrc = 1;
ALUSrc = 1;
FnClass = 0;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b000000 :
case(fn)
6'b100000 : begin
RegWrite = 1;
RegDst = 1;
RegInSrc = 1;
ALUSrc = 0;
Add_Sub = 0;
FnClass = 2;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b100010 : begin
RegWrite = 1;
RegDst = 1;
RegInSrc = 1;
ALUSrc = 0;
Add_Sub = 1;
FnClass = 2;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b101010 : begin
RegWrite = 1;
RegDst = 1;
RegInSrc = 1;
 ALUSrc = 0;
Add_Sub = 1;
FnClass = 1;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b100100 : begin
RegWrite = 1;
RegDst = 1;
RegInSrc = 1;
ALUSrc = 0;
LogicFn = 0;
FnClass = 3;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b100101 : begin
RegWrite = 1;
RegDst = 1;
RegInSrc = 1;
ALUSrc = 0;
LogicFn = 1;
FnClass = 3;
DataRead = 0;
DataWrite= 0;
BrType = 0;
 PCSrc = 0;
end
6'b100110 : begin
RegWrite = 1;
RegDst = 1;
RegInSrc = 1;
ALUSrc = 0;
LogicFn = 2;
FnClass = 3;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b100111 : begin
RegWrite = 1;
RegDst = 1;
RegInSrc = 1;
ALUSrc = 0;
LogicFn = 3;
FnClass = 3;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b001000 : begin
RegWrite = 0;
DataRead = 0;
DataWrite= 0;
 PCSrc = 2;
end
6'b001100 : begin
RegWrite = 0;
DataRead = 0;
DataWrite= 0;
PCSrc = 3;
end
endcase
6'b001000 : begin
RegWrite = 1;
RegDst = 0;
RegInSrc = 1;
ALUSrc = 1;
Add_Sub = 0;
FnClass = 2;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b001010 : begin
RegWrite = 1;
RegDst = 0;
RegInSrc = 1;
ALUSrc = 1;
Add_Sub = 1;
FnClass = 1;
DataRead = 0;
DataWrite= 0;
 BrType = 0;
PCSrc = 0;
end
6'b001100 : begin
RegWrite = 1;
RegDst = 0;
RegInSrc = 1;
ALUSrc = 1;
LogicFn = 0;
FnClass = 3;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b001101 : begin
RegWrite = 1;
RegDst = 0;
RegInSrc = 1;
ALUSrc = 1;
LogicFn = 1;
FnClass = 3;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b001110 : begin
RegWrite = 1;
RegDst = 0;
 RegInSrc = 1;
ALUSrc = 1;
LogicFn = 2;
FnClass = 3;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b100011 : begin
RegWrite = 1;
RegDst = 0;
RegInSrc = 0;
ALUSrc = 1;
Add_Sub = 0;
FnClass = 2;
DataRead = 1;
DataWrite= 0;
BrType = 0;
PCSrc = 0;
end
6'b101011 : begin
RegWrite = 0;
ALUSrc = 1;
Add_Sub = 0;
FnClass = 2;
DataRead = 0;
DataWrite= 1;
BrType = 0;
PCSrc = 0;
end
6'b000010 : begin
RegWrite = 0;
DataRead = 0;
DataWrite= 0;
PCSrc = 1;
end
6'b000001 : begin
RegWrite = 0;
DataRead = 0;
DataWrite= 0;
BrType = 3;
PCSrc = 0;
end
6'b000100 : begin
RegWrite = 0;
DataRead = 0;
DataWrite= 0;
BrType = 1;
PCSrc = 0;
end
6'b000101 : begin
RegWrite = 0;
DataRead = 0;
DataWrite= 0;
BrType = 2;
PCSrc = 0;
end
6'b000011 : begin
RegWrite = 1;
 RegDst = 2;
RegInSrc = 2;
DataRead = 0;
DataWrite= 0;
BrType = 0;
PCSrc = 1;
end
endcase
end
endmodule

Result: