EE5311 Project

Group - 34
Uttam Raj (EE20B118)
Ruthika (EE20B065)
Yashwanth (EE20B048)

Maximum clock frequency w/o pipelining for the 2.15GHz

schematic

Maximum clock frequency w/o pipelining layout 1.57GHz

extracted netlist

Worst case delay for RC-extracted CSM w/o 502.28ps

pipelining(-128x3)

Maximum clock frequency with pipelining using the 2.76GHz

layout extracted netlist

Area of the DRC and LVS clean CSM. 2

113.953µ𝑚

Number of test patterns you verified the functionality 5

of your CSM.
DRC and LVS of Sub blocks used in CSM:

Inverter - (1x)

NAND2 - 1X:
AND2 - 1X:

Full adder - C3S1:

Block diagram of 8-bit signed CSM: (Schematic)

Optimisations done:
● Inverters are removed from the critical path at the rippling stage and instead
placed at inputs of the full adders.
● All the adders used are inverting. Simulated for various sizes and inputs to
find the critical path and optimal sizes.
CSM Layout:

DRC and LVS of CSM layout:

Area :

2 2
Area is 941760λ = 113.953µ𝑚
Using the entire CSM RC Extracted layout, the delay for the input combination
-128x3 is 502.28ps
The critical path of CSM is given below:
By simulating the critical path with the worst propagation input condition:
Schematic: (Non-pipelined)
The worst case combinational delay we got is 439.423ps
Hence, the maximum operating frequency of the CSM (without Pipeline) is
1
= (𝑡𝑐𝑞 + 𝑐𝑜𝑚𝑏𝑖𝑛𝑎𝑡𝑖𝑜𝑛𝑎𝑙 𝑑𝑒𝑙𝑎𝑦 + 𝑡𝑠𝑒𝑡𝑢𝑝)
1
= (3.43 + 439.423 + 22)𝑝𝑠
= 2.15GHz
Using sub-block RC Extracted Netlists: (Non-pipelined)
The worst case combinational delay we got is 612.049ps
Hence, the maximum operating frequency of the CSM (without Pipeline) is
1
= (𝑡𝑐𝑞 + 𝑐𝑜𝑚𝑏𝑖𝑛𝑎𝑡𝑖𝑜𝑛𝑎𝑙 𝑑𝑒𝑙𝑎𝑦 + 𝑡𝑠𝑒𝑡𝑢𝑝)
1
= (3.43 + 612.049 + 22)𝑝𝑠
= 1.57GHz

Construction of D Flip flop:

Constructed a C2MOS Positive edge triggered flip flop. We used dynamic flip flop
instead of static flip flop because it has good performance in terms of setup and
clock to q delays. Since the frequency is high, we will not have much voltage
discharge at output.

Schematic:
 Flip flop Characteristics:

Setup time is t_dc at which t_dq is minimum and the corresponding t_cq is t_pcq.
● Minimum t_dq is observed in the falling edge case that is 25.43ps.
● The corresponding t_dc is 22ps and t_cq is 3.43ps.
Hence, setup time is 22ps and t_pcq is 3.43ps.

The optimal position of flip flops was found to be after 5 flip flops in the
critical path.
Schematic: (Pipelined)
The combinational delays we get are 238ps and 201.5ps
The worst possibility from the above is 238ps.
Hence, the maximum operating frequency of the CSM (without Pipeline) is
1
= (𝑡𝑐𝑞 + 𝑐𝑜𝑚𝑏𝑖𝑛𝑎𝑡𝑖𝑜𝑛𝑎𝑙 𝑑𝑒𝑙𝑎𝑦 + 𝑡𝑠𝑒𝑡𝑢𝑝)
1
= (3.43 + 238 + 22)𝑝𝑠
= 3.79GHz
Verified for 270ps clock period that is 3.7GHz frequency
Using sub-block RC Extracted Netlists: (Pipelined)
The combinational delays we get are 337ps and 201.5ps
The worst possibility from the above is 337ps.
Hence, the maximum operating frequency of the CSM (without Pipeline) is
1
= (𝑡𝑐𝑞 + 𝑐𝑜𝑚𝑏𝑖𝑛𝑎𝑡𝑖𝑜𝑛𝑎𝑙 𝑑𝑒𝑙𝑎𝑦 + 𝑡𝑠𝑒𝑡𝑢𝑝)
1
= (3.43 + 337 + 22)𝑝𝑠
= 2.76GHz
Verified for 370ps clock period that is 2.7GHz frequency
The maximum operating frequency is increased by 1.76 times in
both schematic and Sub block RC extracted cases after using
pipeline.
Pipelined CSM: (Schematic)
Given below is the pipelined schematic along with launch and capture flops.

Test cases:
1) 115*125= 14375 (0011100000100111)
2) -127(10000001) *-127(10000001) = 16129 (0011111100000001)
3) 55* -71 = -3905 (1111000010111111)
4) -1*-1= 1 (0000000000000001)
5) -128* 107= -13696 (11010110000000)
Alternate vector merge: (Linear and Square root)
Instead of ripple carry adder, we used Square root carry select adder to reduce
the overall propagation delay. Since, we need not worry about the area, we are
going with this choice. We also implemented Linear carry select adder.
Designed the 2:1 Multiplexer using transmission gates.

Simulated for the input X= -128 and Y = 3. The simulations and delays obtained are:
 Ripple adder:

Linear carry select:

Square root carry select:

Hence, a speedup is achieved but not much significant because of less number of bits
in the path and multiplexers overhead.

Given below is the schematic of the Square root carry select adder and Liner carry
select adder.