ECE DEPT, PRESIDENCY UNIVERSITY

VLSI Design Lab Laboratory Manual

(ECE 3008)

for

5th Semester B. Tech.

Prepared by Verified by
1. Mr. SYED ABRAR AHMED 1. Dr. BHANU REKHA K

Edited by: Ms Akshaya M

Ganorkar

Department of Electronics and Communication

Engineering

Presidency University
School of Engineering
Itagalpura, Rajanukunte, Yelahanka, Bangalore-560064
08-09-2022

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Contents
Program
TITLE Page No.
No.

P1 Design of Basic Logic Gates using Verilog 3

P2 Design of Half adder, half subtractor, Full Adder using Verilog 8

P3 Design of Multiplexer, De-multiplexer and Encoder using Verilog. 12

P4 Design of SR, JK, D & T Flip Flops and Counters using Verilog 15

Understanding the basic steps for Cadence 22

P5 Plot the Static Characteristics of MOS Transistor 31

P6 Measurement of Parameters of an Inverter 35

P7 Design of 2-Input CMOS NAND and NOR Gate 43

P8 Design of Common Source (CS) with and without resistive load 47

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Experiment No. 1
Design of Basic Logic Gates using Verilog
Objective: The aim of the experiment is to write verilog code for the basic logic Gate circuit
and observe the waveform.
Tool required: Xilinx ISE tool
Theory: Digital systems are said to be constructed by using logic gates. These gates are
the AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are
described below with the aid of truth tables
1. NOT Gate

Test Bench for NOT Gate

Verilog Code module notgate_tb;
wire t_y;
module not1(input a, output b ); reg t_a;
not1 dut1( .a(t_a), .b(t_y) );
assign b= ~a;
initial begin
endmodule t_a = 1'b0;
#5
t_a = 1'b1;
Simulation Waveforms
#5
t_a = 1'b1;
end
initial begin
$monitor (" %d", $time,t_y);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

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2. And Gate

Test Bench for All Other Gates

VERILOG CODE
module logicgate_tb;
module and1( input a,b, output c); wire t_y;
reg t_a, t_b;
assign c= a & b; and1 dut1( .a(t_a), .b(t_b), .
endmodule c(t_y) );
initial begin
$monitor(t_a, t_b, t_y);
t_a = 1'b0;
t_b = 1'b0;
#5
Simulation Waveforms
t_a = 1'b0;
t_b = 1'b1;
#5
t_a = 1'b1;
t_b = 1'b0;
#5
t_a = 1'b1;
t_b = 1'b1;
#5
t_a = 1'b1;
t_b = 1'b1;
end
initial begin
$monitor ("%t | t_a = %d| t_b = %d|
t_y = %d", $time, t_a, t_b, t_y);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

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3. OR Gate

VERILOG CODE
module OR1(input a,b, output c);
assign c=a | b;
Endmodule

Simulation Waveforms

4. NAND Gate

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VERILOG CODE
module nand1( input a,b, output c);

assign c= ~(a & b);

endmodule

Simulation Waveforms

5. NOR Gate

VERILOG CODE
module nor1(input a,b, output c);
assign c=~(a | b);
endmodule

Simulation Waveforms

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6. EX-OR Gate

VERILOG CODE
module xor1(input a,b, output c );
assign c= a ^ b;
endmodule

Simulation Waveforms

Result: The logic Gates Design have been realized and simulated using HDL codes.

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Experiment No. 2
Design of Multiplexer, De-multiplexer and Encoder using Verilog
Objective: The aim of the experiment is to write Verilog code to describe the functions of
4:1 Multiplexer, 1:4 De-multiplexer and 8x3 Priority Encoder.
Tool required: Xilinx ISE tool
Theory and Implementation:
a) 4:1 Multiplexer

Test Bench for MUX

module top_tb;
wire out;
reg p; reg q; reg r; reg s;
reg s0,s1;
VERILOG CODE mux41 dut1(.y(out), .a(p), .b(q), .c(r),
module mux41(input a,b,c,d, input s0,s1, output y); .d(s), .s0(s0), .s1(s1));
initial
assign y= ((~ s0 )& (~ s1) & a)| begin
(s0 & (~ s1)& b) | p=1'b0; q=1'b0; r=1'b0; s=1'b0;
((~ s0) & s1 & c) | s0=1'b0; s1=1'b0;
(s0 & s1 & d); #500 $finish;
end
endmodule always #40 p=~p;
always #20 q=~q;
always #10 r=~r;
Simulation Waveforms always #5 s=~s;
always #80 s0=~s0;
always #160 s1=~s1;
always@(p or q or r or s or s0 or s1)
$monitor (" %d", $time,out);
initial
begin
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

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b) 1:4 Demultiplexer

Test Bench for Demux

VERILOG CODE module top_tb;
wire o1,o2,o3,o4;
module demux(input s1,s0,I,en, output reg e;
y3,y2,y1,y0);
reg i;
assign y0=(~s1)&(~s0)& I& ~en; reg s0, s1;
assign y1=(~s1)& s0& I& ~en; demux dut1(.y0(o1), .y1(o2), .y2(o3),
.y3(o4), .en(e),.I(i), .s0(s0), .s1(s1));
assign y2=s1&(~s0)& I & ~en; initial
assign y3=s1& s0 & I & ~en; begin
e=1'b0; i=1'b0;
endmodule
s0=1'b0; s1=1'b0;
#500 $finish;
end
always #40 i=~i;
always #85 s0=~s0;
always #165 s1=~s1;
always #400 e=~e;
always@(i or e or s0 or s1)
$monitor (" %d, %d, %d, %d ",
$time,o1,o2,o3,o4);
initial
begin
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

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Simulation Waveforms

c) 8x3 Priority Encoder

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VERILOG CODE Test Bench for Priority Encoder

module priority_encoder(I, Y); module top_tb;
input [7:0]I; reg [7:0] A;
output reg [2:0]Y; wire [2:0] out;
always@(I) priority_encoder
begin dut1(.I(A), .Y(out));
casex(I) initial
8'b00000001: Y = 3'b000; begin
8'b0000001x: Y = 3'b001; A = 0;
8'b000001xx: Y = 3'b010; A = 8'b00000000;
8'b00001xxx: Y = 3'b011; #10 A = 8'b10000000;
8'b0001xxxx: Y = 3'b100; #10 A = 8'b01000000;
8'b001xxxxx: Y = 3'b101;
#10 A = 8'b00100000;
8'b01xxxxxx: Y = 3'b110;
8'b1xxxxxxx: Y = 3'b111; #10 A = 8'b00010000;
default:$display("Error!"); #10 A = 8'b00001000;
endcase #10 A = 8'b00000100;
end #10 A = 8'b00000010;
endmodule #10 A = 8'b00000001;
#10 A = 8'b01001000;
#10 A = 8'b10001000;
#10 A = 8'b11001000;
end
initial begin
$monitor (" %d",
$time,out);
$dumpfile("dump.vcd");
$dumpvars();
end
endmodule

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Simulation Waveforms

RESULT: 4:1 Multiplexer, 1:4 De-multiplexer and 8x3 Priority Encoder & 8:3 Encoder has
been realized and simulated using Verilog Code.

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