Chapter 1: High-Level Synthesis

Scheduling and Binding Example

The following figure shows an example of the scheduling and binding phases for this code
example:

int foo(char x, char a, char b, char c) {

char y;
y = x*a+b+c;
return y;
}
X-Ref Target - Figure 1-1

1 2 3
Clock Cycle

Scheduling
Phase a

*
x
+
y
b +

Initial Binding Mul AddSub

Phase
AddSub

Target Binding
DSP48 AddSub
Phase
X14220-061518

Figure 1-1: Scheduling and Binding Example

In the scheduling phase of this example, high-level synthesis schedules the following
operations to occur during each clock cycle:

• First clock cycle: Multiplication and the first addition

• Second clock cycle: Second addition and output generation
Note: In the preceding figure, the square between the first and second clock cycles indicates when
an internal register stores a variable. In this example, high-level synthesis only requires that the
output of the addition is registered across a clock cycle. The first cycle reads x, a, and b data ports.
The second cycle reads data port c and generates output y.

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 Chapter 1: High-Level Synthesis

In the final hardware implementation, high-level synthesis implements the arguments to

the top-level function as input and output (I/O) ports. In this example, the arguments are
simple data ports. Because each input variables is a char type, the input data ports are all
8-bits wide. The function return is a 32-bit int data type, and the output data port is
32-bits wide.

IMPORTANT: The advantage of implementing the C code in the hardware is that all operations finish
in a shorter number of clock cycles. In this example, the operations complete in only two clock cycles.
In a central processing unit (CPU), even this simple code example takes more clock cycles to complete.

In the initial binding phase of this example, high-level synthesis implements the multiplier
operation using a combinational multiplier (Mul) and implements both add operations
using a combinational adder/subtractor (AddSub).

In the target binding phase, high-level synthesis implements both the multiplier and one of
the addition operations using a DSP48 resource. The DSP48 resource is a computational
block available in the FPGA architecture that provides the ideal balance of
high-performance and efficient implementation.

Extracting Control Logic and Implementing I/O Ports Example

The following figure shows the extraction of control logic and implementation of I/O ports
for this code example:

void foo(int in[3], char a, char b, char c, int out[3]) {

int x,y;
for(int i = 0; i < 3; i++) {
x = in[i];
y = a*x + b + c;
out[i] = y;
}
}

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 Chapter 1: High-Level Synthesis

X-Ref Target - Figure 1-2

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Figure 1-2: Control Logic Extraction and I/O Port Implementation Example
This code example performs the same operations as the previous example. However, it
performs the operations inside a for-loop, and two of the function arguments are arrays.
The resulting design executes the logic inside the for-loop three times when the code is
scheduled. High-level synthesis automatically extracts the control logic from the C code
and creates an FSM in the RTL design to sequence these operations. High-level synthesis
implements the top-level function arguments as ports in the final RTL design. The scalar
variable of type char maps into a standard 8-bit data bus port. Array arguments, such as in
and out, contain an entire collection of data.

In high-level synthesis, arrays are synthesized into block RAM by default, but other options
are possible, such as FIFOs, distributed RAM, and individual registers. When using arrays as
arguments in the top-level function, high-level synthesis assumes that the block RAM is
outside the top-level function and automatically creates ports to access a block RAM
outside the design, such as data ports, address ports, and any required chip-enable or
write-enable signals.

The FSM controls when the registers store data and controls the state of any I/O control
signals. The FSM starts in the state C0. On the next clock, it enters state C1, then state C2,
and then state C3. It returns to state C1 (and C2, C3) a total of three times before returning
to state C0.

Note: This closely resembles the control structure in the C code for-loop. The full sequence of states
are: C0,{C1, C2, C3}, {C1, C2, C3}, {C1, C2, C3}, and return to C0.

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