INT100

General Circuit Operation

One phase of a three-phase motor drive observed. The order of signal application The bootstrap capacitor must be large
circuit is shown in Figure 4 to illustrate should be VDD, logic signals, and then enough to provide bias current over the
an application of the INT100. The LS HV+. VDD should be supplied from a entire on-time of the high-side driver
IN signal directly controls MOSFET low impedance voltage source. without significant voltage sag or decay.
Q1. The HS IN signal controls MOSFET The high-side MOSFET gate charge
Q2 via the high voltage level shift The output returns (HS RTN and LS must also be supplied at the desired
transistors communicating with the high- RTN) are isolated from one another by switching frequency. Figure 6 shows
side driver. The INT100 will ignore the internal high-voltage MOSFET level the maximum high-side on-time versus
input signals that would command both shifters. The level shift circuitry is gate charge of the external MOSFET.
Q1 and Q2 to conduct simultaneously, designed to operate properly even when Applications with extremely long high-
protecting against shorting the HV+ bus the HS RTN swings as much as 5 V side on times require special techniques
to HV-. below the LS RTN pin with VDDH biased discussed in AN-10.
at 15 V. The INT100 will also safely
Local bypassing for the low-side driver tolerate more negative voltages (as low The high-side driver is latched on and
is provided by C1. Bootstrap bias for the as -VDDH below LS RTN). off by the edges of the appropriate low-
high-side driver is provided by D1 and side logic signal. The high-side driver
C2. Slew rate and effects of parasitic Maximum frequency of operation is will latch off and stay off if the bootstrap
oscillations in the load waveforms are limited by power dissipation due to high- capacitor discharges below the
controlled by resistors R1 and R2. voltage switching, gate charge, and bias undervoltage lockout threshold.
power. Figure 5 indicates the maximum Undervoltage lockout-induced turn off
The inputs are designed to be compatible switching frequency as a function of can occur during conditions such as
with 5 V CMOS logic levels and should input voltage and gate charge. For higher power ramp up, motor start, or low speed
not be connected to VDD. Normal CMOS ambient temperatures, the switching operation.
power supply sequencing should be frequency should be derated linearly.

CBOOTSTRAP vs. ON TIME

1000
PI-566B-030692
Bootstrap Capacitance (µF)

100

10

QG = 100 nC
1

QG = 20 nC
0.1

0.01
0.01 0.1 1 10 100
High Side On Time (ms)

Figure 6. High-side On Time versus Bootstrap Capacitor.

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 INT100

ABSOLUTE MAXIMUM RATINGS1

VDD Voltage ................................................................ 16.5 V
VDDH Voltage ........................................... HS RTN + 16.5 V
HS RTN ............................................. 800 V - VDDH to -VDDH
HS RTN Slew Rate ................................................... 10V/ns
Logic Input Voltage ...................................... -0.3V to 5.5 V
LS OUT Voltage ................ LS RTN - 0.3 V to VDD + 0.3 V
HS OUT Voltage .............. HS RTN - 0.3 V to VDDH + 0.3 V
Storage Temperature ....................................... –65 to 125°C
Ambient Temperature ........................................ -40 to 85°C
Junction Temperature ................................................. 150°C
Lead Temperature(2). ................................................... 260°C
Power Dissipation (TA = 25°C) .................................. 2.3 W
(TA = 70°C) .................................. 1.5 W
Thermal Impedance (θJA) ......................................... 55°C/W
1. Unless noted, all voltages referenced to COM, TA = 25°C
2. 1/16" from case for 5 seconds.

Conditions
(Unless Otherwise Specified)
Parameter Symbol VDDH = VDD = 15 V Min Typ Max Units
HS RTN = LS RTN = COM = 0 V
TA = -40 to 85°C

LOGIC
V IH = 4.0 V 0 10 150
Input Current, IIH, IIL µA
High or Low V IL = 1.0 V -20 0 20

Input Voltage VIH 4.0 V

High

Input Voltage V IL 1.0 V

Low

Input Voltage V HY 0.3 0.7 V

Hysteresis

LS OUT/HS OUT
Output LS OUT VDD-1.0 VDD-0.5
VOH Io= -20 mA V
Voltage High HS OUT VDDH-1.0 VDDH-0.5

Output VOL Io= 40 mA 0.3 1.0 V

Voltage Low
Output Short Vo= 0 V -150
IOS See Note 1 mA
Circuit Current Vo= 15 V 300

Turn-on Delay td(on)LS LS OUT 0.6 1.0

See Figure 7 µs
Time td(on)HS HS OUT 1.0 1.5

Rise tr ns
See Figure 7 80 120
Time
Turn-off Delay td(off)LS LS OUT 500 1000
See Figure 7 ns
Time td(off)HS HS OUT 420 600

Fall tf ns
See Figure 7 50 100
Time

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 INT100

Conditions
(Unless Otherwise Specified)
Parameter Symbol VDDH = VDD = 15 V Min Typ Max Units
HS RTN = LS RTN = COM = 0 V
TA = -40 to 85°C

LEVEL SHIFT
Breakdown BVDSS VDDH = HS OUT = HS RTN
800 V
Voltage IHS RTN = 100 µA

Leakage IHS RTN) VDDH = HS OUT = HS RTN = 500 V 0.2 30 µA

Current

Interface VDDH = HS OUT = HS RTN = 500 V 20 pF

Capacitance
SYSTEM RESPONSE

Deadtime (Low DtP+ See Figure 7 0 450 ns

Off to High On)
Deadtime (High DtP- See Figure 7 0 300 ns
Off to Low On)
UNDERVOLTAGE LOCKOUT

Input UV VDD(UV)
V DDH(UV) 8.5 9.0 10 V
Trip-off Voltage
Input UV 175 350 mV
Hysteresis
SUPPLY

Supply IDD, IDDH See Note 2 1.5 3.0 mA

Current
Supply VDD, VDDH 10 16 V
Voltage

NOTES:
1. Applying a short circuit to the LS OUT or HS OUT pin for more than 500 µs will exceed the thermal rating of the
package, resulting in destruction of the part.
2. VDD, VDDH supply must have less than 30Ω output impedance.

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 INT100

5V

INPUT 50% 50% 50%

0V
15 V td(off)LS
td(on)LS
tf
tr
15 V
1 µF 90% 90%
1 16
INPUT 2 15
100 nF LS OUT 50% 50%
3 14
INT100

4 13 10% 10%
0V
5 12 Dtp-
6 11 Dtp+
td(off)HS
7 10 td(on)HS
8 9 CL
1000 pF tf
tr
CL 15 V
90% 90%
1000 pF

HS OUT 50% 50%

10% 10%
0V

PI-1459-042695

Figure 7. Switching Time/Deadtime Test Circuit.

BREAKDOWN vs. TEMPERATURE PACKAGE POWER DERATING

1.1 2.5
PI-176B-051391

PI-1808-032096
Breakdown Voltage (V)

2.0
Power Dissipation (W)
(Normalized to 25°C)

1.5
1.0
1

0.5

0.9 0
-50 -25 0 25 50 75 100 125 150 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)

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