ESMT AD82088

2x20W Stereo / 1x40W Mono Digital Audio Amplifier

With 30 bands EQ and DRC Functions
2
Features  Supports I C control without clock
2
 Supply voltage  I C control interface with selectable device
3.3V for digital circuit address
2
8V~26V for loudspeaker driver  I S output with selectable Audio DSP point
 Supports 2.0CH/Mono configuration  Support hardware and software reset
 Loudspeaker output power@12V for stereo  Internal PLL
7W x 2CH into 8Ω <1% THD+N  Anti-pop design
10W x 2CH into 4Ω <1% THD+N  Level meter and power meter
 Loudspeaker output power@18V for stereo  LV Under-voltage shutdown and HV Under-voltage
15W x 2CH into 8Ω <1% THD+N detection
 Loudspeaker output power@24V for stereo  Over voltage protection
20W x 2CH into 8Ω <1% THD+N  Short circuit and over-temperature protection
2
 16/18/20/24-bits input with I S, Left-alignment
and Right-alignment data format Applications
 Multiple sampling frequencies (Fs)  TV audio
32kHz / 44.1kHz / 48kHz and
64kHz / 88.2kHz / 96kHz and Description
128kHz / 176.4kHz / 192kHz
AD82088 is a digital audio amplifier capable of
 System clock = 64x, 128x, 192x, 256x, 384x,
driving 20W (BTL) each to a pair of 8Ω load speaker
512x, 576x, 768x, 1024x Fs
and 40W (PBTL) to a 4Ω load speaker operating at
MCLK system:
24V supply without external heat-sink or fan
64x~1024x Fs for 32kHz / 44.1kHz / 48kHz
requirement with play music. AD82088 provides
64x~512x Fs for 64kHz / 88.2kHz / 96kHz
advanced audio processing functions, such as volume
64x~256x Fs for 128kHz / 176.4kHz / 192kHz
control, 30 EQ bands, audio mixing, 3D surround
BCLK system:
sound and Dynamic Range Control (DRC). These are
64xFs for 32kHz / 44.1kHz / 48kHz 2
fully programmable via a simple I C control interface.
64xFs for 64kHz / 88.2kHz / 96kHz
Robust protection circuits are provided to protect
64xFs for 128kHz / 176.4kHz / 192kHz
AD82088 from damage due to accidental erroneous
 Sound processing including：
operating condition. The full digital circuit design of
30 bands parametric speaker EQ
AD82088 is more tolerant to noise and PVT (Process,
Volume control (+24dB~-103dB, 0.125dB/step)
Voltage, and Temperature) variation than the analog
Dynamic range control
class-AB or class-D audio amplifier counterpart
Three Band plus post Dynamic range control
implemented by analog circuit design. AD82088 is pop
Power Clipping
free during instantaneous power on/off or mute/shut
Programmed 3D surround sound
down switching because of its robust built-in anti-pop
Channel mixing
circuit.
Noise gate with hysteresis window
Bass/Treble tone control
DC-blocking high-pass filter
Pre-scale/post-scale

Elite Semiconductor Memory Technology Inc. Publication Date: Nov. 2019

Revision: 1.8 1/83
ESMT AD82088
Pin Assignment

BST_RA

BST_RA
BST_LB

BST_LB
GNDR
GNDR

GNDR
GNDR
GNDL
GNDL

GNDL
GNDL
NC

NC
NC

NC
NC

NC
RA

RA
NC

NC
LB

LB
48
47
46
45
44
43
42
41
40
39
38
37

48
47
46
45
44
43
42
41
40
39
38
37
LA 1 36 RB LA 1 36 RB
VDDL 2 35 VDDR VDDL 2 35 VDDR
VDDL 3 34 VDDR VDDL 3 34 VDDR
BST_LA 4 33 BST_RB BST_LA 4 33 BST_RB
NC 5 32 GVDD NC 5 32 GVDD
NC 6 AD82088 31 VREG NC 6 AD82088-01 31 VREG
CLK_OUT 7 E-LQFP 48L 30 AGND CLK_OUT 7 E-LQFP 48L 30 AGND
PBTL 8 29 NC PBTL 8 29 NC
NC 9 28 DGND NC 9 28 DGND
NC 10 27 DVDD NC 10 27 DVDD
NC 11 26 TEST NC 11 26 SDATAO
NC 12 25 RESET NC 12 25 RESET
13
14
15
16
17
18
19
20
21
22
23
24

13
14
15
16
17
18
19
20
21
22
23
24
NC

NC
ERROR

ERROR
PD

PD
MCLK
NC
NC

SDA
SCL

MCLK
NC
NC

SDA
SCL
NC

LRCIN
BCLK
SDATA

NC

LRCIN
BCLK
SDATA
AD82088
ERROR 1 24 BST_LA
PD 2 23 VDDL
LRCIN 3 22 LA
BCLK 4 21 GNDL
SDATA 5 20 LB
SDA 6 19 BST_LB
SCL 7 18 BST_RA
SDATAO 8 17 RA
DVDD 9 16 GNDR
DGND 10 15 RB
VREG 11 14 VDDR
GVDD 12 13
BST_RB

E-TSSOP-24L

Pin Description (E-LQFP 48L)

PIN NAME TYPE DESCRIPTION CHARACTERISTICS

1 LA O Left channel output A.
2 VDDL P Left channel supply.
3 VDDL P Left channel supply.
4 BST_LA P Bootstrap supply for left channel output A.
5 NC Not connected.
6 NC Not connected.
PLL ratio setting pin during power up, this
pin is monitored on the rising edge of reset. TTL output buffer, internal pull Low
7 CLK_OUT I/O
PMF register will be default set at 1 or 16 with a 100Kohm resistor.
times PLL ratio.

Elite Semiconductor Memory Technology Inc. Publication Date: Nov. 2019

Revision: 1.8 2/83
ESMT AD82088
High: PMF [3:0] = [0000], 1 time of PLL ratio
to avoid system BCLK over flow.
Low: PMF [3:0] = [0001], 16 times of PLL
ratio.
This pin could be clock output pin also
during normal operating if EN_CLK_OUT
register bit is enabled.
Stereo/Mono configuration pin. TTL output buffer, internal pull Low
8 PBTL I
(Low: Stereo ; High: Mono) with a 100Kohm resistor.
9 NC Not connected.
10 NC Not connected.
11 NC Not connected.
12 NC Not connected.
13 NC Not connected.
2
ERROR pin is a dual function pin. One is I C This pin is monitored on the rising
address setting during power up. The other edge of reset. A value of Low (15-kΩ
2
14 ERROR I/O one is error status report (low active), It sets pull down) sets the I C device
by register of A_SEL_FAULT at address address to 0x30 and a value of High
0x1C B[6] to enable it. (15-kΩ pull up) sets it to 0x31.
Schmitt trigger TTL input buffer,
15 MCLK I Master clock input. internal pull Low with a 100Kohm
resistor.
16 NC Not connected.
17 NC Not connected.
18 NC Not connected.
Schmitt trigger TTL input buffer,
19 PD I Power down, low active. internal pull High with a 330Kohm
resistor.
Schmitt trigger TTL input buffer,
20 LRCIN I Left/Right clock input (Fs). internal pull Low with a 100Kohm
resistor.
Schmitt trigger TTL input buffer,
21 BCLK I Bit clock input (64Fs). internal pull Low with a 100Kohm
resistor.
22 SDATA I Serial audio data input. Schmitt trigger TTL input buffer
2
23 SDA I/O I C bi-directional serial data. Schmitt trigger TTL input buffer
2
24 SCL I I C serial clock input. Schmitt trigger TTL input buffer

Elite Semiconductor Memory Technology Inc. Publication Date: Nov. 2019

Revision: 1.8 3/83
ESMT AD82088
Schmitt trigger TTL input buffer,
25 RESET I Reset, low active. internal pull High with a 330Kohm
resistor.
26 TEST I This pin must connect to GND.
27 DVDD P Digital Power.
28 DGND P Digital Ground.
29 NC Not connected.
30 AGND P Analog Ground.
31 VREG O 1.8V Regulator voltage output.
5V Regulator voltage output. This pin must
32 GVDD O
not be used to drive external devices.
33 BST_RB P Bootstrap supply for right channel output B.
34 VDDR P Right channel supply.
35 VDDR P Right channel supply.
36 RB O Right channel output B.
37 GNDR P Right channel ground.
38 GNDR P Right channel ground.
39 RA O Right channel output A.
40 NC Not connected.
41 NC Not connected.
42 BST_RA P Bootstrap supply for right channel output A.
43 BST_LB P Bootstrap supply for left channel output B.
44 NC Not connected.
45 NC Not connected.
46 LB O Left channel output B.
47 GNDL P Left channel ground.
48 GNDL P Left channel ground.

Pin Description (01-E-LQFP 48L)

PIN NAME TYPE DESCRIPTION CHARACTERISTICS

1 LA O Left channel output A.
2 VDDL P Left channel supply.
3 VDDL P Left channel supply.
4 BST_LA P Bootstrap supply for left channel output A.
5 NC Not connected.
6 NC Not connected.

Elite Semiconductor Memory Technology Inc. Publication Date: Nov. 2019

Revision: 1.8 4/83
ESMT AD82088
PLL ratio setting pin during power up, this
pin is monitored on the rising edge of reset.
PMF register will be default set at 1 or 16
times PLL ratio.
High: PMF [3:0] = [0000], 1 time of PLL ratio
TTL output buffer, internal pull Low
7 CLK_OUT I/O to avoid system BCLK over flow.
with a 100Kohm resistor.
Low: PMF [3:0] = [0001], 16 times of PLL
ratio.
This pin could be clock output pin also
during normal operating if EN_CLK_OUT
register bit is enabled.
Stereo/Mono configuration pin. TTL output buffer, internal pull Low
8 PBTL I
(Low: Stereo ; High: Mono) with a 100Kohm resistor.
9 NC Not connected.
10 NC Not connected.
11 NC Not connected.
12 NC Not connected.
13 NC Not connected.
2
ERROR pin is a dual function pin. One is I C This pin is monitored on the rising
address setting during power up. The other edge of reset. A value of Low (15-kΩ
2
14 ERROR I/O one is error status report (low active), It sets pull down) sets the I C device
by register of A_SEL_FAULT at address address to 0x30 and a value of High
0x1C B[6] to enable it. (15-kΩ pull up) sets it to 0x31.
Schmitt trigger TTL input buffer,
15 MCLK I Master clock input. internal pull Low with a 100Kohm
resistor.
16 NC Not connected.
17 NC Not connected.
18 NC Not connected.
Schmitt trigger TTL input buffer,
19 PD I Power down, low active. internal pull High with a 330Kohm
resistor.
Schmitt trigger TTL input buffer,
20 LRCIN I Left/Right clock input (Fs). internal pull Low with a 100Kohm
resistor.
Schmitt trigger TTL input buffer,
21 BCLK I Bit clock input (64Fs).
internal pull Low with a 100Kohm

Elite Semiconductor Memory Technology Inc. Publication Date: Nov. 2019

Revision: 1.8 5/83
ESMT AD82088
resistor.
22 SDATA I Serial audio data input. Schmitt trigger TTL input buffer
2
23 SDA I/O I C bi-directional serial data. Schmitt trigger TTL input buffer
2
24 SCL I I C serial clock input. Schmitt trigger TTL input buffer
Schmitt trigger TTL input buffer,
25 RESET I Reset, low active. internal pull High with a 330Kohm
resistor.
26 SDATAO O Serial audio data output. Schmitt trigger TTL input buffer
27 DVDD P Digital Power.
28 DGND P Digital Ground.
29 NC Not connected.
30 AGND P Analog Ground.
31 VREG O 1.8V Regulator voltage output.
5V Regulator voltage output. This pin must
32 GVDD O
not be used to drive external devices.
33 BST_RB P Bootstrap supply for right channel output B.
34 VDDR P Right channel supply.
35 VDDR P Right channel supply.
36 RB O Right channel output B.
37 GNDR P Right channel ground.
38 GNDR P Right channel ground.
39 RA O Right channel output A.
40 NC Not connected.
41 NC Not connected.
42 BST_RA P Bootstrap supply for right channel output A.
43 BST_LB P Bootstrap supply for left channel output B.
44 NC Not connected.
45 NC Not connected.
46 LB O Left channel output B.
47 GNDL P Left channel ground.
48 GNDL P Left channel ground.

Elite Semiconductor Memory Technology Inc. Publication Date: Nov. 2019

Revision: 1.8 6/83
ESMT AD82088
Pin Description (E-TSSOP 24L)

PIN NAME TYPE DESCRIPTION CHARACTERISTICS

2
ERROR pin is a dual function pin. One is I C This pin is monitored on the rising
address setting during power up. The other edge of reset. A value of Low (15-kΩ
2
1 ERROR I/O one is error status report (low active), It sets pull down) sets the I C device
by register of A_SEL_FAULT at address address to 0x30 and a value of High
0x1C B[6] to enable it. (15-kΩ pull up) sets it to 0x31.
Schmitt trigger TTL input buffer,
2 PD I Power down, low active. internal pull High with a 330Kohm
resistor.
Schmitt trigger TTL input buffer,
3 LRCIN I Left/Right clock input (Fs). internal pull Low with a 100Kohm
resistor.
Schmitt trigger TTL input buffer,
4 BCLK I Bit clock input (64Fs). internal pull Low with a 100Kohm
resistor.
5 SDATA I Serial audio data input. Schmitt trigger TTL input buffer
2
6 SDA I/O I C bi-directional serial data. Schmitt trigger TTL input buffer
2
7 SCL I I C serial clock input. Schmitt trigger TTL input buffer
8 SDATAO O Serial audio data output. Schmitt trigger TTL input buffer
9 DVDD P Digital Power.
10 DGND P Digital Ground.
11 VREG O 1.8V Regulator voltage output.
5V Regulator voltage output. This pin must
12 GVDD O
not be used to drive external devices.
13 BST_RB P Bootstrap supply for right channel output B.
14 VDDR P Right channel supply.
15 RB O Right channel output B.
16 GNDR P Right channel ground.
17 RA O Right channel output A.
18 BST_RA P Bootstrap supply for right channel output A.
19 BST_LB P Bootstrap supply for left channel output B.
20 LB O Left channel output B.
21 GNDL P Left channel ground.
22 LA O Left channel output A.
23 VDDL P Left channel supply.
24 BST_LA P Bootstrap supply for left channel output A.

Elite Semiconductor Memory Technology Inc. Publication Date: Nov. 2019

Revision: 1.8 7/83